TWI625823B - Pixel structure, method for manufacturing the same, and display usging the same - Google Patents

Abstract

A pixel structure includes a first metal layer, a semiconductor layer, an isolation layer, and a second metal layer. The first metal layer is disposed on the substrate and includes a protection portion and an auxiliary portion, wherein the auxiliary portion is not connected to the protection portion. The semiconductor layer is disposed on the first metal layer, and the vertical projection of the semiconductor layer on the substrate and the vertical projection of the protective portion on the substrate at least partially overlap. The isolation layer is disposed on the semiconductor layer, and at least one first via hole penetrates the isolation layer. The second metal layer is disposed on the isolation layer and has a first connection portion and a second connection portion, wherein at least a part of the second connection portion is located in the first through hole, and the second connection portion is vertically projected from the substrate and The vertical projection of the auxiliary portion on the substrate overlaps at least partially.

Description

Pixel structure, manufacturing method thereof, and display using the same

The invention relates to a pixel structure, a manufacturing method thereof, and a display using the same.

Among various consumer electronic products, liquid crystal displays using thin film transistor (TFT) have been widely used. The liquid crystal display is mainly composed of a thin film transistor array substrate, a color filter array substrate, and a liquid crystal layer. The thin film transistor array substrate includes a plurality of pixel structures. The thin film transistor array substrate is provided with a plurality of thin film transistors arranged in an array. A crystal, and a pixel electrode arranged corresponding to each thin film transistor.

Generally, a thin film transistor array substrate is formed through multiple processes, such as a development process and an etching process. However, when the structure is more complicated, the exposure, development, and etching processes included in the photomask process also need to be performed relatively many times, which will increase the process cost and cause the cost of the manufactured consumer electronics products.

An embodiment of the present disclosure provides a display including a pixel structure, wherein the pixel structure includes a first metal layer, a second metal layer, a semiconductor layer, an isolation layer, a buffer layer, and a through hole penetrating the isolation layer or the buffer layer. The first metal layer includes a protection portion and an auxiliary portion, wherein the semiconductor layer is disposed above the protection portion and the second metal layer of the first metal layer. The protective portion of the first metal layer and the second metal layer can prevent the diffusion of impurities under the semiconductor layer or the intrusion of moisture into the semiconductor layer, thereby reducing the impact of impurities and moisture on the service life of the pixel structure and thereby improving Pixel structure reliability. The auxiliary portion of the first metal layer can be beneficial to the etching process for forming a through hole, thereby improving the problem of etching uniformity that may be extended.

An embodiment of the present disclosure provides a pixel structure including a first metal layer, a semiconductor layer, an isolation layer, and a second metal layer. The first metal layer is disposed on the substrate and includes a protection portion and an auxiliary portion, wherein the auxiliary portion is not connected to the protection portion. The semiconductor layer is disposed on the first metal layer, and the vertical projection of the semiconductor layer on the substrate and the vertical projection of the protective portion on the substrate at least partially overlap. The isolation layer is disposed on the semiconductor layer, and at least one first via hole penetrates the isolation layer. The second metal layer is disposed on the isolation layer and has a first connection portion and a second connection portion. At least a part of the second connection portion is located in the first through hole, and the first connection portion is vertically projected from the substrate. The vertical projection of the semiconductor layer on the substrate at least partially overlaps, and the vertical projection of the second connection portion on the substrate and the vertical projection of the auxiliary portion on the substrate at least partially overlap.

In some embodiments, the pixel structure further includes a third metal layer and a dielectric layer. The third metal layer is disposed on the isolation layer and has a gate portion and One less circuit portion, where the vertical projection of the gate portion on the substrate and the vertical projection of the semiconductor layer on the substrate at least partially overlap, and the vertical projection of the circuit portion on the substrate and the vertical projection of the second connection portion of the second metal layer on the substrate at least partially Partial overlap. The dielectric layer covers the third metal layer, wherein the first via hole penetrates the dielectric layer and the isolation layer, the second via hole penetrates the dielectric layer and the isolation layer, and the first connection portion of the second metal layer passes through the second via. The hole is electrically connected to the semiconductor layer.

In some embodiments, the third through hole penetrates the dielectric layer, and the second connection portion of the second metal layer is electrically connected to the circuit portion of the third metal layer through the third through hole.

In some embodiments, the pixel structure further includes a buffer layer and a fourth metal layer. The buffer layer is disposed between the first metal layer and the semiconductor layer, wherein the first through hole penetrates the buffer layer, the dielectric layer and the isolation layer. The fourth metal layer is disposed between the buffer layer and the semiconductor layer, wherein a vertical projection of the fourth metal layer on the substrate and a vertical projection of the semiconductor layer on the substrate at least partially overlap.

In some embodiments, the semiconductor layer has at least one source portion, at least one drain portion, and at least one channel portion, wherein the vertical projection of the channel portion on the substrate and the vertical projection of the gate portion of the third metal layer on the substrate and the first portion The vertical projection of the four metal layers on the substrate at least partially overlaps.

In some embodiments, the vertical projection of the protective portion on the substrate and the vertical projection of the fourth metal layer on the substrate at least partially overlap.

In some embodiments, the first through hole corresponds to a bent portion of the substrate.

In some embodiments, the auxiliary portion is in contact with a portion of the second connection portion located in the first through hole.

In some embodiments, the material of the first metal layer includes molybdenum.

An embodiment of the present disclosure provides a display including a pixel structure and a circuit board, wherein the circuit board is electrically connected to the second connection portion.

An embodiment of the present disclosure provides a method for manufacturing a pixel structure, including the following steps. A first metal layer is formed on the substrate, wherein the first metal layer includes a protection portion and an auxiliary portion, and the auxiliary portion is not connected to the protection portion. An active element is formed above the first metal layer, wherein the vertical projection of the protective portion on the substrate is a vertical projection of at least a portion of the channel portion of the active element on the substrate. A dielectric layer is formed on the active device. A portion of the dielectric layer directly above the auxiliary portion is removed, wherein the auxiliary portion is located in a predetermined bending region. A bending step is performed on the predetermined bending area to form a bending portion, and the bending portion corresponds to the through hole.

In some embodiments, in the step of removing a portion of the dielectric layer directly above the auxiliary portion, a portion of the auxiliary portion is removed so that the bottom of the through hole does not overlap with the remaining auxiliary portion.

In some embodiments, the remaining auxiliary portions are located on at least two sides of the through hole.

In some embodiments, the step of removing a portion of the dielectric layer directly above the auxiliary portion further includes forming a photoresist layer on the dielectric layer, wherein the photoresist layer has at least one opening, and the opening is vertically projected and assisted by the substrate. The vertical projections on the substrate overlap at least partially.

100‧‧‧ Display

102‧‧‧ Cover

104‧‧‧Circuit Board

106‧‧‧Driver

108‧‧‧ Spacer

110A, 110B, 110C‧‧‧ pixel structure

112‧‧‧ substrate

114‧‧‧first buffer layer

116‧‧‧first metal layer

118‧‧‧Protection Department

119, 120, 120’‧‧‧ Auxiliary Department

122‧‧‧The first isolation layer

124‧‧‧Second buffer layer

126‧‧‧Second metal layer

128‧‧‧Second isolation layer

129‧‧‧ third isolation layer

130‧‧‧Semiconductor layer

132‧‧‧Source Department

134‧‧‧Channel Department

136‧‧‧Drain

137‧‧‧ Third metal layer

138‧‧‧Gate

139‧‧‧Line Department

140‧‧‧ Dielectric layer

142‧‧‧ Fourth metal layer

144‧‧‧first connection

146‧‧‧Second connection section

200‧‧‧ glass substrate

202‧‧‧The first photoresist layer

204‧‧‧Second photoresist layer

1B-1B, 4G-4G, 6C-6C‧‧‧line segments

A‧‧‧ Scheduled bending area

B‧‧‧ Bending section

O1‧‧‧First opening

O2‧‧‧Second opening

O3‧‧‧ third opening

S1‧‧‧ Top surface

S2‧‧‧ lower surface

T1‧‧‧First through hole

T2‧‧‧Second through hole

T3‧‧‧Third through hole

FIG. 1A is a diagram illustrating a display according to some embodiments of the present disclosure. Top view schematic.

FIG. 1B is a schematic cross-sectional view taken along line 1B-1B in FIG. 1A.

FIG. 2 is an enlarged schematic view of the structure shown in FIG. 1B.

FIG. 3 is a schematic diagram before the pixel structure 110A is bent

FIG. 4A to FIG. 4I are flowcharts showing the fabrication of the pixel structure of FIG. 3.

FIG. 5 is a schematic diagram illustrating a pixel structure before being bent according to some embodiments of the present disclosure.

FIG. 6A is a schematic cross-sectional view illustrating a pixel structure in an etching process for forming a first through hole according to some embodiments of the present disclosure.

Fig. 6B is a schematic plan view of the auxiliary portion in Fig. 6A.

FIG. 6C is a schematic cross-sectional view taken along line 6C-6C in FIG. 6B.

FIG. 6D is a schematic diagram illustrating the pixel structure of FIG. 6A after forming the second through hole, the third through hole, and the fourth metal layer according to some embodiments of the present disclosure.

In the following, a plurality of embodiments of the present invention will be disclosed graphically. For the sake of clarity, many practical details will be described in the following description. However, it should be understood that these practical details should not be used to limit the disclosure. That is, in the embodiments of this disclosure, these practical details are unnecessary. In addition, in order to simplify the drawings, some conventional structures and components will be shown in the drawings in a simple and schematic manner.

In this article, use the terms first, second, third, etc. It is used to describe various elements, components, regions, and layers that can be understood. However, these elements, components, regions, and layers should not be limited by these terms. These words are limited to identifying single elements, components, areas, or layers. Therefore, a first element, component, region, and layer in the following can also be referred to as a second element, component, region, and layer without departing from the original meaning of the present disclosure.

In the drawings, the thicknesses of layers, films, panels, regions, etc. are exaggerated for clarity. Throughout the description, the same reference numerals denote the same elements. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to a physical and / or electrical connection.

Please see both FIG. 1A and FIG. 1B at the same time, wherein FIG. 1A is a schematic top view of the display 100 according to some embodiments of the present disclosure, and FIG. 1B shows a line segment 1B-1B along FIG. 1A Schematic cross-section. The display 100 includes a cover plate 102, a circuit board 104, a driving chip 106, a spacer 108, and a pixel structure 110A. In this embodiment, the display 100 may be a wearable display. For example, the display 100 shown in FIG. 1A may be a watch-like style and may be used to provide image information to a wearer.

The cover plate 102 may be a glass cover plate and is disposed on the pixel structure 110A. The circuit board 104 and the driving chip 106 are electrically connected to each other. The circuit board 104 may be a flexible circuit board. The pixel structure 110A can be electrically connected to the driving chip 106 through the circuit board 104. The pixel structure 110A is flexible and curved shape. The pixel structure 110A and the circuit board 104 can form a curved laminated structure together, in which the driving chip 106 and the spacer 108 can be wrapped in the laminated structure, and the cover plate 102 and the circuit board 104 are located on the upper side of the spacer 108, respectively. And underside. In addition, the spacer 108 can be used as a support structure for the laminated structure.

The specific structure of the pixel structure 110A can be as shown in Figure 2. Figure 2 shows an enlarged schematic view of the structure shown in Figure 1B. In order not to make the drawing too complicated, the cover plate 102 shown in Figure 1B is not Draw in Figure 2. In FIG. 2, the pixel structure 110A includes a substrate 112, a first buffer layer 114, a first metal layer 116, a first isolation layer 122, a second buffer layer 124, a second metal layer 126, a second isolation layer 128, and a first The three isolation layers 129, the semiconductor layer 130, the third metal layer 137, the dielectric layer 140, and the fourth metal layer 142. The fourth metal layer 142 of the pixel structure 110A includes a first connection portion 144 and a second connection portion 146.

The substrate 112 is, for example, a flexible substrate, and a material thereof is, for example, polyimide (PI), polyethylene terephthalate (PET), or polyethylene naphthalate (PEN). The base plate 112 has a bent portion B, wherein the bent portion B of the base plate 112 is conformed to the curved contour of the spacer 108. In addition, the second connection portion 146 may be electrically connected to the circuit board 104.

The pixel structure 110A shown in FIG. 2 is formed by bending its internal structure. However, in order to facilitate the description of the relationship between the elements, the state before the pixel structure 110A is bent will be described below. Please see FIG. 3, which shows a schematic diagram of the pixel structure 110A before being bent. In addition, for the isolation layer or the buffer layer described below, the material may be an inorganic material, such as silicon oxide (SiOx) , Silicon nitride (SiNx) or a composite layer composed of silicon oxide and silicon nitride.

As shown in FIG. 3, the first buffer layer 114 is disposed on the substrate 112, the first metal layer 116 is disposed on the first buffer layer 114, and the first isolation layer 122 covers the first metal layer 116, so that the first metal The layer 116 is sandwiched between the first buffer layer 114 and the first isolation layer 122. The first metal layer 116 includes a protective portion 118 and auxiliary portions 120 and 120 '. The protective portion 118 is not connected to the auxiliary portions 120 and 120'. In addition, the auxiliary portions 120 and 120 'are disconnected from each other with a gap therebetween.

The second buffer layer 124 is disposed on the first isolation layer 122, and the second metal layer 126 is disposed on the second buffer layer 124, and the second isolation layer 128 covers the second metal layer 126, so that the second metal layer 126 will be It is sandwiched between the second buffer layer 124 and the second isolation layer 128. The vertical projection of the second metal layer 126 on the substrate 112 may at least partially overlap the vertical projection of the protective portion 118 of the first metal layer 116 on the substrate 112. For example, the vertical projection of the second metal layer 126 on the substrate 112 and the third projection The vertical projection of the leftmost protection part 118 on the substrate 112 in the figure constitutes an overlapping area, and the minimum width of this overlapping area can be between 1 micrometer and 5 micrometers.

The semiconductor layer 130 is disposed on the second isolation layer 128, and the third isolation layer 129 covers the semiconductor layer 130 so that the semiconductor layer 130 is sandwiched between the second isolation layer 128 and the third isolation layer 129. The vertical projection of the semiconductor layer 130 on the substrate 112 at least partially overlaps with the vertical projection of the protective portion 118 of the first metal layer 116 and the second metal layer 126 on the substrate 112.

The material of the semiconductor layer 130 is, for example, polysilicon, and has a source portion 132, a channel portion 134, and a drain portion 136. The source portion 132 and the drain portion 136 are located at both ends of the channel portion 134. The semiconductor layer 130 can define a source portion 132, a channel portion 134, and a drain portion 136 by doping. The doping may be heavily doped or lightly doped. In addition, the source portion 132 and the drain portion 136 may be defined by heavy doping, and there may be a lightly doped region between the channel portion 134 and the source portion 132 or between the channel portion 134 and the drain portion 136.

The vertical projection of the channel portion 134 on the substrate 112 may at least partially overlap the vertical projection of the second metal layer 126 on the substrate 112. In addition, a vertical projection area of the second metal layer 126 on the substrate 112 may be larger than a vertical projection area of the channel portion 134 on the substrate 112. The boundary position of the vertical projection of the second metal layer 126 on the substrate 112 may exceed the boundary position of the vertical projection of the channel portion 134 on the substrate 112, and the excess length may be between 0.5 and 5 microns.

The vertical projection of the source portion 132 and the drain portion 136 on the substrate 112 may at least partially overlap the vertical projection of the protection portion 118 of the first metal layer 116 on the substrate 112. In addition, the boundary position of the vertical projection of the protective portion 118 on the substrate 112 of the first metal layer 116 may exceed the boundary position of the vertical projection of the semiconductor layer 130 on the substrate 112, and the excess length may be between 0.5 and 3 microns. In addition, the vertical projection of the semiconductor layer 130 on the substrate 112 may be smaller than and fall within the vertical projection of the protective portion 118 of the first metal layer 116 and the second metal layer 126 together on the substrate 112.

Through the above configuration, the protective portion 118 and the second metal layer 126 of the first metal layer 116 disposed between the substrate 112 and the semiconductor layer 130 can serve as isolation features, which can be used to prevent the diffusion of impurities or moisture under the semiconductor layer 130 Invaded into the semiconductor layer 130. Therefore, the influence of impurities and water vapor on the pixel structure 110A can be reduced, so that the pixel structure 110A has better reliability and enables Used life.

The third metal layer 137 and the dielectric layer 140 are disposed on the third isolation layer 129, and the dielectric layer 140 covers the third metal layer 137. The material of the dielectric layer 140 may be an inorganic material, such as silicon oxide (SiOx). , Silicon nitride (SiNx), or a stacked structure (SiOx / SiNx or SiNx / SiOx) composed of silicon oxide and silicon nitride, which can be used as interlayer dielectrics (ILD). The third metal layer 137 includes a gate portion 138 and a circuit portion 139, wherein the gate portion 138 and the line portion 139 are electrically connected to each other, and a vertical projection of the gate portion 138 on the substrate 112 is perpendicular to the channel portion 134 on the substrate 112. The projections overlap at least partially. The gate portion 138 and the source portion 132, the channel portion 134, and the drain portion 136 of the semiconductor layer 130 may form an active element together, for example, form a thin film transistor together. In some embodiments, the first metal layer 116, the second metal layer 126, and the third metal layer 137 may have equal potentials. In other embodiments, the potentials of the first metal layer 116 and the second metal layer 126 may be floating.

In addition, in the structure of the pixel structure 110A, it may have a plurality of through holes. In addition to connecting the metal layers between different layers, some of the through holes may be used as the pixel structure 110A. Bend area when bending. As shown in FIG. 3, the pixel structure 110A has a first through hole T1, a second through hole T2, and a third through hole T3.

The first through hole T1 penetrates the first isolation layer 122, the second buffer layer 124, the second isolation layer 128, the third isolation layer 129, and the dielectric layer 140. Please refer to FIG. 2 and FIG. 3 at the same time, and the substrate 112 is located at The portion below the first through hole T1 corresponds to the bent portion B. In other words, when the pixel structure 110A shown in FIG. 3 is to be bent When the pixel structure 110A is shown in FIG. 2, the location of the first through hole T1 can be regarded as a predetermined bending area A of the pixel structure 110A. Then, a bending step can be performed on the predetermined bending area A. For example, in the bending step performed, a portion of the substrate 112 located below the first through hole T1 may be bent, and the bent portion of the substrate 112 may follow the curved contour of the gap 108 in FIG. 2. Deformation occurs, resulting in a bent portion B.

After bending, as shown in FIG. 2, the substrate 112 extends from the upper surface S1 of the spacer 108 to the lower surface S2 of the spacer 108, wherein the upper surface S1 and the lower surface S2 of the spacer 108 are opposite to each other. In addition, after being bent, the substrate 112 is located between the circuit board 104 and the semiconductor layer 130.

Please return to FIG. 3 again. The second through-hole T2 penetrates the third isolation layer 129 and the dielectric layer 140. The second through-hole T2 can be configured in pairs, and the pair of second through-holes T2 The arrangement position may correspond to the source portion 132 and the drain portion 136 of the semiconductor layer 130. The third through-hole T3 penetrates the dielectric layer 140, wherein the third through-hole T3 can be arranged in pairs, and the arrangement position of the pair of third through-holes T3 can correspond to the wiring portion 139 of the third metal layer 137. .

The fourth metal layer 142 is disposed on the dielectric layer 140 and has a first connection portion 144 and a second connection portion 146. The vertical projection of the first connection portion 144 on the substrate 112 at least partially overlaps with the vertical projection of the semiconductor layer 130 on the substrate 112, and a portion of the first connection portion 144 will be located in the second through hole T2, which is located in the second through hole T2. The first connection portion 144 contacts the source portion 132 and the drain portion 136 of the semiconductor layer 130, so that the first connection portion 144 can be electrically connected to the source portion 132 and the drain portion 136. The vertical projection of the second connecting portion 146 on the substrate 112 and the vertical projection of the auxiliary portions 120 and 120 'of the first metal layer 116 on the substrate 112 are at least partially heavy. And the second connecting portions 146 are located in the first through holes T1 and the third through holes T3, respectively. A bottom portion of the second connection portion 146 located in the first through hole T1 may be in contact with the auxiliary portions 120 and 120 'of the first metal layer 116. The second connection portion 146 located in the third through hole T3 contacts the circuit portion 139 of the third metal layer 137, so that the second connection portion 146 can be electrically connected to the third metal layer 137.

The active element of the pixel structure 110A can be electrically connected to an external device through the fourth metal layer 142, and thereby control whether it is driven or not. For example, since the second connection portion 146 is also electrically connected to the circuit board 104 (see FIG. 2), the circuit board 104 (see FIG. 2) can pass through the second connection portion 146 and the third metal layer 137. The circuit portion 139 is electrically connected to the gate portion 138 of the third metal layer 137, so that the driving chip 106 (see FIG. 2) can drive an active element corresponding to the gate portion 138.

On the other hand, the auxiliary portions 120 and 120 'of the first metal layer 116 can facilitate the etching process for forming the first through hole T1, thereby improving the etching uniformity problem that it may extend. Please see FIGS. 4A to 4I FIG. 4A to FIG. 4I are manufacturing flowcharts of the pixel structure 110A of FIG. 3.

As shown in FIG. 4A, the substrate 112 may be first disposed on the glass substrate 200, and then a first buffer layer 114 may be formed on the substrate 112. After the first buffer layer 114 is formed, the protective portion 118 and the auxiliary portion 119 of the first metal layer 116 may be formed through a patterning process, that is, the protective portion 118 and the auxiliary portion 119 are formed by patterning the same metal film material. Formed, wherein the formation position of the auxiliary portion 119 may be designed to be located within the predetermined bending area A in FIG. 3. In the patterning process performed, the protection portion 118 and the auxiliary portion 119 of the first metal layer 116 are disconnected from each other, that is, the protection portion 118 is not connected to the auxiliary portion 119, and the first metal layer 116 The auxiliary part 119 of the present invention may present a plurality of parallel stripe patterns, as shown in FIG. 4B, where FIG. 4B is the auxiliary part 119 viewed from a plan view in FIG. 4A. In addition, the material of the first metal layer 116 may include molybdenum, titanium, or other metal materials capable of withstanding temperatures above 400 degrees, and the thickness of the first metal layer 116 may be between 50 microns and 300 microns.

As shown in FIG. 4C, a first isolation layer 122 covering the first metal layer 116 may be formed, and then a second buffer layer 124 may be formed on the first isolation layer 122. After the second buffer layer 124 is formed, a second metal layer 126 is formed through a patterning process. In addition, the material of the second metal layer 126 may include molybdenum, and the thickness of the second metal layer 126 may be between 50 microns and 300 microns.

As shown in FIG. 4D, a second isolation layer 128 covering the second metal layer 126 can be formed, and then a semiconductor layer 130, a third isolation layer 129, a third metal layer 137, a fourth metal layer 142, and Dielectric layer 140. As described above, after the semiconductor layer 130 is formed, the source portion 132, the channel portion 134, and the drain portion 136 of the semiconductor layer 130 can be defined by doping. The relative positional relationship between the semiconductor layer 130, the first metal layer 116, and the second metal layer 126 may be the same as described above, and details are not described herein again.

In the process of forming the third metal layer 137, the gate portion 138 and the circuit portion 139 of the third metal layer 137 may be formed through a patterning process, that is, the gate portion 138 and the circuit portion 139 are processed by the same metal film material. Formed by patterning, wherein the source portion 132, the channel portion 134, the drain portion 136, and the gate portion 138 of the third metal layer 137 of the semiconductor layer 130 can collectively form an active device.

After the dielectric layer 140 is formed, a first photoresist layer 202 can be formed on the dielectric layer 140, and then the first photoresist layer 202 is exposed and developed. Therefore, the first photoresist layer 202 has a first opening O1, and the first opening O1 is correspondingly formed above the auxiliary portion 119 of the first metal layer 116.

As shown in FIG. 4D and FIG. 4E, an etching process can be performed through the first photoresist layer 202 having the first opening O1 to form a first through hole T1, where the position of the first through hole T1 will correspond to the first Position of the opening O1. During the etching process, the dielectric layer 140, the third isolation layer 129, the second isolation layer 128, the second buffer layer 124, and the first isolation layer 122 under the first opening O1 will be partially removed in order.

During the period when the first isolation layer 122 is gradually removed, a part of the upper surface of the auxiliary portion 119 is also gradually exposed, and the exposed auxiliary portion 119 is gradually removed during the etching process. Under the condition that different materials are used for the first isolation layer 122 and the auxiliary portion 119, the etching rates of the first isolation layer 122 and the auxiliary portion 119 in the etching process will also be different. For example, the first isolation layer 122 and the auxiliary portion 119 will be different. The materials can be silicon oxide and molybdenum respectively, and silicon oxide and molybdenum will have different etching rates in the same etching process. Among the etching processes performed in FIG. 4E, the etching rate of silicon oxide will be greater than that of molybdenum. . Therefore, when the first isolation layer 122 has not been completely removed and the auxiliary portion 119 has gradually started to be exposed, the etching selection ratio of the first isolation layer 122 and the auxiliary portion 119 can be used to change the The first isolation layer 122 removes clean or leaves a little residue that does not affect the pixel structure, and makes the surface at the bottom of the first through hole T1 have better uniformity.

In addition, after the etching process is performed, a part of the auxiliary part 119 is removed, and another part of the auxiliary part 119 is retained in the pixel structure 110A. The remaining part of the auxiliary part 119 corresponds to the auxiliary part of FIG. 4E. 120 and 120 '. In FIG. 4E, the auxiliary portions 120 and 120 'are located on at least two sides of the first through hole T1 and do not overlap the bottom of the first through hole T1.

In addition, please refer to FIG. 4F and FIG. 4G at the same time, where FIG. 4F is a schematic plan view of the auxiliary parts 120 and 120 ′ shown in FIG. A schematic cross-sectional view of the line segment 4G-4G. During the etching process performed in FIG. 4E, after the first isolation layer 122 is removed, since the auxiliary portion 119 of the first metal layer 116 is a plurality of parallel strip patterns (as shown in FIG. 4B), A portion of the first buffer layer 114 corresponding to the first through hole T1 is not covered by the auxiliary portion 119, and the first buffer layer 114 not covered by the auxiliary portion 119 is also removed due to the etching process.

For the auxiliary portion 119 and the first buffer layer 114, in the etching process performed in FIG. 4E, since the etching rate of the first buffer layer 114 is greater than the etching rate of the auxiliary portion 119, it corresponds to the first through hole T1. Before the auxiliary portion 119 is removed, the first buffer layer 114 in the first through hole T1 that is not covered by the auxiliary portion 119 is removed first, and a part of the substrate 112 is exposed through the first through hole T1. After the etching process is completed, the first buffer layer 114 covered by the auxiliary portion 119 corresponding to the first through hole T1 will be retained, and the first buffer layer 114 covered by the auxiliary portion 119 corresponding to the first through hole T1 will be retained. The substrate 112 is removed, and the underlying substrate 112 is also exposed.

After the first through hole T1 is formed, the first photoresist layer 202 is removed, and a second photoresist layer 204 is formed on the dielectric layer 140, as shown in FIG. 4H. Then, the second photoresist layer 204 is exposed and developed, so that the second photoresist layer 204 layer has a second opening O2 and a third opening O3. The second openings O2 may be arranged in pairs, and are formed correspondingly in the source portion 132 and the drain of the semiconductor layer 130, respectively. Above the pole portion 136, the vertical projections of the pair of second openings O2 on the substrate 112 at least partially overlap the vertical projections of the source portion 132 and the drain portion 136 on the substrate 112, respectively. The third openings O3 may be arranged in pairs, and are formed correspondingly above the wiring portions 139 of the third metal layer 137, so that the vertical projections of the pair of third openings O3 on the substrate 112 and the wiring portions are respectively The vertical projection of 139 on the substrate 112 at least partially overlaps.

As shown in FIG. 4H and FIG. 4I, an etching process may be performed through the second photoresist layer 204 having the second opening O2 and the third opening O3, thereby forming the second through hole T2 and the third through hole T3. The positions of the second through hole T2 and the third through hole T3 will correspond to the positions of the second opening O2 and the third opening O3, respectively. After the etching process is performed, the dielectric layer 140 under the second opening O2 and the third isolation layer 129 and the dielectric layer 140 under the third opening O3 are removed, so that the source portion 132 and the drain portion of the semiconductor layer 130 are removed. 136 and the wiring portion 139 of the third metal layer 137 are exposed. After the second through-hole T2 and the third through-hole T3 are formed, the second photoresist layer 204 can be removed first, and then a fourth metal layer 142 can be formed to complete the pixel structure 110A. In addition, after the fourth metal layer 142 is formed, the glass substrate 200 can be detached from the pixel structure 110A, as shown in FIG. 3.

In addition, the fourth metal layer 142 may be formed through a patterning process, wherein the first connection portion 144 and the second connection portion 146 of the fourth metal layer 142 may be formed by patterning the same metal film material. During the patterning process, the first connection portion 144 and the second connection portion 146 of the fourth metal layer 142 are disconnected from each other, that is, the first connection portion 144 is not connected to the second connection portion 146. In addition, in the patterning process of forming the first metal layer 116 and the fourth metal layer 142, the same photomask can be used, thereby reducing the manufacturing cost of the pixel structure 110A.

When the photoresist pattern used in the patterning process of forming the first metal layer 116 and the fourth metal layer 142 is defined by the same mask, the vertical projection of the first metal layer 116 on the substrate 112 and the fourth metal layer The vertical projection of 142 on the substrate 112 will be substantially the same. After the fourth metal layer 142 is formed, as described above, a bending step may be performed, so that the pixel structure 110A of FIG. 3 becomes the pixel structure 110A of FIG. 2, and details are not described herein again.

In other embodiments, the photoresist pattern used in the patterning process of forming the first metal layer 116 and the fourth metal layer 142 may be defined by different photomasks. For example, see FIG. 5. FIG. 5 is a schematic diagram illustrating the pixel structure 110B before being bent according to some embodiments of the present disclosure. As shown in FIG. 5, when the photoresist pattern used in the patterning process of forming the first metal layer 116 and the fourth metal layer 142 is defined by a different photomask, the first metal layer 116 is on the substrate The vertical projection of 112 may have a different profile from the vertical projection of the fourth metal layer 142 on the substrate 112.

In addition, in other embodiments, during the etching process for forming the first through hole, the auxiliary portion may remain in the first through hole. For example, please see FIG. 6A. FIG. 6A is a schematic cross-sectional view of an etching process for forming the pixel structure 110C to form the first through hole T1 according to some embodiments of the present disclosure. The structure shown in FIG. 4 can be regarded as a continuation of the structure shown in FIG. 4D, and the structure shown in FIG. 6A is a schematic diagram of the pixel structure 110C in the production stage.

At least one difference between the etching process performed in FIG. 6A and the etching process performed in FIG. 4E is that in the etching process performed in FIG. 6A, the auxiliary portion 119 corresponding to the first through hole T1 is not completely removed. , Its thickness will It is reduced due to etching, wherein the thickness of the auxiliary portion 119 corresponding to the first through hole T1 is smaller than the thickness of the auxiliary portions 120 and 120 'covered by the first isolation layer 122.

Please see FIG. 6B and FIG. 6C at the same time, wherein FIG. 6B is a schematic plan view of the auxiliary parts 119, 120, and 120 ′ of FIG. 6A, and FIG. 6C is a schematic cross-sectional view along line 6C-6C of FIG. 6B . As mentioned above, during the etching process shown in FIG. 6A, since the auxiliary portion 119 of the first metal layer 116 is a plurality of parallel strip patterns, there will be a portion of the first buffer layer 114 that is not the auxiliary portion. 119 is covered, and the first buffer layer 114 in this part is removed by etching.

In the etching process performed in FIG. 6A, while the thickness of the auxiliary portion 119 corresponding to the first through hole T1 is reduced by etching, the first buffer layer corresponding to the first through hole T1 is not covered by the auxiliary portion 119. 114 will gradually be removed. For the auxiliary portion 119 and the first buffer layer 114, since the etching rate of the first buffer layer 114 is higher than the etching rate of the auxiliary portion 119, the auxiliary portion 119 corresponding to the first through hole T1 is not assisted until the auxiliary portion 119 is removed. The first buffer layer 114 covered by the portion 120 is removed first, and a part of the substrate 112 is exposed through the first through hole T1. The etching process performed in FIG. 6A is performed before the auxiliary portion 119 is removed. Aborted. That is, after the etching process is completed, the auxiliary portion 120 and the first buffer layer 114 covered by the auxiliary portion 120 will be retained, and the first buffer layer 114 not covered by the auxiliary portion 120 will be removed, and the substrate below 112 will also be exposed.

After the first through hole T1 is formed, the first photoresist layer 202 may be removed, and then the processes described in FIGS. 4H to 4I are performed to complete the process of the pixel structure 110C. For example, please refer to FIG. 6A and FIG. 6D at the same time, where FIG. 6D shows FIG. 6A according to some implementations of the disclosure. A schematic diagram of the pixel structure 110C after the second through hole T2, the third through hole T3, and the fourth metal layer 142 are formed. As shown in the pixel structure 110C in FIG. 6D, after the processes described in FIGS. 4H to 4I are performed, the second through holes T2 and the third through holes T3 are formed in the dielectric layer 140. The metal layer 142 is formed on the dielectric layer 140, and the second connection portion 146 of the fourth metal layer 142 is in contact with the auxiliary portion 119 of the first metal layer 116 in the first through hole T1. On the other hand, the glass substrate 200 in FIG. 6A can be detached from the pixel structure 110C. After the fourth metal layer 142 is formed, as described above, a bending step may be performed, and details are not described herein again.

In summary, the display of the present disclosure may be a wearable display, and it includes a pixel structure, wherein the pixel structure includes a first metal layer, a second metal layer, a semiconductor layer, a plurality of isolation layers, and a buffer layer. In addition, The pixel structure also has a through hole penetrating the isolation layer or the buffer layer. The first metal layer includes a protection portion and an auxiliary portion, wherein the semiconductor layer is disposed above the protection portion and the second metal layer of the first metal layer. The protective portion of the first metal layer and the second metal layer can be used as isolation features to prevent the diffusion of impurities under the semiconductor layer or the invasion of water vapor to the semiconductor layer, thereby reducing the impurities and water vapor's lifespan of the pixel structure. And improve the reliability of the pixel structure. On the other hand, the auxiliary portion of the first metal layer can be beneficial to the etching process for forming a through hole, thereby improving the problem of etching uniformity that it may extend. In other words, the first metal layer can simultaneously improve the reliability of the pixel structure and improve the etching uniformity problem that may occur during the etching process through its protective portion and auxiliary portion.

Although the content of this disclosure has been disclosed above in various ways, it is not intended to limit the content of this disclosure. Any person skilled in this art can make various changes and decorations without departing from the spirit and scope of this disclosure. this The scope of protection of the disclosure shall be determined by the scope of the attached patent application.

Claims (14)

A pixel structure includes: a first metal layer disposed on a substrate and including a protection portion and an auxiliary portion, wherein the auxiliary portion is not connected to the protection portion; a semiconductor layer disposed on the first metal Layer, and the vertical projection of the semiconductor layer on the substrate at least partially overlaps the vertical projection of the protective portion on the substrate; an isolation layer is disposed on the semiconductor layer, and at least one first through hole penetrates the isolation layer And the first through hole corresponds to a bent portion of the substrate; and a second metal layer is disposed on the isolation layer and has a first connection portion and a second connection portion, wherein the second connection portion At least a portion of is located in the first through hole, and a vertical projection of the first connection portion on the substrate and a vertical projection of the semiconductor layer on the substrate at least partially overlap, and the second connection portion is perpendicular to the substrate The projection at least partially overlaps the vertical projection of the auxiliary portion on the substrate. The pixel structure according to item 1 of the patent application scope further includes: a third metal layer disposed on the isolation layer, and having a gate portion and at least one circuit portion, wherein the gate portion is on the substrate And the vertical projection of the semiconductor layer on the substrate at least partially overlaps, and the vertical projection of the circuit portion on the substrate and the vertical projection of the second connection portion of the second metal layer on the substrate at least partially overlap; and A dielectric layer covering the third metal layer, wherein the at least one first via hole penetrates the dielectric layer and the isolation layer, at least one second via hole penetrates the dielectric layer and the isolation layer, and the The first connection portion of the second metal layer is electrically connected to the semiconductor layer through the second through hole. The pixel structure according to item 2 of the scope of patent application, wherein at least one third through-hole penetrates the dielectric layer, and the second connection portion of the second metal layer passes through the third through-hole and the third through-hole. The circuit portion of the metal layer is electrically connected. The pixel structure according to item 2 of the patent application scope further includes: a buffer layer disposed between the first metal layer and the semiconductor layer, wherein the at least one first through hole penetrates the buffer layer, the A dielectric layer and the isolation layer; and a fourth metal layer disposed between the buffer layer and the semiconductor layer, wherein a vertical projection of the fourth metal layer on the substrate and a vertical projection of the semiconductor layer on the substrate are at least Partial overlap. The pixel structure according to item 4 of the scope of patent application, wherein the semiconductor layer has at least one source portion, at least one drain portion, and at least one channel portion, wherein a vertical projection of the channel portion on the substrate and the third portion The vertical projection of the gate portion of the metal layer on the substrate and the vertical projection of the fourth metal layer on the substrate at least partially overlap. The pixel structure according to item 4 of the scope of patent application, wherein the vertical projection of the protective portion on the substrate and the vertical projection of the fourth metal layer on the substrate at least partially overlap. The pixel structure according to item 1 of the patent application scope, wherein the auxiliary portion is in contact with a portion of the second connecting portion located in the first through hole. The pixel structure according to item 1 of the application, wherein the material of the first metal layer comprises molybdenum. A display includes: a pixel structure according to any one of claims 1 to 8; and a circuit board electrically connected to the second connection portion. A method for manufacturing a pixel structure includes: forming a first metal layer on a substrate, wherein the first metal layer includes a protection portion and an auxiliary portion, and the auxiliary portion is not connected to the protection portion; forming an active portion The element is above the first metal layer, wherein the vertical projection of the protective portion on the substrate overlaps at least a portion of a channel portion of the active element on the substrate; forming a dielectric layer on the active element; Removing a portion of the dielectric layer directly above the auxiliary portion, wherein the auxiliary portion is located in a predetermined bending area; and performing a bending step on the predetermined bending area to form a bending portion, and the bending The part corresponds to a through hole. According to the manufacturing method of the pixel structure according to item 10 of the scope of patent application, in the step of removing the part of the dielectric layer directly above the auxiliary part, a part of the auxiliary part is removed, so that the communication The bottom of the hole does not overlap with the remaining auxiliary portion. The manufacturing method of the pixel structure according to item 11 of the scope of patent application, wherein the remaining auxiliary parts are located on at least two sides of the through hole. The method for manufacturing a pixel structure according to item 10 of the scope of patent application, wherein the step of removing the portion of the dielectric layer directly above the auxiliary portion further includes: forming a photoresist layer on the dielectric layer Wherein, the photoresist layer has at least one opening, and a vertical projection of the opening on the substrate and a vertical projection of the auxiliary portion on the substrate at least partially overlap. A pixel structure includes: a first metal layer disposed on a substrate and including a protection portion and an auxiliary portion, wherein the auxiliary portion is not connected to the protection portion; a semiconductor layer disposed on the first metal Layer, and the vertical projection of the semiconductor layer on the substrate at least partially overlaps with the vertical projection of the protective portion on the substrate; an isolation layer is disposed on the semiconductor layer, and at least one first through hole penetrates the isolation layer And a second metal layer disposed on the isolation layer and having a first connection portion and a second connection portion, wherein at least a part of the second connection portion is located in the first through hole, and the The auxiliary portion is in contact with a portion of the second connection portion located in the first through hole, wherein a vertical projection of the first connection portion on the substrate and a vertical projection of the semiconductor layer on the substrate at least partially overlap, and the second connection The vertical projection on the substrate and the vertical projection of the auxiliary portion on the substrate at least partially overlap.