KR20150136363A - Thin Film Transistor Array Substrate and Method for Manufacturing the Same - Google Patents

Abstract

The present invention relates to a thin film transistor array substrate capable of not demanding an increase in the number of masks when a light blocking layer is formed, and preventing that operation of a gate line affects a light blocking layer and a channel; and a method for manufacturing the same. According to the present invention, the thin film transistor array substrate comprises: an active layer including multiple channel regions at a distance away from each other in the center, and an impurity injecting region, excluding channel regions on a substrate; a buffer layer and a light blocking layer formed in a width corresponding to the active layer in an interlayer between the active layer and the substrate; a gate line crossing the active layer, and having a gate electrode in the region having an overlap with the channel region; a data line crossing the gate line and defining a pixel region; a first electrode integrated with the data line, whose lateral surface is connected with an impurity injecting region of one end of the active layer, and in contact with a horizontal plane of the buffer layer; and a second electrode whose lateral surface is connected with the impurity injecting region of the other end of the active layer, and connected with the light blocking layer.

Description

[0001] The present invention relates to a thin film transistor array substrate and a manufacturing method thereof,

The present invention relates to a display device, and more particularly, to a thin film transistor array substrate and a method of manufacturing the thin film transistor array substrate, in which driving of a gate line is prevented from affecting a light blocking layer and a channel, .

As the information society develops, the demand for display devices is increasing in various forms. Various display devices such as LCD (Liquid Crystal Display Device), PDP (Plasma Display Panel), ELD (Electro Luminescent Display) and VFD (Vacuum Fluorescent Display) have been studied in response to this, .

The display device includes a thin film transistor array substrate including a thin film transistor which is a switching element formed in each pixel region. The thin film transistor is formed in each pixel region defined by intersecting gate lines and data lines, and forms an active layer, a gate insulating film, a gate electrode, a source electrode, and a drain electrode forming a channel region.

Particularly, when light is incident on the active layer channel region, there is a problem that the light leakage current is increased and deterioration of image quality such as flicker occurs. To solve this problem, a structure for forming a light blocking layer so as to completely overlap with the active layer has been proposed. In this case, there is a burden due to mask increase.

It is an object of the present invention to provide a thin film transistor array substrate which does not require an increase in the number of masks due to the formation of a light blocking layer and prevents the driving of a gate line from affecting a light blocking layer and a channel, It has a purpose to provide a method.

In order to achieve the above object, the thin film transistor array substrate of the present invention includes: an active layer having a plurality of channel regions spaced apart from each other at a center and having an impurity implantation region in regions except for channel regions; A buffer layer and a light blocking layer formed between the substrates and having a width corresponding to the active layer; a gate line crossing the active layer and having a gate electrode overlapping with the channel region; A first electrode connected to the impurity injection region at one end of the active layer and in contact with a horizontal plane of the buffer layer, the first electrode being integrated with the data line; And a second electrode connected to the light-impurity-doped region of the other end of the active layer and connected to the light-blocking layer.

The first electrode is in contact with the upper surface of the horizontal plane of the buffer layer, the thickness of which is partially removed, and the second electrode is in contact with the side of the buffer layer from which the entire thickness is removed.

The pixel electrode may further include a pixel electrode connected to an upper portion of the second electrode and formed in the pixel region. In this case, the voltage applied to the pixel electrode is transferred to the second electrode.

On the other hand, the light blocking layer, the buffer layer, and the active layer are preferably integrated.

The gate insulating film is formed between the gate line and the first and second electrodes, and the first and second electrodes are formed between the gate line and the first and second electrodes. A protective layer may be further formed between the layer of the pixel electrode and the layer of the pixel electrode.

The first electrode is in contact with the horizontal surface of the buffer layer through the first contact hole where the impurity injection region of the one end of the first interlayer insulating film, the gate insulating film and the active layer is removed, and the second electrode contacts the first interlayer insulating film, An insulating layer, a gate insulating layer, an active layer, and a second contact hole from which the buffer layer is removed. Here, the pixel electrode may be connected to the second electrode through a third contact hole formed in the protective film.

The display device may further include a common electrode that is insulated from the pixel electrode and has an opening in the second electrode portion.

On the other hand, the active layer is formed in a "U" shape between both ends, and may have first and second channel regions overlapping with the gate lines on the inner side of both ends and spaced from each other.

A method of manufacturing a thin film transistor array substrate according to the present invention includes the steps of forming a light blocking layer, a buffer layer, and an active layer on a substrate using a first mask; A second step of forming a gate line in a direction across the active layer so as to have a gate electrode at a portion overlapping the active layer, A step of forming a first interlayer insulating film on the entire surface of the gate insulating film including the gate line, a third step of forming a second interlayer insulating film on the gate insulating film, A gate insulating film, an active layer, a buffer layer, and a light-shielding portion by using a third mask having a light- By selectively removing, in the fifth step of forming the semi-light transmitting portion and a first contact hole in each region corresponding to the transmissive portion, the second contact hole; And a sixth step of forming a first electrode and a second electrode which are laterally connected to the active layer in the first contact hole and the second contact hole through a fourth mask and a fourth mask, respectively.

After the fifth step, an upper portion of the buffer layer is removed from the first contact hole, and the buffer layer is completely removed from the second contact hole to expose the light blocking layer.

After the third step, using the gate line as a mask, a seventh step of implanting impurities into the region of the active layer not covered by the gate line may be further included.

Forming a second interlayer insulating film on the first interlayer insulating film including the first and second electrodes after the sixth step; forming a second interlayer insulating film on the second interlayer insulating film, Forming a protective film on the second interlayer insulating film including the common electrode and selectively removing the protective film and the second interlayer insulating film to form a third contact hole, (10); And forming a pixel electrode connected to the second electrode through the third contact hole and branched into a plurality of pixel regions.

The third step may include a step of applying a photoresist film on the first interlayer insulating film, a step of placing the third mask on the photoresist film, and a step of exposing and developing the photoresist film using a third mask Forming a first photoresist pattern by removing a total thickness of the photoresist layer with respect to the opening and leaving a thickness of the photoresist layer with respect to the transflective portion and leaving a total thickness of the photoresist layer with respect to the light- Forming a second contact hole by removing the first interlayer insulating film, the gate insulating film, the active layer, and the buffer layer of the exposed portion corresponding to the transmissive portion using the first photoresist pattern; Forming a second photoresist pattern by ashing the first photoresist pattern so as to remove a thickness of the remaining photoresist layer; And forming the first contact hole by removing the first interlayer insulating film, the gate insulating film, and the active layer from the exposed portion using the second photoresist pattern.

The above-described thin film transistor array substrate of the present invention and its manufacturing method have the following effects.

First, a light blocking layer and an active layer may be formed by one mask, thereby reducing the number of masks and improving the yield of products.

Second, in the process of reducing the number of masks, even if the layer between the side of the light blocking layer and the gate line becomes thin, a certain pixel voltage is applied to the light blocking layer by connecting one side of the light blocking layer to the pixel electrode.

1 is a plan view showing a thin film transistor array substrate according to the present invention;
Fig. 2 is a cross-sectional view taken along line I-I '
FIG. 3 is a plan view showing the thin film transistor forming region of FIG.
Fig. 4 is a cross-sectional view taken along the line II-II '
FIGS. 5A to 5F are cross-sectional views showing a method of manufacturing a thin film transistor substrate according to the present invention
6A and 6B are cross-sectional views showing the difference in effect between the active layer connection structures of the first and second electrodes in a structure having a light blocking layer, a buffer layer, and an active layer integrally

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a plan view of a thin film transistor array substrate according to the present invention, and FIG. 2 is a cross-sectional view taken along line I-I 'of FIG.

As shown in FIGS. 1 and 2, the thin film transistor array substrate includes a substrate 100, a plurality of channel regions 114ch spaced apart from each other at a center, an impurity implantation region 114d (114a, A buffer layer 113B and a light blocking layer 112A formed in a width corresponding to the active layer 114B are formed between the active layer 114B and the substrate and between the active layer 114B and the substrate, A gate line 102 which traverses the active layer 114B and has a gate electrode at an overlapping portion with the channel region 114ch, a data line 104 which intersects the gate line and defines a pixel region, A first electrode 124S integrated with the data line 104 and laterally connected to the impurity injection region 114a at one end of the active layer 114B and in contact with the horizontal plane of the buffer layer 113B; And a second electrode 124D connected to the light-impurity-doped region 114b at the other end of the active layer and connected to the light-blocking layer 112A.

The second electrode 124D is connected to the second electrode 124D, and the pixel electrode 122 is further divided into a plurality of pixel electrodes.

A common electrode 136 having an opening portion 134 corresponding to the portion of the second electrode 124D is formed between the pixel electrode 122 and the first and second electrodes 124S and 124D . In this case, the common electrode 136 is formed on a plate except for the opening 136, and the electrode on the substrate 100 and the pixel electrode 134 formed over the pixel electrode 134 overlap with each other. When a voltage is applied to the lines, a fringe field is formed. For example, when a thin film transistor array is used for a liquid crystal panel, an opposing substrate having a color filter array facing the thin film transistor array substrate having the structure described above, and a liquid crystal layer between the thin film transistor array substrate and the counter substrate In this case, the liquid crystal is driven according to the fringe field and used for display.

In some cases, the vertical relationship between the common electrode 136 and the pixel electrode 134 can be reversed.

Since the light blocking layer 112A, the buffer layer 113B, and the active layer 114B formed in this order on the substrate 100 are integrally formed at one time by using the same mask, they are integrally formed and formed into substantially the same width do.

When the light blocking layer 112A, the buffer layer 113B and the active layer 114B are integrally formed as a unit 1100, they are subjected to a dry etching process using the same mask to form a constant taper so that the lower width of the integrated unit 1100 Make it longer than the width of the top. As a result, the light blocking layer 112A on the lower side of the integral type 1100 is approximately longer than the active layer 114B on the upper side, and the light blocking layer 112A is formed such that the light coming from the lower side thereof, It is possible to effectively prevent the light from being transmitted to the light emitting element 114B.

A gate insulating film 116 is interposed between the integrated light blocking layer 112A, the buffer layer 113B and the active layer 114B and between the gate line 102 and the gate line 102, A first interlayer insulating film 118 is formed between the two electrodes 124S and 124D.

On the other hand, the active layer 114B is formed in a "U" shape between both ends, and both ends are formed by increasing the width for connection with the first and second electrodes. And has first and second channel regions 114ch which are overlapped with the gate line 102 on the inner side of both ends and are spaced apart from each other. The remaining region of the active layer 114B which is not overlapped with the gate line 102 is an impurity implantation region 114d into which an impurity is implanted. The impurity implantation region 114d includes one end 114a and the other end 114b of the active layer and a region 114c between the first and second channel regions 114ch.

The buffer layer 113B and the light blocking layer 112A on the lower side of the active layer 114B are formed integrally with the active layer 114B so that the active layer 114B is formed into a U- .

In some cases, the number of the channel regions may be three or more, and the number of the channel regions depends on the number of the gate lines 102 overlapping the active layer 114B. Even when three or more channel regions are provided in the active layer 114B, an impurity implantation region may be further provided between the channels.

On the other hand, in the above-described embodiment, the impurity implantation region is defined by using the gate line 102 as a mask, and the portions that do not overlap with the gate line 102 may all be objects of the impurity implantation region.

A second interlayer insulating layer 151 is formed between the first and second electrodes 124S and 124D and the common electrode 136. The second interlayer insulating layer 151 is formed between the common electrode 136 and the pixel electrode 122, A protective film 152 is further formed between the layers.

The first electrode 124S includes a first contact hole 218A in which the impurity injection region 114a at one end of the first interlayer insulating layer 118, the gate insulating layer 116, and the active layer 114B is removed. And the second electrode 124D is in contact with the horizontal surface of the buffer layer 113B through the first interlayer insulating film 118, the gate insulating film 116, the impurity injection region 114b at the other end of the active layer 114B, And is connected to the light blocking layer 112A through the second contact hole 218B from which the buffer layer 113B is removed.

The first electrode 124S contacts the upper portion of the horizontal surface of the buffer layer 113B partially removed through the first contact hole 218A and the second electrode 124D contacts the buffer layer 113B, (113B).

The first electrode 124S and the second electrode 124D are a source electrode integrated with or protruded from the data line 104 in the embodiment of the present invention and a drain electrode connected to the pixel electrode. In some cases, the names of the source electrode and the drain electrode may be reversely referred to. However, in the embodiment of the present invention, the side to which the data voltage is applied is referred to as a source and the side having an electrical connection to the pixel electrode is referred to as a drain. In either case, the connection between the electrode (the above-described second electrode) on the side having the electrical connection with the pixel electrode and the active layer is a side contact, and the buffer layer 113B is removed to the full thickness, And the second electrode 124D having a direct connection relationship with the pixel electrode 112A is electrically connected to the pixel electrode again.

The pixel electrode 122 may be connected to the second electrode 124D through the third contact hole 120 defined by removing the protective layer 152 and the second interlayer insulating layer 151. [

Here, the pixel electrode 122 is connected to the second electrode 124D through a third contact hole 120, and the second electrode 124D is connected to the light-blocking layer 124D through the second contact hole 218B. (112A). Therefore, even if a light blocking layer, a buffer layer, and a thin gate insulating film are formed between the active layer and the gate wiring, the light blocking layer 112A can be prevented from being in a constant voltage state And does not have the element variability due to the voltage being applied to the gate line on the gate insulating film.

The light blocking layer 112A is preferably a light shielding metal. The light blocking layer 112A is formed of a light shielding material to prevent light transmitted from the lower portion to the substrate 100 from being transmitted to the active layer 114B, , And after the connection through the third contact hole 120, the light blocking layer 112A is held by the voltage applied to the pixel electrode 122. [

On the other hand, the gate line 102 and the data line 104 intersect each other with the interlayer insulating film 118 therebetween to define respective pixel regions. The gate line 102 supplies the scan signal to the gate electrode of the thin film transistor in each pixel region and the data line 104 supplies the data signal to the first electrode 124S of the thin film transistor in each pixel region.

More specifically, the pixel electrode 122 is formed on the protective film 152 of each pixel region provided at the intersection of the gate line 102 and the data line 104. The pixel electrode 122 includes a first horizontal portion 122A connected to the second electrode 124D exposed through the third contact hole 120 and a second horizontal portion 122B connected to the first horizontal portion 122A and the gate line 102 A second horizontal portion 122B formed in parallel and a branched pixel portion 122C connected between the first and second horizontal portions 122A and 122B.

The common electrode 136 is formed to have an opening 134 that is larger in area than the third contact hole 120 in a region overlapping the third contact hole 120. This common electrode 136 is formed on the second interlayer insulating film 151 in the remaining region except for the opening portion 134. Accordingly, the common electrode 136 is integrated with the common electrode 136 of the adjacent pixel region without a separate common line, and is a plate except for the opening portion 134 described above. Therefore, the same common voltage is applied to the entire common electrode 136, and the common electrode 136 overlaps the pixel electrode 122 with the protective film 152 in each pixel region to form a fringe field. Accordingly, the common electrode 124 to which the common voltage is supplied forms the fringe field with the pixel electrode 122 to which the video signal is supplied through the thin film transistor, and the liquid crystal molecules Are rotated by dielectric anisotropy. The transmittance of light passing through the pixel region is changed according to the degree of rotation of the liquid crystal molecules, thereby realizing the gradation.

The thin film transistor causes the data signal of the data line 104 to be charged and held in the pixel electrode 122 in response to the scan signal of the gate line 102. To this end, the thin film transistor includes a gate electrode (included in the gate line), a first electrode 124S (source electrode), a second electrode 124D (drain electrode), and an active layer 114B.

Hereinafter, the specific structure of the thin film transistor in the embodiment of the present invention will be described with reference to the drawings.

FIG. 3 is a plan view showing a formation region of the thin film transistor of FIG. 1, and FIG. 4 is a sectional view taken along the line II-II 'of FIG.

As shown in FIGS. 3 and 4, in the thin film transistor array substrate of the present invention, the thin film transistor includes a plurality of channel regions 114ch spaced apart from each other at a center, and impurity implantation regions 114d: 114a and 114b A gate line 102 having a gate electrode at an overlapping portion with the channel region 114ch and extending across the active layer 114B; A first electrode 124S that is connected to the impurity injection region 114a at one end of the active layer 114B and is laterally connected to the horizontal plane of the buffer layer 113B and is integrated with the data line 104 defining the pixel region, ; And a second electrode 124D connected to the light-impurity-doped region 114b at the other end of the active layer and connected to the light-blocking layer 112A.

As described above, the buffer layer 113B is formed in contact with the lower portion of the active layer 114B, and the light blocking layer 112A is formed under the buffer layer in an integrated form 1100. [

The gate electrode is defined in the gate line 102 at the overlapping portion with the active layer 114B. Since the width of the gate electrode is relatively thicker than that of the data line 104 in a display device such as a liquid crystal panel, In the structure in which the gate line 102 is a fine line, the width of the gate line 102 can be increased corresponding to the gate electrode at the thin film transistor forming portion.

In the drawing, both the active layer 114B and the first electrode 124S are formed by protruding to both sides of the width of the data line 104 to increase the width.

The portions of the gate line 102 overlapping the first channel region 114A and the second channel region 114B of the active layer 114B are defined as the first and second gate electrodes 106A and 106B. In this case, the first and second gate electrodes 106A and 106B are formed in series on the active layer 114B, and between the source region 114a and the drain region 114b, the first and second channel regions 114A, and 114B are formed. As a result, the entire length of the channel regions 114A and 114B of the thin film transistor becomes longer, so that the first electrode 124S connected to the source region 114a and the drain electrode 124D connected to the drain region 114b . Accordingly, the off current can be lowered when the thin film transistor having a plurality of gate electrodes (i.e., a plurality of channel regions) is turned off.

The active layer 114B forms a channel between the first electrode 124S and the second electrode 124D connected at both ends of the active layer 114B. The active layer 114B is formed in the shape of a "U" character or a reverse "U" character, and the buffer layer 113B and the light blocking layer 112A under the active layer 114B are also formed in a shape corresponding to the active layer 114B. The active layer 114B in the drawing may be divided into first and second channel regions 114ch and an impurity implantation region 114d and the first electrode 124S connected to the data line 104 of the impurity implantation region at both ends The impurity injection region 114a at one end connected to the source region 114a is defined as the source region 114a for convenience and the impurity injection region 114b at the other end is defined as the drain region 114b. In addition, the impurity injection region 114c between the first and second channel regions 114ch can act as a resistor between the first and second gate electrodes 106A and 106B0 formed in series.

The impurity implantation regions 114d, 114a, 114b, and 114c are formed in regions except for the first and second channel regions 114ch, and n-type or p-type impurities are implanted.

The buffer layer 113B is formed as a single layer or a multilayer structure of silicon oxide (SiOx) or silicon nitride (SiNx, SiONx) on a substrate 100 formed of a plastic resin such as glass or polyimide (PI). The buffer layer 113B serves to prevent the diffusion of moisture or impurities generated in the substrate 100 or to control the transfer rate of heat during crystallization, thereby allowing the active layer 114B to be crystallized well. The buffer layer 113B is formed to cover the light blocking layer 112A and is formed to have a thickness of 0.1 mu m to several mu m to obtain the diffraction effect and the transmittance improving effect of the light blocking layer 112A.

The light blocking layer 112A is formed of a light-shielding metal such as Mo, Ti, Al, Cu, Cr, Co, W, Ta, In particular, the light shielding pattern 112A is preferably formed of a material having good heat resistance to withstand a high-temperature thermal process applied when forming a plurality of thin films to be formed on the upper portion.

Hereinafter, a method of manufacturing the thin film transistor array substrate of the present invention will be described with reference to the drawings.

5A to 5F are cross-sectional views illustrating a method of manufacturing a thin film transistor array substrate according to the present invention.

First, as shown in FIG. 5A, a light blocking metal 112, a buffer material 113, and a semiconductor material 114 are entirely deposited on a substrate 100.

The semiconductor material 114, the buffer material 113, and the light-blocking metal 112 are left with substantially equal widths in a planar manner using the first mask, as shown in FIG. 5B, The active layer 114A, the buffer layer 113A, and the light blocking layer 112A are formed.

In the first mask 1000, an opening is defined in the remaining portion of the light-shielding portion on the U-shaped portion where the integrated body 1100 is left, and a photoresist (not shown) is coated on the semiconductor material 114 The first mask 1000 exposes and develops the photoresist to form a photoresist pattern. The photoresist pattern is etched on the substrate including the photoresist pattern to form the integrated structure 1100.

In the etching process, the active layer 114A closest to the etchant or the etching gas is in proximity to the integrated type 1100, and the integrated type 1100 has a constant taper and a trapezoidal shape whose cross section is wider than the upper surface.

Here, the active layer 114A, the buffer layer 113A, and the light blocking layer 112A are defined as an exposure and development process using a single mask. Conventionally, a separate mask is applied to each of the light blocking layer and the active layer 114A There is an advantage of reducing the number of masks versus structure.

5C, a gate insulating layer 116 is formed on the entire surface of the substrate 100 including the light blocking layer 112A, the buffer layer 113A, and the active layer 114A.

Next, in the second mask 1010, the gate line 102 is formed in a direction across the active layer 114A so as to have a gate electrode at a portion overlapping with the active layer 114A. Here, the second mask 1010 is a phenomenon in which a portion corresponding to the gate line 102 formed in one direction is defined as a light-shielding portion, and the remaining portion is defined as an opening portion.

After the gate line 102 is formed, n-type or p-type impurities are implanted using the gate line 102 as a mask to define the impurity injection region 114d. Here, the portion of the active layer 114A covered by the gate line 102 becomes the channel region 114ch, and the region of the active layer 114A exposed from the gate line 102 becomes the impurity injection region 114d .

As shown in FIG. 5D, a first interlayer insulating film 118 is formed on the entire surface of the gate insulating film 116 including the gate line 102.

After the photoresist layer is completely coated on the first interlayer insulating layer 118, the photoresist layer is exposed and developed using a third mask 1020 to form a first photoresist layer pattern 150.

Here, the third mask 1020 includes a transflective portion HF corresponding to a part of one end of both ends of the active layer 114A not covered by the gate line 102, and a transmissive portion O And the light shielding portion S corresponding to the remaining area. Therefore, the third mask 1020 is a kind of halftone mask or diffraction mask, and the portion of the photosensitive film corresponding to the light-shielding portion S during the exposure and development using the third mask 1020 remains the applied thickness , The portion of the photoresist corresponding to the transflective portion HF remains a certain thickness, and the photoresist corresponding to the transmissive portion O is entirely removed.

First, the exposed first interlayer insulating film 118, the gate insulating film 116, the active layer 114A, and the buffer layer 113A under the exposed first interlayer insulating film 118 are selectively formed by using the first photoresist pattern 150 as a mask. And a second contact hole 118B is formed in a region corresponding to the transmissive portion (O). In this process, the buffer layer 113A is removed to the thickness of the second contact hole 118B, and the lower light blocking layer 112A is exposed.

5E, the first photoresist pattern 150 may be ashed so as to remove a part of the remaining thickness of the first photoresist pattern 150 corresponding to the transflective portion HF, (150a).

Subsequently, the first interlayer insulating film 118, the gate insulating film 116 and the active layer 114A under the exposed portion are removed using the second photoresist pattern 150a to form first contact holes 118A ). In this case, in the case of the first contact hole 118A, the buffer layer 113B is excessively deflected in the process of removing the active layer 114A, so that a part of the thickness of the upper portion can be removed together.

After the etching using the third mask 1020, the first interlayer insulating film 118 having the first and second contact holes 118a and 118b, the gate insulating film 116, the active layer 114B, , And a buffer layer 113B remain.

 The first electrode 124S and the second electrode 124B which are laterally connected to the active layer 114B in the first contact hole 118A and the second contact hole 118B through the fourth mask 1030, Thereby forming the electrode 124D.

Here, the light shielding portion is defined as a width larger than the width of the transmissive portion and the transflective portion of the third mask 1020 of the fourth mask 1030, and the transmissive portion of the remaining region.

Next, referring to FIGS. 1 and 2, a second interlayer insulating film 151 is formed on the first interlayer insulating film 118 including the first and second electrodes 124S and 124D.

Next, a common electrode 136 having a portion corresponding to the second electrode 124D as an opening portion 134 is formed on the second interlayer insulating film 151. Next, as shown in FIG.

Next, a protective film 152 is formed on the second interlayer insulating film 151 including the common electrode 136. Next, the protective film 152 and the second interlayer insulating film 151 are selectively removed to form a third contact hole 120. [

A pixel electrode part 122C connected to the second electrode 124D through the third contact hole 120 and branched into a plurality of pixels in the pixel area; A pixel electrode 122 including horizontal portions 122A and 122B for connecting electrodes of the electrode portion 122C is formed. The first horizontal part 122A is connected to the second electrode 124D through a third contact hole 120 and the second horizontal part 122B is partially overlapped with a part of the width of the gate line , A storage capacitor is defined in the overlapping area.

On the other hand, the effect obtained by the difference in the connection structure between the active layer and the light blocking layer in the first and second electrodes of the present invention will be described.

6A and 6B are cross-sectional views showing the difference in effect between the active layer connection structures of the first and second electrodes in a structure having a light blocking layer, a buffer layer, and an active layer integrally.

Conventionally, in a structure having a light blocking layer, a buffer layer is provided between the light blocking layer and the active layer, and the light blocking layer and the active layer are patterned using separate masks to separate the formation regions.

6A, a method of patterning the light blocking layer 12 and the active layer 14 by using the same mask is proposed. In this case, the metallic light blocking layer 12 and the active layer 14 Are formed by interposing the buffer layer 13 between the layers without directly contacting them. Therefore, the metal material of the light blocking layer 12 prevents the active layer 14 from being directly affected by the channel region.

On the other hand, when the light blocking layer 12, the buffer layer 13, and the active layer 14 having the three-layered structure of three-layer structure are formed as one mask 1000 on the substrate 10 in order to reduce the mask, And the second electrodes 7 and 8 can be brought into contact with the upper portion of the active layer 14 in the same shape or side contact as shown in the drawing.

In this case, in the conventional structure in which the light blocking layer and the active layer are separately patterned, since the buffer layer is formed on the entire surface of the substrate 10, the light blocking layer 12 is formed so as to be substantially adjacent to the gate line 5 at the side of the light blocking layer 12 have. This is because only the gate insulating film 16 remains between the side of the light blocking layer 12 and the gate line 5. Particularly, the thickness of the buffer layer 13 is about 3000 Å, and the thickness between the gate line 5 and the light blocking layer 12 is about 4300 Å to 1300 Å. It is a sudden decrease.

Particularly, when a current flows in accordance with channel formation when a signal is applied to the gate line and the data line, the light blocking layer 12 under the second electrode 8 connected to the pixel electrode is blocked by the signal of the gate line 5 An electric field is generated, and such an electric field again affects the channel, resulting in variation of the element of the thin film transistor, and the element stability is deteriorated.

Accordingly, in the thin film transistor array substrate of the present invention, the advantage of reducing the mask by forming the light blocking layer, the buffer layer, and the active layer as one body is maintained while the first and second electrodes 124S and 124D The second contact hole 118B between the second electrode 124D and the active layer 114B is formed to such an extent that the light blocking layer 112A is exposed when the active layer 114B is connected, And the active layer 114B.

In this case, the first electrode 124S is in contact with the upper surface of the buffer layer 113B under the active layer 114B, and maintains the side connection with the active layer 114B. The upper surface of the buffer layer 113B is overexposed when the active layer 114B is removed and the upper surface of the buffer layer 113B is exposed through the first contact hole 118A exposed to the upper surface of the buffer layer 113B. The one electrode 124S contacts the buffer layer 113B.

The first and second contact holes 118A and 118B have different shapes and can be defined together as a mask using a diffraction mask or a halftone mask as described above.

Thus, the second electrode 124D connected to the pixel electrode and the light blocking layer 112A under the second electrode 124D are directly in contact with each other, the pixel voltage is applied to the light blocking layer 112A, The element stability can be achieved with respect to the structure in which a fluid electric field is formed by the application of the signal of the gate line.

The gate line 102, which is not illustrated in FIG. 6B, has first and second gate electrodes 106A and 106B integrally formed in an area overlapping the active layer 114B, and the first and second gate electrodes A channel is formed in the active layer 114B superimposed on the gate electrodes 106A, 106B.

Unexplained reference numerals 116 and 118 denote a gate insulating film and a first interlayer insulating film, respectively.

While the present invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Will be apparent to those of ordinary skill in the art.

100: substrate 114B: active layer
114a, 114b, 114c: impurity injection region 114ch: channel region
112A: light blocking layer 113A: buffer layer
102: gate line 106A, 106B: gate electrode
104: Data line 116: Gate insulating film
118: first interlayer insulating film 151: second interlayer insulating film
152: protective film 122: pixel electrode
136: common electrode 134: opening
124S: first electrode 124D: second electrode
218A: first contact hole 218B: second contact hole
120: Third contact hole 1100: Integrated three-layer structure

Claims (15)

An active layer having on the substrate a plurality of channel regions spaced apart from each other in the center, and having an impurity implantation region in an area excluding the channel regions;
A buffer layer and a light blocking layer formed between the active layer and the substrate and having a width corresponding to the active layer;
A gate line crossing the active layer and having a gate electrode overlapping the channel region;
A data line crossing the gate line and defining a pixel region;
A first electrode that is integrated with the data line and is connected to the impurity injection region at one end of the active layer and is in contact with the horizontal surface of the buffer layer; And
And a second electrode connected to the impurity injection region of the other end of the active layer and connected to the light blocking layer. The method according to claim 1,
Wherein the first electrode is in contact with an upper portion of a horizontal plane of the buffer layer, the thickness of which is partially removed, and the second electrode is in contact with a side of the buffer layer from which a thickness is completely removed. The method according to claim 1,
And a pixel electrode formed on the pixel region, the pixel electrode being connected to an upper portion of the second electrode. The method of claim 3,
And a voltage applied to the pixel electrode is transferred to the second electrode. The method of claim 3,
Wherein the light blocking layer, the buffer layer, and the active layer are integrated. 6. The method of claim 5,
A buffer layer, an active layer, and a gate insulating film interposed between the gate line and the light-
A first interlayer insulating film is formed between the gate line and the first and second electrodes,
Wherein a protective film is further formed between the layers of the first and second electrodes and the layer of the pixel electrode. The method according to claim 6,
The first electrode is in contact with the horizontal surface of the buffer layer through the first contact hole where the first interlayer insulating film, the gate insulating film, and the impurity injection region of one end of the active layer are removed,
Wherein the second electrode is connected to the light blocking layer through the first interlayer insulating film, the gate insulating film, the impurity injection region at the other end of the active layer, and the second contact hole from which the buffer layer is removed. 8. The method of claim 7,
Wherein the pixel electrode is connected to the second electrode through a third contact hole formed in the passivation layer. The method of claim 3,
Further comprising a common electrode which is insulated from the pixel electrode and has an opening at a portion of the second electrode. The method according to claim 1,
The active layer is "U " shaped between both ends,
Wherein the first and second channel regions overlap with the gate line on the inner side of both ends and are spaced apart from each other. A first step of forming, on a substrate, a light blocking layer, a buffer layer, and an active layer as a first mask;
A second step of forming a gate insulating film on the entire surface of the substrate including the light blocking layer, the buffer layer, and the active layer;
A third step of forming a gate line in a direction across the active layer so as to have a gate electrode at a portion overlapping the active layer with a second mask;
A fourth step of forming a first interlayer insulating film on the entire surface of the gate insulating film including the gate line;
And a third mask having a transflective portion corresponding to one end of the active layer and a light shielding portion corresponding to the other end of the active layer not covered by the gate line and corresponding to the other end of the active layer, A fifth step of selectively removing the active layer and the buffer layer to form a first contact hole and a second contact hole in regions corresponding to the transflective portion and the transmissive portion, respectively; And
And a sixth step of forming a first electrode and a second electrode which are laterally connected to the active layer in the first contact hole and the second contact hole through a fourth mask. Gt; 12. The method of claim 11,
The method of manufacturing a thin film transistor array substrate according to claim 1, wherein after the fifth step, an upper portion of the buffer layer is removed from the first contact hole, and the buffer layer is completely removed from the second contact hole, . 12. The method of claim 11,
Further comprising a seventh step of, after the third step, implanting an impurity into a region of the active layer not covered with the gate line by using the gate line as a mask. 12. The method of claim 11,
An eighth step of forming a second interlayer insulating film on the first interlayer insulating film including the first and second electrodes after the sixth step;
Forming a common electrode having a portion corresponding to the second electrode as an opening on the second interlayer insulating film;
A tenth step of forming a third contact hole by selectively removing the protective film and the second interlayer insulating film after forming a protective film on the second interlayer insulating film including the common electrode; And
And forming a pixel electrode connected to the second electrode through the third contact hole and branched into a plurality of pixel regions. 12. The method of claim 11,
In the fifth step,
Applying a photosensitive film on the first interlayer insulating film;
Placing the third mask over the photoresist layer;
The photoresist film is exposed and developed by using a third mask to remove the entire thickness of the photoresist film with respect to the opening and to leave a part of the thickness of the photoresist film with respect to the transflector, Forming a first photoresist pattern leaving a thickness;
Forming a second contact hole by removing the first interlayer insulating film, the gate insulating film, the active layer, and the buffer layer of the exposed portion corresponding to the transmissive portion using the first photosensitive film pattern;
Forming a second photoresist pattern by ashing the first photoresist pattern to such an extent that a part of the remaining photoresist layer corresponding to the transflective portion is removed; And
And forming a first contact hole by removing the first interlayer insulating film, the gate insulating film, and the active layer from the exposed portion using the second photoresist pattern.

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