TWI623086B - Nonvolatile memory elements having conductive paths of semimetals or semiconductors - Google Patents
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Abstract
在不同的阻抗狀態之間可程式化的一記憶體元件可包含一第一電極層,其包括一半金屬或半導體(半金屬/半導體);一第二電極;以及形成在該第一與第二電極之間並且包括一絕緣材料的一開關層;其中該半金屬/半導體的原子藉由施加電場而對於該絕緣材料的傳導性提供可逆的改變。 A memory device that can be programmed between different impedance states can include a first electrode layer including half of a metal or semiconductor (semimetal/semiconductor); a second electrode; and formed in the first and second Between the electrodes and including a switching layer of insulating material; wherein the semi-metal/semiconductor atoms provide a reversible change in the conductivity of the insulating material by application of an electric field.
Description
本申請案係主張2013年3月15日申請的美國專利臨時甲請案案號 61/798,918之權益,該案之內容併入本案作為參考。 This application claims the US Patent Temporary A Case Number filed on March 15, 2013. 61/798, 918, the content of the case is incorporated into the case for reference.
本申請案之揭示內容係關於記憶體元件,更特別地,係關於在二或多個阻抗狀態之間可程式化的記憶體元件,以響應電場的施加。 The disclosure of the present application relates to memory elements, and more particularly to memory elements that are programmable between two or more impedance states in response to application of an electric field.
需要不需使用電力而長時間儲存資訊。例如,在許多電子裝置與系統中,資料可被儲存在非揮發記憶體或是準非揮發記憶體中。準非揮發記憶體可為具有較動態隨機存取記憶體(DRAM)更長的「更新」間隔程度之記憶體。 Need to store information for a long time without using electricity. For example, in many electronic devices and systems, data can be stored in non-volatile memory or quasi-non-volatile memory. Quasi-non-volatile memory can be a memory with a longer "update" interval than dynamic random access memory (DRAM).
一種記憶體形式係為傳導橋接隨機存取記憶體(CBRAM)。CBRAM可具有記憶體元件,其儲存關於兩個終端結構之阻抗程度的資訊,該兩個終端結構可包含金屬/絕緣體/金屬結構。阻抗的改變可來自於傳導路徑的產生與破壞,該傳導路徑主要或者較常見是全部由金屬原子所製成。One form of memory is Conductive Bridged Random Access Memory (CBRAM). The CBRAM can have a memory component that stores information about the degree of impedance of the two termination structures, which can comprise a metal/insulator/metal structure. The change in impedance can result from the creation and destruction of a conduction path that is primarily or more commonly made entirely of metal atoms.
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根據實施例,記憶體元件可包含使用半導體或半金屬(包含類金屬,metalloid)之記憶體胞元,以形成通過可程式化層的傳導路徑。 在一些實施例中,記憶體元件可具有如習知傳導橋接隨機存取記憶體(CBRAM)元件的結構,然而,傳導路徑的產生與破壞可不包含金屬原子,或是傳導路徑的大部分可由非金屬原子形成。半金屬或半導體可形成全部或部分的傳導路徑。 相較於習知以金屬為基礎的CBRAM胞元,由半金屬或半導體所形成的傳導路徑可需要更多原子存在於該傳導路徑中,以達到較低的阻抗程度,使得此傳導路徑較不會受到導通狀態留滯失敗(亦即,從低阻抗至高阻抗之不想要的自發過渡)的影響。 此外,關於產生給定「寬度」(例如,1、2或3原子)之傳導路徑的可程式化操作,以半金屬或半導體為基礎的傳導路徑可具有阻抗實質高於基於金屬(例如,具有1原子狹縮部的鉍(Bi)路徑係為~100kW vs.以1原子狹縮部的銅(Cu)路徑係為~10kW)的可比較路徑之阻抗。相較於習知CBRAM胞元,此可造成對於程式化與/或抹除之較低電流與/或電力需求。 雖然一些習知的CBRAM元件可藉由電性導入金屬原子至位於兩電極之間的絕緣層中而獲得其低阻抗,但金屬氧化物常被使用作為絕緣層,並且低阻抗狀態通常被說為已經自金屬氧化物一些區域移除氧之後從仍有之金屬原子的存在產生。例如,鈦(Ti)原子可在氧(O)已經自氧化鈦(TiO2 )層被移除之後仍存留。因此,在此兩例中,該低阻抗狀態可被歸因為金屬原子的存在。明顯對比下,根據本申請案的實施例,低阻抗狀態(或是低阻抗狀態的重要部分)可被歸因為半金屬與/或半導體原子的存在而非金屬原子。 根據特定實施例,記憶體胞元可包含第一電極(其可為陰極)、第二電極(其可為陽極),以及散布二者之間的絕緣層。該陽極可包含一或多半金屬(例如,Bi)與/或一或多半導體(例如,Si)。此半金屬或半導體亦可包含以下任何一者:在自己可能的結晶相至少其中之一的半金屬或半導體元素(例如,具有高壓金屬形式以及帶寬為0.3 eV之低壓半導體形式的Te);可在還原至奈米等級或原子等級尺寸後可成為半金屬或半導體的元素;或是包含一或多個此元素的合金或其他化合物(例如,TiTex )。 陽極可作為在絕緣層(亦即,至少一部分由半金屬或半導體所形成的傳導路徑)中可形成一或多個傳導路徑的那些原子的來源。其他傳導層可存在於陽極的頂部或是陰極之下,以輔助用於控制該胞元的電路之製造或操作(例如,以降低到該胞元之連接的阻抗)。 在該兩個電極之間可使用電脈衝,以使該半金屬或半導體形成傳導路徑。可使用不同程度或極性的電脈衝瓦解此傳導路徑,以將該裝置回復至高阻抗狀態。初始「形成」電脈衝可被施加至所製造的裝置,以將該半金屬或半導體原子導入絕緣層中,後續程式或抹除操作造成該半金屬或半導體原子分別重新排列於低阻抗或高阻抗路徑中。 此外,可用該裝置的每一個程式/抹除循環,而將該半金屬或半導體導入與移除自該絕緣層移除。 除此之外,或另一種方式,該半金屬或半導體原子可藉由初始熱或化學處理替代電脈衝以及程式/抹除電脈衝(用以將該原子重新排列以分別形成低-高阻抗路徑)而被導入該絕緣層中。 此外,當該絕緣層形成時,該半金屬或半導體可被原位(in situ)導入該絕緣層中。 實施例可包含如同習知CBRAM裝置(包含RRAM裝置)之記憶體裝置架構,但包含本申請案所描述的記憶體元件。因此,實施例之記憶體裝置可具有少於習知裝置的程式化電力供應電壓與/或期間。相較於習知的記憶體裝置,實施例的記憶體裝置可具有較大的磨損循環(wear cycle),或是在「恢復」形式操作之間較長的時間期間。恢復形式操作可為將元件重新程式化為特定狀態的操作(例如,緊縮阻抗分布、將所有胞元抹除/程式化為相同狀態之後,程式化該胞元)。實施例的記憶體裝置可具有磨損運算,其在資料於不同記憶體塊之間偏移前允許更多循環數量或類似者。 在本申請案的實施例中,相似區段係由相同的元件符號表示,但前導數字對應於圖式。 第1圖係為根據實施例說明記憶體元件100之側橫切面圖式。記憶體胞元可包含一第一電極104、一開關層106以及一第二電極108。在一些實施例中,一第一電極104可包含一或多個半金屬或半導體。例如,此半金屬與/或半導體可包含碳(C)、碲(Te)、銻(Sb)、砷(As)、鍺(Ge)、矽(Si)、鉍(Bi)、錫(Sn)、硫(S)、硒(Se)中的任何一者。 一開關層106可形成於第一與第二電極104/108之間。形成開關層106的材料可藉由通過電極施加的電場而切換其傳導性。根據實施例,開關層106可為絕緣材料,其中可藉由施加電場而形成與不形成傳導路徑。可從半金屬與/或半導體形成至少部分之此傳導路徑。在一些實施例中,開關層106可初始不具由陽極104作為該半金屬/半導體的來源之路徑形成半金屬/半導體。然而,在其他實施例中,開關層106可包含貢獻額外半金屬/半導體量之陽極104的一些半金屬/半導體。在其他實施例中,開關層106可包含以陽極104無貢獻或貢獻非常少之其半金屬/半導體於開關層106中傳導路徑形成之半金屬/半導體。 在一些實施例中,開關層106可為金屬氧化物。在特定實施例中,開關層106可包含氧化釓(GdOx)、氧化鉿(HfOx)、氧化鉭(TaOx)、氧化鋁(AlOx)與/或氧化鋅(ZnOx)中任何一者。可理解此金屬氧化物可具有化學計量或非化學計量形式。 在特定實施例中,第一電極104可包含半金屬/半導體以及一或多個其他元素。在特定實施例中,第一電極104可為半金屬/半導體與另一元素的二元合金。用於結合該半金屬/半導體之該第一電極104的金屬可為過渡金屬。在一些實施例中,此金屬可為稀土金屬。然而,在其他實施例中,此金屬可不為過渡金屬(因此也不為稀土金屬)。 在特定實施例中,第一電極可為鋯(Zr)的合金作為金屬,以及Te作為半金屬/半導體。再者,開關層106可為ZrOx。 在一些實施例中,開關層的氧化物可為第一電極所包含的元素之氧化物。在非常特定實施例中,該開關層可包含金屬氧化物,以及該第一陽極可包含該金屬氧化物的金屬。 第二電極108可為適合所欲之阻抗或程序相容性等之傳導材料。 第2A圖至第2C圖係為根據實施例說明以半金屬/半導體形成傳導區域之側橫切面圖式。在非常特定實施例中,第2A圖至第2C圖可為第1圖所示實施方式之一。 第2A圖說明在絕緣開關層206中的半金屬/半導體210。在特定實施例中,210可代表半金屬/半導體元素的原子。 第2B圖說明通過第一極性的電極204/208施加電場。可在該絕緣體材料206中形成傳導結構,改變該絕緣體材料206的傳導性作為響應。此傳導結構可完全由一或多個半金屬/半導體原子形成,或是包含半金屬/半導體原子與其他原子種類的混合物。 第2C圖係說明通過第二極性的電極204/208施加電場。可移除傳導結構作為響應。 可理解第2A圖至第2C圖只是操作之圖式說明。半金屬/半導體的實際位置或狀態可為各種形式。在一些實施例中,部分或全部的傳導結構可不移動,但施加電場可改變半金屬/半導體原子與/或化合物的狀態。 第3A圖至第3D圖係為根據另一實施例說明在記憶體元件內形成傳導區域之側橫切面圖式。第3A圖至第3D圖的實施例說明配置,其中半金屬/半導體可源自於電極304(例如,陽極),並且移動至開關層306中。在非常特定實施例中,第3A圖至第3D圖係為第1圖所示實施方式之一。 第3A圖說明在施加電場之前的記憶體元件。在該開關層306中不存在或存在很少之可在該開關層內形成傳導結構之該半金屬/半導體。 第3B圖說明通過第一極性的電極304/308施加電場。半金屬/半導體310可從該第一電極304(亦即,陽極)移出至該開關層306作為響應。如上述範例,310可代表半金屬/半導體原子,但在其他實施例中,半金屬/半導體可為超過一種原子的化合物。 第3C圖係說明持續施加第3B圖的電場,或是後續施加相同電場。響應該電場,源自第一電極304的該半金屬/半導體310可在絕緣體材料306中形成傳導結構。此傳導結構可完全由一或多種半金屬/半導體原子形成,或是包含半金屬/半導體原子與其他原子種類的混合。 第3D圖係說明通過第二極性的電極304/308施加電場。可移除傳導結構作為響應。在一些實施例中,實質上全部或大部分的半金屬/半導體310可返回至第一電極304,或是遷移至靠近該第一電極304附近。然而,在其他實施例中,源自該第一電極304的該半金屬/半導體310的部分可留存在該開關層中。 可理解第2A圖至第3D圖僅係為操作的圖式代表。半金屬/半導體原子與/或化合物的實際位置或狀態可為各種形式。 第4圖係為根據一非常特定實施例說明記憶體胞元的側橫切面圖。第一電極404可包含層404-0,其係為金屬與半金屬/半導體的混合。層404-0可直接接觸開關層406。在一特定實施例中,層404-0可包含金屬鈦(Ti),以及該半金屬/半導體可為Te(亦即,層404-0係為Ti/Te化合物)。 參閱第4圖,第一電極404可包含在層404-0上的另一傳導層404-0。在一特定實施例中,層404-1可為氮化鈦(TiN)。 在所示的實施例中,開關層406可為金屬氧化物。該絕緣材料406可形成在第二電極408上。 第5A圖至第5C圖係為根據實施例說明產生記憶體元件500之方法。第5A圖至第5C圖說明方法,其中「形成」步驟可用以將半金屬/半導體置入開關層中。 第5A圖係說明「新鮮的」記憶體元件500。新鮮的記憶體元件500可為就在實體處理步驟之後的記憶體元件。亦即,該記憶體元件500尚未受到施加的電偏壓(electrical biases)。在該開關層506中有很少或不存在可在該開關層中形成傳導結構的半金屬/半導體。 第5B圖係說明「形成」步驟。可通過第一極性的電極504/508施加偏壓。半金屬/半導體510可從該第一電極504移出至該開關層506作為響應。如本申請案所示的其他實施例,510可代表半金屬/半導體原子,但在其他實施例,半金屬/半導體可為超過一種原子的化合物。 第5C圖係說明在該形成步驟之後的記憶體元件500。半金屬/半導體510可分布在絕緣開關層506內。 在一些實施例中,元件500之後可被程式化,如第2A圖至第2C圖所示。 第6A圖與第6B圖係為根據另一實施例說明產生記憶體元件500的方法。第6A圖與第6B圖係說明方法,其中製造步驟將半金屬/半導體放入開關層中。 第6A圖係說明用於記憶體元件600的合併步驟。在此步驟之前,可形成記憶體元件的第一電極604,其包含半金屬/半導體用於形成通過絕緣該開關層606的傳導路徑。記憶體元件600可受到製程處理,其造成半金屬/半導體610從該第一電極604(例如,陽極)移出,並且進入該開關層606。此製程處理可包含熱處理、化學處理或光處理。如本申請案所示之其他實施例,610可代表半金屬/半導體原子,但在其他實施例中,半金屬/半導體可為超過一種原子的化合物。 第6B圖係說明在該處理步驟之後的記憶體元件600。半金屬/半導體610可分布在絕緣開關層606內。 在一些實施例中,元件600而後可被程式化,如第2A圖至第2C圖所示。 第7A圖至第7C圖係為根據另一實施例說明產生記憶體元件700的方法。第7A圖至第7C圖說明方法,其中可在開關層內原位(in situ )形成半金屬/半導體。 第7A圖係說明第二電極708的形成。 第7B圖係說明開關層706的形成,其包含半金屬/半導體710。 第7C圖係說明第一電極704的形成。半金屬/半導體710可分布在絕緣開關層706內。 在一些實施例中,元件700而後可被程式化,如第2A圖至第2C圖所示。 注意,雖然實施例說明具有特定垂直定向的層,但是其他實施例可具有不同的定向。只是作為一範例,可在可形成傳導結構之含有該半金屬與/或半導體的層上,形成絕緣材料。再者,其他實施例可具有側向配置,在可形成傳導結構之包含該半金屬與/或半導體的層之間具有垂直定向的絕緣層。 應理解在本申請案中「一實施例」或「實施例」係指連結該實施例所描述的特定特點、結構或特徵係包含在本發明的至少一實施例中。因此,強調且應理解在申請案說明書中的不同部分所述之「實施例」或「一實施例」或「另一實施例」並非必須皆指相同的實施例。再者,特定的特點、結構或特徵可被結合而適用於本發明的一或多個實施例中。 亦理解本發明的其他實施例可於未特別揭示之缺少元件/步驟中實施。 同樣地,應理解在本發明實施例之前述說明中,有時將本發明的不同特點群組在單一實施例、圖式或其說明中,用於簡化揭示內容而有助於理解本發明一或多個方面。然而,此揭示方法並非被解釋為相較於每一個申請專利範圍所主張的內容,該申請專利範圍需要更多特徵的意圖。而是,本發明方面係小於單一前揭實施例的所有特徵。因此,在實施方式之後的申請專利範圍清楚併入此詳細說明中,每一個申請專利範圍係依據本發明的個別實施例。According to an embodiment, the memory component can comprise a memory cell using a semiconductor or semi-metal (including metalloid) to form a conductive path through the programmable layer. In some embodiments, the memory component can have a structure such as a conventional conductive bridged random access memory (CBRAM) device. However, the generation and destruction of the conduction path may not include metal atoms, or most of the conduction path may be non- Metal atoms are formed. The semi-metal or semiconductor can form all or part of the conduction path. Compared to conventional metal-based CBRAM cells, a conductive path formed by a semimetal or semiconductor may require more atoms to be present in the conduction path to achieve a lower impedance level, making this conduction path less It is subject to the failure of the conduction state to fail (ie, an unwanted spontaneous transition from low impedance to high impedance). Furthermore, with respect to a programmable operation that produces a conductive path of a given "width" (eg, 1, 2, or 3 atoms), a semi-metal or semiconductor-based conduction path may have an impedance substantially higher than that based on metal (eg, having The 铋 (Bi) path of the 1 atomic narrowing is the impedance of the comparable path of ~100 kW vs. the copper (Cu) path of the 1 atomic narrow section is ~10 kW). This can result in lower current and/or power requirements for stylization and/or erasing than conventional CBRAM cells. Although some conventional CBRAM devices can obtain their low impedance by electrically introducing metal atoms into an insulating layer between the electrodes, metal oxides are often used as an insulating layer, and a low-impedance state is generally referred to as It has been produced from the presence of still existing metal atoms after removal of oxygen from some areas of the metal oxide. For example, titanium (Ti) atoms may remain after oxygen (O) has been removed from the titanium oxide (TiO 2 ) layer. Thus, in both cases, this low impedance state can be attributed to the presence of a metal atom. In sharp contrast, in accordance with embodiments of the present application, a low impedance state (or an important portion of a low impedance state) can be attributed to the presence of a semi-metal and/or semiconductor atom rather than a metal atom. According to a particular embodiment, the memory cell may comprise a first electrode (which may be a cathode), a second electrode (which may be an anode), and an insulating layer interspersed therebetween. The anode can comprise one or more semi-metals (eg, Bi) and/or one or more semiconductors (eg, Si). The semimetal or semiconductor may also comprise any one of: a semimetal or a semiconductor element in at least one of its possible crystalline phases (eg, Te in the form of a high voltage metal and a low voltage semiconductor having a bandwidth of 0.3 eV); after reduction to atomic level or nano size level can be a semi-metal or a semiconductor element; or comprises one or more alloys, or other compounds (e.g., TiTe x) of this element. The anode can serve as a source of those atoms that can form one or more conductive paths in the insulating layer (i.e., at least a portion of the conductive path formed by the semimetal or semiconductor). Other conductive layers may be present at the top of the anode or below the cathode to aid in the fabrication or operation of circuitry for controlling the cell (e.g., to reduce the impedance to the connection of the cell). Electrical pulses can be used between the two electrodes to cause the semi-metal or semiconductor to form a conductive path. This conductive path can be disrupted using electrical pulses of varying degrees or polarities to return the device to a high impedance state. An initial "forming" electrical pulse can be applied to the fabricated device to direct the semi-metal or semiconductor atom into the insulating layer, and subsequent programming or erasing operations cause the semi-metal or semiconductor atom to be rearranged to a low impedance or a high impedance, respectively. In the path. In addition, each of the program/erase cycles of the device can be used to remove and remove the semi-metal or semiconductor from the insulating layer. In addition or in the alternative, the semi-metal or semiconductor atom may be replaced by an initial thermal or chemical process to replace the electrical pulse and to program/erase the electrical pulse (to rearrange the atoms to form a low-high impedance path, respectively). It is introduced into the insulating layer. Further, when the insulating layer is formed, the semimetal or semiconductor may be introduced into the insulating layer in situ. Embodiments may include a memory device architecture like a conventional CBRAM device (including RRAM devices), but including the memory elements described herein. Thus, the memory device of an embodiment can have less than a programmed power supply voltage and/or period of a conventional device. The memory device of the embodiment may have a larger wear cycle or a longer period of time between "recovery" mode operations than conventional memory devices. A recovery form operation can be an operation that reprograms a component to a particular state (eg, compacting the impedance distribution, programrating the cell after erasing/staging all cells to the same state). The memory device of an embodiment can have a wear operation that allows for more cycles or the like before the data is shifted between different memory blocks. In the embodiments of the present application, similar sections are denoted by the same element symbols, but the leading numbers correspond to the drawings. 1 is a side cross-sectional view of a memory device 100 in accordance with an embodiment. The memory cell can include a first electrode 104, a switching layer 106, and a second electrode 108. In some embodiments, a first electrode 104 can comprise one or more semi-metals or semiconductors. For example, the semimetal and/or semiconductor may comprise carbon (C), tellurium (Te), antimony (Sb), arsenic (As), germanium (Ge), antimony (Si), antimony (Bi), tin (Sn). Any one of sulfur (S) and selenium (Se). A switching layer 106 can be formed between the first and second electrodes 104/108. The material forming the switching layer 106 can be switched in conductivity by an electric field applied through the electrodes. According to an embodiment, the switching layer 106 can be an insulating material in which a conductive path can be formed and not formed by application of an electric field. At least a portion of this conduction path can be formed from the semimetal and/or semiconductor. In some embodiments, the switching layer 106 may initially form a semi-metal/semiconductor from the path of the anode 104 as the source of the semi-metal/semiconductor. However, in other embodiments, the switching layer 106 can include some semi-metal/semiconductor that contributes an additional semi-metal/semiconductor amount of the anode 104. In other embodiments, the switching layer 106 can comprise a semi-metal/semiconductor formed by the conductive path of the semi-metal/semiconductor in the switching layer 106 that does not contribute or contribute very little to the anode 104. In some embodiments, the switch layer 106 can be a metal oxide. In a particular embodiment, the switching layer 106 can comprise any one of yttrium oxide (GdOx), hafnium oxide (HfOx), tantalum oxide (TaOx), aluminum oxide (AlOx), and/or zinc oxide (ZnOx). It will be appreciated that the metal oxide can be in stoichiometric or non-stoichiometric form. In a particular embodiment, the first electrode 104 can comprise a semi-metal/semiconductor and one or more other elements. In a particular embodiment, the first electrode 104 can be a binary alloy of a semi-metal/semiconductor with another element. The metal used to bond the first electrode 104 of the semimetal/semiconductor may be a transition metal. In some embodiments, the metal can be a rare earth metal. However, in other embodiments, the metal may not be a transition metal (and therefore not a rare earth metal). In a particular embodiment, the first electrode can be a zirconium (Zr) alloy as the metal, and Te as the semimetal/semiconductor. Furthermore, the switching layer 106 can be ZrOx. In some embodiments, the oxide of the switching layer can be an oxide of an element included in the first electrode. In a very specific embodiment, the switching layer can comprise a metal oxide, and the first anode can comprise a metal of the metal oxide. The second electrode 108 can be a conductive material suitable for the desired impedance or program compatibility. 2A to 2C are side cross-sectional views illustrating the formation of a conductive region by a semimetal/semiconductor according to an embodiment. In a very specific embodiment, Figures 2A through 2C may be one of the embodiments shown in Figure 1. FIG. 2A illustrates the semimetal/semiconductor 210 in the insulating switch layer 206. In a particular embodiment, 210 can represent an atom of a semi-metal/semiconductor element. Figure 2B illustrates the application of an electric field through electrodes 204/208 of a first polarity. A conductive structure can be formed in the insulator material 206 in response to changing the conductivity of the insulator material 206. The conductive structure may be formed entirely of one or more semi-metal/semiconductor atoms or a mixture of semi-metal/semiconductor atoms and other atomic species. Figure 2C illustrates the application of an electric field through electrodes 204/208 of the second polarity. The conductive structure can be removed in response. It can be understood that Figures 2A through 2C are only schematic illustrations of the operation. The actual location or state of the semi-metal/semiconductor can take a variety of forms. In some embodiments, some or all of the conductive structure may not move, but applying an electric field may change the state of the semi-metal/semiconductor atoms and/or compounds. 3A through 3D are side cross-sectional views illustrating the formation of a conductive region within a memory device in accordance with another embodiment. The embodiments of FIGS. 3A-3D illustrate configurations in which a semi-metal/semiconductor can be derived from electrode 304 (eg, an anode) and moved into switch layer 306. In a very specific embodiment, Figures 3A through 3D are one of the embodiments shown in Figure 1. Figure 3A illustrates the memory element prior to application of the electric field. There are no or very few semi-metals/semiconductors in the switching layer 306 that can form a conductive structure within the switching layer. Figure 3B illustrates the application of an electric field through electrodes 304/308 of a first polarity. The semi-metal/semiconductor 310 can be removed from the first electrode 304 (ie, the anode) to the switch layer 306 in response. As in the above examples, 310 may represent a semi-metal/semiconductor atom, but in other embodiments, the semi-metal/semiconductor may be a compound of more than one atom. Figure 3C illustrates the application of the electric field of Figure 3B continuously or the subsequent application of the same electric field. In response to the electric field, the semi-metal/semiconductor 310 from the first electrode 304 can form a conductive structure in the insulator material 306. The conductive structure may be formed entirely of one or more semi-metal/semiconductor atoms or may comprise a mixture of semi-metal/semiconductor atoms and other atomic species. Figure 3D illustrates the application of an electric field through electrodes 304/308 of the second polarity. The conductive structure can be removed in response. In some embodiments, substantially all or a majority of the semi-metal/semiconductor 310 can be returned to the first electrode 304 or migrated near the first electrode 304. However, in other embodiments, portions of the semi-metal/semiconductor 310 originating from the first electrode 304 may remain in the switching layer. It can be understood that Figures 2A through 3D are merely representative of the operation of the drawings. The actual location or state of the semi-metal/semiconductor atoms and/or compounds can be in a variety of forms. Figure 4 is a side cross-sectional view of a memory cell in accordance with a very specific embodiment. The first electrode 404 can comprise a layer 404-0 which is a mixture of metal and semi-metal/semiconductor. Layer 404-0 can directly contact switch layer 406. In a particular embodiment, layer 404-0 can comprise metallic titanium (Ti), and the semimetal/semiconductor can be Te (ie, layer 404-0 is a Ti/Te compound). Referring to FIG. 4, the first electrode 404 can include another conductive layer 404-0 on layer 404-0. In a particular embodiment, layer 404-1 can be titanium nitride (TiN). In the illustrated embodiment, the switch layer 406 can be a metal oxide. The insulating material 406 can be formed on the second electrode 408. 5A through 5C are diagrams illustrating a method of generating a memory element 500 in accordance with an embodiment. Figures 5A through 5C illustrate a method in which a "forming" step can be used to place a semi-metal/semiconductor into the switch layer. Figure 5A illustrates a "fresh" memory component 500. The fresh memory component 500 can be a memory component just after the physical processing step. That is, the memory element 500 has not been subjected to an applied electrical biases. There is little or no semi-metal/semiconductor in the switching layer 506 that can form a conductive structure in the switching layer. Figure 5B illustrates the "forming" step. A bias voltage can be applied through the electrodes 504/508 of the first polarity. The semi-metal/semiconductor 510 can be removed from the first electrode 504 to the switching layer 506 in response. As with other embodiments shown in this application, 510 can represent a semi-metal/semiconductor atom, but in other embodiments, the semi-metal/semiconductor can be a compound of more than one atom. Figure 5C illustrates the memory element 500 after this forming step. The semi-metal/semiconductor 510 can be distributed within the insulating switch layer 506. In some embodiments, component 500 can be programmed later, as shown in Figures 2A through 2C. 6A and 6B are diagrams illustrating a method of generating a memory element 500 in accordance with another embodiment. Figures 6A and 6B illustrate a method in which a fabrication step places a semi-metal/semiconductor into the switch layer. Figure 6A illustrates the steps of combining for memory element 600. Prior to this step, a first electrode 604 of the memory element can be formed that includes a semi-metal/semiconductor for forming a conductive path by insulating the switching layer 606. The memory element 600 can be subjected to a process process that causes the semi-metal/semiconductor 610 to be removed from the first electrode 604 (eg, the anode) and into the switch layer 606. This process can include heat treatment, chemical treatment, or light treatment. As with other embodiments shown in this application, 610 can represent a semi-metal/semiconductor atom, but in other embodiments, the semi-metal/semiconductor can be a compound of more than one atom. Figure 6B illustrates the memory element 600 after this processing step. The semi-metal/semiconductor 610 can be distributed within the insulating switch layer 606. In some embodiments, component 600 can then be programmed, as shown in Figures 2A through 2C. 7A through 7C are diagrams illustrating a method of generating a memory element 700 in accordance with another embodiment. Figures 7A through 7C illustrate a method in which a semi-metal/semiconductor can be formed in situ in the switching layer. FIG. 7A illustrates the formation of the second electrode 708. FIG. 7B illustrates the formation of a switch layer 706 that includes a semi-metal/semiconductor 710. Figure 7C illustrates the formation of the first electrode 704. The semi-metal/semiconductor 710 can be distributed within the insulating switch layer 706. In some embodiments, component 700 can then be programmed, as shown in Figures 2A through 2C. Note that while the embodiments illustrate layers having a particular vertical orientation, other embodiments may have different orientations. As an example, an insulating material may be formed on a layer containing the semimetal and/or semiconductor that can form a conductive structure. Furthermore, other embodiments may have a lateral configuration with a vertically oriented insulating layer between the layers comprising the semi-metal and/or semiconductor that may form a conductive structure. It is to be understood that the phrase "one embodiment" or "an embodiment" in this application means that the particular features, structures, or characteristics described in connection with the embodiments are included in at least one embodiment of the invention. Therefore, it is to be understood that the "embodiment" or "an embodiment" or "an embodiment" or "an embodiment" or "an embodiment" Furthermore, the particular features, structures, or characteristics may be combined and applied to one or more embodiments of the invention. It is also understood that other embodiments of the invention may be practiced in the absence of elements/steps that are not specifically disclosed. Similarly, it is to be understood that in the foregoing description of the embodiments of the present invention, the various features of the invention may be used in a single embodiment, the drawings or the description thereof Or multiple aspects. However, this method of disclosure is not to be construed as a limitation of the scope of the claims. Rather, the aspects of the invention are less than all features of a single pre-exposed embodiment. Therefore, the scope of the claims after the embodiments are clearly incorporated in this detailed description, each of which is in accordance with the individual embodiments of the invention.
100、200、300、400、500、600、700‧‧‧記憶體元件
104、108、204、208、304、308、404、408、504、508、604、608、704、708‧‧‧電極
106、206、306、406、506、606、706‧‧‧開關層
210、310、510、610、710‧‧‧半金屬/半導體
404-0、404-1‧‧‧層100, 200, 300, 400, 500, 600, 700‧‧‧ memory components
104, 108, 204, 208, 304, 308, 404, 408, 504, 508, 604, 608, 704, 708 ‧ ‧ electrodes
106, 206, 306, 406, 506, 606, 706‧‧ ‧ switch layer
210, 310, 510, 610, 710‧‧‧ Semi-Metal/Semiconductor
404-0, 404-1‧‧ layer
第1圖係為根據實施例說明記憶體元件之橫切面概示圖。 第2A圖至第2C圖係為根據實施例說明在記憶體元件的開關層內傳導區域的形成之側橫切面概示圖。 第3A圖至第3D圖係為根據另一實施例說明記憶體元件之開關層內傳導區域的形成之側橫切面概示圖。 第4圖係為根據另一實施例說明記憶體元件之側橫切面概示圖。 第5A圖至第5C圖係為根據另一實施例說明記憶體元件形成的側橫切面概示圖。 第6A圖與第6B圖係為根據另一實施例說明記憶體元件形成之側橫切面概示圖。 第7A圖至第7C圖係為根據再另一實施例說明記憶體元件形成之側橫切面概示圖。Fig. 1 is a schematic cross-sectional view showing a memory element according to an embodiment. 2A to 2C are schematic views showing a side cross-sectional view of formation of a conductive region in a switching layer of a memory element, according to an embodiment. 3A through 3D are schematic cross-sectional views showing the formation of a conductive region in a switching layer of a memory device in accordance with another embodiment. Figure 4 is a schematic illustration of a side cross-section of a memory device in accordance with another embodiment. 5A through 5C are schematic cross-sectional views showing the formation of a memory element in accordance with another embodiment. 6A and 6B are schematic cross-sectional views showing the formation of a memory element in accordance with another embodiment. 7A through 7C are schematic cross-sectional views showing the formation of a memory element according to still another embodiment.
Claims (27)
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