TWI623086B - Nonvolatile memory elements having conductive paths of semimetals or semiconductors - Google Patents

Abstract

A memory device that can be programmed between different impedance states can include a first electrode layer including half of a metal or semiconductor (semimetal/semiconductor); a second electrode; and formed in the first and second Between the electrodes and including a switching layer of insulating material; wherein the semi-metal/semiconductor atoms provide a reversible change in the conductivity of the insulating material by application of an electric field.

Description

Non-volatile memory component with semi-metal or semiconductor conductive path Cross-references for related applications

This application claims the US Patent Temporary A Case Number filed on March 15, 2013. 61/798, 918, the content of the case is incorporated into the case for reference.

The disclosure of the present application relates to memory elements, and more particularly to memory elements that are programmable between two or more impedance states in response to application of an electric field.

Need to store information for a long time without using electricity. For example, in many electronic devices and systems, data can be stored in non-volatile memory or quasi-non-volatile memory. Quasi-non-volatile memory can be a memory with a longer "update" interval than dynamic random access memory (DRAM).

One form of memory is Conductive Bridged Random Access Memory (CBRAM). The CBRAM can have a memory component that stores information about the degree of impedance of the two termination structures, which can comprise a metal/insulator/metal structure. The change in impedance can result from the creation and destruction of a conduction path that is primarily or more commonly made entirely of metal atoms.

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According to an embodiment, the memory component can comprise a memory cell using a semiconductor or semi-metal (including metalloid) to form a conductive path through the programmable layer. In some embodiments, the memory component can have a structure such as a conventional conductive bridged random access memory (CBRAM) device. However, the generation and destruction of the conduction path may not include metal atoms, or most of the conduction path may be non- Metal atoms are formed. The semi-metal or semiconductor can form all or part of the conduction path. Compared to conventional metal-based CBRAM cells, a conductive path formed by a semimetal or semiconductor may require more atoms to be present in the conduction path to achieve a lower impedance level, making this conduction path less It is subject to the failure of the conduction state to fail (ie, an unwanted spontaneous transition from low impedance to high impedance). Furthermore, with respect to a programmable operation that produces a conductive path of a given "width" (eg, 1, 2, or 3 atoms), a semi-metal or semiconductor-based conduction path may have an impedance substantially higher than that based on metal (eg, having The 铋 (Bi) path of the 1 atomic narrowing is the impedance of the comparable path of ~100 kW vs. the copper (Cu) path of the 1 atomic narrow section is ~10 kW). This can result in lower current and/or power requirements for stylization and/or erasing than conventional CBRAM cells. Although some conventional CBRAM devices can obtain their low impedance by electrically introducing metal atoms into an insulating layer between the electrodes, metal oxides are often used as an insulating layer, and a low-impedance state is generally referred to as It has been produced from the presence of still existing metal atoms after removal of oxygen from some areas of the metal oxide. For example, titanium (Ti) atoms may remain after oxygen (O) has been removed from the titanium oxide (TiO ₂ ) layer. Thus, in both cases, this low impedance state can be attributed to the presence of a metal atom. In sharp contrast, in accordance with embodiments of the present application, a low impedance state (or an important portion of a low impedance state) can be attributed to the presence of a semi-metal and/or semiconductor atom rather than a metal atom. According to a particular embodiment, the memory cell may comprise a first electrode (which may be a cathode), a second electrode (which may be an anode), and an insulating layer interspersed therebetween. The anode can comprise one or more semi-metals (eg, Bi) and/or one or more semiconductors (eg, Si). The semimetal or semiconductor may also comprise any one of: a semimetal or a semiconductor element in at least one of its possible crystalline phases (eg, Te in the form of a high voltage metal and a low voltage semiconductor having a bandwidth of 0.3 eV); after reduction to atomic level or nano size level can be a semi-metal or a semiconductor element; or comprises one or more alloys, or other compounds (e.g., TiTe _x) of this element. The anode can serve as a source of those atoms that can form one or more conductive paths in the insulating layer (i.e., at least a portion of the conductive path formed by the semimetal or semiconductor). Other conductive layers may be present at the top of the anode or below the cathode to aid in the fabrication or operation of circuitry for controlling the cell (e.g., to reduce the impedance to the connection of the cell). Electrical pulses can be used between the two electrodes to cause the semi-metal or semiconductor to form a conductive path. This conductive path can be disrupted using electrical pulses of varying degrees or polarities to return the device to a high impedance state. An initial "forming" electrical pulse can be applied to the fabricated device to direct the semi-metal or semiconductor atom into the insulating layer, and subsequent programming or erasing operations cause the semi-metal or semiconductor atom to be rearranged to a low impedance or a high impedance, respectively. In the path. In addition, each of the program/erase cycles of the device can be used to remove and remove the semi-metal or semiconductor from the insulating layer. In addition or in the alternative, the semi-metal or semiconductor atom may be replaced by an initial thermal or chemical process to replace the electrical pulse and to program/erase the electrical pulse (to rearrange the atoms to form a low-high impedance path, respectively). It is introduced into the insulating layer. Further, when the insulating layer is formed, the semimetal or semiconductor may be introduced into the insulating layer in situ. Embodiments may include a memory device architecture like a conventional CBRAM device (including RRAM devices), but including the memory elements described herein. Thus, the memory device of an embodiment can have less than a programmed power supply voltage and/or period of a conventional device. The memory device of the embodiment may have a larger wear cycle or a longer period of time between "recovery" mode operations than conventional memory devices. A recovery form operation can be an operation that reprograms a component to a particular state (eg, compacting the impedance distribution, programrating the cell after erasing/staging all cells to the same state). The memory device of an embodiment can have a wear operation that allows for more cycles or the like before the data is shifted between different memory blocks. In the embodiments of the present application, similar sections are denoted by the same element symbols, but the leading numbers correspond to the drawings. 1 is a side cross-sectional view of a memory device 100 in accordance with an embodiment. The memory cell can include a first electrode 104, a switching layer 106, and a second electrode 108. In some embodiments, a first electrode 104 can comprise one or more semi-metals or semiconductors. For example, the semimetal and/or semiconductor may comprise carbon (C), tellurium (Te), antimony (Sb), arsenic (As), germanium (Ge), antimony (Si), antimony (Bi), tin (Sn). Any one of sulfur (S) and selenium (Se). A switching layer 106 can be formed between the first and second electrodes 104/108. The material forming the switching layer 106 can be switched in conductivity by an electric field applied through the electrodes. According to an embodiment, the switching layer 106 can be an insulating material in which a conductive path can be formed and not formed by application of an electric field. At least a portion of this conduction path can be formed from the semimetal and/or semiconductor. In some embodiments, the switching layer 106 may initially form a semi-metal/semiconductor from the path of the anode 104 as the source of the semi-metal/semiconductor. However, in other embodiments, the switching layer 106 can include some semi-metal/semiconductor that contributes an additional semi-metal/semiconductor amount of the anode 104. In other embodiments, the switching layer 106 can comprise a semi-metal/semiconductor formed by the conductive path of the semi-metal/semiconductor in the switching layer 106 that does not contribute or contribute very little to the anode 104. In some embodiments, the switch layer 106 can be a metal oxide. In a particular embodiment, the switching layer 106 can comprise any one of yttrium oxide (GdOx), hafnium oxide (HfOx), tantalum oxide (TaOx), aluminum oxide (AlOx), and/or zinc oxide (ZnOx). It will be appreciated that the metal oxide can be in stoichiometric or non-stoichiometric form. In a particular embodiment, the first electrode 104 can comprise a semi-metal/semiconductor and one or more other elements. In a particular embodiment, the first electrode 104 can be a binary alloy of a semi-metal/semiconductor with another element. The metal used to bond the first electrode 104 of the semimetal/semiconductor may be a transition metal. In some embodiments, the metal can be a rare earth metal. However, in other embodiments, the metal may not be a transition metal (and therefore not a rare earth metal). In a particular embodiment, the first electrode can be a zirconium (Zr) alloy as the metal, and Te as the semimetal/semiconductor. Furthermore, the switching layer 106 can be ZrOx. In some embodiments, the oxide of the switching layer can be an oxide of an element included in the first electrode. In a very specific embodiment, the switching layer can comprise a metal oxide, and the first anode can comprise a metal of the metal oxide. The second electrode 108 can be a conductive material suitable for the desired impedance or program compatibility. 2A to 2C are side cross-sectional views illustrating the formation of a conductive region by a semimetal/semiconductor according to an embodiment. In a very specific embodiment, Figures 2A through 2C may be one of the embodiments shown in Figure 1. FIG. 2A illustrates the semimetal/semiconductor 210 in the insulating switch layer 206. In a particular embodiment, 210 can represent an atom of a semi-metal/semiconductor element. Figure 2B illustrates the application of an electric field through electrodes 204/208 of a first polarity. A conductive structure can be formed in the insulator material 206 in response to changing the conductivity of the insulator material 206. The conductive structure may be formed entirely of one or more semi-metal/semiconductor atoms or a mixture of semi-metal/semiconductor atoms and other atomic species. Figure 2C illustrates the application of an electric field through electrodes 204/208 of the second polarity. The conductive structure can be removed in response. It can be understood that Figures 2A through 2C are only schematic illustrations of the operation. The actual location or state of the semi-metal/semiconductor can take a variety of forms. In some embodiments, some or all of the conductive structure may not move, but applying an electric field may change the state of the semi-metal/semiconductor atoms and/or compounds. 3A through 3D are side cross-sectional views illustrating the formation of a conductive region within a memory device in accordance with another embodiment. The embodiments of FIGS. 3A-3D illustrate configurations in which a semi-metal/semiconductor can be derived from electrode 304 (eg, an anode) and moved into switch layer 306. In a very specific embodiment, Figures 3A through 3D are one of the embodiments shown in Figure 1. Figure 3A illustrates the memory element prior to application of the electric field. There are no or very few semi-metals/semiconductors in the switching layer 306 that can form a conductive structure within the switching layer. Figure 3B illustrates the application of an electric field through electrodes 304/308 of a first polarity. The semi-metal/semiconductor 310 can be removed from the first electrode 304 (ie, the anode) to the switch layer 306 in response. As in the above examples, 310 may represent a semi-metal/semiconductor atom, but in other embodiments, the semi-metal/semiconductor may be a compound of more than one atom. Figure 3C illustrates the application of the electric field of Figure 3B continuously or the subsequent application of the same electric field. In response to the electric field, the semi-metal/semiconductor 310 from the first electrode 304 can form a conductive structure in the insulator material 306. The conductive structure may be formed entirely of one or more semi-metal/semiconductor atoms or may comprise a mixture of semi-metal/semiconductor atoms and other atomic species. Figure 3D illustrates the application of an electric field through electrodes 304/308 of the second polarity. The conductive structure can be removed in response. In some embodiments, substantially all or a majority of the semi-metal/semiconductor 310 can be returned to the first electrode 304 or migrated near the first electrode 304. However, in other embodiments, portions of the semi-metal/semiconductor 310 originating from the first electrode 304 may remain in the switching layer. It can be understood that Figures 2A through 3D are merely representative of the operation of the drawings. The actual location or state of the semi-metal/semiconductor atoms and/or compounds can be in a variety of forms. Figure 4 is a side cross-sectional view of a memory cell in accordance with a very specific embodiment. The first electrode 404 can comprise a layer 404-0 which is a mixture of metal and semi-metal/semiconductor. Layer 404-0 can directly contact switch layer 406. In a particular embodiment, layer 404-0 can comprise metallic titanium (Ti), and the semimetal/semiconductor can be Te (ie, layer 404-0 is a Ti/Te compound). Referring to FIG. 4, the first electrode 404 can include another conductive layer 404-0 on layer 404-0. In a particular embodiment, layer 404-1 can be titanium nitride (TiN). In the illustrated embodiment, the switch layer 406 can be a metal oxide. The insulating material 406 can be formed on the second electrode 408. 5A through 5C are diagrams illustrating a method of generating a memory element 500 in accordance with an embodiment. Figures 5A through 5C illustrate a method in which a "forming" step can be used to place a semi-metal/semiconductor into the switch layer. Figure 5A illustrates a "fresh" memory component 500. The fresh memory component 500 can be a memory component just after the physical processing step. That is, the memory element 500 has not been subjected to an applied electrical biases. There is little or no semi-metal/semiconductor in the switching layer 506 that can form a conductive structure in the switching layer. Figure 5B illustrates the "forming" step. A bias voltage can be applied through the electrodes 504/508 of the first polarity. The semi-metal/semiconductor 510 can be removed from the first electrode 504 to the switching layer 506 in response. As with other embodiments shown in this application, 510 can represent a semi-metal/semiconductor atom, but in other embodiments, the semi-metal/semiconductor can be a compound of more than one atom. Figure 5C illustrates the memory element 500 after this forming step. The semi-metal/semiconductor 510 can be distributed within the insulating switch layer 506. In some embodiments, component 500 can be programmed later, as shown in Figures 2A through 2C. 6A and 6B are diagrams illustrating a method of generating a memory element 500 in accordance with another embodiment. Figures 6A and 6B illustrate a method in which a fabrication step places a semi-metal/semiconductor into the switch layer. Figure 6A illustrates the steps of combining for memory element 600. Prior to this step, a first electrode 604 of the memory element can be formed that includes a semi-metal/semiconductor for forming a conductive path by insulating the switching layer 606. The memory element 600 can be subjected to a process process that causes the semi-metal/semiconductor 610 to be removed from the first electrode 604 (eg, the anode) and into the switch layer 606. This process can include heat treatment, chemical treatment, or light treatment. As with other embodiments shown in this application, 610 can represent a semi-metal/semiconductor atom, but in other embodiments, the semi-metal/semiconductor can be a compound of more than one atom. Figure 6B illustrates the memory element 600 after this processing step. The semi-metal/semiconductor 610 can be distributed within the insulating switch layer 606. In some embodiments, component 600 can then be programmed, as shown in Figures 2A through 2C. 7A through 7C are diagrams illustrating a method of generating a memory element 700 in accordance with another embodiment. Figures 7A through 7C illustrate a method in which a semi-metal/semiconductor can be formed in situ in the switching layer. FIG. 7A illustrates the formation of the second electrode 708. FIG. 7B illustrates the formation of a switch layer 706 that includes a semi-metal/semiconductor 710. Figure 7C illustrates the formation of the first electrode 704. The semi-metal/semiconductor 710 can be distributed within the insulating switch layer 706. In some embodiments, component 700 can then be programmed, as shown in Figures 2A through 2C. Note that while the embodiments illustrate layers having a particular vertical orientation, other embodiments may have different orientations. As an example, an insulating material may be formed on a layer containing the semimetal and/or semiconductor that can form a conductive structure. Furthermore, other embodiments may have a lateral configuration with a vertically oriented insulating layer between the layers comprising the semi-metal and/or semiconductor that may form a conductive structure. It is to be understood that the phrase "one embodiment" or "an embodiment" in this application means that the particular features, structures, or characteristics described in connection with the embodiments are included in at least one embodiment of the invention. Therefore, it is to be understood that the "embodiment" or "an embodiment" or "an embodiment" or "an embodiment" or "an embodiment" Furthermore, the particular features, structures, or characteristics may be combined and applied to one or more embodiments of the invention. It is also understood that other embodiments of the invention may be practiced in the absence of elements/steps that are not specifically disclosed. Similarly, it is to be understood that in the foregoing description of the embodiments of the present invention, the various features of the invention may be used in a single embodiment, the drawings or the description thereof Or multiple aspects. However, this method of disclosure is not to be construed as a limitation of the scope of the claims. Rather, the aspects of the invention are less than all features of a single pre-exposed embodiment. Therefore, the scope of the claims after the embodiments are clearly incorporated in this detailed description, each of which is in accordance with the individual embodiments of the invention.

100, 200, 300, 400, 500, 600, 700‧‧‧ memory components
104, 108, 204, 208, 304, 308, 404, 408, 504, 508, 604, 608, 704, 708 ‧ ‧ electrodes
106, 206, 306, 406, 506, 606, 706‧‧ ‧ switch layer
210, 310, 510, 610, 710‧‧‧ Semi-Metal/Semiconductor
404-0, 404-1‧‧ layer

Fig. 1 is a schematic cross-sectional view showing a memory element according to an embodiment. 2A to 2C are schematic views showing a side cross-sectional view of formation of a conductive region in a switching layer of a memory element, according to an embodiment. 3A through 3D are schematic cross-sectional views showing the formation of a conductive region in a switching layer of a memory device in accordance with another embodiment. Figure 4 is a schematic illustration of a side cross-section of a memory device in accordance with another embodiment. 5A through 5C are schematic cross-sectional views showing the formation of a memory element in accordance with another embodiment. 6A and 6B are schematic cross-sectional views showing the formation of a memory element in accordance with another embodiment. 7A through 7C are schematic cross-sectional views showing the formation of a memory element according to still another embodiment.

Claims (27)

A memory element programmable between different impedance states, comprising: a first electrode layer comprising a half metal or a semiconductor (semimetal/semiconductor); a second electrode; and a switching layer coupled to the first And the second electrode is in physical contact and includes an insulating material, the switching layer being configured to change an impedance across the conductive region of the insulating material by applying an electric field to cause an irreversible change in impedance of the memory device, The conductive regions comprise semi-metal/semiconductor atoms from the first electrode layer; wherein the impedance system is relatively high due to the application of a voltage associated with the first polarity of one of the first and second electrodes, and the correlation is relevant The impedance is relatively low at the application of a voltage of the second polarity of one of the first and second electrodes. The memory device according to claim 1, wherein the semimetal/semiconductor is selected from, for example, carbon (C), tellurium (Te), antimony (Sb), arsenic (As), germanium (Ge). Groups of bismuth (Si), bismuth (Bi), tin (Sn), sulfur (S), and selenium (Se). The memory device of claim 1, wherein the first electrode comprises the semimetal/semiconductor in combination with at least one first electrode metal. The memory device of claim 3, wherein the first electrode metal is a transition metal. The memory device of claim 4, wherein the first electrode metal is a rare earth metal. The memory component of claim 4, wherein: The first electrode metal is not a transition metal. The memory device of claim 1, wherein the insulating material comprises an oxide. The memory device of claim 7, wherein the oxide is a metal oxide, and the metal of the metal oxide is a transition metal. The memory device according to claim 7, wherein the oxide is a metal oxide, and the metal of the metal oxide is a rare earth metal. The memory device of claim 7, wherein the oxide is a metal oxide and the metal of the metal oxide is not a transition metal. The memory device of claim 5, wherein the insulating material is selected from the group consisting of stoichiometric or non-stoichiometric cerium oxide, cerium oxide, cerium oxide, aluminum oxide and zinc oxide. The memory device of claim 1, wherein: the first electrode comprises the semimetal/semiconductor and an electrode material; and the insulating material is a metal oxide of the electrode metal. The memory device of claim 1, wherein: the semimetal/semiconductor comprises germanium; the first electrode further comprises a metal selected from the group consisting of titanium, zirconium and hafnium; and the switch layer comprises a metal Oxide. A method of fabricating a memory component programmable between different impedance states, comprising: forming a switching layer in physical contact with a first electrode and a second electrode, the switching layer comprising an insulating material; Applying an electric field to reversibly change a conductivity of the insulating material by movement of a semimetal and/or semiconductor (semimetal/semiconductor) atom in the metal material, including applying one of the first and second electrodes An electric field of a polarity to set the switching layer to a relatively low conductivity and an electric field associated with a second polarity of one of the first and second electrodes to set the switching layer to a relatively high Conductivity. The method of claim 14, wherein the electric field of the first polarity causes the semi-metal/semiconductor atom to be removed from the first electrode. The method of claim 14, wherein the semimetal/semiconductor is selected from, for example, carbon (C), tellurium (Te), antimony (Sb), arsenic (As), germanium (Ge), germanium. A group of (Si), bismuth (Bi), tin (Sn), sulfur (S), and selenium (Se). The method of claim 14, wherein the insulating material comprises a metal oxide. The method of claim 17, wherein the insulating material is selected from the group consisting of stoichiometric or non-stoichiometric cerium oxide, cerium oxide, cerium oxide, aluminum oxide and zinc oxide. The method of claim 14, wherein the first electrode comprises the semimetal/semiconductor. The method of claim 14, wherein: the semimetal/semiconductor comprises germanium; the first electrode further comprises titanium; and the switching layer comprises a metal oxide. A method of fabricating a memory component programmable between different impedance states, comprising: forming a switch layer in physical contact with a first electrode and a second electrode, the switch layer package An insulating material and a half of a metal and/or a semiconductor (semimetal/semiconductor); and an electric field applied to reversibly change the insulating material by generating and decomposing a conductive structure in the insulating material including the atom of the semimetal/semiconductor a conductivity comprising applying an electric field associated with a first polarity of one of the first and second electrodes to set the switching layer to a relatively low conductivity, and applying an associated first and second electrode An electric field of one of the second polarities sets the switching layer to a relatively high conductivity. The method of claim 21, wherein forming the switching layer comprises forming the semimetal/semiconductor in situ with the insulating material. The method of claim 21, wherein the forming the switching layer comprises introducing the semimetal/semiconductor into the insulating material in a manufacturing step selected from a chemical processing step and a heat treatment step. The method of claim 21, wherein the semimetal/semiconductor is selected from the group consisting of strontium (Te), strontium (Sb), arsenic (As), germanium (Ge), germanium (Si), germanium ( Group of Po) and boron (B). The method of claim 21, wherein the insulating material comprises a metal oxide. The method of claim 21, wherein the semimetal/semiconductor is selected from, for example, carbon (C), tellurium (Te), antimony (Sb), arsenic (As), germanium (Ge), germanium. A group of (Si), bismuth (Bi), tin (Sn), sulfur (S), and selenium (Se). The method of claim 21, wherein: the semimetal/semiconductor comprises germanium; the first electrode further comprises titanium; and the switching layer comprises a metal oxide.