TWI623067B - Semiconductor package, semiconductor package assembly and a method for fabricating a semiconductor package - Google Patents

Semiconductor package, semiconductor package assembly and a method for fabricating a semiconductor package

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Publication number
TWI623067B
TWI623067B TW105106849A TW105106849A TWI623067B TW I623067 B TWI623067 B TW I623067B TW 105106849 A TW105106849 A TW 105106849A TW 105106849 A TW105106849 A TW 105106849A TW I623067 B TWI623067 B TW I623067B
Authority
TW
Taiwan
Prior art keywords
structure
semiconductor package
semiconductor
redistribution layer
germanium wafer
Prior art date
Application number
TW105106849A
Other languages
Chinese (zh)
Other versions
TW201635451A (en
Inventor
林子閎
彭逸軒
蕭景文
Original Assignee
聯發科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US201562134128P priority Critical
Priority to US62/134,128 priority
Priority to US14/932,147 priority
Priority to US14/932,147 priority patent/US20160079205A1/en
Application filed by 聯發科技股份有限公司 filed Critical 聯發科技股份有限公司
Publication of TW201635451A publication Critical patent/TW201635451A/en
Application granted granted Critical
Publication of TWI623067B publication Critical patent/TWI623067B/en

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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568Temporary substrate used as encapsulation process aid
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73267Layer and HDI connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Abstract

The present invention provides a semiconductor package, a semiconductor package structure, and a method of fabricating a semiconductor package. The semiconductor package structure includes: a first semiconductor package. The first semiconductor package includes: a first semiconductor germanium wafer; a first redistribution layer structure coupled to the first semiconductor germanium wafer; and a conductive pillar structure disposed away from the first redistribution layer structure On the surface of the first germanium wafer, wherein the conductive pillar structure is coupled to the first redistribution layer structure.

Description

Semiconductor package, semiconductor package structure, and method of fabricating semiconductor package

The present invention relates to a semiconductor package structure, and more particularly to a hybrid DRAM (Dynamic Random Access Memory) package structure.

The POP (Package-on-Package) structure is an integrated circuit packaging method for vertically combining discrete SOC (System-On-Chip) and memory package. A standard interface is used to mount (eg, stack) two or more packages on top of each other to route signals between the two or more packages. The POP package structure allows the device to have a higher component density, such as a mobile phone, a Personal Digital Assistant (PDA), and a digital camera.

For memory applications with enhanced integration levels, improved performance, bandwidth, latency, power, weight, and form factor, the ratio of signal pads to ground pads becomes important in improving coupling effects.

As such, an innovative semiconductor package structure is desired.

Accordingly, it is a primary object of the present invention to provide a semiconductor package, a semiconductor package structure, and a method of fabricating a semiconductor package that can improve the stability of the semiconductor package.

A semiconductor package according to at least one embodiment of the present invention includes: a first semiconductor germanium wafer; a first redistribution layer structure coupled to the first semiconductor germanium wafer; and a conductive pillar structure disposed at the first A surface of the redistribution layer structure remote from the first germanium wafer, wherein the conductive pillar structure is coupled to the first redistribution layer structure.

A semiconductor package structure according to at least one embodiment of the present invention includes: a first semiconductor package; the first semiconductor package includes: a first semiconductor germanium wafer; and a first redistribution layer structure coupled to the first a semiconductor germanium wafer; and a conductive pillar structure disposed on a surface of the first redistribution layer structure remote from the first germanium wafer, wherein the conductive pillar structure is coupled to the first redistribution layer structure.

A method of fabricating a semiconductor package according to at least one embodiment of the present invention includes: disposing a semiconductor germanium wafer on a carrier, wherein the semiconductor germanium wafer has a conductive via on a top surface of the semiconductor germanium wafer a hole away from the carrier, wherein the conductive via is coupled to a wafer pad of the semiconductor wafer; applying a molding compound to the carrier to form a molding substrate; forming a redistribution on the molding compound a layer structure, and the redistribution layer structure is coupled to the semiconductor germanium wafer; forming a conductive pillar structure coupled to the redistribution layer structure over the redistribution layer structure; removing the strip from the back side of the semiconductor germanium wafer Carrier.

The semiconductor package of the embodiment of the invention adopts a conductive pillar Structure, so it can improve its stability.

500a, 500b‧‧‧ semiconductor package structure

300a‧‧‧ Mixed SOC package

300b‧‧‧SOC package

400b‧‧‧ Mixed DRAM package

400a‧‧‧DRAM package

200‧‧‧Base

202, 420‧‧‧祼 wafer contact surface

322, 432, 452‧‧‧ conductive structure

302‧‧‧SOC chip

600‧‧‧DRAM chip

316, 440, 716‧‧‧ RDL structure

308, 310, 314, 444‧‧‧ through holes

302a‧‧‧Back surface

302b‧‧‧ front surface

324, 702b, 714a, 712a‧‧‧ top

304, 306, 408, 410‧‧‧ pads

602, 602a, 602b‧‧‧TSV interconnected structure

312, 412, 442, 712‧‧

317, 446‧‧‧IMD layer

318, 448‧‧‧ conductive traces

320, 450‧‧‧RDL contact pads

321‧‧‧solder layer

418‧‧‧ Subject

402, 404, 406‧‧‧LPDDR DRAM memory chips

422‧‧‧Bump contact surface

414, 416‧‧‧ bonding wire

424, 426, 430‧‧‧ metal pads

428‧‧‧ Circuitry

600a, 600b‧‧‧ wide I/O DRAM memory chips

700‧‧‧ Carrier

702‧‧‧Semiconductor wafer

701‧‧‧ dielectric layer

702a‧‧‧Back

703‧‧‧祼 wafer pad

704‧‧‧ conductive vias

714‧‧‧through hole structure

718‧‧‧Electrical circuit

720, 718a~718e‧‧‧RDL contact pads

721‧‧‧passivation layer

726‧‧‧conductive column structure

719, 719a~719e‧‧‧ conductive plug

722‧‧‧ welding cap

712b‧‧‧ bottom

S1, S2‧‧‧ Scratch line

350a, 350b, 350c‧‧‧ half body package

1 is a cross-sectional view of a semiconductor package structure including a hybrid SOC package and a DRAM package stacked over the hybrid SOC package, in accordance with some embodiments of the present invention.

2 is a cross-sectional view of a semiconductor package structure including an SOC package and a hybrid DRAM package stacked over the SOC package, in accordance with some embodiments of the present invention.

3A-3E are cross-sectional schematic views for explaining a method of fabricating a semiconductor package in accordance with some embodiments of the present invention.

4A-4E are plan views showing the shapes of the conductive plugs and the RDL contact pads in the RDL (Redistribution Layer) structure in the conductive pillar structure according to some embodiments of the present invention.

5 is a cross-sectional view of a semiconductor package structure including a SOC package and a DRAM package stacked thereon, in accordance with some embodiments of the present invention.

Figure 6 is a cross-sectional view of a semiconductor package including a SOC package and a DRAM package stacked thereon, in accordance with some embodiments of the present invention.

Certain terms are used throughout the description and following claims to refer to particular elements. It should be understood by those skilled in the art that electronic device manufacturers may refer to the same component by different nouns. The scope of this specification and the subsequent patent application does not use the difference in name as the way to distinguish the components, but the difference in the function of the components. then. The term "including" as used throughout the specification and subsequent claims is an open term and should be interpreted as "including but not limited to". In addition, the term "coupled" is used herein to include any direct and indirect electrical connection. Thus, if a first device is described as being coupled to a second device, it is meant that the first device can be directly electrically coupled to the second device or indirectly electrically connected to the second device through other devices or means.

The present invention will be described with reference to the specific embodiments and related drawings, but the invention is not limited to the specific embodiments and the related drawings, and the invention is limited only by the scope of the claims. The drawings described are only schematic and do not have a limiting meaning. In the drawings, the size of some of the elements are exaggerated, and the drawings are not drawn to scale. The dimensions and relative dimensions in the drawings do not correspond to the actual dimensions in the practice of the invention.

1 is a cross-sectional view of a semiconductor package structure 500a including a hybrid SOC package 300a and a DRAM package 400a stacked over the hybrid SOC package 300a, in accordance with some embodiments of the present invention. In some embodiments, the semiconductor package structure 500a can be a POP semiconductor package structure. The semiconductor package structure 500a includes at least two vertically stacked wafer-level semiconductor packages mounted on a substrate 200. In the present embodiment, the vertically stacked wafer level semiconductor package includes a hybrid SOC package 300a and a DRAM package 400a stacked vertically over the mixed SOC package 300a.

As shown in FIG. 1, the substrate 200 (for example, a Printed Circuit Board (PCB)) may be formed of PP (polypropylene). It should be noted that the substrate 200 may be a single layer or a multilayer structure. plural Pads and/or conductive traces (none of which are shown) are disposed over the wafer contact surface 202 of the substrate 200. In one embodiment, the conductive traces may include a signal line portion or a ground line portion for input/output (I/O) connections of the SOC package 300a and the DRAM package 400a. In addition, the SOC package 300a is directly mounted on the conductive line. In some other embodiments, the pads are disposed over the germanium wafer contact surface 202 and are connected to different ends of the conductive traces. The SOC package 300a is directly mounted on the pads.

As shown in FIG. 1, the hybrid SOC package 300a is mounted over the germanium wafer contact surface 202 of the substrate 200 by a bonding process. The hybrid SOC package 300a is mounted over the substrate 200 by a conductive structure 322. The hybrid SOC package 300a may be a three-dimensional (3D) semiconductor package including a SOC 祼 wafer 302, a DRAM 祼 wafer 600, and an RDL structure 316. For example, the SOC祼 chip 302 may include a logic chip including at least one of a CPU (Central Processing Unit), a GPU (Graphic Processing Unit), and a DRAM controller. The DRAM(R) wafer 600 can include a wide I/O (DRAM I/O) DRAM(R) wafer stacked vertically above the SOC(R) wafer 302. In the present embodiment, the DRAM germanium wafer 600 in the hybrid SOC package 300a is assembled by TSV (Through Silicon Via) technology. The SOC(R) wafer 302 and the DRAM(R) wafer 600 in the hybrid SOC package 300a are interconnected and/or connected to the RDL structure 316 by vias (such as vias 308, 310). It should be noted that the number of SOC 祼 wafers 302 and the number of DRAM 祼 wafers 600 are not limited to the disclosed embodiments.

As shown in FIG. 1, the SOC(R) wafer 302 has a rear surface 302a. And front surface 302b. The SOC(R) wafer 302 is assembled by flip chip technology. The rear surface 302a of the SOC(R) wafer 302 is near or aligned to the top surface of the hybrid SOC package 300a. The pads 304 of the SOC(R) wafer 302 are disposed over the front surface 302b to electrically connect to the circuitry (not shown) of the SOC(R) wafer 302. In some embodiments, pads 304 are the topmost metal layer of the interconnect structure (not shown) of SOC(R) wafer 302. The pads 304 of the SOC(R) wafer 302 are in contact with corresponding vias 308.

As shown in FIG. 1, DRAM(R) wafer 600 is stacked on top surface 302b of SOC(R) wafer 302. The DRAM(R) wafer 600 is coupled to the pads 304 of the SOC(R) wafer 302 via vias 308 disposed over the SOC(R) wafer 302. The DRAM germanium wafer 600 can include a TSV interconnect structure 602 formed through the DRAM germanium wafer 600. The TSV interconnect structure 602 arranged in an array can be used to transfer I/O signals, ground signals, or power signals from the DRAM chip 300 to the SOC chip 302 and/or the substrate 200. The TSV interconnect structure 602 can be designed to conform to pin placement rules, such as the JEDEC (Joint Electron Device Engineering Council) wide I/O memory specification. It is noted that the number of TSV interconnect structures in the array is determined by the design of the DRAM(R) wafer 600 and the SOC(R) wafer 302 mounted thereon, and is not limited to the scope of the disclosure. The via 308 is coupled to the TSV interconnect structure 602.

As shown in FIG. 1, the hybrid SOC package 300a additionally includes a molding compound 312 surrounding any of the SOC 祼 wafer 302 and the DRAM 祼 wafer 600 and filling the SOC 祼 wafer 302 and the DRAM 祼 wafer 600. gap. Molding compound 312 is in contact with SOC(R) wafer 302 and DRAM(R) wafer 600. Molding compound 312 also covers SOC祼 wafer 302 Front surface 302b. In some embodiments, the molding compound 312 can be formed from a non-conductive material, such as an epoxy, a tree finger, a moldable polymer, and the like. It is used when the molding compound 312 is substantially liquid and then cured by a chemical reaction, such as in an epoxy resin or a resin. In some other embodiments, the molding compound 312 can be an ultraviolet (UV) or thermally cured polymer that acts as a gel or a moldable solid that can be disposed adjacent to the SOC祼 wafer 302 and the DRAM wafer 600. The polymer is then cured by a UV process or a thermal curing process. The molding compound 312 is cured in a mold.

As shown in FIG. 1, the hybrid SOC package 300a additionally includes an RDL structure 316 disposed over the DRAM 祼 wafer 600 and the SOC 祼 wafer 302 such that the DRAM 祼 wafer 600 is positioned between the SOC 祼 wafer 302 and the RDL structure 316. . The RDL structure 316 can be in contact with the TSV interconnect structure 602 of the molding compound 312 and the DRAM silicon wafer 600. In some embodiments, the RDL structure 316 can have one or a plurality of conductive traces 318 disposed in one or more IMD (Intermetal Dielectric) layers 317. Conductive line 318 is electrically connected to corresponding RDL contact pads 320. The RDL contact pad 320 is exposed at the opening of the passivation layer 321 . However, it should be noted that the number of conductive traces 318, the number of IMD layers 317, and the number of RDL contact pads 320 shown in FIG. 1 are merely examples and are not intended to limit the invention.

As shown in FIG. 1, the hybrid SOC package 300a additionally includes a conductive structure 322 disposed on a surface of the RDL structure 316 remote from the DRAM germanium wafer 600 and the SOC germanium wafer 302. The conductive structure 322 is coupled to the conductive traces 318 through the RDL contact pads 320. In some embodiments, the conductive structure 322 may include: a conductive bump structure (eg, a copper bump or solder bump structure), a conductive pillar junction Structure, conductive wire structure or conductive adhesive structure.

As shown in FIG. 1, DRAM(R) wafer 600 uses TSV interconnect structure 602 and vias 308 to connect pads 304 of SOC(R) wafer 302 to conductive lines 318 of RDL structure 316. In addition, the via 310 passes through the molding compound 312 between the SOC 祼 wafer 302 and the RDL structure 316 through which the pads 306 of the SOC 祼 wafer 302 are coupled to the conductive traces 318 of the RDL structure 316. The via 310 surrounds the DRAM germanium wafer 600.

As shown in FIG. 1, the conductive traces 318 are designed to fan out from one or more of the pads 304 and 306 of the SOC(R) wafer 302 and the TSV interconnect structure 602 of the DRAM(R) wafer 600 to provide SOC祼. The electrical connection between the wafer 302, the DRAM(R) wafer 600 and the RDL contact pads 320. Thus, the RDL contact pads 320 can have a larger bond pitch than the pads 304 and 306 of the SOC(R) wafer 302 and the TSV interconnect structure 602 of the DRAM(R) wafer 600, which has a larger joint pitch RDL. Contact pads 320 are suitable for ball grid arrays or additional package mounting systems.

As shown in FIG. 1, the DRAM package 400a is stacked on the hybrid SOC package 300a by a bonding process. In one embodiment, DRAM package 400a is a LPDDR DRAM (Low-Power Double Data Rate DRAM) package having pin placement rules such as JEDEC LPDDR I/O memory specifications. DRAM package 400a includes a body 418 and at least one LPDDR DRAM chip, such as three LPDDR DRAM chips 402, 404, and 406 stacked on top of body 418. The body 418 has a tantalum wafer contact surface 420 and a bump contact surface 422 with respect to the tantalum wafer contact surface 420. In some embodiments, wide I/O DRAM 祼 wafer I/O The number of pins is designed to be different from the number of I/O pins per LPDDR DRAM 祼 wafers 402, 404, and 406. In one embodiment, the number of I/O pins of the wide I/O DRAM(R) wafer is greater than eight times the number of I/O pins of each of the LPDDR DRAM(R) chips 402, 404, and 406. In the present embodiment, as shown in FIG. 1, three LPDDR DRAM chips 402, 404 and 406 are mounted over the germanium wafer contact surface 420 of the body 418. The LPDDR DRAM(R) wafer 404 is stacked on the LPDDR DRAM(R) wafer 402 using an adhesive (not shown), and the LPDDR DRAM(R) wafer 406 is stacked on the LPDDR DRAM(R) wafer 404 using a paste. The LPDDR DRAM(R) wafers 402, 404, and 406 can be coupled to the body 418 by bond wires, such as bond wires 414 and 416, which are joined to the pads 408 of the metal pads 424 and the LPDDR DRAM chip 402, respectively. The pads 416 and the pads 410 of the LPDDR DRAM(R) wafer 406 are connected to the ends of the 416, respectively. However, the number of stacked DRAM devices is not limited to the disclosed embodiments. Alternatively, the three LPDDR DRAM(R) wafers 402, 404, and 406 shown in FIG. 1 may be arranged side by side. As such, the LPDDR DRAM(R) wafers 402, 404, and 406 can be mounted on the tantalum wafer contact surface 420 of the body 418 using an adhesive. Body 418 can include circuitry 428 and metal pads 424, 426, and 430. Metal pads 424 and 426 are disposed over circuit 428 near the top of germanium wafer contact surface 420. Metal pad 430 is disposed over circuit 428 near the bottom of bump contact surface 422. A plurality of conductive structures 432 are disposed over the bump contact faces 422 of the body 418, and the circuitry 428 of the DRAM package 400a and the conductive traces 318 of the RDL structure 316 are internally connected through the plurality of conductive structures 432. In some embodiments, the conductive structure 432 may include: a conductive bump structure (such as a copper bump or a solder bump structure), and a conductive Column structure, conductive wire structure or conductive adhesive structure. In some embodiments, the vias 314 pass through the molding compound 312 between the DRAM package 400a and the RDL structure 316 in the hybrid SOC package 300a through which the DRAM package 400a is coupled to the conductive traces 318 of the RDL structure 316. . Via 314 surrounds SOC 祼 wafer 302 and DRAM 祼 wafer 600.

In one embodiment, as shown in FIG. 1, the DRAM package 400a additionally includes a molding compound 412 covering the germanium wafer contact surface 420 of the body 418 and encapsulating the LPDDR DRAM wafers 402, 404, and 406, and Bonding lines 414 and 416.

2 is a cross-sectional view of a semiconductor package structure 500b including an SOC package 300b and a hybrid DRAM package 400b stacked over the SOC package 300b, in accordance with further embodiments of the present invention. For the sake of brevity, elements in the following embodiments that are identical or similar to those described above with reference to FIG. 1 are not repeated. The difference between the semiconductor package structure 500a and the semiconductor package structure 500b is that the semiconductor package structure 500b includes a pure SOC package 300b and a hybrid DRAM package 400b vertically stacked on the pure SOC package 300b.

As shown in FIG. 2, the SOC package 300b is a semiconductor package including a SOC 祼 wafer 302 and an RDL structure 316. The SOC package 300b does not include any DRAM germanium wafers integrated therein. The SOC(R) wafer 302 in the SOC package 300b is connected to the RDL structure 316 by a via (e.g., via 310). The pads 304 of the SOC 祼 wafer 302 are in contact with the corresponding vias 310. It should be noted that the number of SOC(R) wafers 302 is not limited to the disclosed embodiments.

As shown in Figure 2, the hybrid DRAM package 400b is bonded The process is stacked on top of the SOC package 300b. The hybrid DRAM package 400b is a three-dimensional semiconductor package including: a wire bonded DRAM package stacked on top of an ISV DRAM package. In this embodiment, the hybrid DRAM package 400b is a LPDDR DRAM/wide I/O DRAM hybrid package including: LPDDR DRAM(R) wafers conforming to specific pin placement rules (eg JEDEC) LPDDR I/O memory specification); and wide I/O DRAM(R) chips that conform to other specific pin placement rules (such as the JEDEC wide I/O memory specification). The hybrid DRAM package 400b includes a body 418, at least one LPDDR DRAM chip stacked on the body 418, and at least one wide I/O DRAM chip stacked on the body 418. In some embodiments as shown in FIG. 2, there are three LPDDR DRAM(R) wafers 402, 404 and 406 mounted over the germanium wafer contact surface 420 of the body 418. The LPDDR DRAM(R) wafer 404 is stacked on the LPDDR DRAM(R) wafer 402 using an adhesive (not shown), and the LPDDR DRAM(R) wafer 406 is stacked on the LPDDR DRAM(R) wafer 404 using an adhesive (not shown). LPDDR DRAM(R) wafers 402, 404, and 406 are coupled to body 418, such as bond wires 414 and 416, by bond wires. However, the number of stacked LPDDR DRAM(R) chips is not limited to the disclosed embodiments. Alternatively, the three LPDDR DRAM chips 402, 404, and 406 shown in FIG. 2 may be arranged side by side. As such, the LPDDR DRAM(R) wafers 402, 404, and 406 can be affixed to the tantalum wafer contact surface 420 of the body 418 using an adhesive.

In one embodiment, as shown in FIG. 2, body 418 can include circuitry (not shown) and metal pads 424, 426, and 430. Metal pads 424 and 426 are disposed on top of the circuit, which is adjacent to the germanium wafer contact surface 420. gold The pad 430 is disposed at the bottom of the circuit, the bottom being adjacent to the bump contact surface 422. The two ends of the bonding wire 414 are respectively connected with the metal pad 424 and the pad 408 of the LPDDR DRAM chip 402. The two ends of the bonding wire 416 are respectively connected with the metal pad 426 and the pad 410 of the LPDDR DRAM chip 406.

In one embodiment, as shown in FIG. 2, the hybrid DRAM package 400b additionally includes a molding compound 412 covering the germanium wafer contact surface 420 of the body 418 and encapsulating the LPDDR DRAM germanium wafers 402, 404, and 406, and bonding. Lines 414 and 416.

As shown in FIG. 2, the hybrid DRAM package 400b additionally includes at least one wide I/O DRAM chip, such as two wide I/O DRAM chips 600a and 600b embedded therein. In this embodiment, two wide I/O DRAM(R) wafers 600a and 600b are mounted over the bump contact surface 422 and coupled to the metal pad 430 of the body 418. The wide I/O DRAM chips 600a and 600b are arranged side by side. However, the number and arrangement of wide I/O DRAM 祼 wafers is not limited to the disclosed embodiments. The wide I/O DRAM(R) wafers 600a and 600b may include corresponding TSV interconnect structures 602a and 602b formed through the wide I/O DRAM(R) wafers 600a and 600b, respectively. TSV interconnect structures 602a and 602b arranged in an array can be used to transfer I/O signals, ground signals, or power signals from wide I/O DRAM chips 600a and 600b to LPDDR DRAM chips 402, 404 and 406 and/or substrate 200. . The TSV interconnect structures 602a and 602b can be designed to conform to pin placement rules (such as the JEDEC wide I/O memory specification). It should be noted that the number of TSV interconnect structures in the array is determined by the design of the wide I/O DRAM chips 600a and 600b and the LPDDR DRAM chips 402, 404 and 406 mounted thereon, and is not limited. The scope of the disclosure. The TSV interconnect structures 602a and 602b are coupled to the metal pads 430 of the body 418. In some embodiments, the number of I/O pins of the wide I/O DRAM 祼 chips 600a and 600b is designed to be different from the number of I/O pins of any of the LPDDR DRAM 祼 chips 402, 404, and 406. In one embodiment, the number of I/O pins of the wide I/O DRAM chips 600a and 600b is greater than eight times the number of I/O pins of any of the LPDDR DRAM chips 402, 404, and 406.

As shown in FIG. 2, the hybrid DRAM package 400b further includes a molding compound 442 disposed on the bump contact surface 422 of the body 418. The molding compound 442 surrounds the wide I/O DRAM 祼 wafers 600a and 600b and fills any voids around the wide I/O DRAM 祼 wafers 600a and 600b. Molding compound 442 is in contact with wide I/O DRAM(R) wafers 600a and 600b.

As shown in FIG. 2, the hybrid DRAM package 400b further includes an RDL structure 440 over the bump contact surface 422 of the body 418. RDL structure 440 is also disposed over LPDDR DRAM(R) wafers 402, 404, and 406, as well as wide I/O DRAM(R) chips 600a and 600b. Wide I/O DRAM(R) wafers 600a and 600b are located between body 418 and RDL structure 440. The RDL structure 440 can be in contact with the TSV interconnect structures 602a and 602b of the molding compound 442 and the wide I/O DRAM 祼 wafers 600a and 600b. The RDL structure 440 can have one or a plurality of conductive traces 448 disposed in one or more of the IMD layers 446. The conductive line 448 is electrically connected to the corresponding RDL contact pad. However, it should be noted that the number of conductive traces 448 shown in FIG. 2, the number of IMD layers 446, and the number of RDL contact pads are merely examples and are not limiting of the present invention.

As shown in FIG. 2, the through hole 444 is connected through the bump of the main body 418. The molding compound 442 between the contact surface 422 and the RDL structure 440, through which the LPDDR DRAM(R) wafers 402, 404, and 406 can be coupled to the RDL contact pads 450 of the RDL structure 440. Vias 444 surround the wide I/O DRAM 祼 wafers 600a and 600b.

As shown in FIG. 2, a plurality of conductive structures 452 are disposed over the RDL contact pads 450 of the RDL structure 440, and the conductive traces 448 of the DRAM package 400b pass through the plurality of conductive structures 452 and the conductive traces of the RDL structure 316 of the SOC package 300b. 318 interconnection. In some embodiments, the conductive structure 452 can include: a conductive bump structure (such as a copper bump or a solder bump structure), a conductive pillar structure, a conductive line structure, or a conductive paste structure. In some embodiments, the vias 314 pass through the molding compound between the DRAM package 400b and the RDL structure 316 of the SOC package 300b, and the conductive structures 452 of the DRAM package 400b are coupled by the vias 314 to the RDL structure 316 of the SOC package 300b. . Via 314 surrounds SOC 祼 wafer 302.

The embodiment provides semiconductor package structures 500a and 500b. Any of the semiconductor package structures 500a and 500b provides a LPDDR DRAM and a wide I/O DRAM mixed memory integrated using a POP semiconductor package structure. The POP semiconductor package structure 500a includes a SOC/wide I/O DRAM hybrid package 300a and an LPDDR DRAM package 400a stacked thereon. The POP semiconductor package structure 500b includes a pure SOC package 300b and an LPDDR/wide I/O DRAM hybrid package 400b stacked thereon. The semiconductor package structures 500a and 500b have advantages of LPDDR DRAM package structures (such as cost effects, fast transitions, etc.) and advantages of wide I/O DRAM package structures (such as high frequency bandwidth, low power consumption, etc.). Semiconductor package structures 500a and 500b can meet cost The need for effects, high bandwidth, low power consumption and fast transitions.

In some embodiments, the conductive structure coupled to the hybrid SOC package 300a shown in FIG. 1 or the pure SOC package 300b shown in FIG. 2 is a conductive pillar structure. In some embodiments, the conductive pillar structure may be composed of a metal stack including: a UBM (Under Bump Metallurgy) layer (not shown), a conductive plug, and a Corresponding solder cap. 3A-3E are cross-sectional schematic views of a method of fabricating a semiconductor package, such as semiconductor packages 350a-350c, in accordance with some embodiments of the present disclosure.

As shown in Fig. 3A, a carrier 700 is provided. The carrier 700 can be used to provide structural rigidity or a substrate for subsequent non-rigid layer deposits. Next, a plurality of semiconductor germanium wafers 702 separated from each other are disposed to be attached to the carrier 700 through a dielectric layer 701. The back surface 702a of the semiconductor germanium wafer 702 is in contact with the dielectric layer 701. The top surface 702b of the semiconductor germanium wafer 702 faces away from the carrier 700. In some embodiments, the semiconductor germanium wafer 702 is an SOC germanium wafer that is the same or similar to the SOC germanium wafer 302 shown in FIGS. 1 and 2.

In some embodiments shown in FIG. 3A, each semiconductor germanium wafer 702 has a germanium wafer pad 703 and a corresponding conductive via 704. The formed germanium wafer pad 703 covers the top surface 702b of the semiconductor germanium wafer 702 and the portion of the germanium wafer pad 703 near the top surface 702b. The conductive via 704 is placed at a location corresponding to the germanium wafer pad 703, and the conductive via 704 is disposed over the top surface 702b of the semiconductor germanium wafer 702. Conductive vias 704 pass through dielectric layer 706. The conductive vias 704 are in contact with and coupled to the germanium wafer pads 703 of the semiconductor germanium wafer 702. In some other embodiments, at least one via structure 714 is disposed above the carrier 700. Additionally, via structure 714 is disposed beside semiconductor germanium wafer 702.

Next, as shown in FIG. 3B, a molding compound 712 can be applied to the carrier 700. The molding compound 712 can surround the semiconductor germanium wafer 702 and fill the gap around the semiconductor germanium wafer 702. The molding compound 712 also covers the top surface 702b of the semiconductor germanium wafer 702 and the conductive vias 704. In some other embodiments, the molding compound 712 surrounds the via structure 714 leaving the top surface 714a of the via structure 714 exposed from the top surface 712a of the molding compound 712. In some embodiments, the materials and manufacturing processes of the molding compound 312 shown in FIGS. 1 and 2 are the same as or similar to the materials and manufacturing processes of the molding compound 712.

Next, as shown in FIG. 3C, the RDL structure 716 is formed over the molding compound 712 and coupled to the semiconductor germanium wafer 702 by a deposition process, a photolithography process, an anisotropic etching process, and an electroplating process. In some embodiments, RDL structure 716 can have one or a plurality of conductive traces 718 disposed in one or more IMD layers 717. Additionally, the RDL structure can have one or a plurality of RDL contact pads 720 and a passivation layer 721. The RDL contact pads 720 are in contact with corresponding conductive traces 718 and are covered by a passivation layer 721. In some embodiments, the materials and fabrication processes of the RDL structures 316 shown in FIGS. 1 and 2 are the same as or similar to the materials and fabrication processes of the RDL structures 716.

In some embodiments, as shown in FIG. 3C, prior to forming the RDL structure 716, a photolithography process can be used to form a plurality of openings (not shown) that are adjacent to the first semiconductor from the molding compound 712. The face of the top surface 702b of the germanium wafer 702 is formed through a portion of the molding compound 712. Therefore, it also forms The conductive line 718 of the opening of the molding compound 712 is filled to be coupled to the conductive via 704. Additionally, conductive traces 718 are electrically coupled to corresponding RDL contact pads 720. The RDL contact pad 720 is exposed to an opening (not shown) of the passivation layer 721.

Next, as shown in FIGS. 3C-3D, a conductive pillar structure 726 is formed over the RDL structure 716 and coupled to the RDL structure 716. As shown in FIG. 3C, a photolithography process is performed to form a photoresist pattern (not shown) covering the passivation layer 721. Next, an anisotropic etch process is performed to form an opening (not shown) through the passivation layer 721 of the RDL structure 716. In some embodiments, an opening (not shown) is placed at a location corresponding to the RDL contact pad 720 of the RDL structure 716.

Then, the photoresist pattern is removed from the passivation layer 721. Next, an electroplating process is performed to form a fill opening (not shown) and connect the conductive plugs 719 of the RDL contact pads 720. The formed conductive plug 719 protrudes from the RDL structure 716. As shown in FIG. 3C, the conductive plug 719 has a lower portion embedded in the passivation layer 721 and an upper portion protruding from the passivation layer 721. The upper portion of the conductive plug 719 is wider than the lower portion of the conductive plug 719. In some embodiments, the width of the upper portion of the conductive plug 719 ranges from about 2 [mu]m to about 5 [mu]m. In some embodiments, the upper and lower portions of the conductive plug 719 have the same or similar shape.

In some other embodiments, the photoresist pattern is removed from the passivation layer 721 after the conductive plug 719 is formed. Therefore, the width of the upper portion of the conductive plug 719 is substantially equal to the width of the lower portion of the conductive plug 719.

Next, as shown in FIG. 3D, the solder caps 722 are respectively formed on the corresponding conductive plugs 719 by a photolithography process, a solder plating process, a photoresist strip process, and a solder reflow process. Next, from the semiconductor germanium wafer 702 The back side 702a removes the carrier 700 and the dielectric layer 701 (shown in FIG. 3C). In some embodiments, the conductive plug 719 and the corresponding solder cap 722 collectively form a conductive pillar structure 726.

In some embodiments, the back side 702a of the semiconductor germanium wafer 702 and the bottom surface 714b of the via structure 714 are exposed from the bottom surface 712b of the molding compound 712.

Next, as shown in FIG. 3E, a separation process is performed to cut the RDL structure 716 and the molding compound 712 along the scribe lines S1 and S2 placed between the semiconductor bare wafers 702. After the separation process is performed, separate semiconductor packages 350a, 350b, and 350c are formed. For example, each of the semiconductor packages 350a and 350c includes a via structure 714 that passes through the molding compound 712. In some embodiments, the fabrication of the material of vias 314 shown in FIGS. 1 and 2 is the same as or similar to the material and fabrication process of via structure 714. The semiconductor package 350b is fabricated without any via structure. It should be noted that the number of semiconductor packages is not limited to the disclosed embodiments.

4A-4E are schematic plan views of the shape of the conductive plug and the RDL contact pad of the RDL structure in the conductive pillar structure, in accordance with some embodiments of the present disclosure. In some embodiments, in the plan views shown in FIGS. 4A-4E, the conductive plugs 719a-719e can be designed to have a shape similar to the RDL contact pads 718a-718e of the corresponding RDL structure. In some embodiments, in the plan views shown in FIGS. 4A-4E, the conductive plugs 719a-719e of the conductive pillar structure may be designed to have an intermediate point C around the conductive plugs 719a-719e and rotated 180 degrees. The 2-fold rotational symmetry. In some embodiments, in the plan view shown in FIG. 4A, the conductive plug 719a and the corresponding RDL contact pad 718a are square. In the plan view shown in FIG. 4B, the conductive plug 719b and the corresponding RDL are connected The contact pad 718b is rectangular. In the plan view shown in FIG. 4C, the conductive plug 719c and the corresponding RDL contact pad 718 are circular. In the plan view shown in FIG. 4D, the conductive plug 719d and the corresponding RDL contact pad 718d are elliptical. In the plan view shown in Fig. 4E, the conductive plug 719e and the corresponding RDL contact pad 718e are octagonal.

5 is a cross-sectional view of a semiconductor package structure 500d including a hybrid SOC package 300d and a DRAM package 400a stacked over the hybrid SOC package 300d, in accordance with some embodiments of the present disclosure. For the sake of brevity, descriptions of the same or similar elements in the following embodiments as those previously described with reference to FIGS. 1 to 2 are omitted.

As shown in FIG. 5, a difference between the semiconductor package structure 500a shown in FIG. 1 and the semiconductor package structure 500d is that the semiconductor package structure 500d includes: disposed in the first RDL structure 316 away from the first semiconductor germanium wafer 302. Conductive post structure 326 on the face. The conductive pillar structure 326 is coupled to the RDL contact pads 320 in the first RDL structure 316 of the corresponding hybrid SOC package 300d. In some embodiments, each of the conductive pillar structures can be comprised of a metal stack including conductive plugs 319 and corresponding solder caps 324. In some embodiments, the molding compound 312, the through hole 314, and the first RDL structure 316 shown in FIG. 5 are made of the same material or manufacturing process as the molding compound 712, through hole shown in FIGS. 3A-3C. Materials and manufacturing processes for structures 714 and RDL structures 716. In some embodiments, the material and manufacturing process of the conductive plug 319 and the solder cap 324 shown in FIG. 5 are the same or similar to those of the conductive plug 719 and the solder cap 722 shown in FIGS. 3C-3E. Manufacturing process. In addition, the conductive plug 319 and the corresponding RDL contact pad 320 have the same shape or are similar in plane view. The shapes of the conductive plugs 719a to 719e and the corresponding RDL contact pads 718a to 718e in the plan view shown in FIGS. 4A to 4E.

6 is a cross-sectional view of a semiconductor package structure 500e including an SOC package 300e and a hybrid DRAM package 400b stacked over the SOC package 300e, in accordance with some embodiments of the present disclosure. For the sake of brevity, descriptions of the same or similar elements in the following embodiments as those previously described with reference to FIGS. 1 to 2 and 5 are omitted.

As shown in FIG. 6, a difference between the semiconductor package structure 500b shown in FIG. 2 and the semiconductor package structure 500e is that the semiconductor package structure 500e includes: disposed in the first RDL structure 316 away from the first semiconductor germanium wafer 302. Conductive post structure 326 on the face. The conductive pillar structure 326 is coupled to the RDL contact pads 320 in the first RDL structure 316 of the corresponding SOC package 300e. In some embodiments, the conductive pillar structures 326 in the semiconductor package 500e are identical or similar to the conductive pillar structures 326 of the semiconductor package structure 500d shown in FIG. In some embodiments, the material and manufacturing process of the conductive plug 319 and the solder cap 324 shown in FIG. 6 are the same or similar to those of the conductive plug 719 and the solder cap 722 shown in FIGS. 3C-3E. Manufacturing process. In addition, the conductive plug 319 and the corresponding RDL contact pad 320 have the same shape in plan view or the conductive plugs 719a-719e and the corresponding RDL contact pads 718a in the plan view shown in FIGS. 4A-4E. The shape of the 718e.

In some embodiments, a conductive pillar structure disposed over a pure SOC package or a hybrid SOC package in a semiconductor package structure can have the following advantages. The conductive post structure consists of a metal stack containing conductive plugs and corresponding solder caps. The conductive plug of the formed conductive pillar structure protrudes from the RDL structure. In order to avoid ball bridge problems and package warpage problems. Improved performance of the substrate (printed circuit board). In addition, the conductive pillar structure can facilitate the SMT (surface-mount technology) rework process, which is used for wafer-level semiconductor package solder caps. Therefore, the stability of the SOC package and the semiconductor package structure is improved.

The above is only the preferred embodiment of the present invention, and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection of the present invention. Within the scope.

Claims (23)

  1. A semiconductor package comprising: a first semiconductor germanium wafer; a first redistribution layer structure; and a conductive pillar structure; wherein the first semiconductor germanium wafer and the conductive pillar structure are respectively disposed on the first redistribution layer structure And electrically coupled to the first redistribution layer structure; wherein the conductive pillar structure comprises: a metal stack, the metal stack comprises: a conductive plug and a contact with the conductive plug A welding cap.
  2. The semiconductor package of claim 1, wherein the conductive plug comprises: a first portion embedded in the redistribution layer structure and a second portion protruding from the redistribution layer, and the second portion is wide In the first portion; wherein the welding cap contacts the second portion.
  3. The semiconductor package of claim 1, wherein the conductive plug is square, rectangular, circular, octagonal or elliptical in plan view.
  4. The semiconductor package of claim 1, wherein the conductive plug has a shape similar to that of the corresponding redistribution layer contact pad in the first redistribution layer structure in plan view.
  5. The semiconductor package of claim 1, wherein the conductive plug is a two-fold rotationally symmetric structure capable of rotating 180° around a center point of the conductive plug in plan view.
  6. A semiconductor package structure comprising: a first semiconductor package; the first The semiconductor package is the semiconductor package according to any one of claims 1 to 5.
  7. The semiconductor package structure of claim 6, wherein the semiconductor package structure further comprises: a second semiconductor package stacked on the first semiconductor package, and comprising: a body having a germanium wafer contact And a bump contact surface with respect to the contact surface of the germanium wafer; and a second dynamic random access memory germanium wafer mounted over the germanium wafer contact surface and coupled to the body by a bond wire.
  8. The semiconductor package structure of claim 7, wherein the first semiconductor package further comprises: a first DRAM chip mounted on the first semiconductor NMOS wafer; wherein The number of input/output pins of the first DRAM chip is different from the number of input/output pins of the second DRAM chip.
  9. The semiconductor package structure of claim 7, wherein the second semiconductor package further comprises: an additional dynamic random access memory chip embedded in the second semiconductor package; wherein the additional The DRAM chip has a 矽-via interconnect structure formed through the additional DRAM chip; wherein the additional DRAM is input/output of the chip The number of pins is different from the number of input/output pins of the second DRAM chip.
  10. The semiconductor package structure of claim 8, wherein the number of input/output pins of the first dynamic random access memory chip is greater than the input/output of the second dynamic random access memory chip 8 times the number of pins.
  11. The semiconductor package structure of claim 8, wherein the first semiconductor germanium wafer has a first pad, the first redistribution layer structure is coupled to the first pad; the first semiconductor package The method further includes: a first via disposed over the first semiconductor germanium wafer and coupled to the first via.
  12. The semiconductor package structure of claim 11, wherein the first semiconductor package is a system-on-chip package, and the first semiconductor chip is an on-chip system chip; the first dynamic random access memory device is coupled to the chip. Connecting the first via hole over the first semiconductor germanium wafer and the first redistribution layer structure.
  13. The semiconductor package structure of claim 12, wherein the first DRAM chip is disposed between the first semiconductor NMOS wafer and the first redistribution layer structure.
  14. The semiconductor package structure of claim 12, wherein the first semiconductor package further comprises: a molding compound surrounding the first semiconductor germanium wafer and the first dynamic random access memory germanium wafer, and The first redistribution layer structure, the first The semiconductor germanium wafer and the first dynamic random access memory (NMOS) wafer are in contact.
  15. The semiconductor package structure of claim 14, wherein the plurality of second vias pass through the molding compound between the second semiconductor package and the first redistribution layer structure; the second semiconductor package passes The second vias are coupled to the conductive lines in the first redistribution layer structure.
  16. The semiconductor package structure of claim 15, wherein the second vias surround the first semiconductor germanium wafer.
  17. The semiconductor package structure of claim 14, wherein a plurality of third via holes pass through the molding compound between the first semiconductor germanium wafer and the first redistribution layer structure; the first semiconductor germanium The wafer is coupled to the conductive lines in the first redistribution layer structure through the third vias.
  18. The semiconductor package structure of claim 17, wherein the third vias surround the first DRAM chip.
  19. The semiconductor package structure of claim 9, wherein the second semiconductor package is a dynamic random access memory package; the dynamic random access memory package comprises: a second redistribution layer structure, Above the bump contact surface.
  20. The semiconductor package structure of claim 19, wherein the additional DRAM chip is disposed between the body and the second redistribution layer structure.
  21. The semiconductor package structure according to any one of claims 6 to 20, further comprising: a substrate, wherein the first semiconductor package is mounted on the conductive pillar structure Above the substrate.
  22. A method of fabricating a semiconductor package, comprising: disposing a semiconductor germanium wafer on a carrier, wherein the semiconductor germanium wafer has a conductive via on a top surface of the semiconductor germanium wafer, the top surface being away from the carrier, The conductive via is coupled to a germanium wafer pad of the semiconductor germanium wafer; a molding compound is applied to the carrier to form a molding substrate; a redistribution layer structure is formed on the molding compound, and the redistribution layer structure is formed Coupling to the semiconductor germanium wafer; forming a conductive pillar structure coupled to the redistribution layer structure over the redistribution layer structure; removing the carrier from a back side of the semiconductor germanium wafer; wherein the conductive pillar structure is formed The step of forming: forming an opening through a passivation layer in the redistribution layer structure, wherein the opening is disposed at a position corresponding to a redistribution contact pad in the redistribution layer structure; forming the opening and connecting to the opening a conductive plug of the redistribution layer contact pad, wherein the conductive plug protrudes from the passivation layer, and the conductive plug protrudes from the passivation layer to be wider than the guide Embedded in the plug portion of the passivation layer; and forming a solder on the plug in the conductive cap.
  23. The method of manufacturing a semiconductor package according to claim 22, further comprising: providing a via structure on the carrier before applying the molding compound to the carrier And the via structure is located beside the semiconductor germanium wafer.
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