CN105990326B - Semiconductor packages, semiconductor package and the method for manufacturing semiconductor packages - Google Patents
Semiconductor packages, semiconductor package and the method for manufacturing semiconductor packages Download PDFInfo
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- CN105990326B CN105990326B CN201610140408.8A CN201610140408A CN105990326B CN 105990326 B CN105990326 B CN 105990326B CN 201610140408 A CN201610140408 A CN 201610140408A CN 105990326 B CN105990326 B CN 105990326B
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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Abstract
The invention discloses a kind of semiconductor packages, semiconductor package and the methods for manufacturing semiconductor packages, to improve the stability of semiconductor packages.Wherein the semiconductor package includes: semiconductor packages.The semiconductor packages includes: semiconductor Naked chip, redistribution layer structure and conductive pillar structure.Wherein, to semiconductor Naked chip, which is arranged on the surface in the redistribution layer structure far from the Naked chip redistribution layer structure couples, and is coupled to the redistribution layer structure.
Description
Technical field
The present invention relates to a kind of semiconductor packages, more particularly to a kind of mixed DRAM (Dynamic Random
Access Memory, dynamic random access memory) encapsulating structure.
Background technique
POP (Package-on-Package, package on package or stacked package) structure be it is a kind of for vertical cartel from
The integrated circuit packaging method of scattered SOC (System-On-Chip, system on chip) and memory package.Use standard interface
(standard interface) installs two or more encapsulation (as stacked) on top each other, thus in these envelopes
Route signal between dress.POP encapsulating structure allows equipment to have higher component density, and equipment is, for example, mobile phone, individual
Digital assistants (Personal Digital Assistant, PDA) or digital camera.
For having the integrated horizontal enhanced, performance, bandwidth, delay, power, weight and the form factor improved
The ratio of the memory application of (form factor), signal pad and ground mat becomes important in improving coupling effect.
As such, it is desired to the semiconductor package of innovation.
Summary of the invention
In view of this, the present invention provides a kind of semiconductor packages, semiconductor package and manufacture semiconductor packages
Method, to improve the stability of semiconductor packages.
The present invention provides a kind of semiconductor packages, comprising: the first semiconductor Naked chip；First redistribution layer structure, coupling
It is connected to the first semiconductor Naked chip；And conductive pillar structure, it is arranged in the first redistribution layer structure far from the first Naked
On the surface of chip, wherein the conductive pillar structure is coupled to the first redistribution layer structure.
Wherein, which includes: metal stack, the metal stack include: conductive plunger and with the conductive plunger
The weld cap of contact.
Wherein, the conductive plunger be square in plan view, rectangle, circle, octagonal or ellipse.
Wherein, in plan view, which has and the redistribution in the corresponding first redistribution layer structure
The similar shape of contact pad layer.
Wherein, in plan view, which is can be around 2 weights of 180 ° of central point rotations of the conductive plunger
Rotational symmetry structure.
The present invention provides a kind of semiconductor packages, comprising: the first semiconductor packages, first semiconductor packages are
Semiconductor packages as described above.
Wherein, further comprise: the second semiconductor packages is stacked on first semiconductor packages, and includes: master
Body has Naked chip contact surface and the bump contact face relative to the Naked chip contact surface；And second dynamic randon access deposit
Reservoir Naked chip is mounted on the Naked chip contact surface and is coupled to the main body by closing line.
Wherein, first semiconductor packages further include: the first dynamic random access memory Naked chip, be installed on this first
On semiconductor Naked chip；Wherein, the input/output pin number of the first dynamic random access memory Naked chip is different from
The input/output pin number of the second dynamic random access memory memory Naked chip.
Wherein, which further comprises: additional dynamic random access memory Naked chip is embedded in
In second semiconductor packages；Wherein, which has across the additional dynamic
Random access memory Naked chip and the silicon through hole interconnection structure formed；Wherein, the additional dynamic random access memory Naked
The input/output pin number of chip is different from the input/output number of pins of the second dynamic random access memory Naked chip
Amount.
Wherein, the input/output pin number of the first dynamic random access memory Naked chip is greater than second dynamic
8 times of the input/output pin number of random access memory Naked chip.
Wherein, which has the first connection pad, which first connects to this
Pad；First semiconductor packages further include: first through hole is arranged on the first semiconductor Naked chip, and is coupled to this
First connection pad.
Wherein, which is system on chip encapsulation, which is system on chip Naked core
Piece；The first dynamic random access memory Naked chip be coupled to the first through hole on the first semiconductor Naked chip and
The first redistribution layer structure.
Wherein, which is arranged in the first semiconductor Naked chip and first weight
Between distribution layer construction.
Wherein, first semiconductor packages further include: moulding compound, around the first semiconductor Naked chip and this is first dynamic
State random access memory Naked chip, and with the first redistribution layer structure, the first semiconductor Naked chip and this first
The contact of dynamic random access memory Naked chip.
Wherein, the molding of multiple second through-holes across second semiconductor packages and the first redistribution layer structure
Material；Second semiconductor packages is coupled to the conducting wire in the first redistribution layer structure by multiple second through-hole.
Wherein, multiple second through-hole surrounds the first semiconductor Naked chip.
Wherein, the mould of multiple third through-holes across the first semiconductor Naked chip and the first redistribution layer structure
Plastics；The first semiconductor Naked chip is coupled to the conductor wire in the first redistribution layer structure by multiple third through-hole
Road.
Wherein, multiple third through-hole surrounds the first dynamic random access memory Naked chip.
Wherein, which is dynamic random access memory encapsulation；Dynamic random access memory envelope
Dress includes: the second redistribution layer structure, is arranged on the bump contact face.
Wherein, which is arranged in the main body and the second redistribution layer structure
Between.
Wherein, further comprise: substrate, wherein first semiconductor packages is installed on the substrate by the conductive pillar structure
On.
The present invention provides it is a kind of manufacture semiconductor packages method, comprising: by semiconductor Naked chip setting carrier it
On, wherein semiconductor Naked chip has the conductive through hole on the top surface of semiconductor Naked chip, and the top surface is far from the load
Body, wherein the conductive through hole is coupled to the Naked chip mat of semiconductor Naked chip；Using moulding compound to the carrier, to form mould
Mould substrate；Redistribution layer structure is formed on the moulding compound, and the redistribution layer structure couples are to semiconductor Naked chip；?
The conductive pillar structure for being coupled to the redistribution layer structure is formed on the redistribution layer structure；From the back side of semiconductor Naked chip
Remove the carrier.
Wherein, the step of forming the conductive pillar structure includes: the passivation layer to be formed in the redistribution layer structure
The position of the redistribution engagement pad in the corresponding redistribution layer structure is arranged in opening, the opening；It is formed and fills the opening and company
It is connected to the conductive plunger of the redistribution layer engagement pad, wherein the conductive plunger protrudes from the redistribution layer structure；And it leads at this
A weld cap is formed in electric plug.
Wherein, further comprise: application the moulding compound to the carrier before, on this carrier be arranged through-hole structure and
The through-hole structure is located at the side of semiconductor Naked chip.
The beneficial effect of the embodiment of the present invention is:
Above semiconductor packages improves its stability using conductive pillar structure.
Detailed description of the invention
Fig. 1 is the cross-sectional view of semiconductor package according to some embodiments of the invention, the semiconductor packages
Structure includes: that the SOC encapsulation of mixing and the DRAM being stacked on the SOC encapsulation of the mixing are encapsulated.
Fig. 2 is the cross-sectional view of semiconductor package according to some embodiments of the invention, the semiconductor packages
Structure includes: that SOC encapsulation and the mixed DRAM being stacked on SOC encapsulation are encapsulated.
Fig. 3 A~3E is the cross section for illustrating the method for manufacture semiconductor packages according to some embodiments of the invention
Schematic diagram.
Fig. 4 A~4E is conductive plunger (plug) and RDL in conductive pillar structure according to some embodiments of the invention
The plane of the shape of RDL engagement pad in (Redistribution Layer, redistribution layer or re-wiring layer) structure is illustrated
Figure.
Fig. 5 is the semiconductor that DRAM encapsulation thereon is encapsulated and stacked containing SOC according to some embodiments of the invention
The cross-sectional view of encapsulating structure.
Fig. 6 is the semiconductor that DRAM encapsulation thereon is encapsulated and stacked containing SOC according to some embodiments of the invention
The cross-sectional view of encapsulation.
Specific embodiment
In present specification and claim, some vocabulary has been used to censure specific component.This field skill
Art personnel are, it is to be appreciated that hardware manufacturer may call the same component with different nouns.This specification and right are wanted
In a manner of asking not using the difference of title as differentiation component, but using the difference of component functionally as the criterion distinguished.
Mentioned "include", "comprise" are an open term throughout the specification and claims, therefore should be construed to " packet
It includes and (contains) but be not limited to ".In addition, " coupling " word is to include any direct and indirect electrical connection herein.Therefore,
If it is described herein that first device is coupled to second device, then representing the first device can directly be electrically connected to the second device,
Or it is electrically connected indirectly through other devices or connection means to the second device.
The present invention will be described with reference to specific embodiment and relevant drawings, specific but the invention is not limited to this
Embodiment and attached drawing, and the present invention is only limited by claim.The attached drawing of description is only schematic diagram and does not have
Limitation.In the accompanying drawings, the sizes of certain components is exaggerated for purpose of explanation, and it is to draw in proportion that attached drawing, which is not,
System.The full-size(d) in the not corresponding present invention practice of size and relative size in attached drawing.
Fig. 1 is the cross-sectional view of semiconductor package 500a according to some embodiments of the invention, the semiconductor
Encapsulating structure 500a includes: that the SOC encapsulation 300a of mixing and the DRAM being stacked on the SOC encapsulation 300a of the mixing are encapsulated
400a.In some embodiments, semiconductor package 500a can be POP semiconductor package.Semiconductor package
500a includes: wafer scale (wafer-level) semiconductor packages at least two vertical stackings being installed in substrate 200.?
In the present embodiment, the wafer level semiconductor encapsulation of the vertical stacking includes: that the SOC encapsulation 300a of mixing is mixed with this is stacked vertically in
DRAM on the SOC encapsulation 300a of conjunction encapsulates 400a.
As shown in Figure 1, substrate 200 (such as printed circuit board (Printed Circuit Board, PCB)) can be by PP
(polypropylene, polypropylene) is formed.It is to be noted that substrate 200 can be single layer structure or multilayered structure.It is multiple
Connection pad (pad) and/or conducting wire (conductive trace) (not shown) are set to the Naked chip contact surface of substrate 200
On 202.In one embodiment, conducting wire may include: signal line part or ground path part, seal for SOC
Fill input/output (I/O) connection of 300a and DRAM encapsulation 400a.In addition, SOC encapsulation 300a can be directly mounted at conductor wire
On road.In some other embodiments, connection pad is set on Naked chip contact surface 202, and is connected to conducting wire
Different ends.SOC encapsulation 300a is directly mounted on connection pad.
As shown in Figure 1, mixed SOC encapsulation 300a is installed on substrate 200 by joint technology (bonding process)
Naked chip contact surface 202 on.Mixed SOC encapsulation 300a is installed on substrate 200 by conductive structure 322.Mixing
SOC encapsulation 300a can be three-dimensional (3D) semiconductor package of the chip of Naked containing SOC 302, DRAM Naked chip 600 and RDL structure 316
Dress.For example, SOC Naked chip 302 may include: logic Naked chip, logic Naked chip includes at least one of following: CPU
(Central Processing Unit, central processing unit), GPU (Graphic Processing Unit, image procossing list
Member) and dram controller.DRAM Naked chip 600 may include wide I/O (Wide I/O) DRAM Naked chip, be stacked vertically in SOC
On Naked chip 302.In the present embodiment, pass through the assembly mixing of TSV (Through Silicon Via, through silicon via) technology
SOC encapsulates the DRAM Naked chip 600 in 300a.SOC Naked chip 302 and DRAM Naked chip 600 in mixed SOC encapsulation 300a
RDL structure 316 is interconnected and/or is connected to by through-hole (such as through-hole 308,310).It is to be noted that SOC Naked chip
302 quantity and the quantity of DRAM Naked chip 600 are not restricted to disclosed embodiment.
As shown in Figure 1, SOC Naked chip 302 has rear surface 302a and front surface 302b.SOC is assembled by Flip Chip
Naked chip 302.The rear surface 302a of SOC Naked chip 302 is close or is aligned in the top surface of the SOC of mixing encapsulation 300a.SOC Naked
The connection pad 304 of chip 302 is set on front surface 302b, to be electrically connected to the circuit (not shown) of SOC Naked chip 302.
In some embodiments, connection pad 304 belongs to the topmost metal layer of the interconnection structure (not shown) of SOC Naked chip 302.SOC Naked
The connection pad 304 of chip 302 is contacted with corresponding through-hole 308.
As shown in Figure 1, DRAM Naked chip 600 is stacked on the front surface 302b of SOC Naked chip 302.DRAM Naked chip
600 connection pads 304 for being coupled to SOC Naked chip 302 by being set to the through-hole 308 on SOC Naked chip 302.DRAM Naked chip
600 may include: the TSV interconnection structure 602 formed across DRAM Naked chip 600.It is arranged as the TSV interconnection structure of array
602 can be used for transmitting I/O signal, ground signalling or power from DRAM Naked chip 600 to SOC Naked chip 302 and/or substrate 200
Signal.TSV interconnection structure 602 can be designed as meeting pin arrangement rule, such as JEDEC (Joint Electron Device
Engineering Council, solid state technology association) wide I/O memory specification.It should be noted that connecting in TSV in array
The quantity of structure is determined by the design of DRAM Naked chip 600 and the SOC Naked chip 302 being mounted thereon, and is not limited to
Scope of disclosure.Through-hole 308 is coupled to TSV interconnection structure 602.
As shown in Figure 1, mixed SOC encapsulation 300a is further comprising: moulding compound (molding compound) 312, surrounds
Around SOC Naked chip 302 and DRAM Naked chip 600 and fill around SOC Naked chip 302 and DRAM Naked chip 600
Any gap.Moulding compound 312 is contacted with SOC Naked chip 302 and DRAM Naked chip 600.Moulding compound 312 also covers SOC Naked chip
302 front surface 302b.In some embodiments, moulding compound 312 can be formed by non-conducting material, such as epoxy resin, tree
Finger, plastic polymer (moldable polymer), etc..Moulding compound 312 is used in substantially liquid, then passing through
Reaction solidification is learned, such as in epoxy resin or resin.In some other embodiments, moulding compound 312 can be ultraviolet
(ultraviolet；UV) or SOC Naked chip 302 and DRAM Naked can be arranged in the polymer of heat cure, polymer conduct
Perhaps then plastic solid solidifies the polymer by UV technique or heat curing process near chip 600 gel.Molding
Material 312 can be with mold curing.
As shown in Figure 1, mixed SOC encapsulation 300a is further comprising: RDL structure 316, is set to 600 He of DRAM Naked chip
On SOC Naked chip 302, in order to which DRAM Naked chip 600 is between SOC Naked chip 302 and RDL structure 316.RDL structure
316 can contact with the TSV interconnection structure 602 of moulding compound 312 and DRAM Naked chip 600.In some embodiments, RDL structure
316, which can have one or more, is set to one or more IMD (Intermetal Dielectric, inter-metal dielectric)
Conducting wire 318 in layer 317.Conducting wire 318 is electrically connected to corresponding RDL engagement pad 320.The exposure of RDL engagement pad 320
In the opening of passivation layer 321.However, it is noted that: the number of the quantity of conducting wire 318 shown in FIG. 1, IMD layer 317
The quantity of amount and RDL engagement pad 320 is only citing, is not intended to restrict the invention.
As shown in Figure 1, mixed SOC encapsulation 300a is further comprising: conductive structure 322, is set in RDL structure 316 remote
Surface from DRAM Naked chip 600 and SOC Naked chip 302.Conductive structure 322 is coupled to conducting wire by RDL engagement pad 320
318.In some embodiments, conductive structure 322 may include: conductive lug structure (such as copper bump or solder projection knot
Structure), conductive pillar structure, conductive line structure or conductive adhesive structure.
As shown in Figure 1, DRAM Naked chip 600 is using TSV interconnection structure 602 and through-hole 308 come by SOC Naked chip 302
Connection pad 304 is connected to the conducting wire 318 of RDL structure 316.In addition, through-hole 310 passes through SOC Naked chip 302 and RDL structure 316
Between moulding compound 312, the connection pad 306 of SOC Naked chip 302 is coupled to the conducting wire of RDL structure 316 by the through-hole 310
318.Through-hole 310 surrounds DRAM Naked chip 600.
As shown in Figure 1, design connection pad 304 and 306 and DRAM Naked chip of the conducting wire 318 from SOC Naked chip 302
One or more of 600 TSV interconnection structure 602 sheds (fan out), to provide SOC Naked chip 302, DRAM Naked chip
Electric connection between 600 and RDL engagement pad 320.Therefore, RDL engagement pad 320 can have the connection pad than SOC Naked chip 302
The bigger engagement pitch (bond pitch) of the TSV interconnection structure 602 of 304 and 306 and DRAM Naked chip 600, this has more
The RDL engagement pad 320 of big engagement pitch is suitable for ball grid array or other encapsulation installation system.
It is encapsulated on 300a as shown in Figure 1, DRAM encapsulates 400a by the SOC that joint technology is stacked on mixing.At one
In embodiment, DRAM encapsulation 400a is with the LPDDR for meeting pin arrangement regular (such as JEDEC LPDDR I/O memory specification)
DRAM (Low-Power Double Data Rate DRAM, low-power consumption Double Data Rate DRAM) encapsulation.DRAM encapsulates 400a packet
It includes: main body 418 and at least one LPDDR DRAM Naked chip, such as it is stacked in three LPDDR DRAM Naked on main body 418
Chip 402,404 and 406.Main body 418 has Naked chip contact surface 420 and the bump contact relative to Naked chip contact surface 420
Face 422.In some embodiments, the I/O pin number of wide I/O DRAM Naked chip is designed as being different from each LPDDR DRAM
The I/O pin number of Naked chip 402,404 and 406.In one embodiment, the I/O pin number of wide I/O DRAM Naked chip
Greater than 8 times of the I/O pin number of each LPDDR DRAM Naked chip 402,404 and 406.In the present embodiment, such as Fig. 1 institute
Show, is installed on the Naked chip contact surface 420 of main body 418 there are three LPDDR DRAM Naked chip 402,404 and 406.LPDDR
DRAM Naked chip 404 is stacked on LPDDR DRAM Naked chip 402 using alite paste (not shown) and LPDDR DRAM Naked
Chip 406 is stacked on LPDDR DRAM Naked chip 404 using alite paste (paste).LPDDR DRAM Naked chip 402,404
Main body 418, such as closing line 414 and 416 can be coupled to by closing line with 406, the both ends of closing line 414 are separately connected metal
The connection pad 408 of pad 424 and LPDDR DRAM Naked chip 402, the both ends of closing line 416 are separately connected metal gasket 426 and LPDDR
The connection pad 410 of DRAM Naked chip 406.But the quantity of the DRAM device of stacking is not limited to disclosed embodiment.Optionally,
Three LPDDR DRAM Naked chip 402,404 and 406 shown in FIG. 1 (side by side) can be arranged side by side.In this way,
LPDDR DRAM Naked chip 402,404 and 406 can be used alite paste and be installed on the Naked chip contact surface 420 of main body 418.
Main body 418 may include: circuit 428 and metal gasket 424,426 and 430.Metal gasket 424 and 426 be set to circuit 428 close to
On the top of Naked chip contact surface 420.Metal gasket 430 be arranged in circuit 428 close to bump contact face 422 bottom it
On.Multiple conductive structures 432 are set on the bump contact face 422 of main body 418, and DRAM encapsulates the circuit 428 and RDL of 400a
The conducting wire 318 of structure 316 realizes internal connection by multiple conductive structure 432.In some embodiments, conductive structure
432 may include: conductive lug structure (such as copper bump or solder tappet structure), conductive pillar structure, conductive line structure or
Conductive adhesive structure.In some embodiments, through-hole 314 passes through the DRAM encapsulation 400a and RDL knot in mixed SOC encapsulation 300a
Moulding compound 312 between structure 316, DRAM encapsulation 400a are coupled to the conducting wire 318 of RDL structure 316 by the through-hole 314.
Through-hole 314 surrounds SOC Naked chip 302 and DRAM Naked chip 600.
In one embodiment, as shown in Figure 1, DRAM encapsulation 400a is further comprising: moulding compound 412, covers main body 418
Naked chip contact surface 420, and (encapsulating) LPDDR DRAM Naked chip 402,404 and 406 is encapsulated, and engagement
Line 414 and 416.
Fig. 2 is the cross-sectional view of the semiconductor package 500b of other embodiments according to the present invention, this is partly led
Body encapsulating structure 500b includes: that SOC encapsulation 300b and the mixed DRAM being stacked on SOC encapsulation 300b are encapsulated
400b.For succinct, in the component that Examples below is related to, the same or similar component in earlier figures 1 is not repeated.Half
Difference between conductor package structure 500a and semiconductor package 500b is: semiconductor package 500b includes: pure
SOC encapsulation 300b and the mixed DRAM encapsulation 400b that is vertically stacked on pure SOC encapsulation 300b.
As shown in Fig. 2, SOC encapsulation 300b is the semiconductor packages containing SOC Naked chip 302 and RDL structure 316.The SOC
Encapsulating 300b does not include any DRAM Naked chip being fully integrated therein.SOC encapsulate 300b in SOC Naked chip 302 by through-hole (such as
Through-hole 310) it is connected to RDL structure 316.The connection pad 304 of SOC Naked chip 302 is contacted with corresponding through-hole 310.It should be noted that
It is that the quantity of SOC Naked chip 302 is not limited to disclosed embodiment.
As shown in Fig. 2, mixed DRAM encapsulation 400b is stacked on SOC by joint technology and encapsulates on 300b.Mixing
DRAM encapsulates 400b as 3 D semiconductor encapsulation, and 3 D semiconductor encapsulation includes: the line being stacked on TSV DRAM encapsulation
The DRAM of engagement is encapsulated.In the present embodiment, mixed DRAM encapsulation 400b is LPDDR DRAM/ wide I/O DRAM mixing envelope
Dress, which includes: LPDDR DRAM Naked chip, meets special pin layout rules
(such as JEDEC LPDDR I/O memory specification)；And width I/O DRAM Naked chip, meet other specific pin arrangement rules
(such as JEDEC wide I/O memory specification).Mixed DRAM encapsulation 400b includes: main body 418, is stacked on main body 418 at least
One LPDDR DRAM Naked chip and at least one width I/O DRAM Naked chip being stacked on main body 418.As shown in Figure 2
Some embodiments in, there are three LPDDR DRAM Naked chips 402,404 and 406 be installed on main body 418 Naked chip contact
On face 420.LPDDR DRAM Naked chip 404 is stacked on LPDDR DRAM Naked chip 402 using alite paste (not shown),
And LPDDR DRAM Naked chip 406 is stacked on LPDDR DRAM Naked chip 404 using alite paste (not shown).LPDDR
DRAM Naked chip 402,404 and 406 is coupled to main body 418, such as closing line 414 and 416 by closing line.But stacking
The quantity of LPDDR DRAM Naked chip is not limited to disclosed embodiment.Optionally, three LPDDR DRAM Naked core shown in Fig. 2
Piece 402,404 and 406 can be abreast arranged.In this way, alite paste can be used in LPDDR DRAM Naked chip 402,404 and 406
To be pasted on the Naked chip contact surface 420 of main body 418.
In one embodiment, as shown in Fig. 2, main body 418 may include: circuit (not shown) and metal gasket 424,426
With 430.Metal gasket 424 and 426 is set to the top of circuit, and the top is close to Naked chip contact surface 420.Metal gasket 430 is arranged
Bottom in circuit, the bottom is close to bump contact face 422.The both ends of closing line 414 are separately connected 424 He of metal gasket
The connection pad 408 of LPDDR DRAM Naked chip 402, the both ends of closing line 416 are separately connected metal gasket 426 and LPDDR DRAM Naked core
The connection pad 410 of piece 406.
In one embodiment, as shown in Fig. 2, mixed DRAM encapsulation 400b is further comprising: moulding compound 412, covering master
The Naked chip contact surface 420 of body 418, and encapsulate LPDDR DRAM Naked chip 402,404 and 406 and 414 He of closing line
416。
As shown in Fig. 2, mixed DRAM encapsulation 400b is further comprising: at least one width I/O DRAM Naked chip, such as two
It is a to be embedded in width I/O DRAM Naked chip 600a and 600b therein.In this embodiment, two wide I/O DRAM Naked chip
600a and 600b is mounted on bump contact face 422 and is coupled to the metal gasket 430 of main body 418.Wide I/O DRAM Naked core
Piece 600a and 600b are arranged side by side.But the quantity and arrangement of wide I/O DRAM Naked chip are not limited to disclosed implementation
Example.Wide I/O DRAM Naked chip 600a and 600b may include: it is corresponding be each passed through wide I/O DRAM Naked chip 600a and
600b and TSV the interconnection structure 602a and 602b formed.TSV the interconnection structure 602a and 602b for being arranged as array can be used for leniently
I/O DRAM Naked chip 600a and 600b transmits I/O letter to LPDDR DRAM Naked chip 402,404 and 406 and/or substrate 200
Number, ground signalling or power signal.TSV interconnection structure 602a and 602b can be designed as meeting pin arrangement rule (such as
JEDEC wide I/O memory specification).It is to be noted that the quantity of the TSV interconnection structure in array is by being used for width I/O DRAM Naked
Depending on the design of chip 600a and 600b and the LPDDR DRAM Naked chip 402,404 and 406 being mounted thereon, and it is unlimited
Scope of disclosure processed.TSV interconnection structure 602a and 602b are coupled to the metal gasket 430 of main body 418.In some embodiments, wide
The I/O pin number of I/O DRAM Naked chip 600a and 600b are designed as being different from any LPDDR DRAM Naked chip 402,404
With 406 I/O pin number.In one embodiment, the I/O pin number of wide I/O DRAM Naked chip 600a and 600b are greater than
8 times of the I/O pin number of any LPDDR DRAM Naked chip 402,404 and 406.
As shown in Fig. 2, mixed DRAM encapsulation 400b further comprises: moulding compound 442 is set to the convex block of main body 418
On contact surface 422.The moulding compound 442 surrounds width I/O DRAM Naked chip 600a and 600b, and fills wide I/O DRAM Naked
Any gap around chip 600a and 600b.Moulding compound 442 is contacted with width I/O DRAM Naked chip 600a and 600b.
As shown in Fig. 2, mixed DRAM encapsulation 400b further comprises: RDL structure 440, the convex block positioned at main body 418 connect
On contacting surface 422.RDL structure 440 is also disposed at LPDDR DRAM Naked chip 402,404 and 406, and width I/O DRAM Naked core
On piece 600a and 600b.Wide I/O DRAM Naked chip 600a and 600b are between main body 418 and RDL structure 440.RDL knot
Structure 440 can be contacted with TSV the interconnection structure 602a and 602b of moulding compound 442 and width I/O DRAM Naked chip 600a and 600b.
RDL structure 440 can have one or more conducting wires 448, which is set to one or more
In a IMD layer 446.Conducting wire 448 is electrically connected to corresponding RDL engagement pad 450.However, it is noted that: Fig. 2 institute
The quantity for the conducting wire 448 shown, the quantity of IMD layer 446 and the quantity of RDL engagement pad 450 are only exemplary rather than the present invention
Limitation.
As shown in Fig. 2, moulding compound of the through-hole 444 across the bump contact face 422 of main body 418 and RDL structure 440
442, LPDDR DRAM Naked chips 402,404 and 406 can be coupled to the RDL engagement pad of RDL structure 440 by the through-hole 444
450.Through-hole 444 surrounds the width I/O DRAM Naked chip 600a and 600b.
As shown in Fig. 2, multiple conductive structures 452 are set on the RDL engagement pad 450 of RDL structure 440, DRAM encapsulation
The conducting wire 448 of 400b encapsulates the conducting wire 318 of the RDL structure 316 of 300b by multiple conductive structure 452 and SOC
Interconnection.In some embodiments, conductive structure 452 may include: conductive lug structure (such as copper bump or solder projection knot
Structure), conductive pillar structure, conductive line structure or conductive adhesive structure.In some embodiments, through-hole 314 is encapsulated across DRAM
Moulding compound between the RDL structure 316 of 400b and SOC encapsulation 300b, DRAM encapsulate the conductive structure 452 of 400b by the through-hole
314 are coupled to the RDL structure 316 of SOC encapsulation 300b.Through-hole 314 surrounds SOC Naked chip 302.
Embodiment provides semiconductor package 500a and 500b.Any in semiconductor package 500a and 500b
Provide the LPDDR DRAM and width I/O DRAM mixing memory integrated using POP semiconductor package.POP semiconductor package
Assembling structure 500a includes: that SOC/ wide I/O DRAM hybrid package 300a and the LPDDR DRAM stacked thereon encapsulate 400a.POP
Semiconductor package 500b includes: the LPDDR/ wide I/O DRAM hybrid package of pure SOC encapsulation 300b and stacking thereon
400b.Semiconductor package 500a and 500b have the advantages that (such as cost effect quickly turns LPDDR DRAM encapsulating structure
Become, etc.) and the advantages of width I/O DRAM encapsulating structure (such as high bandwidth, low-power consumption, etc.).Semiconductor package
500a and 500b can satisfy the demand of cost effect, high bandwidth, low-power consumption and fast transition.
In some embodiments, mixed SOC encapsulation 300a shown in FIG. 1 or pure SOC envelope shown in Fig. 2 are coupled to
The conductive structure for filling 300b is a conductive pillar structure.In some embodiments, which can be made of metal stack,
The metal stack includes: UBM (Under Bump Metallurgy, Underbump metallization) layer (not shown), conductive plunger
(conductive plug) and corresponding weld cap (solder cap).Fig. 3 A~3E is disclosed according to the present invention for illustrating
The cross-sectional view of the method for the manufacture semiconductor packages (such as semiconductor packages 350a~350c) of some embodiments.
As shown in Figure 3A, a carrier 700 is provided.The carrier 700 may be used to provide structural rigidity or for subsequent
The substrate of non-rigid surface sediments.Next, the multiple semiconductor Naked chips 702 being separated from each other of configuration pass through dielectric layer 701
It is affixed to carrier 700.The back side 702a of semiconductor Naked chip 702 is contacted with dielectric layer 701.The top surface of semiconductor Naked chip 702
702b is backwards to carrier 700.In some embodiments, semiconductor Naked chip 702 is to be the same as or similar to Fig. 1 and shown in Fig. 2
The SOC Naked chip of SOC Naked chip 302.
In some embodiments shown in Fig. 3 A, each semiconductor Naked chip 702 all has Naked chip mat 703 and corresponding
Conductive through hole 704.The Naked chip mat 703 of formation is close to top surface 702b.The dielectric layer 706 of formation covers semiconductor Naked chip
702 top surface 702b and partial Naked chip mat 703.Conductive through hole 704 is placed on the position of corresponding Naked chip mat 703,
And the conductive through hole 704 is arranged on the top surface 702b of semiconductor Naked chip 702.Conductive through hole 704 passes through dielectric layer
706.Conductive through hole 704 is contacted and is coupled with the Naked chip mat 703 of semiconductor Naked chip 702.In some other embodiments, until
A few through-hole structure 714 is arranged on carrier 700.In addition, the setting of through-hole structure 714 is on 702 side of semiconductor Naked chip.
Next, as shown in Figure 3B, it can be using moulding compound 712 to carrier 700.Moulding compound 712 can surround semiconductor
Naked chip 702, and the gap around filling semiconductor Naked chip 702.Moulding compound 712 also covers semiconductor Naked chip 702
Top surface 702b and conductive through hole 704.In some other embodiments, moulding compound 712 surrounds through-hole structure 714, leaves through-hole
The top surface 714a of structure 714 is exposed from the top surface 712a of moulding compound 712.In some embodiments, Fig. 1 and molding shown in Fig. 2
Material 312 material and manufacturing process be identical to or similar to moulding compound 712 material and manufacturing process.
Next, as shown in Figure 3 C, RDL structure 716 by depositing operation, photoetching (photolithography) technique,
Anisotropic etching process and electroplating technology and be formed on moulding compound 712 and be coupled to semiconductor Naked chip 702.One
In a little embodiments, RDL structure 716 can have one or more conducting wires being arranged in one or more IMD layers 717
718.In addition, RDL structure can have one or more RDL engagement pads 720 and passivation layer 721.RDL engagement pad 720 with it is corresponding
Conducting wire 718 contact, and covered by passivation layer 721.In some embodiments, Fig. 1 and RDL structure shown in Fig. 2
316 material and manufacturing process is identical or similar to the material and manufacturing process of RDL structure 716.
In some embodiments, as shown in Figure 3 C, before forming RDL structure 716, photoetching process can be used to be formed more
It wears in the face of a opening (not shown), top surface 702b of multiple opening from moulding compound 712 close to the first semiconductor Naked chip 702
It crosses part mouldings material 712 and is formed.Therefore, the conducting wire 718 for also forming the opening of filling moulding compound 712, is led with being coupled to
Electric through-hole 704.In addition, conducting wire 718 is electrically connected to corresponding RDL engagement pad 720.RDL engagement pad 720 is exposed to passivation
The opening (not shown) of layer 721.
Next, conductive pillar structure 726 is formed in RDL structure 716 and is coupled to RDL knot as shown in Fig. 3 C~3D
Structure 716.As shown in Figure 3 C, photoetching process is executed to form photoresist (photoresist) pattern of covering passivation layer 721 (not
It shows).(do not shown next, executing anisotropic etching process with the opening for forming the passivation layer 721 across RDL structure 716
Out).In some embodiments, opening (not shown) is placed in position corresponding with the RDL engagement pad 720 of RDL structure 716.
Then, photoresist pattern is removed from passivation layer 721.Next, executing electroplating technology to form filling opening and (not show
Out) and connect the conductive plunger 719 of RDL engagement pad 720.The conductive plunger 719 of formation protrudes from RDL structure 716.Such as Fig. 3 C
Shown, conductive plunger 719, which has, to be embedded in the lower part of passivation layer 721 and protrudes from the top of passivation layer 721.Conductive plunger
719 top is wider than the lower part of conductive plunger 719.In some embodiments, the width on the top of conductive plunger 719 is at about 2 μm
In the range of~about 5 μm.In some embodiments, the upper and lower part of conductive plunger 719 has same or similar shape.
In some other embodiments, after forming conductive plunger 719, photoresist pattern is removed from passivation layer 721.Cause
This, the width on the top of conductive plunger 719 is substantially equal to the width of the lower part of conductive plunger 719.
Next, as shown in Figure 3D, being returned by photoetching process, solder electroplating technology, photoresist stripping technology and solder
Weld cap 722 is respectively formed on corresponding conductive plunger 719 by stream technique.Next, from the back side of semiconductor Naked chip 702
702a removes carrier 700 and dielectric layer 701 (shown in Fig. 3 C).In some embodiments, conductive plunger 719 and corresponding weldering
Cap 722 is collectively form conductive pillar structure 726.
In some embodiments, the bottom surface 714b of the back side 702a of semiconductor Naked chip 702 and through-hole structure 714 is from mould
The bottom surface 712b exposure of plastics 712.
Next, as shown in FIGURE 3 E, executing separating technology along the score line S1 being placed between semiconductor bare chip 702
RDL structure 716 and moulding compound 712 are cut with S2.After executing separating technology, form independent semiconductor packages 350a,
350b and 350c.For example, each semiconductor packages 350a and 350c includes: the through-hole structure 714 across moulding compound 712.?
In some embodiments, the manufacturing process of the material of Fig. 1 and through-hole shown in Fig. 2 314 is identical to or is similar to through-hole structure 714
Material and manufacturing process.Semiconductor packages 350b manufacture is at without any through-hole structure.It is to be noted that semiconductor package
The quantity of dress is not limited to disclosed embodiment.
Fig. 4 A~4E is the conductive plunger and RDL structure in the conductive pillar structure of disclosed some embodiments according to the present invention
RDL engagement pad shape floor map.In some embodiments, conductive in the plan view shown in Fig. 4 A~4E
Plug 719a~719e can be designed as the shape with the RDL engagement pad 718a~718e for being similar to corresponding RDL structure.One
In a little embodiments, in the plan view shown in Fig. 4 A~4E, conductive plunger 719a~719e of conductive pillar structure can be designed
For the 2 fold rotational symmetry structures that can surround the intermediate point C of conductive plunger 719a~719e and 180 ° of rotations.In some embodiments
In, in the plan view shown in Fig. 4 A, conductive plunger 719a and corresponding RDL engagement pad 718a are square.Shown in Fig. 4 B
Plan view in, conductive plunger 719b and corresponding RDL engagement pad 718b are rectangle.It is conductive in the plan view shown in Fig. 4 C
Plug 719c and corresponding RDL engagement pad 718 are circle.In the plan view shown in Fig. 4 D, conductive plunger 719d and corresponding
RDL engagement pad 718d is ellipse.In the plan view shown in Fig. 4 E, conductive plunger 719e and corresponding RDL engagement pad 718e
For octagonal.
Fig. 5 is the cross-sectional view for disclosing the semiconductor package 500d of some embodiments according to the present invention, should be partly
Conductor package structure 500d includes: the DRAM that the SOC of mixing encapsulates 300d and is stacked on the SOC encapsulation 300d of the mixing
Encapsulate 400a.For succinct, the group same or similar with the component described previously with reference to Fig. 1~2 in omission following embodiment
The description of part.
As shown in figure 5, one between semiconductor package 500a shown in FIG. 1 and semiconductor package 500d is not
Same to be: semiconductor package 500d includes: to be arranged in the first RDL structure 316 far from the first semiconductor Naked chip 302
Conductive pillar structure 326 on face.The conductive pillar structure 326 is coupled to the first RDL structure of corresponding mixed SOC encapsulation 300d
RDL engagement pad 320 in 316.In some embodiments, each conductive pillar structure can be by including conductive plunger 319 and correspondence
Weld cap 324 metal stack composition.In some embodiments, moulding compound 312, through-hole 314 shown in Fig. 5 and the first RDL
The material and manufacturing process of structure 316 are the same as or similar to moulding compound 712 shown in Fig. 3 A~3C, 714 and of through-hole structure
The material and manufacturing process of RDL structure 716.In some embodiments, the material of conductive plunger 319 and weld cap 324 shown in fig. 5
The material and manufacturing process of identical with manufacturing process or the similar conductive plunger 719 shown in Fig. 3 C~3E and weld cap 722.
In addition, conductive plunger 319 is identical or similar in Fig. 4 A~4E with shape of the corresponding RDL engagement pad 320 in plan view
Shown in conductive plunger 719a~719e and corresponding RDL engagement pad 718a~718e in plan view shape.
Fig. 6 is the cross-sectional view for disclosing the semiconductor package 500e of some embodiments according to the present invention, should be partly
Conductor package structure 500e includes: that SOC encapsulation 300e and the mixed DRAM being stacked on SOC encapsulation 300e are encapsulated
400b.For succinct, omit same or similar with the component described previously with reference to Fig. 1~2 and Fig. 5 in following embodiment
Component description.
As shown in fig. 6, one between semiconductor package 500b shown in Fig. 2 and semiconductor package 500e is not
Same to be: semiconductor package 500e includes: to be arranged in the first RDL structure 316 far from the first semiconductor Naked chip 302
Conductive pillar structure 326 on face.The conductive pillar structure 326 is coupled in the first RDL structure 316 of corresponding SOC encapsulation 300e
RDL engagement pad 320.In some embodiments, the conductive pillar structure 326 in semiconductor packages 500e is identical or similar in figure
The conductive pillar structure 326 of semiconductor package 500d shown in 5.In some embodiments, conductive plunger 319 shown in fig. 6
With the material of weld cap 324 is identical with manufacturing process or the similar conductive plunger 719 shown in Fig. 3 C~3E and weld cap 722
Material and manufacturing process.In addition, conductive plunger 319 it is identical with shape of the corresponding RDL engagement pad 320 in plan view or
Conductive plunger 719a~719e and corresponding RDL engagement pad 718a in the similar plan view shown in Fig. 4 A~4E~
The shape of 718e.
In some embodiments, the pure SOC encapsulation or mixed SOC being arranged in semiconductor package encapsulate it
On conductive pillar structure can have following advantages.Conductive pillar structure by include conductive plunger and corresponding weld cap metal stack
It is stacked.The conductive plunger of the conductive pillar structure of formation protrudes from RDL structure, in order to avoid ball bridge (ball bridge) from asking
Topic and warpage of packaging assembly problem.Improve the performance of substrate (printed circuit board).In addition, conductive pillar structure can promote SMT
(surface-mount technology, surface mounting technique) does over again (rework) technique, which is used for wafer
The weld cap of level semiconductor encapsulation.Therefore, the stability of SOC encapsulation and semiconductor package is improved.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all in essence of the invention
Made any modifications, equivalent replacements, and improvements etc., should all be included in the protection scope of the present invention within mind and principle.
Claims (22)
1. a kind of semiconductor package characterized by comprising the first semiconductor packages and be stacked on first semiconductor package
The second semiconductor packages on dress；
Wherein, which includes:
First semiconductor Naked chip；
First dynamic random access memory Naked chip is installed on the first semiconductor Naked chip
First redistribution layer structure is coupled to the first semiconductor Naked chip；And
Conductive pillar structure is arranged on the surface in the first redistribution layer structure far from the first semiconductor Naked chip, wherein
The conductive pillar structure is coupled to the first redistribution layer structure；
Wherein, which includes:
Main body has Naked chip contact surface and the bump contact face relative to the Naked chip contact surface；And
Second dynamic random access memory Naked chip is mounted on the Naked chip contact surface and is coupled to by closing line
The main body；
Wherein, the input/output pin number of the first dynamic random access memory Naked chip be different from second dynamic with
The input/output pin number of machine access storage memory Naked chip.
2. semiconductor package as described in claim 1, which is characterized in that the conductive pillar structure includes: metal stack, should
Metal stack includes: conductive plunger and the weld cap that contacts with the conductive plunger.
3. semiconductor package as claimed in claim 2, which is characterized in that the conductive plunger is square in plan view
Shape, circle, octagonal or ellipse.
4. semiconductor package as claimed in claim 2, which is characterized in that in plan view, which has
With the identical shape of redistribution layer engagement pad in the corresponding first redistribution layer structure.
5. semiconductor package as claimed in claim 2, which is characterized in that in plan view, which is energy
Enough around 2 fold rotational symmetry structures of 180 ° of central point rotations of the conductive plunger.
6. semiconductor package as described in claim 1, which is characterized in that the first dynamic random access memory Naked core
The input/output pin number of piece is greater than the 8 of the input/output pin number of the second dynamic random access memory Naked chip
Times.
7. semiconductor package as described in claim 1, which is characterized in that the first semiconductor Naked chip has first to connect
Pad, the first redistribution layer structure couples to first connection pad；
First semiconductor packages further include:
First through hole is arranged on the first semiconductor Naked chip, and is coupled to first connection pad.
8. semiconductor package as claimed in claim 7, which is characterized in that first semiconductor packages is system on chip envelope
Dress, the first semiconductor Naked chip are system on chip Naked chip；
The first dynamic random access memory Naked chip be coupled to the first through hole on the first semiconductor Naked chip with
And the first redistribution layer structure.
9. semiconductor package as claimed in claim 8, which is characterized in that the first dynamic random access memory Naked core
Piece is arranged between the first semiconductor Naked chip and the first redistribution layer structure.
10. semiconductor package as claimed in claim 8, which is characterized in that first semiconductor packages further include:
Moulding compound, surround the first semiconductor Naked chip and the first dynamic random access memory Naked chip, and with this
First redistribution layer structure, the first semiconductor Naked chip and the first dynamic random access memory Naked chip contact.
11. semiconductor package as claimed in claim 10, which is characterized in that multiple second through-holes pass through this and the second half lead
The moulding compound between body encapsulation and the first redistribution layer structure；Second semiconductor packages passes through multiple second through-hole coupling
The conducting wire being connected in the first redistribution layer structure.
12. semiconductor package as claimed in claim 11, which is characterized in that multiple second through-hole around this first half
Conductor Naked chip.
13. semiconductor package as claimed in claim 10, which is characterized in that multiple third through-holes pass through this and the first half lead
The moulding compound between body Naked chip and the first redistribution layer structure；The first semiconductor Naked chip is logical by multiple third
Hole is coupled to the conducting wire in the first redistribution layer structure.
14. semiconductor package as claimed in claim 13, which is characterized in that multiple third through-hole is first dynamic around this
State random access memory Naked chip.
15. a kind of semiconductor package characterized by comprising the first semiconductor packages and be stacked on first semiconductor
The second semiconductor packages on encapsulation；
Wherein, which includes:
First semiconductor Naked chip；
First redistribution layer structure is coupled to the first semiconductor Naked chip；And
Conductive pillar structure is arranged on the surface in the first redistribution layer structure far from the first semiconductor Naked chip, wherein
The conductive pillar structure is coupled to the first redistribution layer structure；
Wherein, which includes:
Main body has Naked chip contact surface and the bump contact face relative to the Naked chip contact surface；
Second dynamic random access memory Naked chip is mounted on the Naked chip contact surface and is coupled to by closing line
The main body；And
Additional dynamic random access memory Naked chip, is embedded in second semiconductor packages；Wherein, the additional dynamic
Random access memory Naked chip has the through silicon via formed across the additional dynamic random access memory Naked chip mutual
Link structure；
Wherein, the input/output pin number of the additional dynamic random access memory Naked chip is different from second dynamic
The input/output pin number of random access memory Naked chip.
16. semiconductor package as claimed in claim 15, which is characterized in that second semiconductor packages is dynamic random
Access memory package；Dynamic random access memory encapsulation includes: the second redistribution layer structure, and being somebody's turn to do for the main body is arranged in
On bump contact face.
17. semiconductor package as claimed in claim 16, which is characterized in that the additional dynamic random access memory
Naked chip is arranged between the main body and the second redistribution layer structure.
18. semiconductor package as claimed in claim 15, which is characterized in that the conductive pillar structure includes: metal stack,
The metal stack includes: conductive plunger and the weld cap that contacts with the conductive plunger.
19. semiconductor package as claimed in claim 18, which is characterized in that the conductive plunger is square in plan view
Shape, circle, octagonal or ellipse.
20. semiconductor package as claimed in claim 18, which is characterized in that in plan view, conductive plunger tool
Have and the identical shape of redistribution layer engagement pad in the corresponding first redistribution layer structure.
21. semiconductor package as claimed in claim 18, which is characterized in that in plan view, which is
It can be around 2 fold rotational symmetry structures of 180 ° of central point rotations of the conductive plunger.
22. semiconductor package as claimed in claim 15, which is characterized in that further comprise:
Substrate, wherein first semiconductor packages is installed on the substrate by the conductive pillar structure.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201562134128P | 2015-03-17 | 2015-03-17 | |
| US62/134,128 | 2015-03-17 | ||
| US14/932,147 US20160079205A1 (en) | 2014-09-15 | 2015-11-04 | Semiconductor package assembly |
| US14/932,147 | 2015-11-04 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105990326A CN105990326A (en) | 2016-10-05 |
| CN105990326B true CN105990326B (en) | 2019-04-26 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201610140408.8A Expired - Fee Related CN105990326B (en) | 2015-03-17 | 2016-03-11 | Semiconductor packages, semiconductor package and the method for manufacturing semiconductor packages |
Country Status (2)
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| CN (1) | CN105990326B (en) |
| TW (1) | TWI623067B (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20180175004A1 (en) * | 2016-12-18 | 2018-06-21 | Nanya Technology Corporation | Three dimensional integrated circuit package and method for manufacturing thereof |
| CN111599701B (en) * | 2019-06-20 | 2022-08-26 | 矽磐微电子(重庆)有限公司 | Semiconductor packaging method and semiconductor packaging structure |
| US11830800B2 (en) | 2021-03-25 | 2023-11-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metallization structure and package structure |
| CN113594152B (en) * | 2021-07-12 | 2024-03-19 | 南京国博电子股份有限公司 | Three-dimensional integrated module of heavy-current PMOS tube and driver |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102867808A (en) * | 2011-07-06 | 2013-01-09 | 联发科技股份有限公司 | Package structure and method for fabricating the same |
| CN103178047A (en) * | 2011-12-23 | 2013-06-26 | 新科金朋有限公司 | Semiconductor device and method for manufacturing the same |
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| KR101855294B1 (en) * | 2010-06-10 | 2018-05-08 | 삼성전자주식회사 | Semiconductor package |
| US20140159231A1 (en) * | 2011-08-04 | 2014-06-12 | Sony Mobile Communications Ab | Semiconductor assembly |
| US9502360B2 (en) * | 2012-01-11 | 2016-11-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stress compensation layer for 3D packaging |
| US9881894B2 (en) * | 2012-03-08 | 2018-01-30 | STATS ChipPAC Pte. Ltd. | Thin 3D fan-out embedded wafer level package (EWLB) for application processor and memory integration |
| US9553040B2 (en) * | 2012-03-27 | 2017-01-24 | Mediatek Inc. | Semiconductor package |
| US9378982B2 (en) * | 2013-01-31 | 2016-06-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Die package with openings surrounding end-portions of through package vias (TPVs) and package on package (PoP) using the die package |
-
2016
- 2016-03-07 TW TW105106849A patent/TWI623067B/en not_active IP Right Cessation
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102867808A (en) * | 2011-07-06 | 2013-01-09 | 联发科技股份有限公司 | Package structure and method for fabricating the same |
| CN103178047A (en) * | 2011-12-23 | 2013-06-26 | 新科金朋有限公司 | Semiconductor device and method for manufacturing the same |
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| CN105990326A (en) | 2016-10-05 |
| TW201635451A (en) | 2016-10-01 |
| TWI623067B (en) | 2018-05-01 |
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