TWI622041B - Signal masking unit, signal masking method, and display panel - Google Patents

Signal masking unit, signal masking method, and display panel Download PDF

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TWI622041B
TWI622041B TW106128795A TW106128795A TWI622041B TW I622041 B TWI622041 B TW I622041B TW 106128795 A TW106128795 A TW 106128795A TW 106128795 A TW106128795 A TW 106128795A TW I622041 B TWI622041 B TW I622041B
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signal
unit
control signal
voltage level
control
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TW106128795A
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TW201913637A (en
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洪森全
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友達光電股份有限公司
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Priority to CN201711085358.9A priority patent/CN107633803B/en
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Abstract

信號遮罩單元包含重置單元及第一開關單元。重置單元用以接收重置電壓及根據驅動信號接收第一控制信號。第一開關單元用以接收時脈信號及根據驅動信號接收第二控制信號。第二控制信號與第一控制信號反相。當第一控制信號處於第一電壓準位且第二控制信號處於第二電壓準位時,重置單元不作動,第一開關單元被導通並輸出時脈信號。當第一控制信號處於第二電壓準位且第二控制信號處於第一電壓準位時,重置單元輸出工作電壓至第一開關單元,第一開關單元被關斷。 The signal mask unit includes a reset unit and a first switch unit. The reset unit is configured to receive the reset voltage and receive the first control signal according to the driving signal. The first switching unit is configured to receive the clock signal and receive the second control signal according to the driving signal. The second control signal is inverted from the first control signal. When the first control signal is at the first voltage level and the second control signal is at the second voltage level, the reset unit is not activated, and the first switching unit is turned on and outputs the clock signal. When the first control signal is at the second voltage level and the second control signal is at the first voltage level, the reset unit outputs the operating voltage to the first switching unit, and the first switching unit is turned off.

Description

信號遮罩單元、信號遮罩方法及顯示面 板 Signal mask unit, signal mask method and display surface board

本案是有關於一種信號遮罩單元、一種信號遮罩方法及一種顯示面板,且特別是有關於低功耗的信號遮罩單元、信號遮罩方法及顯示面板。 The present invention relates to a signal mask unit, a signal mask method, and a display panel, and particularly to a signal mask unit, a signal mask method, and a display panel for low power consumption.

隨著顯示裝置的快速發展,人們在任何場合任何時間都會使用大大小小的顯示裝置,例如:手機、電腦等。在使用顯示裝置的同時,每次顯示裝置的畫面變動時皆會造成不同的耗電量,而耗電量也直接影響了人們對於使用顯示裝置的更多顧慮。 With the rapid development of display devices, people can use display devices of various sizes at any time, such as mobile phones, computers, etc., at any time. When the display device is used, different power consumption is generated each time the screen of the display device changes, and the power consumption directly affects people's concerns about using the display device.

因此,隨著人們對省電節能的問題日漸重視,如何在不降低顯示裝置的效能的同時,降低顯示裝置的功耗,為本領域待改進的問題之一。 Therefore, as people pay more and more attention to the problem of power saving and energy saving, how to reduce the power consumption of the display device without reducing the performance of the display device is one of the problems to be improved in the field.

本案之一態樣是在提供一種信號遮罩單元。此 信號遮罩單元包含重置單元以及第一開關單元。重置單元用以接收重置電壓及根據驅動信號接收第一控制信號。第一開關單元與重置單元電性連接,用以接收時脈信號及根據驅動信號接收第二控制信號。上述第二控制信號與第一控制信號反相。當第一控制信號處於第一電壓準位且第二控制信號處於第二電壓準位時,重置單元不作動,第二控制信號導通第一開關單元以使第一開關單元輸出時脈信號。當第一控制信號處於第二電壓準位且第二控制信號處於第一電壓準位時,重置單元輸出工作電壓至第一開關單元,工作電壓與第二控制信號關斷第一開關單元。 One aspect of the case is to provide a signal mask unit. this The signal mask unit includes a reset unit and a first switch unit. The reset unit is configured to receive the reset voltage and receive the first control signal according to the driving signal. The first switching unit is electrically connected to the reset unit for receiving the clock signal and receiving the second control signal according to the driving signal. The second control signal is inverted from the first control signal. When the first control signal is at the first voltage level and the second control signal is at the second voltage level, the reset unit is not activated, and the second control signal turns on the first switch unit to cause the first switch unit to output the clock signal. When the first control signal is at the second voltage level and the second control signal is at the first voltage level, the reset unit outputs the operating voltage to the first switching unit, and the operating voltage and the second control signal turn off the first switching unit.

本案之另一態樣是在提供一種信號遮罩方法,用於驅動電路。此信號遮罩方法包含以下步驟:使驅動電路根據驅動信號接收第一控制信號及第二控制信號;使驅動電路接收時脈信號;當第一控制信號處於第一電壓準位且第二控制信號處於第二電壓準位時,使驅動電路輸出時脈信號;以及當第一控制信號處於第二電壓準位且第二控制信號處於第一電壓準位時,使驅動電路停止輸出時脈信號。 Another aspect of the present invention is to provide a signal masking method for driving a circuit. The signal masking method includes the steps of: causing the driving circuit to receive the first control signal and the second control signal according to the driving signal; causing the driving circuit to receive the clock signal; when the first control signal is at the first voltage level and the second control signal When the second voltage level is at the second voltage level, the driving circuit outputs the clock signal; and when the first control signal is at the second voltage level and the second control signal is at the first voltage level, the driving circuit stops outputting the clock signal.

本案之另一態樣是在提供一種顯示面板。此顯示面板包含多條掃描線、多級信號產生器以及多級信號遮罩單元。每一信號產生器分別產生驅動信號,並將驅動信號傳送至下一級信號產生器。多個信號遮罩單元分別耦接於多條掃描線中之一者與多級信號產生器之間。每一級之信號遮罩單元根據相耦接的當級信號產生器所傳送之驅動信號以接收第一控制信號及第二控制信號,其中第二控制信號與第一 控制信號反相,且當第一控制信號處於第一電壓準位且第二控制信號處於第二電壓準位時,當級信號遮罩單元將時脈信號發送至多條掃描線中之一者。 Another aspect of the present invention is to provide a display panel. The display panel includes a plurality of scan lines, a multi-level signal generator, and a multi-level signal mask unit. Each of the signal generators generates a drive signal and transmits the drive signal to the next stage signal generator. The plurality of signal mask units are respectively coupled between one of the plurality of scan lines and the multi-level signal generator. The signal masking unit of each stage receives the first control signal and the second control signal according to the driving signal transmitted by the coupled level signal generator, wherein the second control signal and the first The control signal is inverted, and when the first control signal is at the first voltage level and the second control signal is at the second voltage level, the stage signal mask unit transmits the clock signal to one of the plurality of scan lines.

因此,根據本案之技術態樣,本案之實施例藉由提供一種信號遮罩單元、一種信號遮罩方法及一種顯示面板,且特別是有關於低功耗的信號遮罩單元、信號遮罩方法及顯示面板,藉以有效在不降低顯示裝置的效能的同時,降低顯示裝置的功耗。 Therefore, according to the technical aspect of the present invention, an embodiment of the present invention provides a signal mask unit, a signal mask method, and a display panel, and particularly relates to a signal mask unit and a signal mask method for low power consumption. And the display panel, thereby effectively reducing the power consumption of the display device without reducing the performance of the display device.

100‧‧‧顯示面板 100‧‧‧ display panel

110-1~110-N‧‧‧信號產生器 110-1~110-N‧‧‧Signal Generator

120-1~120-N‧‧‧信號遮罩單元 120-1~120-N‧‧‧Signal Mask Unit

120‧‧‧信號遮罩單元 120‧‧‧Signal mask unit

130‧‧‧主動區域 130‧‧‧Active area

G1~GN‧‧‧掃描線 G1~GN‧‧‧ scan line

En‧‧‧驅動信號 En‧‧‧ drive signal

Vrst‧‧‧重置電壓 Vrst‧‧‧Reset voltage

VDD‧‧‧工作電壓 VDD‧‧‧ working voltage

Vin_1、Vin_2‧‧‧控制信號 Vin_1, Vin_2‧‧‧ control signals

RST1‧‧‧重置單元 RST1‧‧‧Reset unit

T1、T2、T3、T4、T5、T6‧‧‧開關單元 T1, T2, T3, T4, T5, T6‧‧‧ switch units

CLK‧‧‧時脈信號 CLK‧‧‧ clock signal

G[n]‧‧‧掃描線電壓 G[n]‧‧‧ scan line voltage

BT、Q‧‧‧節點 BT, Q‧‧‧ nodes

OUT‧‧‧輸出端 OUT‧‧‧ output

400、500‧‧‧操作波形 400, 500‧‧‧ operating waveforms

P1、P2、P3、P4、P5、P6‧‧‧期間 During P1, P2, P3, P4, P5, P6‧‧

P7、P8、P9、P10、P11、P12‧‧‧期間 During P7, P8, P9, P10, P11, P12‧‧

600‧‧‧信號遮罩方法 600‧‧‧Signal mask method

S610、S620、S630、S640、S650‧‧‧步驟 S610, S620, S630, S640, S650‧‧ steps

為讓本發明之上述和其他目的、特徵、優點與實施例能更明顯易懂,所附圖式之說明如下:第1圖係根據本案之一些實施例所繪示之一種顯示面板的示意圖;第2圖係根據本案之一些實施例所繪示之一種信號遮罩單元的示意圖;第3圖係根據本案之一些實施例所繪示之一種信號遮罩單元的詳細示意圖;以及第4圖係根據本案之一些實施例所繪示之一種操作波形的示意圖;第5圖係依照本案第3圖所示之實施例所繪示之一種信號遮罩單元的操作示意圖;第6圖係依照本案第3圖所示之實施例所繪示之一種信號遮罩單元的操作示意圖; 第7圖係依照本案第3圖所示之實施例所繪示之一種信號遮罩單元的操作示意圖;第8圖係依照本案第3圖所示之實施例所繪示之一種信號遮罩單元的操作示意圖;第9圖係依照本案第3圖所示之實施例所繪示之一種信號遮罩單元的操作示意圖;第10圖係依照本案第3圖所示之實施例所繪示之一種信號遮罩單元的操作示意圖;第11圖係根據本案之一些實施例所繪示之一種操作波形的示意圖;第12圖係依照本案第3圖所示之實施例所繪示之一種信號遮罩單元的操作示意圖;第13圖係依照本案第3圖所示之實施例所繪示之一種信號遮罩單元的操作示意圖;第14圖係依照本案第3圖所示之實施例所繪示之一種信號遮罩單元的操作示意圖;第15圖係依照本案第3圖所示之實施例所繪示之一種信號遮罩單元的操作示意圖;第16圖係依照本案第3圖所示之實施例所繪示之一種信號遮罩單元的操作示意圖;第17圖係依照本案第3圖所示之實施例所繪示之一種信號遮罩單元的操作示意圖;以及第18圖係根據本案之一些實施例所繪示之一種信號遮罩方法的流程圖。 The above and other objects, features, advantages and embodiments of the present invention will become more apparent and understood. The description of the drawings is as follows: FIG. 1 is a schematic view of a display panel according to some embodiments of the present invention; 2 is a schematic diagram of a signal mask unit according to some embodiments of the present invention; FIG. 3 is a detailed schematic diagram of a signal mask unit according to some embodiments of the present disclosure; and FIG. 4 A schematic diagram of an operational waveform according to some embodiments of the present invention; FIG. 5 is a schematic diagram of operation of a signal mask unit according to the embodiment shown in FIG. 3 of the present invention; FIG. 6 is in accordance with the present invention. 3 is a schematic diagram of the operation of a signal mask unit according to the embodiment shown in the figure; Figure 7 is a schematic diagram showing the operation of a signal mask unit according to the embodiment shown in Figure 3 of the present invention; Figure 8 is a signal mask unit according to the embodiment shown in Figure 3 of the present invention. FIG. 9 is a schematic diagram showing the operation of a signal mask unit according to the embodiment shown in FIG. 3 of the present invention; FIG. 10 is a diagram according to the embodiment shown in FIG. 3 of the present invention. FIG. 11 is a schematic diagram showing an operation waveform according to some embodiments of the present invention; and FIG. 12 is a signal mask according to the embodiment shown in FIG. 3 of the present invention. Figure 13 is a schematic view showing the operation of a signal mask unit according to the embodiment shown in Figure 3 of the present invention; Figure 14 is a diagram showing the embodiment shown in Figure 3 of the present invention. FIG. 15 is a schematic diagram showing the operation of a signal mask unit according to the embodiment shown in FIG. 3 of the present invention; and FIG. 16 is an embodiment according to FIG. 3 of the present invention. a signal mask Figure 17 is a schematic diagram showing the operation of a signal mask unit according to the embodiment shown in Figure 3 of the present invention; and Figure 18 is a signal mask according to some embodiments of the present invention. Flow chart of the hood method.

以下揭示提供許多不同實施例或例證用以實施本發明的不同特徵。特殊例證中的元件及配置在以下討論中被用來簡化本揭示。所討論的任何例證只用來作解說的用途,並不會以任何方式限制本發明或其例證之範圍和意義。此外,本揭示在不同例證中可能重複引用數字符號且/或字母,這些重複皆為了簡化及闡述,其本身並未指定以下討論中不同實施例且/或配置之間的關係。 The following disclosure provides many different embodiments or illustrations for implementing different features of the invention. The elements and configurations of the specific illustrations are used in the following discussion to simplify the disclosure. Any examples discussed are for illustrative purposes only and are not intended to limit the scope and meaning of the invention or its examples. In addition, the present disclosure may repeatedly recite numerical symbols and/or letters in different examples, which are for simplicity and elaboration, and do not specify the relationship between the various embodiments and/or configurations in the following discussion.

在全篇說明書與申請專利範圍所使用之用詞(terms),除有特別註明外,通常具有每個用詞使用在此領域中、在此揭露之內容中與特殊內容中的平常意義。某些用以描述本揭露之用詞將於下或在此說明書的別處討論,以提供本領域技術人員在有關本揭露之描述上額外的引導。 The terms used in the entire specification and the scope of the patent application, unless otherwise specified, generally have the ordinary meaning of each term used in the field, the content disclosed herein, and the particular content. Certain terms used to describe the disclosure are discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art in the description of the disclosure.

關於本文中所使用之『耦接』或『連接』,均可指二或多個元件相互直接作實體或電性接觸,或是相互間接作實體或電性接觸,而『耦接』或『連接』還可指二或多個元件相互操作或動作。 "Coupling" or "connecting" as used herein may mean that two or more elements are in direct physical or electrical contact with each other, or indirectly in physical or electrical contact with each other, and "coupled" or " Connections may also mean that two or more elements operate or interact with each other.

在本文中,使用第一、第二與第三等等之詞彙,是用於描述各種元件、組件、區域、層與/或區塊是可以被理解的。但是這些元件、組件、區域、層與/或區塊不應該被這些術語所限制。這些詞彙只限於用來辨別單一元件、組件、區域、層與/或區塊。因此,在下文中的一第一元件、組件、區域、層與/或區塊也可被稱為第二元件、組件、區 域、層與/或區塊,而不脫離本發明的本意。如本文所用,詞彙『與/或』包含了列出的關聯項目中的一個或多個的任何組合。本案文件中提到的「及/或」是指表列元件的任一者、全部或至少一者的任意組合。 The use of the terms first, second, and third, etc., is used to describe various elements, components, regions, layers and/or blocks. However, these elements, components, regions, layers and/or blocks should not be limited by these terms. These terms are only used to identify a single element, component, region, layer, and/or block. Therefore, a first element, component, region, layer and/or block may also be referred to as a second element, component, or region. Domains, layers and/or blocks without departing from the spirit of the invention. As used herein, the term "and/or" encompasses any combination of one or more of the listed associated items. "and/or" as used in this document refers to any combination of any, all or at least one of the listed elements.

請參閱第1圖。第1圖係根據本案之一些實施例所繪示之一種顯示面板100的示意圖。如第1圖所繪示,顯示面板100包含多級信號產生器110-1~110-N、多個信號遮罩單元120-1~120-N、多條掃描線G1~GN以及主動區域130。信號遮罩單元120-1~120-N分別耦接於掃描線G1~GN中之一者與多級信號產生器110-1~110-N中之一者之間。主動區域130耦接於多條掃描線G1~GN。在一些實施例中,多級信號產生器110-1~110-N中之每一者分別產生驅動信號En,並將驅動信號En傳送至多級信號產生器110-1~110-N中之下一級信號產生器。舉例來說,如第1圖所繪示,信號產生器110-1傳送驅動信號En至信號產生器110-2,信號產生器110-2傳送驅動信號En至信號產生器110-3,其餘依此類推。 Please refer to Figure 1. FIG. 1 is a schematic diagram of a display panel 100 according to some embodiments of the present disclosure. As shown in FIG. 1 , the display panel 100 includes multi-level signal generators 110-1 ~ 110-N, a plurality of signal mask units 120-1 ~ 120-N, a plurality of scan lines G1 GN GN, and an active area 130 . . The signal mask units 120-1 120 120-N are respectively coupled between one of the scan lines G1 GN GN and one of the multi-level signal generators 110-1 ~ 110-N. The active area 130 is coupled to the plurality of scan lines G1 GN GN. In some embodiments, each of the multi-level signal generators 110-1~110-N generates a drive signal En and transmits the drive signal En to the multi-level signal generators 110-1~110-N. Primary signal generator. For example, as shown in FIG. 1, the signal generator 110-1 transmits the driving signal En to the signal generator 110-2, and the signal generator 110-2 transmits the driving signal En to the signal generator 110-3. This type of push.

在一些實施例中,舉例來說,僅有當輸出至掃描線G1的掃描線電壓G[n]為低電壓準位時,掃描線G1會更新與掃描線G1相耦接之主動區域130,但本案不以此為限。其餘之掃描線G2~GN依此類推。關於各元件之間的作動,將配合第2圖於以下說明。 In some embodiments, for example, only when the scan line voltage G[n] output to the scan line G1 is at a low voltage level, the scan line G1 updates the active region 130 coupled to the scan line G1. However, this case is not limited to this. The rest of the scan lines G2~GN and so on. The operation between the respective elements will be described below with reference to Fig. 2 .

請參閱第2圖。第2圖係根據本案之一些實施例所繪示之一種信號遮罩單元120的示意圖。在一些實施例 中,第2圖的信號遮罩單元120用以實現第一圖中的信號遮罩單元120-1、120-2、120-3...或120-N。信號遮罩單元120根據相耦接的信號產生器所傳送之驅動信號接收第一控制信號及第二控制信號。第二控制信號與第一控制信號反相。當第一控制信號處於第一電壓準位且第二控制信號處於第二電壓準位時,信號遮罩單元120將時脈信號發送至多條掃描線中G1~GN之一者。舉例來說,第1圖中之信號遮罩單元120-1根據與信號遮罩單元120-1相耦接的信號產生器110-1所傳送之驅動信號En接收第一控制信號Vin_1及第二控制信號Vin_2。當第一控制信號處於第一電壓準位且第二控制信號處於第二電壓準位時,信號遮罩單元120-1將時脈信號CLK發送至掃描線G1。其餘之信號遮罩單元120-2~120-N依此類推。 Please refer to Figure 2. FIG. 2 is a schematic diagram of a signal mask unit 120 according to some embodiments of the present disclosure. In some embodiments The signal mask unit 120 of FIG. 2 is used to implement the signal mask units 120-1, 120-2, 120-3, ... or 120-N in the first figure. The signal mask unit 120 receives the first control signal and the second control signal according to the driving signal transmitted by the coupled signal generator. The second control signal is inverted from the first control signal. When the first control signal is at the first voltage level and the second control signal is at the second voltage level, the signal mask unit 120 transmits the clock signal to one of the plurality of scan lines G1 GN GN. For example, the signal mask unit 120-1 in FIG. 1 receives the first control signal Vin_1 and the second according to the driving signal En transmitted by the signal generator 110-1 coupled to the signal mask unit 120-1. Control signal Vin_2. When the first control signal is at the first voltage level and the second control signal is at the second voltage level, the signal mask unit 120-1 transmits the clock signal CLK to the scan line G1. The rest of the signal mask units 120-2~120-N and so on.

如第2圖所繪示,信號遮罩單元120包含重置單元RST1、開關單元T1、開關單元T2以及開關單元T3。開關單元T1與重置單元RST1電性連接。開關單元T2與重置單元RST1電性連接。開關單元T3與開關單元T1電性連接。 As shown in FIG. 2, the signal mask unit 120 includes a reset unit RST1, a switch unit T1, a switch unit T2, and a switch unit T3. The switch unit T1 is electrically connected to the reset unit RST1. The switch unit T2 is electrically connected to the reset unit RST1. The switch unit T3 is electrically connected to the switch unit T1.

重置單元RST1接收重置電壓Vrst及根據驅動信號En以決定是否接收控制信號Vin_1。開關單元T1接收時脈信號CLK及根據驅動信號En以決定是否接收控制信號Vin_2。上述控制信號Vin_1與控制信號Vin_2反相。當控制信號Vin_1處於第一電壓準位且控制信號Vin_2處於第二電壓準位時,重置單元RST1不作動,且控制信號Vin_2導通開關單元T1以使開關單元T1輸出時脈信號CLK至如 第1圖所繪示之多條掃描線G1~GN中之一者。當控制信號Vin_1處於第二電壓準位且控制信號Vin_2處於第一電壓準位時,重置單元RST1輸出工作電壓VDD至開關單元T1,工作電壓VDD與控制信號Vin_2關斷開關單元T1。 The reset unit RST1 receives the reset voltage Vrst and determines whether to receive the control signal Vin_1 according to the drive signal En. The switching unit T1 receives the clock signal CLK and determines whether to receive the control signal Vin_2 according to the driving signal En. The control signal Vin_1 is inverted from the control signal Vin_2. When the control signal Vin_1 is at the first voltage level and the control signal Vin_2 is at the second voltage level, the reset unit RST1 is not activated, and the control signal Vin_2 turns on the switching unit T1 to cause the switching unit T1 to output the clock signal CLK to One of the plurality of scanning lines G1 to GN shown in FIG. When the control signal Vin_1 is at the second voltage level and the control signal Vin_2 is at the first voltage level, the reset unit RST1 outputs the operating voltage VDD to the switching unit T1, and the operating voltage VDD and the control signal Vin_2 turn off the switching unit T1.

在一些實施中,開關單元T2接收控制信號Vin_1並根據驅動信號En導通控制信號Vin_1至重置單元RST1。開關單元T3接收控制信號Vin_2並根據驅動信號En導通控制信號Vin_2至開關單元T1。 In some implementations, the switching unit T2 receives the control signal Vin_1 and turns on the control signal Vin_1 to the reset unit RST1 according to the driving signal En. The switching unit T3 receives the control signal Vin_2 and turns on the control signal Vin_2 to the switching unit T1 according to the driving signal En.

請參見第3圖。第3圖係根據本案之一些實施例所繪示之一種信號遮罩單元120的詳細示意圖。如第3圖所繪示,在一些實施例中,開關單元T1具有控制端及輸出端。控制端用以接收控制信號Vin_2,輸出端用以輸出時脈信號CLK。重置單元RST1分別與控制端及輸出端電性連接以根據控制信號Vin_1選擇性輸出工作電壓VDD至開關單元T1的控制端及輸出端。 See Figure 3. FIG. 3 is a detailed schematic diagram of a signal mask unit 120 according to some embodiments of the present disclosure. As shown in FIG. 3, in some embodiments, the switching unit T1 has a control terminal and an output terminal. The control terminal is configured to receive the control signal Vin_2, and the output terminal is configured to output the clock signal CLK. The resetting unit RST1 is electrically connected to the control end and the output end respectively to selectively output the operating voltage VDD to the control end and the output end of the switching unit T1 according to the control signal Vin_1.

如第3圖所繪示,在一些實施例中,重置單元RST1包含開關單元T4、開關單元T5、開關單元T6與電容器C1。開關單元T4用以接收重置電壓Vrst。開關單元T5用以接收重置電壓Vrst。開關單元T5的控制端用以接收控制信號Vin_1並與開關單元T4電性連接以接收重置電壓Vrst。開關單元T6接收重置電壓Vrst,開關單元T6具有控制端及輸出端,開關單元T6的控制端與開關單元T5的控制端電性連接,開關單元T6的輸出端與開關單元T1的輸出端電性連接。電容器C1與開關單元T5的控制端電性連接並用 以接收重置電壓Vrst。 As shown in FIG. 3, in some embodiments, the reset unit RST1 includes a switching unit T4, a switching unit T5, a switching unit T6, and a capacitor C1. The switching unit T4 is configured to receive the reset voltage Vrst. The switching unit T5 is configured to receive the reset voltage Vrst. The control terminal of the switch unit T5 is configured to receive the control signal Vin_1 and is electrically connected to the switch unit T4 to receive the reset voltage Vrst. The switch unit T6 receives the reset voltage Vrst, and the switch unit T6 has a control end and an output end. The control end of the switch unit T6 is electrically connected to the control end of the switch unit T5, and the output end of the switch unit T6 and the output end of the switch unit T1 are electrically connected. Sexual connection. The capacitor C1 is electrically connected to the control end of the switch unit T5 and used To receive the reset voltage Vrst.

在一些實施例中,當重置電壓Vrst與控制信號Vin_1導通開關單元T4、開關單元T5以及開關單元T6時,工作電壓VDD被導通至開關單元T1的控制端及輸出端以使開關單元T1的控制端及輸出端具有第一電壓準位。 In some embodiments, when the reset voltage Vrst and the control signal Vin_1 turn on the switching unit T4, the switching unit T5, and the switching unit T6, the operating voltage VDD is turned on to the control terminal and the output terminal of the switching unit T1 to make the switching unit T1 The control terminal and the output terminal have a first voltage level.

如第3圖所繪示,在一些實施例中,開關單元T1~T6為P型金屬氧化物半導體場效電晶體(PMOSFET)。然本案不以第3圖之實施例為限。 As shown in FIG. 3, in some embodiments, the switching units T1 T T6 are P-type metal oxide semiconductor field effect transistors (PMOSFETs). However, this case is not limited to the embodiment of Figure 3.

請參閱第4圖。第4圖係根據本案之一些實施例所繪示之一種操作波形400的示意圖。如第4圖所繪式,於期間P1~P6,控制信號Vin_1均為高電壓準位,而控制信號Vin_2均為低電壓準位。關於第4圖的詳細內容將配合第5圖~第10圖於以下進行說明。 Please refer to Figure 4. 4 is a schematic diagram of an operational waveform 400 depicted in accordance with some embodiments of the present disclosure. As shown in Fig. 4, during the period P1~P6, the control signal Vin_1 is at the high voltage level, and the control signal Vin_2 is at the low voltage level. The details of Fig. 4 will be described below with reference to Figs. 5 to 10 .

請參閱第5圖。第5圖係依照本案第3圖所示之實施例所繪示之一種信號遮罩單元120的操作示意圖。請一併參閱第4圖與第5圖。於期間P1,驅動信號En為高電壓準位,因此開關單元T2與開關單元T3皆不導通。重置電壓Vrst為低電壓準位,開關單元T4因此導通,使得節點Q為低電壓準位,開關單元T5與開關單元T6皆導通。由於開關單元T5與開關單元T6皆導通,工作電壓VDD透過開關單元T5與開關單元T6提供至節點BT及輸出端OUT,此時節點BT為高電壓準位,因此開關單元T1不導通。信號遮罩單元120並未將時脈信號CLK輸出至多條掃描線G1~GN中之一者,而掃描線電壓G[n]為高電壓準位,因此多條掃描線G1~GN中 之一者並未更新與多條掃描線G1~GN中之一者相耦接之主動區域130。 Please refer to Figure 5. Figure 5 is a schematic view showing the operation of a signal mask unit 120 according to the embodiment shown in Figure 3 of the present invention. Please refer to Figure 4 and Figure 5 together. During the period P1, the driving signal En is at a high voltage level, so neither the switching unit T2 nor the switching unit T3 is turned on. The reset voltage Vrst is at a low voltage level, and the switching unit T4 is thus turned on, so that the node Q is at a low voltage level, and the switching unit T5 and the switching unit T6 are both turned on. Since the switching unit T5 and the switching unit T6 are both turned on, the operating voltage VDD is supplied to the node BT and the output terminal OUT through the switching unit T5 and the switching unit T6. At this time, the node BT is at a high voltage level, so the switching unit T1 is not turned on. The signal mask unit 120 does not output the clock signal CLK to one of the plurality of scan lines G1 GN GN, and the scan line voltage G[n] is a high voltage level, and thus the plurality of scan lines G1 GN GN One of the active areas 130 coupled to one of the plurality of scan lines G1 GN is not updated.

請參閱第6圖。第6圖係依照本案第3圖所示之實施例所繪示之一種信號遮罩單元120的操作示意圖。請一併參閱第4圖與第6圖。於期間P2,驅動信號En為低電壓準位,因此開關單元T2與開關單元T3皆導通。高電壓準位的控制信號Vin_1透過開關單元T2提供至節點Q,因此節點Q為高電壓準位。低電壓準位的控制信號Vin_2透過開關單元T3提供至節點BT,因此節點BT為低電壓準位。重置電壓Vrst為高電壓準位,因此開關單元T4不導通。由於節點Q為高電壓準位,節點BT為低電壓準位,因此開關單元T5與開關單元T6不導通,而開關單元T1導通,信號遮罩單元120將時脈信號CLK輸出至多條掃描線G1~GN中之一者。此時,時脈信號CLK為高電壓準位,因此多條掃描線G1~GN中之一者並未更新與多條掃描線G1~GN中之一者相耦接之主動區域130。 Please refer to Figure 6. Figure 6 is a schematic diagram showing the operation of a signal mask unit 120 according to the embodiment shown in Figure 3 of the present invention. Please refer to Figure 4 and Figure 6 together. During the period P2, the driving signal En is at a low voltage level, so the switching unit T2 and the switching unit T3 are both turned on. The high voltage level control signal Vin_1 is supplied to the node Q through the switching unit T2, so the node Q is at a high voltage level. The low voltage level control signal Vin_2 is supplied to the node BT through the switching unit T3, so the node BT is at a low voltage level. The reset voltage Vrst is at a high voltage level, so the switching unit T4 is not turned on. Since the node Q is at a high voltage level, the node BT is at a low voltage level, so the switching unit T5 and the switching unit T6 are not turned on, and the switching unit T1 is turned on, and the signal mask unit 120 outputs the clock signal CLK to the plurality of scanning lines G1. One of ~GN. At this time, the clock signal CLK is at a high voltage level, and therefore one of the plurality of scan lines G1 to GN does not update the active region 130 coupled to one of the plurality of scan lines G1 to GN.

請參閱第7圖。第7圖係依照本案第3圖所示之實施例所繪示之一種信號遮罩單元120的操作示意圖。請一併參閱第4圖與第7圖。於期間P3,驅動信號En為高電壓準位,因此開關單元T2與開關單元T3皆不導通。重置電壓Vrst為高電壓準位,因此開關單元T4不導通。工作電壓VDD透過電容C1提供至節點Q,因此節點Q為高電壓準位,使得開關單元T5與開關單元T6不導通。節點BT為低電壓準位,開關單元T1導通。信號遮罩單元120將時脈信號CLK輸出至 多條掃描線G1~GN中之一者。此時,時脈信號CLK為低電壓準位,因此多條掃描線G1~GN中之一者更新與多條掃描線G1~GN中之一者相耦接之主動區域130。 Please refer to Figure 7. Figure 7 is a schematic view showing the operation of a signal mask unit 120 according to the embodiment shown in Figure 3 of the present invention. Please refer to Figure 4 and Figure 7 together. During the period P3, the driving signal En is at a high voltage level, so neither the switching unit T2 nor the switching unit T3 is turned on. The reset voltage Vrst is at a high voltage level, so the switching unit T4 is not turned on. The operating voltage VDD is supplied to the node Q through the capacitor C1, so the node Q is at a high voltage level, so that the switching unit T5 and the switching unit T6 are not turned on. The node BT is at a low voltage level, and the switching unit T1 is turned on. The signal mask unit 120 outputs the clock signal CLK to One of the plurality of scanning lines G1 to GN. At this time, the clock signal CLK is at a low voltage level, and therefore one of the plurality of scanning lines G1 to GN updates the active region 130 coupled to one of the plurality of scanning lines G1 to GN.

請參閱第8圖。第8圖係依照本案第3圖所示之實施例所繪示之一種信號遮罩單元120的操作示意圖。請一併參閱第4圖與第8圖。於期間P4,驅動信號En為高電壓準位,因此開關單元T2與開關單元T3皆不導通。重置電壓Vrst為低電壓準位,因此開關單元T4導通。由於開關單元T4導通,因此節點Q為低電壓準位,使得開關單元T5與開關單元T6導通。工作電壓VDD透過開關單元T5提供至節點BT,因此節點BT為高電壓準位,使得開關單元T1不導通。工作電壓VDD透過開關單元T6提供至輸出端OUT,因此輸出端OUT為高電壓準位。信號遮罩單元120並未將時脈信號CLK輸出至多條掃描線G1~GN中之一者,且掃描線電壓G[n]為高電壓準位,因此多條掃描線G1~GN中之一者並未更新與多條掃描線G1~GN中之一者相耦接之主動區域130。 Please refer to Figure 8. Figure 8 is a schematic view showing the operation of a signal mask unit 120 according to the embodiment shown in Figure 3 of the present invention. Please refer to Figure 4 and Figure 8 together. During the period P4, the driving signal En is at a high voltage level, so neither the switching unit T2 nor the switching unit T3 is turned on. The reset voltage Vrst is at a low voltage level, so the switching unit T4 is turned on. Since the switching unit T4 is turned on, the node Q is at a low voltage level, so that the switching unit T5 and the switching unit T6 are turned on. The operating voltage VDD is supplied to the node BT through the switching unit T5, so the node BT is at a high voltage level, so that the switching unit T1 is not turned on. The operating voltage VDD is supplied to the output terminal OUT through the switching unit T6, so the output terminal OUT is at a high voltage level. The signal mask unit 120 does not output the clock signal CLK to one of the plurality of scan lines G1 GN GN, and the scan line voltage G[n] is a high voltage level, and thus one of the plurality of scan lines G1 GN GN The active area 130 coupled to one of the plurality of scan lines G1 GN GN is not updated.

請參閱第9圖。第9圖係依照本案第3圖所示之實施例所繪示之一種信號遮罩單元120的操作示意圖。請一併參閱第4圖與第9圖。於期間P5,驅動信號En為高電壓準位,因此開關單元T2與開關單元T3皆不導通。重置電壓Vrst為高電壓準位,因此開關單元T4不導通,節點Q維持在低電壓準位,使得開關單元T5與開關單元T6導通,工作電壓VDD透過開關單元T5提供至節點BT,因此節點BT為高電 壓準位。節點BT為高電壓準位,因此開關單元T1不導通。工作電壓VDD透過開關單元T6提供至輸出端OUT,因此輸出端OUT為高電壓準位。信號遮罩單元120並未將時脈信號CLK輸出至多條掃描線G1~GN中之一者,且掃描線電壓G[n]為高電壓準位,因此多條掃描線G1~GN中之一者並未更新與多條掃描線G1~GN中之一者相耦接之主動區域130。 Please refer to Figure 9. Figure 9 is a schematic view showing the operation of a signal mask unit 120 according to the embodiment shown in Figure 3 of the present invention. Please refer to Figure 4 and Figure 9 together. During the period P5, the driving signal En is at a high voltage level, so neither the switching unit T2 nor the switching unit T3 is turned on. The reset voltage Vrst is at a high voltage level, so the switching unit T4 is not turned on, the node Q is maintained at a low voltage level, so that the switching unit T5 and the switching unit T6 are turned on, and the operating voltage VDD is supplied to the node BT through the switching unit T5, so the node BT is high power Pressure level. The node BT is at a high voltage level, so the switching unit T1 is not turned on. The operating voltage VDD is supplied to the output terminal OUT through the switching unit T6, so the output terminal OUT is at a high voltage level. The signal mask unit 120 does not output the clock signal CLK to one of the plurality of scan lines G1 GN GN, and the scan line voltage G[n] is a high voltage level, and thus one of the plurality of scan lines G1 GN GN The active area 130 coupled to one of the plurality of scan lines G1 GN GN is not updated.

請參閱第10圖。第10圖係依照本案第3圖所示之實施例所繪示之一種信號遮罩單元120的操作示意圖。請一併參閱第4圖與第10圖。於期間P6,驅動信號En為高電壓準位,因此開關單元T2與開關單元T3皆不導通。重置電壓Vrst為高電壓準位,因此開關單元T4不導通,節點Q維持在低電壓準位。節點Q為低電壓準位,因此開關單元T5與開關單元T6導通,工作電壓VDD透過開關單元T5提供至節點BT,因此節點BT為高電壓準位,使得開關單元T1不導通。工作電壓VDD透過開關單元T6提供至輸出端OUT,因此輸出端OUT為高電壓準位。信號遮罩單元120並未將時脈信號CLK輸出至多條掃描線G1~GN中之一者。因此,即使在期間P6時時脈信號CLK為低電壓準位,由於信號遮罩單元120並未將時脈信號CLK輸出至多條掃描線G1~GN中之一者,掃描線電壓G[n]為高電壓準位,因此多條掃描線G1~GN中之一者並未更新與多條掃描線G1~GN中之一者相耦接之主動區域130。 Please refer to Figure 10. Figure 10 is a schematic view showing the operation of a signal mask unit 120 according to the embodiment shown in Figure 3 of the present invention. Please refer to Figure 4 and Figure 10 together. During the period P6, the driving signal En is at a high voltage level, so neither the switching unit T2 nor the switching unit T3 is turned on. The reset voltage Vrst is at a high voltage level, so the switching unit T4 is not turned on, and the node Q is maintained at a low voltage level. The node Q is at a low voltage level, so the switching unit T5 is turned on and the switching unit T6 is turned on, and the operating voltage VDD is supplied to the node BT through the switching unit T5, so the node BT is at a high voltage level, so that the switching unit T1 is not turned on. The operating voltage VDD is supplied to the output terminal OUT through the switching unit T6, so the output terminal OUT is at a high voltage level. The signal mask unit 120 does not output the clock signal CLK to one of the plurality of scanning lines G1 to GN. Therefore, even if the clock signal CLK is at a low voltage level during the period P6, since the signal mask unit 120 does not output the clock signal CLK to one of the plurality of scanning lines G1 to GN, the scanning line voltage G[n] The high voltage level is such that one of the plurality of scan lines G1 GN GN does not update the active area 130 coupled to one of the plurality of scan lines G1 GN GN.

請參閱第11圖。第11圖係根據本案之一些實施 例所繪示之一種操作波形500的示意圖。如第11圖所繪式,於期間P7~P12,控制信號Vin_1均為低電壓準位,而控制信號Vin_2均為高電壓準位。關於第11圖的詳細內容將配合第12圖~第17圖於以下說明。 Please refer to Figure 11. Figure 11 is based on some implementations of this case. A schematic diagram of an operational waveform 500 is illustrated. As shown in Fig. 11, during the period P7~P12, the control signal Vin_1 is at a low voltage level, and the control signal Vin_2 is at a high voltage level. The details of Fig. 11 will be described below in conjunction with Figs. 12 to 17 .

請參閱第12圖。第12圖係依照本案第3圖所示之實施例所繪示之一種信號遮罩單元120的操作示意圖。請一併參閱第11圖與第12圖。於期間P7,驅動信號En為高電壓準位,因此開關單元T2與開關單元T3皆不導通。重置電壓Vrst為低電壓準位,因此開關單元T4導通,節點Q為低電壓準位,使得開關單元T5與開關單元T6導通,工作電壓VDD透過開關單元T5提供至節點BT,因此節點BT為高電壓準位,因此開關單元T1不導通。工作電壓VDD透過開關單元T6提供至輸出端OUT,因此輸出端OUT為高電壓準位。信號遮罩單元120並未將時脈信號CLK輸出至多條掃描線G1~GN中之一者,而掃描線電壓G[n]為高電壓準位,因此多條掃描線G1~GN中之一者並未更新與多條掃描線G1~GN中之一者相耦接之主動區域130。 Please refer to Figure 12. Figure 12 is a schematic diagram showing the operation of a signal mask unit 120 according to the embodiment shown in Figure 3 of the present invention. Please refer to Figure 11 and Figure 12 together. During the period P7, the driving signal En is at a high voltage level, so neither the switching unit T2 nor the switching unit T3 is turned on. The reset voltage Vrst is at a low voltage level, so the switching unit T4 is turned on, the node Q is at a low voltage level, so that the switching unit T5 and the switching unit T6 are turned on, and the operating voltage VDD is supplied to the node BT through the switching unit T5, so the node BT is The high voltage level is such that the switching unit T1 is not turned on. The operating voltage VDD is supplied to the output terminal OUT through the switching unit T6, so the output terminal OUT is at a high voltage level. The signal mask unit 120 does not output the clock signal CLK to one of the plurality of scan lines G1 GN GN, and the scan line voltage G[n] is a high voltage level, and thus one of the plurality of scan lines G1 GN GN The active area 130 coupled to one of the plurality of scan lines G1 GN GN is not updated.

請參閱第13圖。第13圖係依照本案第3圖所示之實施例所繪示之一種信號遮罩單元120的操作示意圖。請一併參閱第11圖與第13圖。於期間P8,驅動信號En為低電壓準位,因此開關單元T2與開關單元T3皆導通。重置電壓Vrst為高電壓準位,因此開關單元T4不導通。低電壓準位的控制信號Vin_1透過開關單元T2提供至節點Q,因此節點Q為低電壓準位。高電壓準位的控制信號Vin_2透過開關單元 T3提供至節點BT,因此節點BT為高電壓準位。由於節點Q為低電壓準位,節點BT為高電壓準位,因此開關單元T5與開關單元T6導通,而開關單元T1不導通。工作電壓VDD透過開關單元T6提供至輸出端OUT,因此輸出端OUT為高電壓準位。信號遮罩單元120並未將時脈信號CLK輸出至多條掃描線G1~GN中之一者。此時,掃描線電壓G[n]為高電壓準位,因此多條掃描線G1~GN中之一者並未更新與多條掃描線G1~GN中之一者相耦接之主動區域130。 Please refer to Figure 13. Figure 13 is a schematic view showing the operation of a signal mask unit 120 according to the embodiment shown in Figure 3 of the present invention. Please refer to Figure 11 and Figure 13 together. During the period P8, the driving signal En is at a low voltage level, so the switching unit T2 and the switching unit T3 are both turned on. The reset voltage Vrst is at a high voltage level, so the switching unit T4 is not turned on. The low voltage level control signal Vin_1 is supplied to the node Q through the switching unit T2, so the node Q is at a low voltage level. High voltage level control signal Vin_2 through switching unit T3 is provided to node BT, so node BT is at a high voltage level. Since the node Q is at a low voltage level, the node BT is at a high voltage level, so the switching unit T5 and the switching unit T6 are turned on, and the switching unit T1 is not turned on. The operating voltage VDD is supplied to the output terminal OUT through the switching unit T6, so the output terminal OUT is at a high voltage level. The signal mask unit 120 does not output the clock signal CLK to one of the plurality of scanning lines G1 to GN. At this time, the scan line voltage G[n] is a high voltage level, and therefore one of the plurality of scan lines G1 GN GN does not update the active area 130 coupled to one of the plurality of scan lines G1 GN GN .

請參閱第14圖。第14圖係依照本案第3圖所示之實施例所繪示之一種信號遮罩單元120的操作示意圖。請一併參閱第11圖與第14圖。於期間P9,驅動信號En為高電壓準位,因此開關單元T2與開關單元T3皆不導通。重置電壓Vrst為高電壓準位,因此開關單元T4不導通,節點Q為低電壓準位,使得開關單元T5與開關單元T6導通。工作電壓VDD透過開關單元T5提供至節點BT,因此節點BT為高電壓準位。節點BT為高電壓準位,因此開關單元T1不導通。工作電壓VDD透過開關單元T6提供至輸出端OUT,因此輸出端OUT為高電壓準位。信號遮罩單元120並未將時脈信號CLK輸出至多條掃描線G1~GN中之一者。因此,即使在期間P12時時脈信號CLK為低電壓準位,由於信號遮罩單元120並未將時脈信號CLK輸出至多條掃描線G1~GN中之一者,此時掃描線電壓G[n]為高電壓準位,因此多條掃描線G1~GN中之一者並未更新與多條掃描線G1~GN中之一者相耦接之主動區域130。 Please refer to Figure 14. Figure 14 is a schematic view showing the operation of a signal mask unit 120 according to the embodiment shown in Figure 3 of the present invention. Please refer to Figure 11 and Figure 14 together. During the period P9, the driving signal En is at a high voltage level, so neither the switching unit T2 nor the switching unit T3 is turned on. The reset voltage Vrst is at a high voltage level, so the switching unit T4 is not turned on, and the node Q is at a low voltage level, so that the switching unit T5 and the switching unit T6 are turned on. The operating voltage VDD is supplied to the node BT through the switching unit T5, so the node BT is at a high voltage level. The node BT is at a high voltage level, so the switching unit T1 is not turned on. The operating voltage VDD is supplied to the output terminal OUT through the switching unit T6, so the output terminal OUT is at a high voltage level. The signal mask unit 120 does not output the clock signal CLK to one of the plurality of scanning lines G1 to GN. Therefore, even if the clock signal CLK is at a low voltage level during the period P12, since the signal mask unit 120 does not output the clock signal CLK to one of the plurality of scanning lines G1 to GN, the scanning line voltage G[ n] is a high voltage level, and therefore one of the plurality of scanning lines G1 to GN does not update the active area 130 coupled to one of the plurality of scanning lines G1 to GN.

請參閱第15圖。第15圖係依照本案第3圖所示之實施例所繪示之一種信號遮罩單元120的操作示意圖。請一併參閱第11圖與第15圖。於期間P10,驅動信號En為高電壓準位,因此開關單元T2與開關單元T3皆不導通。重置電壓Vrst為低電壓準位,因此開關單元T4導通。重置電壓Vrst透過開關單元T4提供至節點Q,因此節點Q為低電壓準位,使得開關單元T5與開關單元T6導通。工作電壓VDD透過開關單元T5提供至節點BT,因此節點BT為高電壓準位。節點BT為高電壓準位,因此開關單元T1不導通。工作電壓VDD透過開關單元T6提供至輸出端OUT,因此輸出端OUT為高電壓準位。信號遮罩單元120並未將時脈信號CLK輸出至多條掃描線G1~GN中之一者。此時,掃描線電壓G[n]為高電壓準位,因此多條掃描線G1~GN中之一者並未更新與多條掃描線G1~GN中之一者相耦接之主動區域130。 Please refer to Figure 15. Figure 15 is a schematic view showing the operation of a signal mask unit 120 according to the embodiment shown in Figure 3 of the present invention. Please refer to Figure 11 and Figure 15 together. During the period P10, the driving signal En is at a high voltage level, so neither the switching unit T2 nor the switching unit T3 is turned on. The reset voltage Vrst is at a low voltage level, so the switching unit T4 is turned on. The reset voltage Vrst is supplied to the node Q through the switching unit T4, so the node Q is at a low voltage level, so that the switching unit T5 and the switching unit T6 are turned on. The operating voltage VDD is supplied to the node BT through the switching unit T5, so the node BT is at a high voltage level. The node BT is at a high voltage level, so the switching unit T1 is not turned on. The operating voltage VDD is supplied to the output terminal OUT through the switching unit T6, so the output terminal OUT is at a high voltage level. The signal mask unit 120 does not output the clock signal CLK to one of the plurality of scanning lines G1 to GN. At this time, the scan line voltage G[n] is a high voltage level, and therefore one of the plurality of scan lines G1 GN GN does not update the active area 130 coupled to one of the plurality of scan lines G1 GN GN .

請參閱第16圖。第16圖係依照本案第3圖所示之實施例所繪示之一種信號遮罩單元120的操作示意圖。請一併參閱第11圖與第16圖。於期間P11,驅動信號En為高電壓準位,因此開關單元T2與開關單元T3皆不導通。重置電壓Vrst為高電壓準位,因此開關單元T4不導通,節點Q為低電壓準位,使得開關單元T5與開關單元T6導通。工作電壓VDD透過開關單元T5提供至節點BT,因此節點BT為高電壓準位,使得開關單元T1不導通。工作電壓VDD透過開關單元T6提供至輸出端OUT,因此輸出端OUT為高電壓準位。信號遮罩單元120並未將時脈信號CLK輸出至多條掃 描線G1~GN中之一者。此時,掃描線電壓G[n]為高電壓準位,因此多條掃描線G1~GN中之一者並未更新與多條掃描線G1~GN中之一者相耦接之主動區域130。 Please refer to Figure 16. Figure 16 is a schematic view showing the operation of a signal mask unit 120 according to the embodiment shown in Figure 3 of the present invention. Please refer to Figure 11 and Figure 16 together. During the period P11, the driving signal En is at a high voltage level, so neither the switching unit T2 nor the switching unit T3 is turned on. The reset voltage Vrst is at a high voltage level, so the switching unit T4 is not turned on, and the node Q is at a low voltage level, so that the switching unit T5 and the switching unit T6 are turned on. The operating voltage VDD is supplied to the node BT through the switching unit T5, so the node BT is at a high voltage level, so that the switching unit T1 is not turned on. The operating voltage VDD is supplied to the output terminal OUT through the switching unit T6, so the output terminal OUT is at a high voltage level. The signal mask unit 120 does not output the clock signal CLK to multiple sweeps One of the lines G1 to GN. At this time, the scan line voltage G[n] is a high voltage level, and therefore one of the plurality of scan lines G1 GN GN does not update the active area 130 coupled to one of the plurality of scan lines G1 GN GN .

請參閱第17圖。第17圖係依照本案第3圖所示之實施例所繪示之一種信號遮罩單元120的操作示意圖。請一併參閱第11圖與第17圖。於期間P12,驅動信號En為高電壓準位,因此開關單元T2與開關單元T3皆不導通。重置電壓Vrst為高電壓準位,因此開關單元T4不導通,節點Q為低電壓準位,使得開關單元T5與開關單元T6導通。工作電壓VDD透過開關單元T5提供至節點BT,因此節點BT為高電壓準位。節點BT為高電壓準位,因此開關單元T1不導通。工作電壓VDD透過開關單元T6提供至輸出端OUT,因此輸出端OUT為高電壓準位。信號遮罩單元120並未將時脈信號CLK輸出至多條掃描線G1~GN中之一者。因此,即使在期間P12時時脈信號CLK為低電壓準位,由於信號遮罩單元120並未將時脈信號CLK輸出至多條掃描線G1~GN中之一者,此時掃描線電壓G[n]為高電壓準位,因此多條掃描線G1~GN中之一者並未更新與多條掃描線G1~GN中之一者相耦接之主動區域130。 Please refer to Figure 17. Figure 17 is a schematic diagram showing the operation of a signal mask unit 120 according to the embodiment shown in Figure 3 of the present invention. Please refer to Figure 11 and Figure 17 together. During the period P12, the driving signal En is at a high voltage level, so neither the switching unit T2 nor the switching unit T3 is turned on. The reset voltage Vrst is at a high voltage level, so the switching unit T4 is not turned on, and the node Q is at a low voltage level, so that the switching unit T5 and the switching unit T6 are turned on. The operating voltage VDD is supplied to the node BT through the switching unit T5, so the node BT is at a high voltage level. The node BT is at a high voltage level, so the switching unit T1 is not turned on. The operating voltage VDD is supplied to the output terminal OUT through the switching unit T6, so the output terminal OUT is at a high voltage level. The signal mask unit 120 does not output the clock signal CLK to one of the plurality of scanning lines G1 to GN. Therefore, even if the clock signal CLK is at a low voltage level during the period P12, since the signal mask unit 120 does not output the clock signal CLK to one of the plurality of scanning lines G1 to GN, the scanning line voltage G[ n] is a high voltage level, and therefore one of the plurality of scanning lines G1 to GN does not update the active area 130 coupled to one of the plurality of scanning lines G1 to GN.

請參閱第18圖。第18圖係根據本案之一些實施例所繪示之一種信號遮罩方法600的流程圖。如第18圖所示,信號遮罩方法600包含以下步驟:步驟S610:使驅動電路根據驅動信號接收第一控制信號及第二控制信號; 步驟S620:使驅動電路接收時脈信號;步驟S630:當第一控制信號處於第一電壓準位且第二控制信號處於第二電壓準位時,使驅動電路輸出時脈信號;步驟S640:當第一控制信號處於第二電壓準位且第二控制信號處於第一電壓準位時,使驅動電路停止輸出時脈信號;以及步驟S650:使驅動電路根據重置電壓與第一控制信號選擇性接收重置電壓,其中重置電壓具有第二電壓準位,且重置電壓使驅動電路停止輸出時脈信號。 Please refer to Figure 18. Figure 18 is a flow diagram of a signal masking method 600, in accordance with some embodiments of the present disclosure. As shown in FIG. 18, the signal mask method 600 includes the following steps: Step S610: The driving circuit receives the first control signal and the second control signal according to the driving signal; Step S620: The driving circuit receives the clock signal; Step S630: when the first control signal is at the first voltage level and the second control signal is at the second voltage level, causing the driving circuit to output the clock signal; Step S640: When When the first control signal is at the second voltage level and the second control signal is at the first voltage level, causing the driving circuit to stop outputting the clock signal; and step S650: selecting the driving circuit to be selective according to the reset voltage and the first control signal A reset voltage is received, wherein the reset voltage has a second voltage level, and the reset voltage causes the drive circuit to stop outputting the clock signal.

為使本案實施例之信號遮罩方法600易於理解,請一併參閱第3圖~第18圖。 In order to make the signal mask method 600 of the embodiment of the present invention easy to understand, please refer to FIG. 3 to FIG. 18 together.

於步驟S610中,使驅動電路根據驅動信號接收第一控制信號及第二控制信號。在一些實施例中,驅動電路可為如第3圖所繪示之信號遮罩單元120。舉例來說,在一些實施例中,當驅動信號En為低電壓準位時,開關單元T2與開關單元T3導通,則信號遮罩單元120接收控制信號Vin_1及控制信號Vin_2。 In step S610, the driving circuit is configured to receive the first control signal and the second control signal according to the driving signal. In some embodiments, the drive circuit can be the signal mask unit 120 as depicted in FIG. For example, in some embodiments, when the driving signal En is at a low voltage level, the switching unit T2 and the switching unit T3 are turned on, and the signal mask unit 120 receives the control signal Vin_1 and the control signal Vin_2.

於步驟S620中,使驅動電路接收時脈信號。在一些實施例中,而時脈信號CLK是由信號遮罩單元120的開關單元T1所接收。 In step S620, the driving circuit is caused to receive the clock signal. In some embodiments, the clock signal CLK is received by the switching unit T1 of the signal mask unit 120.

於步驟S630中,當第一控制信號處於第一電壓準位且第二控制信號處於第二電壓準位時,使驅動電路輸出時脈信號。舉例來說,如第7圖所繪示,此時控制信號Vin_1 處於高電壓準位,控制信號Vin_2處於低電壓準位。節點Q為高電壓準位,因此開關單元T5與開關單元T6不導通。節點BT為低電壓準位,開關單元T1導通。信號遮罩單元120將時脈信號CLK輸出至多條掃描線G1~GN中之一者。此時,時脈信號CLK為低電壓準位,因此多條掃描線G1~GN中之一者更新與多條掃描線G1~GN中之一者相耦接之主動區域130。 In step S630, when the first control signal is at the first voltage level and the second control signal is at the second voltage level, the driving circuit is caused to output a clock signal. For example, as shown in Figure 7, the control signal Vin_1 at this time At the high voltage level, the control signal Vin_2 is at a low voltage level. The node Q is at a high voltage level, so the switching unit T5 and the switching unit T6 are not turned on. The node BT is at a low voltage level, and the switching unit T1 is turned on. The signal mask unit 120 outputs the clock signal CLK to one of the plurality of scanning lines G1 to GN. At this time, the clock signal CLK is at a low voltage level, and therefore one of the plurality of scanning lines G1 to GN updates the active region 130 coupled to one of the plurality of scanning lines G1 to GN.

於步驟S640中,當第一控制信號處於第二電壓準位且第二控制信號處於第一電壓準位時,使驅動電路停止輸出時脈信號。舉例來說,如第12圖到第17圖所繪示,於第12圖到第17圖中,控制信號Vin_1處於低電壓準位,控制信號Vin_2處於高電壓準位,且開關單元T1皆不導通,因此信號遮罩單元120並未將時脈信號CLK輸出至多條掃描線G1~GN中之一者。 In step S640, when the first control signal is at the second voltage level and the second control signal is at the first voltage level, the driving circuit stops the output of the clock signal. For example, as shown in FIG. 12 to FIG. 17, in FIG. 12 to FIG. 17, the control signal Vin_1 is at a low voltage level, the control signal Vin_2 is at a high voltage level, and the switching unit T1 is not Turning on, the signal mask unit 120 does not output the clock signal CLK to one of the plurality of scan lines G1 to GN.

於步驟S650中,使驅動電路根據重置電壓與第一控制信號選擇性接收重置電壓,其中重置電壓具有第二電壓準位,且重置電壓使驅動電路停止輸出時脈信號。舉例來說,請參閱第8圖,當重置電壓Vrst為低電壓準位時,開關單元T4導通,此時節點Q為低電壓準位,並使開關單元T5及開關單元T6導通。此時節點BT為高電壓準位,開關單元T1不導通,因此信號遮罩單元120並未將時脈信號CLK輸出至多條掃描線G1~GN中之一者。 In step S650, the driving circuit selectively receives the reset voltage according to the reset voltage and the first control signal, wherein the reset voltage has a second voltage level, and the reset voltage stops the driving circuit from outputting the clock signal. For example, referring to FIG. 8, when the reset voltage Vrst is at a low voltage level, the switching unit T4 is turned on, at which time the node Q is at a low voltage level, and the switching unit T5 and the switching unit T6 are turned on. At this time, the node BT is at a high voltage level, and the switching unit T1 is not turned on, so the signal mask unit 120 does not output the clock signal CLK to one of the plurality of scanning lines G1 to GN.

在一些實施例中,驅動信號En是由如第1圖所繪示之信號產生器110所產生並輸入至信號遮罩單元120。 在其他一些實施例中,驅動信號En是由顯示面板100中之前一級信號遮罩單元120所產生並輸入至當級的信號遮罩單元120。 In some embodiments, the drive signal En is generated by the signal generator 110 as depicted in FIG. 1 and input to the signal mask unit 120. In some other embodiments, the drive signal En is generated by the previous stage signal mask unit 120 in the display panel 100 and input to the signal mask unit 120 of the stage.

在一些實施例中,第4圖與第11圖所繪示的重置電壓Vrst與時脈信號CLK為週期性改變。 In some embodiments, the reset voltage Vrst and the clock signal CLK shown in FIGS. 4 and 11 are periodically changed.

如第4圖~第17圖所示,當控制信號Vin_1處於高電壓準位,而控制信號Vin_2處於低電壓準位時,信號遮罩單元120將時脈信號CLK輸出至多條掃描線G1~GN中之一者。而若時脈信號CLK為低電壓準位,掃描線電壓G[n]為低電壓準位,因此多條掃描線G1~GN中之一者更新與多條掃描線G1~GN中之一者相耦接之主動區域130。另一方面,當控制信號Vin_1處於低電壓準位,而控制信號Vin_2處於高電壓準位時,信號遮罩單元120皆不會將時脈信號CLK輸出至多條掃描線G1~GN中之一者,因此多條掃描線G1~GN中之一者不會更新與多條掃描線G1~GN中之一者相耦接之主動區域130。透過上述方式,本案之實施例可透過控制控制信號Vin_1與控制信號Vin_2,使顯示面板100僅需更新需要更新的部分主動區域130,以降低顯示面板100的功耗。 As shown in FIG. 4 to FIG. 17, when the control signal Vin_1 is at the high voltage level and the control signal Vin_2 is at the low voltage level, the signal mask unit 120 outputs the clock signal CLK to the plurality of scanning lines G1 to GN. One of them. If the clock signal CLK is at a low voltage level, the scan line voltage G[n] is a low voltage level, so one of the plurality of scan lines G1 GN GN is updated with one of the plurality of scan lines G1 GN GN The active region 130 is coupled to the active region 130. On the other hand, when the control signal Vin_1 is at the low voltage level and the control signal Vin_2 is at the high voltage level, the signal mask unit 120 does not output the clock signal CLK to one of the plurality of scan lines G1 to GN. Therefore, one of the plurality of scanning lines G1 to GN does not update the active area 130 coupled to one of the plurality of scanning lines G1 to GN. In the above manner, the embodiment of the present invention can enable the display panel 100 to update only the partial active area 130 that needs to be updated by controlling the control signal Vin_1 and the control signal Vin_2 to reduce the power consumption of the display panel 100.

由上述本案之實施方式可知,本案之實施例藉由提供一種信號遮罩單元、一種信號遮罩方法及一種顯示面板,且特別是有關於低功耗的信號遮罩單元、信號遮罩方法及顯示面板,藉以有效在不降低顯示裝置的效能的同時,降低顯示裝置的功耗。 According to the embodiment of the present invention, the embodiment of the present invention provides a signal mask unit, a signal mask method, and a display panel, and particularly relates to a low power consumption signal mask unit, a signal mask method, and The display panel is effective to reduce the power consumption of the display device without degrading the performance of the display device.

另外,上述例示包含依序的示範步驟,但該些步驟不必依所顯示的順序被執行。以不同順序執行該些步驟皆在本揭示內容的考量範圍內。在本揭示內容之實施例的精神與範圍內,可視情況增加、取代、變更順序及/或省略該些步驟。 In addition, the above examples include exemplary steps in sequence, but the steps are not necessarily performed in the order shown. Performing these steps in a different order is within the scope of the present disclosure. Such steps may be added, substituted, altered, and/or omitted as appropriate within the spirit and scope of the embodiments of the present disclosure.

雖然本案已以實施方式揭示如上,然其並非用以限定本案,任何熟習此技藝者,在不脫離本案之精神和範圍內,當可作各種之更動與潤飾,因此本案之保護範圍當視後附之申請專利範圍所界定者為準。 Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make various changes and refinements without departing from the spirit and scope of the present case. The scope defined in the patent application is subject to change.

Claims (10)

一種信號遮罩單元,包含:一重置單元,用以接收一重置電壓及根據一驅動信號接收一第一控制信號;以及一第一開關單元,與該重置單元電性連接,用以接收一時脈信號及根據該驅動信號接收一第二控制信號,其中該第二控制信號與該第一控制信號反相;其中當該第一控制信號處於一第一電壓準位且該第二控制信號處於一第二電壓準位時,該重置單元不作動,該第二控制信號導通該第一開關單元以使該第一開關單元輸出該時脈信號;其中當該第一控制信號處於該第二電壓準位且該第二控制信號處於該第一電壓準位時,該重置單元輸出一工作電壓至該第一開關單元,該工作電壓與該第二控制信號關斷該第一開關單元。 A signal mask unit includes: a reset unit for receiving a reset voltage and receiving a first control signal according to a driving signal; and a first switch unit electrically connected to the reset unit for Receiving a clock signal and receiving a second control signal according to the driving signal, wherein the second control signal is inverted with the first control signal; wherein when the first control signal is at a first voltage level and the second control When the signal is at a second voltage level, the reset unit is not activated, and the second control signal turns on the first switch unit to cause the first switch unit to output the clock signal; wherein when the first control signal is in the When the second voltage level is at the first voltage level, the reset unit outputs an operating voltage to the first switching unit, and the operating voltage and the second control signal turn off the first switch unit. 如請求項1所述之信號遮罩單元,更包含:一第二開關單元,與該重置單元電性連接,用以接收該第一控制信號並根據該驅動信號導通該第一控制信號至該重置單元。 The signal mask unit of claim 1, further comprising: a second switch unit electrically connected to the reset unit for receiving the first control signal and conducting the first control signal according to the driving signal to The reset unit. 如請求項1所述之信號遮罩單元,更包含:一第三開關單元,與該第一開關單元電性連接,用以接收該第二控制信號並根據該驅動信號導通該第二控制信 號至該第一開關單元。 The signal mask unit of claim 1, further comprising: a third switch unit electrically connected to the first switch unit for receiving the second control signal and conducting the second control signal according to the driving signal Number to the first switching unit. 如請求項1所述之信號遮罩單元,其中該第一開關單元具有一控制端及一輸出端,該控制端用以接收該第二控制信號,該輸出端用以輸出該時脈信號,該重置單元分別與該控制端及該輸出端電性連接以根據該第一控制信號選擇性輸出該工作電壓至該控制端及該輸出端。 The signal mask unit of claim 1, wherein the first switch unit has a control end and an output end, wherein the control end is configured to receive the second control signal, and the output end is configured to output the clock signal, The reset unit is electrically connected to the control terminal and the output terminal to selectively output the operating voltage to the control terminal and the output terminal according to the first control signal. 如請求項4所述之信號遮罩單元,其中該重置單元包含:一第四開關單元,用以接收該重置電壓;一第五開關單元,用以接收該工作電壓,該第五開關單元具有一控制端,其中該第五開關單元的該控制端用以接收該第一控制信號並與該第四開關單元電性連接;一第六開關單元,用以接收該工作電壓,該第六開關單元具有一控制端及一輸出端,其中該第六開關單元的該控制端與該第五開關單元的該控制端電性連接,該第六開關單元的該輸出端與該第一開關單元的該輸出端電性連接;以及一電容器,與該第五開關單元的該控制端電性連接。 The signal mask unit of claim 4, wherein the reset unit comprises: a fourth switch unit for receiving the reset voltage; and a fifth switch unit for receiving the working voltage, the fifth switch The unit has a control end, wherein the control end of the fifth switch unit is configured to receive the first control signal and is electrically connected to the fourth switch unit; a sixth switch unit is configured to receive the operating voltage, the first The sixth switch unit has a control end and an output end, wherein the control end of the sixth switch unit is electrically connected to the control end of the fifth switch unit, the output end of the sixth switch unit and the first switch The output end of the unit is electrically connected; and a capacitor is electrically connected to the control end of the fifth switch unit. 如請求項5所述之信號遮罩單元,其中當該重置電壓與該第一控制信號導通該第四開關單元、該第五開關單元及該第六開關單元時,該工作電壓被導通至該第一開關單元的該控制端及該輸出端使該第一開關單元的該控制 端及該輸出端具有該第一電壓準位。 The signal mask unit of claim 5, wherein when the reset voltage and the first control signal turn on the fourth switch unit, the fifth switch unit, and the sixth switch unit, the operating voltage is turned on to The control end of the first switch unit and the output end enable the control of the first switch unit The terminal and the output have the first voltage level. 一種信號遮罩方法,用於一驅動電路,包含:使該驅動電路根據一驅動信號接收一第一控制信號及一第二控制信號;使該驅動電路接收一時脈信號;當該第一控制信號處於一第一電壓準位且該第二控制信號處於一第二電壓準位時,使該驅動電路輸出該時脈信號;以及當該第一控制信號處於該第二電壓準位且該第二控制信號處於該第一電壓準位時,使該驅動電路停止輸出該時脈信號。 A signal masking method for a driving circuit, comprising: causing the driving circuit to receive a first control signal and a second control signal according to a driving signal; causing the driving circuit to receive a clock signal; and when the first control signal When the first control signal is at a second voltage level, the driving circuit outputs the clock signal; and when the first control signal is at the second voltage level and the second When the control signal is at the first voltage level, the driving circuit stops outputting the clock signal. 如請求項7所述之信號遮罩方法,更包含:使該驅動電路根據該重置電壓與該第一控制信號選擇性接收一工作電壓,其中該工作電壓具有該第二電壓準位,且該工作電壓使該驅動電路停止輸出該時脈信號。 The signal masking method of claim 7, further comprising: causing the driving circuit to selectively receive an operating voltage according to the reset voltage and the first control signal, wherein the operating voltage has the second voltage level, and The operating voltage causes the drive circuit to stop outputting the clock signal. 一種顯示面板,包含:複數條掃描線;複數級信號產生器,其中每一級之該些信號產生器分別產生一驅動信號,並將該驅動信號傳送至下一級信號產生器;複數級信號遮罩單元,分別耦接於該些掃描線中之一者 與該些信號產生器中之一級之間,每一級之該些信號遮罩單元根據相耦接的當級信號產生器所傳送之該驅動信號以接收一第一控制信號及一第二控制信號,其中該第二控制信號與該第一控制信號反相,且當該第一控制信號處於一第一電壓準位且該第二控制信號處於一第二電壓準位時,當級信號遮罩單元將一時脈信號發送至該些掃描線中之一者。 A display panel comprising: a plurality of scan lines; a plurality of levels of signal generators, wherein each of the signal generators of each stage generates a drive signal and transmits the drive signal to a next stage signal generator; a plurality of levels of signal masks Units respectively coupled to one of the scan lines The signal masking unit of each stage is configured to receive a first control signal and a second control signal according to the driving signal transmitted by the phase signal generator coupled to the stage. The second control signal is inverted from the first control signal, and when the first control signal is at a first voltage level and the second control signal is at a second voltage level, the level signal mask The unit sends a clock signal to one of the scan lines. 如請求項9所述之顯示面板,其中每一級之該些信號遮罩單元包含:一重置單元,用以接收一重置電壓及根據該信號產生器所傳送之該驅動信號接收該第一控制信號;以及一第一開關單元,與該重置單元以及該些掃描線中之一者電性連接,該第一開關單元根據該信號產生器所傳送之該驅動信號接收該第二控制信號,當該第一開關單元導通時用以將該時脈信號發送至該些掃描線中之一者;其中當該第一控制信號處於該第二電壓準位且該第二控制信號處於該第一電壓準位時,該重置單元輸出一工作電壓至該第一開關單元,該工作電壓與該第二控制信號關斷該第一開關單元。 The display panel of claim 9, wherein the signal mask units of each stage comprise: a reset unit for receiving a reset voltage and receiving the first signal according to the driving signal transmitted by the signal generator a control signal; and a first switching unit electrically connected to the reset unit and one of the scan lines, the first switch unit receiving the second control signal according to the driving signal transmitted by the signal generator Transmitting the clock signal to one of the scan lines when the first switch unit is turned on; wherein when the first control signal is at the second voltage level and the second control signal is at the At a voltage level, the reset unit outputs an operating voltage to the first switching unit, and the operating voltage and the second control signal turn off the first switching unit.
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