TWI622041B - Signal masking unit, signal masking method, and display panel - Google Patents

Abstract

The signal mask unit includes a reset unit and a first switch unit. The reset unit is configured to receive the reset voltage and receive the first control signal according to the driving signal. The first switching unit is configured to receive the clock signal and receive the second control signal according to the driving signal. The second control signal is inverted from the first control signal. When the first control signal is at the first voltage level and the second control signal is at the second voltage level, the reset unit is not activated, and the first switching unit is turned on and outputs the clock signal. When the first control signal is at the second voltage level and the second control signal is at the first voltage level, the reset unit outputs the operating voltage to the first switching unit, and the first switching unit is turned off.

Description

Signal mask unit, signal mask method and display surface board

The present invention relates to a signal mask unit, a signal mask method, and a display panel, and particularly to a signal mask unit, a signal mask method, and a display panel for low power consumption.

With the rapid development of display devices, people can use display devices of various sizes at any time, such as mobile phones, computers, etc., at any time. When the display device is used, different power consumption is generated each time the screen of the display device changes, and the power consumption directly affects people's concerns about using the display device.

Therefore, as people pay more and more attention to the problem of power saving and energy saving, how to reduce the power consumption of the display device without reducing the performance of the display device is one of the problems to be improved in the field.

One aspect of the case is to provide a signal mask unit. this The signal mask unit includes a reset unit and a first switch unit. The reset unit is configured to receive the reset voltage and receive the first control signal according to the driving signal. The first switching unit is electrically connected to the reset unit for receiving the clock signal and receiving the second control signal according to the driving signal. The second control signal is inverted from the first control signal. When the first control signal is at the first voltage level and the second control signal is at the second voltage level, the reset unit is not activated, and the second control signal turns on the first switch unit to cause the first switch unit to output the clock signal. When the first control signal is at the second voltage level and the second control signal is at the first voltage level, the reset unit outputs the operating voltage to the first switching unit, and the operating voltage and the second control signal turn off the first switching unit.

Another aspect of the present invention is to provide a signal masking method for driving a circuit. The signal masking method includes the steps of: causing the driving circuit to receive the first control signal and the second control signal according to the driving signal; causing the driving circuit to receive the clock signal; when the first control signal is at the first voltage level and the second control signal When the second voltage level is at the second voltage level, the driving circuit outputs the clock signal; and when the first control signal is at the second voltage level and the second control signal is at the first voltage level, the driving circuit stops outputting the clock signal.

Another aspect of the present invention is to provide a display panel. The display panel includes a plurality of scan lines, a multi-level signal generator, and a multi-level signal mask unit. Each of the signal generators generates a drive signal and transmits the drive signal to the next stage signal generator. The plurality of signal mask units are respectively coupled between one of the plurality of scan lines and the multi-level signal generator. The signal masking unit of each stage receives the first control signal and the second control signal according to the driving signal transmitted by the coupled level signal generator, wherein the second control signal and the first The control signal is inverted, and when the first control signal is at the first voltage level and the second control signal is at the second voltage level, the stage signal mask unit transmits the clock signal to one of the plurality of scan lines.

Therefore, according to the technical aspect of the present invention, an embodiment of the present invention provides a signal mask unit, a signal mask method, and a display panel, and particularly relates to a signal mask unit and a signal mask method for low power consumption. And the display panel, thereby effectively reducing the power consumption of the display device without reducing the performance of the display device.

100‧‧‧ display panel

110-1~110-N‧‧‧Signal Generator

120-1~120-N‧‧‧Signal Mask Unit

120‧‧‧Signal mask unit

130‧‧‧Active area

G1~GN‧‧‧ scan line

En‧‧‧ drive signal

Vrst‧‧‧Reset voltage

VDD‧‧‧ working voltage

Vin_1, Vin_2‧‧‧ control signals

RST1‧‧‧Reset unit

T1, T2, T3, T4, T5, T6‧‧‧ switch units

CLK‧‧‧ clock signal

G[n]‧‧‧ scan line voltage

BT, Q‧‧‧ nodes

OUT‧‧‧ output

400, 500‧‧‧ operating waveforms

During P1, P2, P3, P4, P5, P6‧‧

During P7, P8, P9, P10, P11, P12‧‧

600‧‧‧Signal mask method

S610, S620, S630, S640, S650‧‧ steps

The above and other objects, features, advantages and embodiments of the present invention will become more apparent and understood. The description of the drawings is as follows: FIG. 1 is a schematic view of a display panel according to some embodiments of the present invention; 2 is a schematic diagram of a signal mask unit according to some embodiments of the present invention; FIG. 3 is a detailed schematic diagram of a signal mask unit according to some embodiments of the present disclosure; and FIG. 4 A schematic diagram of an operational waveform according to some embodiments of the present invention; FIG. 5 is a schematic diagram of operation of a signal mask unit according to the embodiment shown in FIG. 3 of the present invention; FIG. 6 is in accordance with the present invention. 3 is a schematic diagram of the operation of a signal mask unit according to the embodiment shown in the figure; Figure 7 is a schematic diagram showing the operation of a signal mask unit according to the embodiment shown in Figure 3 of the present invention; Figure 8 is a signal mask unit according to the embodiment shown in Figure 3 of the present invention. FIG. 9 is a schematic diagram showing the operation of a signal mask unit according to the embodiment shown in FIG. 3 of the present invention; FIG. 10 is a diagram according to the embodiment shown in FIG. 3 of the present invention. FIG. 11 is a schematic diagram showing an operation waveform according to some embodiments of the present invention; and FIG. 12 is a signal mask according to the embodiment shown in FIG. 3 of the present invention. Figure 13 is a schematic view showing the operation of a signal mask unit according to the embodiment shown in Figure 3 of the present invention; Figure 14 is a diagram showing the embodiment shown in Figure 3 of the present invention. FIG. 15 is a schematic diagram showing the operation of a signal mask unit according to the embodiment shown in FIG. 3 of the present invention; and FIG. 16 is an embodiment according to FIG. 3 of the present invention. a signal mask Figure 17 is a schematic diagram showing the operation of a signal mask unit according to the embodiment shown in Figure 3 of the present invention; and Figure 18 is a signal mask according to some embodiments of the present invention. Flow chart of the hood method.

The following disclosure provides many different embodiments or illustrations for implementing different features of the invention. The elements and configurations of the specific illustrations are used in the following discussion to simplify the disclosure. Any examples discussed are for illustrative purposes only and are not intended to limit the scope and meaning of the invention or its examples. In addition, the present disclosure may repeatedly recite numerical symbols and/or letters in different examples, which are for simplicity and elaboration, and do not specify the relationship between the various embodiments and/or configurations in the following discussion.

The terms used in the entire specification and the scope of the patent application, unless otherwise specified, generally have the ordinary meaning of each term used in the field, the content disclosed herein, and the particular content. Certain terms used to describe the disclosure are discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art in the description of the disclosure.

"Coupling" or "connecting" as used herein may mean that two or more elements are in direct physical or electrical contact with each other, or indirectly in physical or electrical contact with each other, and "coupled" or " Connections may also mean that two or more elements operate or interact with each other.

The use of the terms first, second, and third, etc., is used to describe various elements, components, regions, layers and/or blocks. However, these elements, components, regions, layers and/or blocks should not be limited by these terms. These terms are only used to identify a single element, component, region, layer, and/or block. Therefore, a first element, component, region, layer and/or block may also be referred to as a second element, component, or region. Domains, layers and/or blocks without departing from the spirit of the invention. As used herein, the term "and/or" encompasses any combination of one or more of the listed associated items. "and/or" as used in this document refers to any combination of any, all or at least one of the listed elements.

Please refer to Figure 1. FIG. 1 is a schematic diagram of a display panel 100 according to some embodiments of the present disclosure. As shown in FIG. 1 , the display panel 100 includes multi-level signal generators 110-1 ～ 110-N, a plurality of signal mask units 120-1 ～ 120-N, a plurality of scan lines G1 GN GN, and an active area 130 . . The signal mask units 120-1 120 120-N are respectively coupled between one of the scan lines G1 GN GN and one of the multi-level signal generators 110-1 ～ 110-N. The active area 130 is coupled to the plurality of scan lines G1 GN GN. In some embodiments, each of the multi-level signal generators 110-1~110-N generates a drive signal En and transmits the drive signal En to the multi-level signal generators 110-1~110-N. Primary signal generator. For example, as shown in FIG. 1, the signal generator 110-1 transmits the driving signal En to the signal generator 110-2, and the signal generator 110-2 transmits the driving signal En to the signal generator 110-3. This type of push.

In some embodiments, for example, only when the scan line voltage G[n] output to the scan line G1 is at a low voltage level, the scan line G1 updates the active region 130 coupled to the scan line G1. However, this case is not limited to this. The rest of the scan lines G2~GN and so on. The operation between the respective elements will be described below with reference to Fig. 2 .

Please refer to Figure 2. FIG. 2 is a schematic diagram of a signal mask unit 120 according to some embodiments of the present disclosure. In some embodiments The signal mask unit 120 of FIG. 2 is used to implement the signal mask units 120-1, 120-2, 120-3, ... or 120-N in the first figure. The signal mask unit 120 receives the first control signal and the second control signal according to the driving signal transmitted by the coupled signal generator. The second control signal is inverted from the first control signal. When the first control signal is at the first voltage level and the second control signal is at the second voltage level, the signal mask unit 120 transmits the clock signal to one of the plurality of scan lines G1 GN GN. For example, the signal mask unit 120-1 in FIG. 1 receives the first control signal Vin_1 and the second according to the driving signal En transmitted by the signal generator 110-1 coupled to the signal mask unit 120-1. Control signal Vin_2. When the first control signal is at the first voltage level and the second control signal is at the second voltage level, the signal mask unit 120-1 transmits the clock signal CLK to the scan line G1. The rest of the signal mask units 120-2~120-N and so on.

As shown in FIG. 2, the signal mask unit 120 includes a reset unit RST1, a switch unit T1, a switch unit T2, and a switch unit T3. The switch unit T1 is electrically connected to the reset unit RST1. The switch unit T2 is electrically connected to the reset unit RST1. The switch unit T3 is electrically connected to the switch unit T1.

The reset unit RST1 receives the reset voltage Vrst and determines whether to receive the control signal Vin_1 according to the drive signal En. The switching unit T1 receives the clock signal CLK and determines whether to receive the control signal Vin_2 according to the driving signal En. The control signal Vin_1 is inverted from the control signal Vin_2. When the control signal Vin_1 is at the first voltage level and the control signal Vin_2 is at the second voltage level, the reset unit RST1 is not activated, and the control signal Vin_2 turns on the switching unit T1 to cause the switching unit T1 to output the clock signal CLK to One of the plurality of scanning lines G1 to GN shown in FIG. When the control signal Vin_1 is at the second voltage level and the control signal Vin_2 is at the first voltage level, the reset unit RST1 outputs the operating voltage VDD to the switching unit T1, and the operating voltage VDD and the control signal Vin_2 turn off the switching unit T1.

In some implementations, the switching unit T2 receives the control signal Vin_1 and turns on the control signal Vin_1 to the reset unit RST1 according to the driving signal En. The switching unit T3 receives the control signal Vin_2 and turns on the control signal Vin_2 to the switching unit T1 according to the driving signal En.

See Figure 3. FIG. 3 is a detailed schematic diagram of a signal mask unit 120 according to some embodiments of the present disclosure. As shown in FIG. 3, in some embodiments, the switching unit T1 has a control terminal and an output terminal. The control terminal is configured to receive the control signal Vin_2, and the output terminal is configured to output the clock signal CLK. The resetting unit RST1 is electrically connected to the control end and the output end respectively to selectively output the operating voltage VDD to the control end and the output end of the switching unit T1 according to the control signal Vin_1.

As shown in FIG. 3, in some embodiments, the reset unit RST1 includes a switching unit T4, a switching unit T5, a switching unit T6, and a capacitor C1. The switching unit T4 is configured to receive the reset voltage Vrst. The switching unit T5 is configured to receive the reset voltage Vrst. The control terminal of the switch unit T5 is configured to receive the control signal Vin_1 and is electrically connected to the switch unit T4 to receive the reset voltage Vrst. The switch unit T6 receives the reset voltage Vrst, and the switch unit T6 has a control end and an output end. The control end of the switch unit T6 is electrically connected to the control end of the switch unit T5, and the output end of the switch unit T6 and the output end of the switch unit T1 are electrically connected. Sexual connection. The capacitor C1 is electrically connected to the control end of the switch unit T5 and used To receive the reset voltage Vrst.

In some embodiments, when the reset voltage Vrst and the control signal Vin_1 turn on the switching unit T4, the switching unit T5, and the switching unit T6, the operating voltage VDD is turned on to the control terminal and the output terminal of the switching unit T1 to make the switching unit T1 The control terminal and the output terminal have a first voltage level.

As shown in FIG. 3, in some embodiments, the switching units T1 T T6 are P-type metal oxide semiconductor field effect transistors (PMOSFETs). However, this case is not limited to the embodiment of Figure 3.

Please refer to Figure 4. 4 is a schematic diagram of an operational waveform 400 depicted in accordance with some embodiments of the present disclosure. As shown in Fig. 4, during the period P1~P6, the control signal Vin_1 is at the high voltage level, and the control signal Vin_2 is at the low voltage level. The details of Fig. 4 will be described below with reference to Figs. 5 to 10 .

Please refer to Figure 5. Figure 5 is a schematic view showing the operation of a signal mask unit 120 according to the embodiment shown in Figure 3 of the present invention. Please refer to Figure 4 and Figure 5 together. During the period P1, the driving signal En is at a high voltage level, so neither the switching unit T2 nor the switching unit T3 is turned on. The reset voltage Vrst is at a low voltage level, and the switching unit T4 is thus turned on, so that the node Q is at a low voltage level, and the switching unit T5 and the switching unit T6 are both turned on. Since the switching unit T5 and the switching unit T6 are both turned on, the operating voltage VDD is supplied to the node BT and the output terminal OUT through the switching unit T5 and the switching unit T6. At this time, the node BT is at a high voltage level, so the switching unit T1 is not turned on. The signal mask unit 120 does not output the clock signal CLK to one of the plurality of scan lines G1 GN GN, and the scan line voltage G[n] is a high voltage level, and thus the plurality of scan lines G1 GN GN One of the active areas 130 coupled to one of the plurality of scan lines G1 GN is not updated.

Please refer to Figure 6. Figure 6 is a schematic diagram showing the operation of a signal mask unit 120 according to the embodiment shown in Figure 3 of the present invention. Please refer to Figure 4 and Figure 6 together. During the period P2, the driving signal En is at a low voltage level, so the switching unit T2 and the switching unit T3 are both turned on. The high voltage level control signal Vin_1 is supplied to the node Q through the switching unit T2, so the node Q is at a high voltage level. The low voltage level control signal Vin_2 is supplied to the node BT through the switching unit T3, so the node BT is at a low voltage level. The reset voltage Vrst is at a high voltage level, so the switching unit T4 is not turned on. Since the node Q is at a high voltage level, the node BT is at a low voltage level, so the switching unit T5 and the switching unit T6 are not turned on, and the switching unit T1 is turned on, and the signal mask unit 120 outputs the clock signal CLK to the plurality of scanning lines G1. One of ~GN. At this time, the clock signal CLK is at a high voltage level, and therefore one of the plurality of scan lines G1 to GN does not update the active region 130 coupled to one of the plurality of scan lines G1 to GN.

Please refer to Figure 7. Figure 7 is a schematic view showing the operation of a signal mask unit 120 according to the embodiment shown in Figure 3 of the present invention. Please refer to Figure 4 and Figure 7 together. During the period P3, the driving signal En is at a high voltage level, so neither the switching unit T2 nor the switching unit T3 is turned on. The reset voltage Vrst is at a high voltage level, so the switching unit T4 is not turned on. The operating voltage VDD is supplied to the node Q through the capacitor C1, so the node Q is at a high voltage level, so that the switching unit T5 and the switching unit T6 are not turned on. The node BT is at a low voltage level, and the switching unit T1 is turned on. The signal mask unit 120 outputs the clock signal CLK to One of the plurality of scanning lines G1 to GN. At this time, the clock signal CLK is at a low voltage level, and therefore one of the plurality of scanning lines G1 to GN updates the active region 130 coupled to one of the plurality of scanning lines G1 to GN.

Please refer to Figure 8. Figure 8 is a schematic view showing the operation of a signal mask unit 120 according to the embodiment shown in Figure 3 of the present invention. Please refer to Figure 4 and Figure 8 together. During the period P4, the driving signal En is at a high voltage level, so neither the switching unit T2 nor the switching unit T3 is turned on. The reset voltage Vrst is at a low voltage level, so the switching unit T4 is turned on. Since the switching unit T4 is turned on, the node Q is at a low voltage level, so that the switching unit T5 and the switching unit T6 are turned on. The operating voltage VDD is supplied to the node BT through the switching unit T5, so the node BT is at a high voltage level, so that the switching unit T1 is not turned on. The operating voltage VDD is supplied to the output terminal OUT through the switching unit T6, so the output terminal OUT is at a high voltage level. The signal mask unit 120 does not output the clock signal CLK to one of the plurality of scan lines G1 GN GN, and the scan line voltage G[n] is a high voltage level, and thus one of the plurality of scan lines G1 GN GN The active area 130 coupled to one of the plurality of scan lines G1 GN GN is not updated.

Please refer to Figure 9. Figure 9 is a schematic view showing the operation of a signal mask unit 120 according to the embodiment shown in Figure 3 of the present invention. Please refer to Figure 4 and Figure 9 together. During the period P5, the driving signal En is at a high voltage level, so neither the switching unit T2 nor the switching unit T3 is turned on. The reset voltage Vrst is at a high voltage level, so the switching unit T4 is not turned on, the node Q is maintained at a low voltage level, so that the switching unit T5 and the switching unit T6 are turned on, and the operating voltage VDD is supplied to the node BT through the switching unit T5, so the node BT is high power Pressure level. The node BT is at a high voltage level, so the switching unit T1 is not turned on. The operating voltage VDD is supplied to the output terminal OUT through the switching unit T6, so the output terminal OUT is at a high voltage level. The signal mask unit 120 does not output the clock signal CLK to one of the plurality of scan lines G1 GN GN, and the scan line voltage G[n] is a high voltage level, and thus one of the plurality of scan lines G1 GN GN The active area 130 coupled to one of the plurality of scan lines G1 GN GN is not updated.

Please refer to Figure 10. Figure 10 is a schematic view showing the operation of a signal mask unit 120 according to the embodiment shown in Figure 3 of the present invention. Please refer to Figure 4 and Figure 10 together. During the period P6, the driving signal En is at a high voltage level, so neither the switching unit T2 nor the switching unit T3 is turned on. The reset voltage Vrst is at a high voltage level, so the switching unit T4 is not turned on, and the node Q is maintained at a low voltage level. The node Q is at a low voltage level, so the switching unit T5 is turned on and the switching unit T6 is turned on, and the operating voltage VDD is supplied to the node BT through the switching unit T5, so the node BT is at a high voltage level, so that the switching unit T1 is not turned on. The operating voltage VDD is supplied to the output terminal OUT through the switching unit T6, so the output terminal OUT is at a high voltage level. The signal mask unit 120 does not output the clock signal CLK to one of the plurality of scanning lines G1 to GN. Therefore, even if the clock signal CLK is at a low voltage level during the period P6, since the signal mask unit 120 does not output the clock signal CLK to one of the plurality of scanning lines G1 to GN, the scanning line voltage G[n] The high voltage level is such that one of the plurality of scan lines G1 GN GN does not update the active area 130 coupled to one of the plurality of scan lines G1 GN GN.

Please refer to Figure 11. Figure 11 is based on some implementations of this case. A schematic diagram of an operational waveform 500 is illustrated. As shown in Fig. 11, during the period P7~P12, the control signal Vin_1 is at a low voltage level, and the control signal Vin_2 is at a high voltage level. The details of Fig. 11 will be described below in conjunction with Figs. 12 to 17 .

Please refer to Figure 12. Figure 12 is a schematic diagram showing the operation of a signal mask unit 120 according to the embodiment shown in Figure 3 of the present invention. Please refer to Figure 11 and Figure 12 together. During the period P7, the driving signal En is at a high voltage level, so neither the switching unit T2 nor the switching unit T3 is turned on. The reset voltage Vrst is at a low voltage level, so the switching unit T4 is turned on, the node Q is at a low voltage level, so that the switching unit T5 and the switching unit T6 are turned on, and the operating voltage VDD is supplied to the node BT through the switching unit T5, so the node BT is The high voltage level is such that the switching unit T1 is not turned on. The operating voltage VDD is supplied to the output terminal OUT through the switching unit T6, so the output terminal OUT is at a high voltage level. The signal mask unit 120 does not output the clock signal CLK to one of the plurality of scan lines G1 GN GN, and the scan line voltage G[n] is a high voltage level, and thus one of the plurality of scan lines G1 GN GN The active area 130 coupled to one of the plurality of scan lines G1 GN GN is not updated.

Please refer to Figure 13. Figure 13 is a schematic view showing the operation of a signal mask unit 120 according to the embodiment shown in Figure 3 of the present invention. Please refer to Figure 11 and Figure 13 together. During the period P8, the driving signal En is at a low voltage level, so the switching unit T2 and the switching unit T3 are both turned on. The reset voltage Vrst is at a high voltage level, so the switching unit T4 is not turned on. The low voltage level control signal Vin_1 is supplied to the node Q through the switching unit T2, so the node Q is at a low voltage level. High voltage level control signal Vin_2 through switching unit T3 is provided to node BT, so node BT is at a high voltage level. Since the node Q is at a low voltage level, the node BT is at a high voltage level, so the switching unit T5 and the switching unit T6 are turned on, and the switching unit T1 is not turned on. The operating voltage VDD is supplied to the output terminal OUT through the switching unit T6, so the output terminal OUT is at a high voltage level. The signal mask unit 120 does not output the clock signal CLK to one of the plurality of scanning lines G1 to GN. At this time, the scan line voltage G[n] is a high voltage level, and therefore one of the plurality of scan lines G1 GN GN does not update the active area 130 coupled to one of the plurality of scan lines G1 GN GN .

Please refer to Figure 14. Figure 14 is a schematic view showing the operation of a signal mask unit 120 according to the embodiment shown in Figure 3 of the present invention. Please refer to Figure 11 and Figure 14 together. During the period P9, the driving signal En is at a high voltage level, so neither the switching unit T2 nor the switching unit T3 is turned on. The reset voltage Vrst is at a high voltage level, so the switching unit T4 is not turned on, and the node Q is at a low voltage level, so that the switching unit T5 and the switching unit T6 are turned on. The operating voltage VDD is supplied to the node BT through the switching unit T5, so the node BT is at a high voltage level. The node BT is at a high voltage level, so the switching unit T1 is not turned on. The operating voltage VDD is supplied to the output terminal OUT through the switching unit T6, so the output terminal OUT is at a high voltage level. The signal mask unit 120 does not output the clock signal CLK to one of the plurality of scanning lines G1 to GN. Therefore, even if the clock signal CLK is at a low voltage level during the period P12, since the signal mask unit 120 does not output the clock signal CLK to one of the plurality of scanning lines G1 to GN, the scanning line voltage G[ n] is a high voltage level, and therefore one of the plurality of scanning lines G1 to GN does not update the active area 130 coupled to one of the plurality of scanning lines G1 to GN.

Please refer to Figure 15. Figure 15 is a schematic view showing the operation of a signal mask unit 120 according to the embodiment shown in Figure 3 of the present invention. Please refer to Figure 11 and Figure 15 together. During the period P10, the driving signal En is at a high voltage level, so neither the switching unit T2 nor the switching unit T3 is turned on. The reset voltage Vrst is at a low voltage level, so the switching unit T4 is turned on. The reset voltage Vrst is supplied to the node Q through the switching unit T4, so the node Q is at a low voltage level, so that the switching unit T5 and the switching unit T6 are turned on. The operating voltage VDD is supplied to the node BT through the switching unit T5, so the node BT is at a high voltage level. The node BT is at a high voltage level, so the switching unit T1 is not turned on. The operating voltage VDD is supplied to the output terminal OUT through the switching unit T6, so the output terminal OUT is at a high voltage level. The signal mask unit 120 does not output the clock signal CLK to one of the plurality of scanning lines G1 to GN. At this time, the scan line voltage G[n] is a high voltage level, and therefore one of the plurality of scan lines G1 GN GN does not update the active area 130 coupled to one of the plurality of scan lines G1 GN GN .

Please refer to Figure 16. Figure 16 is a schematic view showing the operation of a signal mask unit 120 according to the embodiment shown in Figure 3 of the present invention. Please refer to Figure 11 and Figure 16 together. During the period P11, the driving signal En is at a high voltage level, so neither the switching unit T2 nor the switching unit T3 is turned on. The reset voltage Vrst is at a high voltage level, so the switching unit T4 is not turned on, and the node Q is at a low voltage level, so that the switching unit T5 and the switching unit T6 are turned on. The operating voltage VDD is supplied to the node BT through the switching unit T5, so the node BT is at a high voltage level, so that the switching unit T1 is not turned on. The operating voltage VDD is supplied to the output terminal OUT through the switching unit T6, so the output terminal OUT is at a high voltage level. The signal mask unit 120 does not output the clock signal CLK to multiple sweeps One of the lines G1 to GN. At this time, the scan line voltage G[n] is a high voltage level, and therefore one of the plurality of scan lines G1 GN GN does not update the active area 130 coupled to one of the plurality of scan lines G1 GN GN .

Please refer to Figure 17. Figure 17 is a schematic diagram showing the operation of a signal mask unit 120 according to the embodiment shown in Figure 3 of the present invention. Please refer to Figure 11 and Figure 17 together. During the period P12, the driving signal En is at a high voltage level, so neither the switching unit T2 nor the switching unit T3 is turned on. The reset voltage Vrst is at a high voltage level, so the switching unit T4 is not turned on, and the node Q is at a low voltage level, so that the switching unit T5 and the switching unit T6 are turned on. The operating voltage VDD is supplied to the node BT through the switching unit T5, so the node BT is at a high voltage level. The node BT is at a high voltage level, so the switching unit T1 is not turned on. The operating voltage VDD is supplied to the output terminal OUT through the switching unit T6, so the output terminal OUT is at a high voltage level. The signal mask unit 120 does not output the clock signal CLK to one of the plurality of scanning lines G1 to GN. Therefore, even if the clock signal CLK is at a low voltage level during the period P12, since the signal mask unit 120 does not output the clock signal CLK to one of the plurality of scanning lines G1 to GN, the scanning line voltage G[ n] is a high voltage level, and therefore one of the plurality of scanning lines G1 to GN does not update the active area 130 coupled to one of the plurality of scanning lines G1 to GN.

Please refer to Figure 18. Figure 18 is a flow diagram of a signal masking method 600, in accordance with some embodiments of the present disclosure. As shown in FIG. 18, the signal mask method 600 includes the following steps: Step S610: The driving circuit receives the first control signal and the second control signal according to the driving signal; Step S620: The driving circuit receives the clock signal; Step S630: when the first control signal is at the first voltage level and the second control signal is at the second voltage level, causing the driving circuit to output the clock signal; Step S640: When When the first control signal is at the second voltage level and the second control signal is at the first voltage level, causing the driving circuit to stop outputting the clock signal; and step S650: selecting the driving circuit to be selective according to the reset voltage and the first control signal A reset voltage is received, wherein the reset voltage has a second voltage level, and the reset voltage causes the drive circuit to stop outputting the clock signal.

In order to make the signal mask method 600 of the embodiment of the present invention easy to understand, please refer to FIG. 3 to FIG. 18 together.

In step S610, the driving circuit is configured to receive the first control signal and the second control signal according to the driving signal. In some embodiments, the drive circuit can be the signal mask unit 120 as depicted in FIG. For example, in some embodiments, when the driving signal En is at a low voltage level, the switching unit T2 and the switching unit T3 are turned on, and the signal mask unit 120 receives the control signal Vin_1 and the control signal Vin_2.

In step S620, the driving circuit is caused to receive the clock signal. In some embodiments, the clock signal CLK is received by the switching unit T1 of the signal mask unit 120.

In step S630, when the first control signal is at the first voltage level and the second control signal is at the second voltage level, the driving circuit is caused to output a clock signal. For example, as shown in Figure 7, the control signal Vin_1 at this time At the high voltage level, the control signal Vin_2 is at a low voltage level. The node Q is at a high voltage level, so the switching unit T5 and the switching unit T6 are not turned on. The node BT is at a low voltage level, and the switching unit T1 is turned on. The signal mask unit 120 outputs the clock signal CLK to one of the plurality of scanning lines G1 to GN. At this time, the clock signal CLK is at a low voltage level, and therefore one of the plurality of scanning lines G1 to GN updates the active region 130 coupled to one of the plurality of scanning lines G1 to GN.

In step S640, when the first control signal is at the second voltage level and the second control signal is at the first voltage level, the driving circuit stops the output of the clock signal. For example, as shown in FIG. 12 to FIG. 17, in FIG. 12 to FIG. 17, the control signal Vin_1 is at a low voltage level, the control signal Vin_2 is at a high voltage level, and the switching unit T1 is not Turning on, the signal mask unit 120 does not output the clock signal CLK to one of the plurality of scan lines G1 to GN.

In step S650, the driving circuit selectively receives the reset voltage according to the reset voltage and the first control signal, wherein the reset voltage has a second voltage level, and the reset voltage stops the driving circuit from outputting the clock signal. For example, referring to FIG. 8, when the reset voltage Vrst is at a low voltage level, the switching unit T4 is turned on, at which time the node Q is at a low voltage level, and the switching unit T5 and the switching unit T6 are turned on. At this time, the node BT is at a high voltage level, and the switching unit T1 is not turned on, so the signal mask unit 120 does not output the clock signal CLK to one of the plurality of scanning lines G1 to GN.

In some embodiments, the drive signal En is generated by the signal generator 110 as depicted in FIG. 1 and input to the signal mask unit 120. In some other embodiments, the drive signal En is generated by the previous stage signal mask unit 120 in the display panel 100 and input to the signal mask unit 120 of the stage.

In some embodiments, the reset voltage Vrst and the clock signal CLK shown in FIGS. 4 and 11 are periodically changed.

As shown in FIG. 4 to FIG. 17, when the control signal Vin_1 is at the high voltage level and the control signal Vin_2 is at the low voltage level, the signal mask unit 120 outputs the clock signal CLK to the plurality of scanning lines G1 to GN. One of them. If the clock signal CLK is at a low voltage level, the scan line voltage G[n] is a low voltage level, so one of the plurality of scan lines G1 GN GN is updated with one of the plurality of scan lines G1 GN GN The active region 130 is coupled to the active region 130. On the other hand, when the control signal Vin_1 is at the low voltage level and the control signal Vin_2 is at the high voltage level, the signal mask unit 120 does not output the clock signal CLK to one of the plurality of scan lines G1 to GN. Therefore, one of the plurality of scanning lines G1 to GN does not update the active area 130 coupled to one of the plurality of scanning lines G1 to GN. In the above manner, the embodiment of the present invention can enable the display panel 100 to update only the partial active area 130 that needs to be updated by controlling the control signal Vin_1 and the control signal Vin_2 to reduce the power consumption of the display panel 100.

According to the embodiment of the present invention, the embodiment of the present invention provides a signal mask unit, a signal mask method, and a display panel, and particularly relates to a low power consumption signal mask unit, a signal mask method, and The display panel is effective to reduce the power consumption of the display device without degrading the performance of the display device.

In addition, the above examples include exemplary steps in sequence, but the steps are not necessarily performed in the order shown. Performing these steps in a different order is within the scope of the present disclosure. Such steps may be added, substituted, altered, and/or omitted as appropriate within the spirit and scope of the embodiments of the present disclosure.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make various changes and refinements without departing from the spirit and scope of the present case. The scope defined in the patent application is subject to change.

Claims (10)

A signal mask unit includes: a reset unit for receiving a reset voltage and receiving a first control signal according to a driving signal; and a first switch unit electrically connected to the reset unit for Receiving a clock signal and receiving a second control signal according to the driving signal, wherein the second control signal is inverted with the first control signal; wherein when the first control signal is at a first voltage level and the second control When the signal is at a second voltage level, the reset unit is not activated, and the second control signal turns on the first switch unit to cause the first switch unit to output the clock signal; wherein when the first control signal is in the When the second voltage level is at the first voltage level, the reset unit outputs an operating voltage to the first switching unit, and the operating voltage and the second control signal turn off the first switch unit. The signal mask unit of claim 1, further comprising: a second switch unit electrically connected to the reset unit for receiving the first control signal and conducting the first control signal according to the driving signal to The reset unit. The signal mask unit of claim 1, further comprising: a third switch unit electrically connected to the first switch unit for receiving the second control signal and conducting the second control signal according to the driving signal Number to the first switching unit. The signal mask unit of claim 1, wherein the first switch unit has a control end and an output end, wherein the control end is configured to receive the second control signal, and the output end is configured to output the clock signal, The reset unit is electrically connected to the control terminal and the output terminal to selectively output the operating voltage to the control terminal and the output terminal according to the first control signal. The signal mask unit of claim 4, wherein the reset unit comprises: a fourth switch unit for receiving the reset voltage; and a fifth switch unit for receiving the working voltage, the fifth switch The unit has a control end, wherein the control end of the fifth switch unit is configured to receive the first control signal and is electrically connected to the fourth switch unit; a sixth switch unit is configured to receive the operating voltage, the first The sixth switch unit has a control end and an output end, wherein the control end of the sixth switch unit is electrically connected to the control end of the fifth switch unit, the output end of the sixth switch unit and the first switch The output end of the unit is electrically connected; and a capacitor is electrically connected to the control end of the fifth switch unit. The signal mask unit of claim 5, wherein when the reset voltage and the first control signal turn on the fourth switch unit, the fifth switch unit, and the sixth switch unit, the operating voltage is turned on to The control end of the first switch unit and the output end enable the control of the first switch unit The terminal and the output have the first voltage level. A signal masking method for a driving circuit, comprising: causing the driving circuit to receive a first control signal and a second control signal according to a driving signal; causing the driving circuit to receive a clock signal; and when the first control signal When the first control signal is at a second voltage level, the driving circuit outputs the clock signal; and when the first control signal is at the second voltage level and the second When the control signal is at the first voltage level, the driving circuit stops outputting the clock signal. The signal masking method of claim 7, further comprising: causing the driving circuit to selectively receive an operating voltage according to the reset voltage and the first control signal, wherein the operating voltage has the second voltage level, and The operating voltage causes the drive circuit to stop outputting the clock signal. A display panel comprising: a plurality of scan lines; a plurality of levels of signal generators, wherein each of the signal generators of each stage generates a drive signal and transmits the drive signal to a next stage signal generator; a plurality of levels of signal masks Units respectively coupled to one of the scan lines The signal masking unit of each stage is configured to receive a first control signal and a second control signal according to the driving signal transmitted by the phase signal generator coupled to the stage. The second control signal is inverted from the first control signal, and when the first control signal is at a first voltage level and the second control signal is at a second voltage level, the level signal mask The unit sends a clock signal to one of the scan lines. The display panel of claim 9, wherein the signal mask units of each stage comprise: a reset unit for receiving a reset voltage and receiving the first signal according to the driving signal transmitted by the signal generator a control signal; and a first switching unit electrically connected to the reset unit and one of the scan lines, the first switch unit receiving the second control signal according to the driving signal transmitted by the signal generator Transmitting the clock signal to one of the scan lines when the first switch unit is turned on; wherein when the first control signal is at the second voltage level and the second control signal is at the At a voltage level, the reset unit outputs an operating voltage to the first switching unit, and the operating voltage and the second control signal turn off the first switching unit.