TWI537915B - Common voltage providing circuit - Google Patents

Common voltage providing circuit Download PDF

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TWI537915B
TWI537915B TW103142868A TW103142868A TWI537915B TW I537915 B TWI537915 B TW I537915B TW 103142868 A TW103142868 A TW 103142868A TW 103142868 A TW103142868 A TW 103142868A TW I537915 B TWI537915 B TW I537915B
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transistor
common voltage
level
coupled
level signal
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TW103142868A
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TW201621860A (en
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塗俊達
陳勇志
洪凱尉
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友達光電股份有限公司
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Priority to CN201510060827.6A priority patent/CN104658468A/en
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Publication of TW201621860A publication Critical patent/TW201621860A/en

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共同電壓供應電路 Common voltage supply circuit

本發明係有關於一種控制電路,且特別是有關於一種共同電壓供應電路。 The present invention relates to a control circuit, and more particularly to a common voltage supply circuit.

現有的共同電壓供應電路為配合資料電壓之寫入時序,需在一個幀(frame)的時間內進行多次準位轉換,導致共同電壓供應電路之功耗較高。 The existing common voltage supply circuit cooperates with the writing timing of the data voltage, and needs to perform multiple level conversion in one frame time, resulting in high power consumption of the common voltage supply circuit.

對於上述狀況,雖可藉由修改電路並採用額外的開關元件,以透過控制上述開關元件之切換,而配合資料電壓的寫入時序。如此,僅需於一個幀的時間內切換一次,以降低共同電壓供應電路之功耗。然而,修改電路將導致整體佈線之設計方式複雜,且額外採用開關元件亦會增加共同電壓供應電路之成本。 In the above case, the writing timing of the data voltage can be matched by controlling the switching of the switching elements by modifying the circuit and using an additional switching element. In this way, it is only necessary to switch once in one frame time to reduce the power consumption of the common voltage supply circuit. However, modifying the circuit will result in a complicated design of the overall wiring, and the additional use of switching elements will also increase the cost of the common voltage supply circuit.

由此可見,上述現有的方式,顯然仍存在不便與缺陷,而有待改進。為了解決上述問題,相關領域莫不費盡心思來謀求解決之道,但長久以來仍未發展出適當的解決方案。 It can be seen that the above existing methods obviously have inconveniences and defects, and need to be improved. In order to solve the above problems, the relevant fields have not tried their best to find a solution, but for a long time, no suitable solution has been developed.

發明內容旨在提供本揭示內容的簡化摘要,以使閱讀者對本揭示內容具備基本的理解。此發明內容並非本揭示內容的完整概述,且其用意並非在指出本發明實施例的重要/關鍵元件或界定本發明的範圍。 SUMMARY OF THE INVENTION The Summary of the Disclosure is intended to provide a basic understanding of the present disclosure. This Summary is not an extensive overview of the disclosure, and is not intended to be an

本發明內容之一目的是在提供一種共同電壓供應電路,藉以改善先前技術的問題。 It is an object of the present invention to provide a common voltage supply circuit for improving the problems of the prior art.

為達上述目的,本發明內容之一技術態樣係關於一種共同電壓供應電路。此共同電壓供應電路包含第一電晶體、第二電晶體、第三電晶體、第一電容、第四電晶體及第二電容。第一電晶體、第二電晶體、第三電晶體及第四電晶體皆包含第一端、控制端及控制端。第一電晶體的第一端用以接收第一準位信號,第一電晶體的控制端用以接收掃描信號。第二電晶體的第一端用以接收第二準位信號,上述第一準位信號之電壓準位不同於第二準位信號之電壓準位,第二電晶體的控制端用以接收掃描信號。第三電晶體的第一端用以接收第一共同電壓,第三電晶體的控制端耦接於第一電晶體之第二端,第三電晶體的第二端耦接於輸出端。第一電容耦接於第三電晶體之控制端。第四電晶體的第一端用以接收第二共同電壓,第四電晶體的控制端耦接於第二電晶體之第二端,第四電晶體的第二端耦接於輸出端。第二電容耦接於第四電晶體之控制端。 To achieve the above object, a technical aspect of the present invention relates to a common voltage supply circuit. The common voltage supply circuit includes a first transistor, a second transistor, a third transistor, a first capacitor, a fourth transistor, and a second capacitor. The first transistor, the second transistor, the third transistor, and the fourth transistor each include a first end, a control end, and a control end. The first end of the first transistor is configured to receive the first level signal, and the control end of the first transistor is configured to receive the scan signal. The first end of the second transistor is configured to receive a second level signal, the voltage level of the first level signal is different from the voltage level of the second level signal, and the control end of the second transistor is configured to receive the scan signal. The first end of the third transistor is configured to receive the first common voltage, the control end of the third transistor is coupled to the second end of the first transistor, and the second end of the third transistor is coupled to the output end. The first capacitor is coupled to the control end of the third transistor. The first end of the fourth transistor is configured to receive the second common voltage, the control end of the fourth transistor is coupled to the second end of the second transistor, and the second end of the fourth transistor is coupled to the output end. The second capacitor is coupled to the control end of the fourth transistor.

因此,根據本發明之技術內容,本發明實施例藉由提供一種共同電壓供應電路,藉以在不增加電路佈線之複雜度且不增加電路成本的狀況下,減少共同電壓供應電路輸出之共同電壓的準位切換次數,從而同時達到降低成本及功 耗之目的。 Therefore, according to the technical content of the present invention, the embodiment of the present invention reduces the common voltage outputted by the common voltage supply circuit by providing a common voltage supply circuit, without increasing the complexity of the circuit wiring and increasing the circuit cost. The number of times to switch, so as to reduce costs and work at the same time The purpose of consumption.

在參閱下文實施方式後,本發明所屬技術領域中具有通常知識者當可輕易瞭解本發明之基本精神及其他發明目的,以及本發明所採用之技術手段與實施態樣。 The basic spirit and other objects of the present invention, as well as the technical means and implementations of the present invention, will be readily apparent to those skilled in the art of the invention.

C1~C2‧‧‧電容 C1~C2‧‧‧ capacitor

frame1~frame2‧‧‧幀 Frame1~frame2‧‧‧ frame

G(n)、G(n+3)‧‧‧掃描信號 G(n), G(n+3)‧‧‧ scan signals

Gnd‧‧‧接地端 Gnd‧‧‧ Grounding

Output‧‧‧輸出端 Output‧‧‧output

P1~P2‧‧‧期間 During the period of P1~P2‧‧

T1~T4‧‧‧電晶體 T1~T4‧‧‧O crystal

V1‧‧‧第一準位信號 V1‧‧‧ first level signal

V2‧‧‧第二準位信號 V2‧‧‧second level signal

Vcom+‧‧‧第一共同電壓 Vcom+‧‧‧ first common voltage

Vcom-‧‧‧第二共同電壓 Vcom-‧‧‧second common voltage

Vcom(n)‧‧‧輸出共同電壓 Vcom(n)‧‧‧ output common voltage

為讓本發明之上述和其他目的、特徵、優點與實施例能更明顯易懂,所附圖式之說明如下:第1圖係依照本發明一實施例繪示一種共同電壓供應電路的示意圖。 The above and other objects, features, advantages and embodiments of the present invention will become more <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt;

第2圖係依照本發明另一實施例繪示一種共同電壓供應電路的驅動波形示意圖。 2 is a schematic diagram showing driving waveforms of a common voltage supply circuit according to another embodiment of the present invention.

第3圖係依照本發明又一實施例繪示一種共同電壓供應電路的示意圖。 FIG. 3 is a schematic diagram showing a common voltage supply circuit according to still another embodiment of the present invention.

根據慣常的作業方式,圖中各種特徵與元件並未依比例繪製,其繪製方式是為了以最佳的方式呈現與本發明相關的具體特徵與元件。此外,在不同圖式間,以相同或相似的元件符號來指稱相似的元件/部件。 The various features and elements in the figures are not drawn to scale, and are in the In addition, similar elements/components are referred to by the same or similar element symbols throughout the different drawings.

為了使本揭示內容的敘述更加詳盡與完備,下文針對了本發明的實施態樣與具體實施例提出了說明性的描述;但這並非實施或運用本發明具體實施例的唯一形式。實施方式中涵蓋了多個具體實施例的特徵以及用以建構與操作這 些具體實施例的方法步驟與其順序。然而,亦可利用其他具體實施例來達成相同或均等的功能與步驟順序。 The description of the embodiments of the present invention is intended to be illustrative and not restrictive. The features of the specific embodiments are covered in the embodiments and are used to construct and operate The method steps of the specific embodiments and their order. However, other specific embodiments may be utilized to achieve the same or equivalent function and sequence of steps.

除非本說明書另有定義,此處所用的科學與技術詞彙之含義與本發明所屬技術領域中具有通常知識者所理解與慣用的意義相同。此外,在不和上下文衝突的情形下,本說明書所用的單數名詞涵蓋該名詞的複數型;而所用的複數名詞時亦涵蓋該名詞的單數型。 The scientific and technical terms used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the invention pertains, unless otherwise defined herein. In addition, the singular noun used in this specification covers the plural of the noun in the case of no conflict with the context; the plural noun of the noun is also included in the plural noun used.

另外,關於本文中所使用之「耦接」,可指二或多個元件相互直接作實體或電性接觸,或是相互間接作實體或電性接觸,亦可指二或多個元件相互操作或動作。 In addition, the term "coupled" as used herein may mean that two or more elements are in direct physical or electrical contact with each other, or indirectly in physical or electrical contact with each other, or that two or more elements are interoperable. Or action.

為改善降低共同電壓供應電路之功耗所導致整體佈線之設計方式複雜,且額外增加共同電壓供應電路之成本的問題,本發明提出一種新式共同電壓供應電路,說明如後。 In order to improve the design of the overall wiring by reducing the power consumption of the common voltage supply circuit, and additionally increasing the cost of the common voltage supply circuit, the present invention proposes a new common voltage supply circuit, as explained later.

第1圖係依照本發明一實施例繪示一種共同電壓供應電路的示意圖。如圖所示,共同電壓供應電路包含第一電晶體T1、第二電晶體T2、第三電晶體T3、第一電容C1、第四電晶體T4及第二電容C2。進一步而言,上述第一電晶體T1至第四電晶體T4皆包含第一端、控制端及第二端。 FIG. 1 is a schematic diagram showing a common voltage supply circuit according to an embodiment of the invention. As shown, the common voltage supply circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a first capacitor C1, a fourth transistor T4, and a second capacitor C2. Further, each of the first to fourth transistors T1 to T4 includes a first end, a control end, and a second end.

於連接關係上,第三電晶體T3之控制端耦接於第一電晶體T1之第二端,第三電晶體T3之第二端耦接於輸出端Output。第一電容C1耦接於第三電晶體T3之控制端。第四電晶體T4之控制端耦接於第二電晶體T2之第二端,第四電晶體T4之第二端耦接於輸出端Output。第二電容C2耦接於第四電 晶體T4之控制端。 In the connection relationship, the control end of the third transistor T3 is coupled to the second end of the first transistor T1, and the second end of the third transistor T3 is coupled to the output terminal Output. The first capacitor C1 is coupled to the control terminal of the third transistor T3. The control terminal of the fourth transistor T4 is coupled to the second terminal of the second transistor T2, and the second terminal of the fourth transistor T4 is coupled to the output terminal. The second capacitor C2 is coupled to the fourth battery The control end of crystal T4.

於操作關係上,第一電晶體T1之第一端用以接收第一準位信號V1,第一電晶體T1之控制端用以接收掃描信號G(n)。第二電晶體T2之第一端用以接收第二準位信號V2,上述第一準位信號V1之電壓準位不同於第二準位信號V2之電壓準位,此外,第二電晶體T2之控制端用以接收掃描信號G(n)。第三電晶體T3之第一端用以接收第一共同電壓Vcom+。第四電晶體T4之第一端用以接收第二共同電壓Vcom-。 In an operational relationship, the first end of the first transistor T1 is configured to receive the first level signal V1, and the control end of the first transistor T1 is configured to receive the scan signal G(n). The first end of the second transistor T2 is configured to receive the second level signal V2. The voltage level of the first level signal V1 is different from the voltage level of the second level signal V2. In addition, the second transistor T2 The control terminal is configured to receive the scan signal G(n). The first end of the third transistor T3 is configured to receive the first common voltage Vcom+. The first end of the fourth transistor T4 is configured to receive the second common voltage Vcom-.

為瞭解共同電壓供應電路之驅動模式及提供共同電壓的方式,請一併參閱第2圖,其係依照本發明另一實施例繪示一種共同電壓供應電路的驅動波形示意圖。請參閱第2圖,首先,於期間P1之前,共同電壓供應電路由其輸出端Output輸出高準位之共同電壓Vcom(n)。 In order to understand the driving mode of the common voltage supply circuit and the manner of providing a common voltage, please refer to FIG. 2, which is a schematic diagram of driving waveforms of a common voltage supply circuit according to another embodiment of the present invention. Referring to FIG. 2, first, before the period P1, the common voltage supply circuit outputs a common voltage Vcom(n) of the high level from its output terminal Output.

隨後,於期間P1,掃描信號G(n)為高準位信號,第一電晶體T1及第二電晶體T2依據高準位信號而導通。同時,第一準位信號V1為低準位信號,而第二準位信號V2為高準位信號,第三電晶體T3依據低準位信號而關閉,第四電晶體T4則根據高準位信號而導通,此時,第四電晶體T4提供第二共同電壓Vcom-至輸出端Output,而由輸出端Output提供低準位之第二共同電壓Vcom-,並於一個幀frame1內維持同一準位。換言之,輸出端Output輸出之共同電壓Vcom(n)被第四電晶體T4拉低,並於一個幀frame1內維持低準位。 Subsequently, during the period P1, the scan signal G(n) is a high level signal, and the first transistor T1 and the second transistor T2 are turned on according to the high level signal. At the same time, the first level signal V1 is a low level signal, and the second level signal V2 is a high level signal, the third transistor T3 is turned off according to the low level signal, and the fourth transistor T4 is according to the high level. The signal is turned on. At this time, the fourth transistor T4 provides the second common voltage Vcom- to the output terminal, and the output terminal Output provides the second common voltage Vcom- of the low level, and maintains the same standard in one frame1. Bit. In other words, the common voltage Vcom(n) outputted by the output terminal is pulled low by the fourth transistor T4 and maintained at a low level within one frame frame1.

再者,請參閱第2圖之空白期間blanking,於此期間,第一準位信號V1轉換為高準位信號,而第二準位信號 V2轉換為低準位信號。接著,請參閱第2圖之期間P2,於此期間,掃描信號G(n)為高準位信號,第一電晶體T1及第二電晶體T2依據高準位信號而導通。同時,第三電晶體T3依據高準位之第一準位信號V1而導通,第四電晶體T4則根據低準位之第二準位信號V2而關閉,此時,第三電晶體T3提供第一共同電壓Vcom+至輸出端Output,而由輸出端Output提供高準位之第一共同電壓Vcom+,並於一個幀frame2內維持高準位。 Furthermore, please refer to the blank period blanking in FIG. 2, during which the first level signal V1 is converted into a high level signal, and the second level signal is V2 is converted to a low level signal. Next, please refer to the period P2 of FIG. 2, during which the scan signal G(n) is a high level signal, and the first transistor T1 and the second transistor T2 are turned on according to the high level signal. At the same time, the third transistor T3 is turned on according to the first level signal V1 of the high level, and the fourth transistor T4 is turned off according to the second level signal V2 of the low level. At this time, the third transistor T3 provides The first common voltage Vcom+ is output to the output, and the first common voltage Vcom+ of the high level is provided by the output terminal, and the high level is maintained in one frame 2 .

如此一來,本發明實施例之共同電壓供應電路可配合資料電壓之寫入時序而相應地提供所需之共同電壓,且在同一幀的時間內維持同一準位,藉以減少共同電壓之切換次數,而降低共同電壓供應電路之功耗。此外,本發明實施例之共同電壓供應電路的電路佈線之設計方式簡單,僅需4T2C(4個電晶體與2個電容)之架構,而能降低共同電壓供應電路之成本,並易於與陣列上閘極(Gate IC on Array,GOA)電路進行整合。 In this way, the common voltage supply circuit of the embodiment of the present invention can provide the required common voltage according to the write timing of the data voltage, and maintain the same level within the same frame time, thereby reducing the number of common voltage switching. And reduce the power consumption of the common voltage supply circuit. In addition, the circuit layout of the common voltage supply circuit of the embodiment of the present invention is simple in design, only requires 4T2C (4 transistors and 2 capacitors), and can reduce the cost of the common voltage supply circuit, and is easy to be on the array. The Gate IC on Array (GOA) circuit is integrated.

本發明實施例之共同電壓供應電路之解決問題的主要技術手段已說明如上,以下僅舉幾個實現共同電壓供應電路之實施例,以使本發明更易於理解,然本發明並不以後續實施例為限,合先敘明。 The main technical means for solving the problem of the common voltage supply circuit of the embodiment of the present invention has been described above. Only the embodiments implementing the common voltage supply circuit will be described below to make the present invention easier to understand, but the present invention is not implemented in the following. The example is limited to the first.

在一實施例中,請參閱第1圖,上述第一共同電壓Vcom+之電壓值大於第二共同電壓Vcom-之電壓值。舉例而言,第一共同電壓Vcom+之電壓值可為5V(伏特),第二共同電壓Vcom-之電壓值可為0V,相應地,資料電壓可為1V~5V。相較於一般資料驅動電路提供的資料電壓為1V~5V 及-1V~-5V,搭配本發明實施例之共同電壓供應電路,可使資料驅動電路提供的資料電壓之電壓值大幅度減少,因而進一步減少功耗。 In an embodiment, referring to FIG. 1, the voltage value of the first common voltage Vcom+ is greater than the voltage value of the second common voltage Vcom-. For example, the voltage value of the first common voltage Vcom+ may be 5V (volts), and the voltage value of the second common voltage Vcom- may be 0V. Accordingly, the data voltage may be 1V~5V. Compared with the general data drive circuit, the data voltage is 1V~5V. And -1V~-5V, with the common voltage supply circuit of the embodiment of the invention, the voltage value of the data voltage provided by the data driving circuit can be greatly reduced, thereby further reducing power consumption.

在另一實施例中,請一併參閱第1圖及第2圖,第一電晶體T1及第二電晶體T2於期間P1根據高準位之掃描信號G(n)而開啟,第一電晶體T1及第二電晶體T2分別將低準位之第一準位信號V1及高準位之第二準位信號V2提供給第三電晶體T3及第四電晶體T4之控制端,使得第四電晶體T4根據高準位之第二準位信號V2而開啟並提供第二共同電壓Vcom-給輸出端Output。 In another embodiment, referring to FIG. 1 and FIG. 2 together, the first transistor T1 and the second transistor T2 are turned on according to the high-level scan signal G(n) during the period P1, and the first The crystal T1 and the second transistor T2 respectively supply the first level signal V1 of the low level and the second level signal V2 of the high level to the control ends of the third transistor T3 and the fourth transistor T4, so that The fourth transistor T4 is turned on according to the second level signal V2 of the high level and provides a second common voltage Vcom- to the output terminal Output.

於又一實施例中,請一併參閱第1圖及第2圖,第一電晶體T1及第二電晶體T2於期間P2根據高準位之掃描信號G(n)而開啟,第一電晶體T1及第二電晶體T2分別將高準位之第一準位信號V1及低準位之第二準位信號V2提供給第三電晶體T3及第四電晶體T4之控制端,使得第三電晶體T3根據高準位之第一準位信號V1而開啟並提供第一共同電壓Vcom+給輸出端Output。 In still another embodiment, referring to FIG. 1 and FIG. 2 together, the first transistor T1 and the second transistor T2 are turned on according to the high-level scan signal G(n) during the period P2, and the first The crystal T1 and the second transistor T2 respectively supply the first level signal V1 of the high level and the second level signal V2 of the low level to the control ends of the third transistor T3 and the fourth transistor T4, respectively The three transistors T3 are turned on according to the first level signal V1 of the high level and provide the first common voltage Vcom+ to the output terminal Output.

於再一實施例中,請參閱第1圖,第一電容C1包含第一端及第二端,上述第一電容C1之第一端耦接於第三電晶體T3之控制端,而第一電容C1之第二端用以耦接於接地端Gnd。另一方面,第二電容C2包含第一端及第二端,上述第二電容C2之第一端耦接於第四電晶體T4之控制端,而第二電容C2之第二端耦接於接地端Gnd。 In another embodiment, referring to FIG. 1 , the first capacitor C1 includes a first end and a second end, and the first end of the first capacitor C1 is coupled to the control end of the third transistor T3, and the first The second end of the capacitor C1 is coupled to the ground end Gnd. On the other hand, the second capacitor C2 includes a first end and a second end, the first end of the second capacitor C2 is coupled to the control end of the fourth transistor T4, and the second end of the second capacitor C2 is coupled to the second end Ground terminal Gnd.

另一方面,本發明實施例之共同電壓供應電路的 電容有另一種配置方式,此配置方式請參閱第3圖,其係依照本發明又一實施例繪示一種共同電壓供應電路的示意圖。如圖所示,第一電容C1包含第一端及第二端,上述第一電容C1之第一端耦接於第三電晶體T3之控制端,而第一電容C1之第二端耦接於第三電晶體T3之第二端。另一方面,第二電容C2包含第一端及第二端,上述第二電容C2之第一端耦接於第四電晶體T4之控制端,而第二電容C2之第二端第二端耦接於第四電晶體T4之第二端。在本實施例中,上述第一電容C1及第二電容C2可分別為第三電晶體T3及第四電晶體T4之寄生電容,因此,相較於第1圖所示之共同電壓供應電路,在第3圖中之共同電壓供應電路由於採用電晶體本身之寄生電容,從而不需額外配置電容,進而節省成本。 On the other hand, the common voltage supply circuit of the embodiment of the present invention There is another configuration of the capacitor. For the configuration, please refer to FIG. 3 , which is a schematic diagram of a common voltage supply circuit according to another embodiment of the invention. As shown in the figure, the first capacitor C1 includes a first end and a second end. The first end of the first capacitor C1 is coupled to the control end of the third transistor T3, and the second end of the first capacitor C1 is coupled. At the second end of the third transistor T3. On the other hand, the second capacitor C2 includes a first end and a second end, the first end of the second capacitor C2 is coupled to the control end of the fourth transistor T4, and the second end of the second capacitor C2 is connected to the second end. The second end of the fourth transistor T4 is coupled. In this embodiment, the first capacitor C1 and the second capacitor C2 may be parasitic capacitances of the third transistor T3 and the fourth transistor T4, respectively. Therefore, compared to the common voltage supply circuit shown in FIG. The common voltage supply circuit in Fig. 3 uses the parasitic capacitance of the transistor itself, so that no additional capacitance is required, thereby saving cost.

由上述本發明實施方式可知,應用本發明具有下列優點。本發明實施例藉由提供一種共同電壓供應電路,藉以在不增加電路佈線之複雜度且不增加電路成本的狀況下,減少共同電壓供應電路輸出之共同電壓的準位切換次數,從而同時達到降低成本及功耗之目的。 It will be apparent from the above-described embodiments of the present invention that the application of the present invention has the following advantages. The embodiment of the present invention provides a common voltage supply circuit, thereby reducing the number of times of common voltage switching of the common voltage supply circuit output without increasing the complexity of the circuit wiring and increasing the circuit cost, thereby simultaneously reducing The purpose of cost and power consumption.

雖然上文實施方式中揭露了本發明的具體實施例,然其並非用以限定本發明,本發明所屬技術領域中具有通常知識者,在不悖離本發明之原理與精神的情形下,當可對其進行各種更動與修飾,因此本發明之保護範圍當以附隨申請專利範圍所界定者為準。 Although the embodiments of the present invention are disclosed in the above embodiments, the present invention is not intended to limit the invention, and the present invention may be practiced without departing from the spirit and scope of the invention. Various changes and modifications may be made thereto, and the scope of the invention is defined by the scope of the appended claims.

C1~C2‧‧‧電容 C1~C2‧‧‧ capacitor

G(n)‧‧‧掃描信號 G(n)‧‧‧ scan signal

Gnd‧‧‧接地端 Gnd‧‧‧ Grounding

Output‧‧‧輸出端 Output‧‧‧output

T1~T4‧‧‧電晶體 T1~T4‧‧‧O crystal

V1‧‧‧第一準位信號 V1‧‧‧ first level signal

V2‧‧‧第二準位信號 V2‧‧‧second level signal

Vcom+‧‧‧第一共同電壓 Vcom+‧‧‧ first common voltage

Vcom-‧‧‧第二共同電壓 Vcom-‧‧‧second common voltage

Claims (10)

一種共同電壓供應電路,包含:一第一電晶體,包含:一第一端,用以接收一第一準位信號;一控制端,用以接收一掃描信號;以及一第二端;一第二電晶體,包含:一第一端,用以接收一第二準位信號,其中該第一準位信號之電壓準位不同於該第二準位信號之電壓準位;一控制端,用以接收該掃描信號;以及一第二端;一第三電晶體,包含:一第一端,用以接收一第一共同電壓;一控制端,耦接於該第一電晶體之該第二端;以及一第二端,耦接於一輸出端;一第一電容,耦接於該第三電晶體之該控制端;一第四電晶體,包含:一第一端,用以接收一第二共同電壓;一控制端,耦接於該第二電晶體之該第二端;以及一第二端,耦接於該輸出端;以及一第二電容,耦接於該第四電晶體之該控制端,其中該第一準位信號之電壓準位和該第二準位信號之電壓準位在同一幀的時間內不發生改變。 A common voltage supply circuit includes: a first transistor, comprising: a first end for receiving a first level signal; a control end for receiving a scan signal; and a second end; The second transistor includes: a first end for receiving a second level signal, wherein a voltage level of the first level signal is different from a voltage level of the second level signal; Receiving the scan signal; and a second end; a third transistor, comprising: a first end for receiving a first common voltage; and a control end coupled to the second of the first transistor And a second end coupled to the output end; a first capacitor coupled to the control end of the third transistor; a fourth transistor comprising: a first end for receiving a a second common voltage; a control end coupled to the second end of the second transistor; and a second end coupled to the output end; and a second capacitor coupled to the fourth transistor The control terminal, wherein the voltage level of the first level signal and the second level signal Pressure level does not change within the same time frame. 如請求項1所述之共同電壓供應電路,其中該第一電容包含:一第一端,耦接於該第三電晶體之該控制端;以及一第二端,用以耦接於一接地端。 The common voltage supply circuit of claim 1, wherein the first capacitor comprises: a first end coupled to the control end of the third transistor; and a second end coupled to a ground end. 如請求項2所述之共同電壓供應電路,其中該第二電容包含:一第一端,耦接於該第四電晶體之該控制端;以及一第二端,耦接於該接地端。 The common voltage supply circuit of claim 2, wherein the second capacitor comprises: a first end coupled to the control end of the fourth transistor; and a second end coupled to the ground end. 如請求項1所述之共同電壓供應電路,其中該若該第一準位信號為高電壓準位,則該第二準位信號為低電壓準位。 The common voltage supply circuit of claim 1, wherein the second level signal is a low voltage level if the first level signal is a high voltage level. 如請求項1所述之共同電壓供應電路,其中該若該第一準位信號為低電壓準位,則該第二準位信號為高電壓準位。 The common voltage supply circuit of claim 1, wherein the second level signal is a high voltage level if the first level signal is a low voltage level. 如請求項1所述之共同電壓供應電路,其中該第一共同電壓之電壓值大於該第二共同電壓之電壓值。 The common voltage supply circuit of claim 1, wherein the voltage value of the first common voltage is greater than the voltage value of the second common voltage. 如請求項1所述之共同電壓供應電路,其中該第一電晶體及該第二電晶體於一第一期間根據高準位之該掃描信號而開啟,該第一電晶體及該第二電晶體分別將低準 位之該第一準位信號及高準位之該第二準位信號提供予該第三電晶體及該第四電晶體之該控制端,俾使該第四電晶體根據高準位之該第二準位信號而開啟並提供該第二共同電壓予該輸出端。 The common voltage supply circuit of claim 1, wherein the first transistor and the second transistor are turned on according to the scan signal of a high level during a first period, the first transistor and the second transistor The crystal will be low The second level signal of the first level signal and the high level are supplied to the control terminals of the third transistor and the fourth transistor, so that the fourth transistor is in accordance with the high level The second level signal is turned on and the second common voltage is supplied to the output terminal. 如請求項7所述之共同電壓供應電路,其中該第一電晶體及該第二電晶體於一第二期間根據高準位之該掃描信號而開啟,該第一電晶體及該第二電晶體分別將高準位之該第一準位信號及低準位之該第二準位信號提供予該第三電晶體及該第四電晶體之該控制端,俾使該第三電晶體根據高準位之該第一準位信號而開啟並提供該第一共同電壓予該輸出端。 The common voltage supply circuit of claim 7, wherein the first transistor and the second transistor are turned on according to the scan signal of a high level during a second period, the first transistor and the second transistor The crystal respectively supplies the first level signal of the high level and the second level signal of the low level to the control end of the third transistor and the fourth transistor, so that the third transistor is The first level signal of the high level turns on and provides the first common voltage to the output terminal. 一種共同電壓供應電路,包含:一第一電晶體,包含:一第一端,用以接收一第一準位信號;一控制端,用以接收一掃描信號;以及一第二端;一第二電晶體,包含:一第一端,用以接收一第二準位信號,其中該第一準位信號之電壓準位不同於該第二準位信號之電壓準位;一控制端,用以接收該掃描信號;以及一第二端;一第三電晶體,包含: 一第一端,用以接收一第一共同電壓;一控制端,耦接於該第一電晶體之該第二端;以及一第二端,耦接於一輸出端;一第一電容,包含:一第一端,耦接於該第三電晶體之該控制端;以及一第二端,耦接於該第三電晶體之該第二端;一第四電晶體,包含:一第一端,用以接收一第二共同電壓;一控制端,耦接於該第二電晶體之該第二端;以及一第二端,耦接於該輸出端;以及一第二電容,耦接於該第四電晶體之該控制端。 A common voltage supply circuit includes: a first transistor, comprising: a first end for receiving a first level signal; a control end for receiving a scan signal; and a second end; The second transistor includes: a first end for receiving a second level signal, wherein a voltage level of the first level signal is different from a voltage level of the second level signal; Receiving the scan signal; and a second end; a third transistor comprising: a first end is configured to receive a first common voltage; a control end is coupled to the second end of the first transistor; and a second end is coupled to an output end; a first capacitor, The first end is coupled to the control end of the third transistor; and the second end is coupled to the second end of the third transistor; a fourth transistor includes: One end is configured to receive a second common voltage; a control end is coupled to the second end of the second transistor; and a second end is coupled to the output end; and a second capacitor coupled Connected to the control end of the fourth transistor. 如請求項9所述之共同電壓供應電路,其中該第二電容包含:一第一端,耦接於該第四電晶體之該控制端;以及一第二端,耦接於該第四電晶體之該第二端。 The common voltage supply circuit of claim 9, wherein the second capacitor comprises: a first end coupled to the control end of the fourth transistor; and a second end coupled to the fourth The second end of the crystal.
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