TWI443626B - Common voltage supply circuit of display - Google Patents

Description

Display common voltage supply circuit

The present invention relates to a voltage supply circuit, and more particularly to a common voltage supply circuit for a display.

In the current design of the common voltage supply circuit, the power consumption can be reduced by a Capacitance Coupling Driver (CCD) technology. The principle of the capacitive coupling driver technology is to divide the common voltage of the pixels of each column into an AC common voltage (AC VCOM) and a DC common voltage (DC VCOM). After each data writing is completed, after the pixel film transistor is turned off, the AC VCOM signal is flipped again. At this time, the capacitive coupling effect will push or lower the pixel voltage to the correct level, thus, the data The write voltage only needs to be 1/2 of the original (for example, from 5V to -5V to 5V~0V), so the power saving effect can be achieved.

Since different process thin film transistors have their own advantages and disadvantages, how to choose a suitable thin film transistor to make a common voltage supply circuit that meets the design requirements is also considered by researchers. For example, the uniformity of an amorphous germanium film transistor (abbreviated as α-TFT) is good, but the electron mobility of the α-TFT is poor. If a common voltage supply circuit is to be fabricated using an α-TFT, the required circuit layout area is required. Larger, it is more difficult to meet the design requirements of narrowing the width of the border. Therefore, the current capacitively coupled driver technology is applied to low temperature polycrystalline germanium (LTPS) products, but low temperature polycrystalline germanium thin film transistors (LTPS-TFT) have higher electron mobility, but are limited by the crystallization process. However, it is impossible to make a large area, and in particular, the number of masks required for the LTPS-TFT process is large, and the relative manufacturing cost is high.

In addition, since the amorphous indium gallium zinc oxide thin film transistor (abbreviated as α-IGZO TFT) has a high electron mobility, it is generally about 10 times that of hydrogen-containing amorphous germanium (abbreviated as α-Si:H). The α-IGZO TFT is also more uniform than LTPS-TFTF, and because the process is similar to α-Si:H, it is easy to produce in the current α-Si:H production line. However, in the current common voltage supply circuit designed with an α-IGZO TFT, 0 volts is usually regarded as the turn-off voltage of the TFT. However, sometimes a serious leakage path may occur due to the drifting of the shutdown voltage, which may cause the output voltage of the shared voltage supply circuit to fail. In addition, the architecture of the current shared voltage supply circuit is somewhat complicated.

The invention provides a common voltage supply circuit for a display, which improves the problem that the current common voltage supply circuit may fail due to the drift condition of the closing voltage of the transistor with a relatively simplified circuit structure.

Therefore, the common voltage supply circuit of the display of the present invention includes a control stage and an output stage. The control stage has a first control unit and a second control unit. The first control unit receives the scan signal and the clock signal respectively to provide the first control signal. The second control unit receives the scan signal and the complementary clock signal respectively to provide a second control signal. The output stage is electrically coupled to the control stage. The output stage has a first switching element, a second switching element and an output. The first switching element receives the first control signal and the first common voltage, respectively, and is turned on by the level of the first control signal to output the first common voltage to the output end. The second switching element receives the second control signal and the second common voltage respectively, and is turned on by the second control signal to output the second common voltage to the output end.

In summary, the common voltage supply circuit of the display of the present invention realizes a simplified circuit structure by using four switching elements and two capacitors, and correspondingly gives a clock of different phases of the common voltage supply circuit according to the time of each frame. The signal is such that some of the switching elements can be stably maintained in a closed state, thereby avoiding a leakage path. Therefore, the common voltage supply circuit of the display of the present invention can reduce or solve the problem that the switching element may cause an output failure due to the drift of the off voltage, thereby improving the stability of the common voltage supply circuit.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

Please refer to FIG. 1. FIG. 1 is a block diagram of a circuit according to an embodiment of the present invention. As shown in FIG. 1, the common voltage supply circuit 100 of the display of the embodiment of the present invention includes a control stage 10 and an output stage 20.

The control stage 10 has a first control unit 12 and a second control unit 14. The first control unit 12 is electrically coupled to the gate driving unit 30 and receives the scan signal Gn and the clock signal CK, respectively, and provides the first control signal at the node QH. The scan signal Gn is transmitted from the gate driving unit 30 to the first control unit 12 through the scan line 32. The clock signal CK is independently given, and the level of the clock signal CK is inverted once per frame. In another embodiment of the present invention, the clock signal CK may also be input to the clock signal of the displacement register (not shown) in the gate driving unit 30 and matched with the signal switching circuit (in the figure). Not shown), or provided by a clock signal generator (not shown).

More specifically, the first control unit 12 includes a switching element T1 and a capacitor C1. The switching element T1 has a gate terminal 111, a source terminal 113, and a 汲 terminal 115. The switching element T1 can be an NMOS type thin film transistor switch, but is not limited thereto. The 汲 terminal 115 of the switching element T1 receives the clock signal CK. The gate terminal 111 of the switching element T1 receives the scan signal Gn. Capacitor C1 has a first end (not shown) and a second end (not shown). The first end of the capacitor C1 is electrically coupled to the node QH. The node QH is electrically coupled to the source terminal 113 of the switching element T1. The second end of the capacitor C1 is electrically coupled to the ground.

As shown in FIG. 1 , the second control unit 14 is electrically coupled to the gate driving unit 30 and receives the scan signal Gn and the complementary clock signal XCK, respectively, and provides a second control signal at the node QL. The scan signal Gn is transmitted from the gate driving unit 30 to the second control unit 14 through the scan line 32. The complementary clock signal XCK is independently given, and the level of the complementary clock signal XCK is inverted once per frame. In another embodiment of the present invention, the complementary clock signal XCK can be input to the complementary clock signal of the displacement register (not shown) in the gate driving unit 30 and matched with the signal switching circuit (Fig. Not shown), or provided by a clock signal generator (not shown). In addition, the clock signal CK is opposite to the phase of the complementary clock signal XCK.

More specifically, the second control unit 14 includes a switching element T2 and a capacitor C2. The switching element T2 has a gate terminal 211, a source terminal 213, and a drain terminal 215. The switching element T2 can be an NMOS type thin film transistor switch, but is not limited thereto. The 汲 terminal 215 of the switching element T2 receives the complementary clock signal XCK. The gate terminal 211 of the switching element T2 receives the scan signal Gn. Capacitor C2 has a first end (not shown) and a second end (not shown). The first end of the capacitor C2 is electrically coupled to the node QL. The node QL is electrically coupled to the source terminal 213 of the switching element T2. The second end of the capacitor C2 is electrically coupled to the ground.

As shown in FIG. 1 , the output stage 20 is electrically coupled to the control stage 10 . The output stage 20 has a switching element T3, a switching element T4 and an output terminal VCOM(n). The switching element T3 has a gate terminal 311, a source terminal 313, and a drain terminal 315. The switching element T3 can be an NMOS type thin film transistor switch, but is not limited thereto. The gate terminal 311 of the switching element T3 is electrically coupled to the node QH to receive the first control signal. The drain terminal 315 of the switching element T3 receives the first common voltage VCOMH. The source terminal 313 of the switching element T3 is electrically coupled to the output terminal VCOM(n). The switching element T3 receives the first control signal and the first common voltage VCOMH, respectively. The switching element T3 is turned on by the level of the first control signal to output the first common voltage VCOMH to the output terminal VCOM(n).

The switching element T4 has a gate terminal 411, a source terminal 413, and a drain terminal 415. The switching element T4 can be an NMOS type thin film transistor switch, but is not limited thereto. The gate terminal 411 of the switching element T4 is electrically coupled to the node QL to receive the second control signal. The 汲 terminal 415 of the switching element T4 is electrically coupled to the output terminal VCOM(n). The source terminal 413 of the switching element T4 receives the second common voltage VCOML. The switching element T4 receives the second control signal and the second common voltage VCOML, respectively. The switching element T4 is turned on by the level of the second control signal to output the second common voltage VCOML to the output terminal VCOM(n). In addition, the switching elements T1 to T4 in the embodiment of the present invention are preferably Indium Gallium Zinc Oxide (IGZO) thin film transistors.

Next, please refer to FIG. 1 and FIG. 2 together. FIG. 2 is a schematic diagram of signal waveforms according to an embodiment of the present invention. The principle of operation of the shared voltage supply circuit 100 will be briefly described below.

When the switching element T1 is turned on by the high level GnH of the scan signal Gn, the capacitor C1 is charged to the first voltage level by the clock signal CK having the first phase to provide the first control signal at the node QH. The switching element T3 is turned on according to the level of the first control signal, so that the first common voltage VCOMH is outputted from the output terminal VCOM(n) of the output stage 20. At the same time, when the switching element T2 is turned on by the high level GnH of the scanning signal Gn, the capacitor C2 is charged to the second voltage level by the complementary clock signal XCK having the second phase to provide the second control signal at the node QL. The switching element T4 is kept off according to the level of the second control signal.

As shown in FIG. 2, the high level GnH of the scan signal Gn is higher than the high level CKH of the clock signal CK and the high level XCKH of the complementary clock signal XCK. The high level CKH of the clock signal CK is the same as the high level XCKH of the complementary clock signal XCK. The high level CKH of the clock signal CK is higher than the high level VCOM(n)H of the first common voltage VCOMH.

It should be noted that the low level GnL of the scan signal Gn is lower than the low level CKL of the clock signal CK and the low level XCKL of the complementary clock signal XCK. The low level CKL of the clock signal CK is the same as the low level XCKL of the complementary clock signal XCK. Therefore, the gate voltage difference of the switching element T2 of the second control unit 14 is a negative value, wherein the gate voltage difference can be, for example, a voltage difference between the gate terminal 211 and the source terminal 213 of the switching element T2. Therefore, it is ensured that the switching element T2 is less susceptible to leakage due to the drift of the off voltage.

In addition, the low level CKL of the clock signal CK is lower than the low level VCOM(n)L of the second common voltage VCOML. Similarly, the gate voltage difference of the switching element T4 of the output stage 20 is a negative value, wherein the gate voltage difference can be, for example, the voltage difference between the gate terminal 411 and the source terminal 413 of the switching element T4. Therefore, it is ensured that the switching element T4 is less susceptible to leakage due to the drift of the off voltage.

In other words, during the Nth frame NF time, the switching element T2 is turned off by the first negative voltage, and the switching element T4 is turned off by the second negative voltage, where N is a positive integer greater than or equal to zero. During the Nth frame NF time, the low level GnL of the scan signal Gn is lower than the low level XCKL of the complementary clock signal XCK to form the first negative voltage. In addition, the low level of the second control signal outputted by the node QL (corresponding to the level of the source terminal 213 of the switching element T2) is lower than the low level VCOM(n)L of the second common voltage VCOML to form the first Two negative voltages.

As a result, when the output terminal VCOM(n) outputs the first common voltage VCOMH, the switching element T2 and the switching element T4 are less likely to be affected by the drift of the off voltage, thereby causing leakage, thereby improving the stability of the common voltage supply circuit 100.

Then, when the next scan signal Gn is transmitted to the control stage 10 again, the control stage 10 receives the clock signal CK having the second phase and the complementary clock signal XCK having the first phase.

The capacitor C1 is charged to the second voltage level by the clock signal CK having the second phase to provide the first control signal at the node QH. The switching element T3 is kept off according to the level of the first control signal. At the same time, when the switching element T2 is turned on by the high level GnH of the scanning signal Gn, the capacitor C2 is charged to the first voltage level by the complementary clock signal XCK having the first phase to provide the second control signal at the node QL. The switching element T4 is turned on according to the level of the second control signal, so that the output terminal VCOM(n) of the output stage 20 outputs the second common voltage VCOML.

It should be noted that the low level GnL of the scan signal Gn is lower than the low level CKL of the clock signal CK and the low level XCKL of the complementary clock signal XCK. The low level CKL of the clock signal CK is the same as the low level XCKL of the complementary clock signal XCK. Therefore, the gate voltage difference of the switching element T1 of the first control unit 12 is a negative value, wherein the gate voltage difference can be, for example, a voltage difference between the gate terminal 111 of the switching element T1 and the source terminal 113. Therefore, it is ensured that the switching element T1 is less susceptible to leakage due to the drift of the off voltage.

In addition, the low level CKL of the clock signal CK is lower than the low level VCOM(n)L of the second common voltage VCOML. Similarly, the gate voltage difference of the switching element T3 of the output stage 20 is a negative value, wherein the gate voltage difference can be, for example, the voltage difference between the gate terminal 311 and the source terminal 313 of the switching element T3. Therefore, it is ensured that the switching element T3 is less susceptible to leakage due to the drift of the off voltage.

In other words, during the N+1th frame N+1F, the switching element T1 is turned off by the third negative voltage, and the switching element T3 is turned off by the fourth negative voltage, where N is a positive integer greater than or equal to zero. During the N+1th frame N+1F, the low level GnL of the scan signal Gn is lower than the low level CKL of the clock signal CK to form the third negative voltage. In addition, the low level of the first control signal outputted by the node QH (corresponding to the level of the source terminal 113 of the switching element T1) is lower than the low level VCOM(n)H of the first common voltage VCOMH to form the first Four negative voltages.

Viewed from another aspect, during the Nth frame NF, the control stage 10 provides a first control signal having a first phase to the switching element T3 and a second control signal having a second phase to the switching element T4. During the N+1th frame N+1F, the control stage 10 provides a first control signal having a second phase to the switching element T3, and a second control signal having a first phase to the switching element T4.

As a result, when the output terminal VCOM(n) outputs the second common voltage VCOML, the switching element T1 and the switching element T3 are less likely to be affected by the drift of the off voltage, thereby causing leakage, thereby improving the stability of the common voltage supply circuit 100.

In summary, the common voltage supply circuit of the display of the present invention realizes a simplified circuit structure by using four switching elements and two capacitors, and correspondingly gives a clock of different phases of the common voltage supply circuit according to the time of each frame. The signal is such that some of the switching elements can be stably maintained in a closed state, thereby avoiding a leakage path. Therefore, the common voltage supply circuit of the display of the present invention can reduce or solve the problem that the switching element may cause an output failure due to the drift of the off voltage, thereby improving the stability of the common voltage supply circuit.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

10. . . Control level

12. . . First control unit

14. . . Second control unit

100. . . Shared voltage supply circuit

111. . . Gate extreme

113. . . Source extreme

115. . . Extreme

20. . . Output stage

211. . . Gate extreme

213. . . Source extreme

215. . . Extreme

30. . . Gate drive unit

32. . . Sweep line

311. . . Gate extreme

313. . . Source extreme

315. . . Extreme

411. . . Gate extreme

413. . . Source extreme

415. . . Extreme

C1. . . Capacitor

C2. . . Capacitor

CK. . . Clock signal

CKH. . . High standard

CKL. . . Low level

Gn. . . Scan signal

GnH. . . High standard

GnL. . . Low level

NF. . . Nth frame

N+1F. . . N+1th frame

T1. . . Switching element

T2. . . Switching element

T3. . . Switching element

T4. . . Switching element

VCOM(n). . . Output

VCOM(n)H. . . High standard

VCOM(n)L. . . Low level

VCOMH. . . First common voltage

VCOML. . . Second common voltage

QH. . . node

QL‧‧‧ node

XCK‧‧‧ complementary clock signal

XCKH‧‧‧ high standard

XCKL‧‧‧ low level

1 is a block diagram of a circuit according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of signal waveforms according to an embodiment of the present invention.

10. . . Control level

12. . . First control unit

14. . . Second control unit

100. . . Shared voltage supply circuit

111. . . Gate extreme

113. . . Source extreme

115. . . Extreme

20. . . Output stage

211. . . Gate extreme

213. . . Source extreme

215. . . Extreme

30. . . Gate drive unit

32. . . Sweep line

311. . . Gate extreme

313. . . Source extreme

315. . . Extreme

411. . . Gate extreme

413. . . Source extreme

415. . . Extreme

C1. . . Capacitor

C2. . . Capacitor

CK. . . Clock signal

Gn. . . Scan signal

T1. . . Switching element

T2. . . Switching element

T3. . . Switching element

T4. . . Switching element

VCOM(n). . . Output

VCOMH. . . First common voltage

VCOML. . . Second common voltage

QH. . . node

QL. . . node

XCK. . . Complementary clock signal

Claims (10)

A common voltage supply circuit for a display includes: a control stage having a first control unit and a second control unit, the first control unit receiving a scan signal and a clock signal respectively to provide a first control signal And the second control unit receives the scan signal and a complementary clock signal to provide a second control signal; and an output stage electrically coupled to the control stage, the output stage having a first switch The first switching element receives a first control signal and a first common voltage, and is turned on by the first control signal to output the first common voltage. Up to the output end, the second switching component respectively receives the second control signal and a second common voltage, and is turned on by the second control signal to output the second common voltage to the output end; wherein The first control unit includes: a third switching element having a 汲 terminal, a gate terminal and a source terminal, wherein the 汲 terminal of the third switching element receives the clock signal, the third opening The gate terminal of the component receives the scan signal; and a first capacitor having a first end and a second end, the first end of the first capacitor being electrically coupled to the source terminal of the third switching component, The second end of the first capacitor is electrically coupled to the ground; wherein the second control unit comprises: a fourth switching element having a 汲 terminal, a gate terminal and a source terminal, and the 汲 terminal of the fourth switching element Receiving the complementary clock signal, the gate terminal of the fourth switching element receives the scan signal; and a second capacitor having a first end and a second end, the first end of the second capacitor being electrically coupled At the source terminal of the fourth switching element, the second capacitor The second end of the device is electrically coupled to the ground. The common voltage supply circuit of the display of claim 1, wherein the first switching element has a 汲 terminal, a gate terminal and a source terminal, and the 汲 terminal of the first switching element receives the first common voltage The gate of the first switching element is electrically coupled to the source terminal of the third switching element. The source of the first switching element is electrically coupled to the output terminal, and the second switching element has a terminal. The gate of the second switching element is electrically coupled to the output terminal, and the gate terminal of the second switching element is electrically coupled to the source terminal of the fourth switching element. The source terminal of the two switching elements receives the second common voltage. The common voltage supply circuit of the display of claim 1, wherein the first capacitor is charged by the clock signal to a first voltage level when the third switching element is turned on by the scan signal. Providing the first control signal, and when the fourth switching element is turned on by the scan signal, the second capacitor is charged by the complementary clock signal to a second voltage level to provide the second control Signal. The common voltage supply circuit of the display of claim 1, wherein the first switching element, the second switching element, the third switching element, and the fourth switching element are made of indium zinc oxide (IGZO) Thin film transistor structure. The common voltage supply circuit of the display of claim 1, wherein the fourth switching element is turned off by a first negative voltage and the second negative voltage is replaced by a second negative voltage during an Nth frame time Close, on the first N+1 During the frame time, the third switching element is turned off by a third negative voltage, and the first switching element is turned off by a fourth negative voltage. The common voltage supply circuit of the display of claim 5, wherein the low level of the scan signal is lower than the low level of the complementary clock signal during the Nth frame period to form the first negative a voltage, the low level of the second control signal is lower than a low level of the second common voltage to form the second negative voltage, and the low level of the scan signal is lower than the time during the (N+1)th frame time The low level of the pulse signal forms the third negative voltage, and the low level of the first control signal is lower than the low level of the first common voltage to form the fourth negative voltage. The shared voltage supply circuit of the display of claim 1, wherein the control stage receives the clock signal having a first phase and the complementary clock having a second phase during an Nth frame time a signal, and outputting the first common voltage by an output of the output stage, the control stage receiving the clock signal having the second phase and the complementary phase having the first phase during an N+1th frame time a pulse signal, and the second common voltage is output by the output of the output stage, where N is a positive integer greater than or equal to zero. The shared voltage supply circuit of the display of claim 7, wherein the control stage provides the first control signal having the first phase to the first switching element during the Nth frame time, and provides a second control signal of the second phase to the second switching element, wherein the control stage provides a first control signal having the second phase to the first switching element during the (N+1)th frame period, and provides The second control signal of the first phase is to the second switching element. The common voltage supply circuit of the display of claim 1, wherein the high level of the scan signal is higher than the high level of the clock signal and the complementary clock signal, and higher than the first common voltage. The high level is lower, and the lower level of the scan signal is lower than the low level of the clock signal and the complementary clock signal, and lower than the low level of the second common voltage. The common voltage supply circuit of the display of claim 1, further comprising a gate driving unit electrically coupled to the control stage for providing the scan signal to the control stage through a scan line .