CN107633803B - Signal masking unit, signal masking method and display panel - Google Patents

Abstract

The disclosure provides a signal shielding unit, a signal shielding method and a display panel. The reset unit is used for receiving a reset voltage and receiving a first control signal according to the driving signal. The first switch unit is used for receiving the pulse signal and receiving a second control signal according to the driving signal. The second control signal is inverted from the first control signal. When the first control signal is at the first voltage level and the second control signal is at the second voltage level, the reset unit does not work, the first switch unit is conducted and outputs the pulse signal. When the first control signal is at the second voltage level and the second control signal is at the first voltage level, the reset unit outputs the working voltage to the first switch unit, and the first switch unit is turned off. The display device and the display method can reduce the power consumption of the display device while not reducing the efficiency of the display device.

Description

Signal masking unit, signal masking method and display panel

Technical Field

The present disclosure relates to a signal masking unit, a signal masking method, and a display panel, and more particularly, to a signal masking unit, a signal masking method, and a display panel with low power consumption.

Background

With the rapid development of display devices, people can use large and small display devices at any time in any occasion, such as: mobile phones, computers, etc. When the display device is used, different power consumption is caused every time the frame of the display device changes, and the power consumption directly influences more concerns of people for using the display device.

Therefore, as people pay more attention to the problem of saving power and energy, how to reduce the power consumption of the display device without reducing the performance of the display device is one of the problems to be improved in the art.

Disclosure of Invention

One embodiment of the present disclosure provides a signal masking unit. The signal mask unit includes a reset unit and a first switch unit. The reset unit is used for receiving a reset voltage and receiving a first control signal according to the driving signal. The first switch unit is electrically connected with the reset unit and used for receiving the pulse signal and receiving a second control signal according to the driving signal. The second control signal is in anti-phase with the first control signal. When the first control signal is at the first voltage level and the second control signal is at the second voltage level, the reset unit does not work, and the second control signal conducts the first switch unit to enable the first switch unit to output the pulse signal. When the first control signal is at the second voltage level and the second control signal is at the first voltage level, the reset unit outputs the working voltage to the first switch unit, and the working voltage and the second control signal turn off the first switch unit.

Another embodiment of the present disclosure provides a signal masking method for a driving circuit. The signal masking method comprises the following steps: enabling the driving circuit to receive a first control signal and a second control signal according to the driving signal; enabling the driving circuit to receive the pulse signal; when the first control signal is at a first voltage level and the second control signal is at a second voltage level, enabling the driving circuit to output a pulse signal; and stopping the driving circuit from outputting the pulse signal when the first control signal is at the second voltage level and the second control signal is at the first voltage level.

Another embodiment of the present disclosure provides a display panel. The display panel comprises a plurality of scanning lines, a multi-stage signal generator and a multi-stage signal mask unit. Each signal generator generates a driving signal and transmits the driving signal to the next-stage signal generator. The plurality of signal mask units are respectively coupled between one of the plurality of scanning lines and the multi-stage signal generator. The signal masking unit of each stage receives a first control signal and a second control signal according to a driving signal transmitted by the coupled current-stage signal generator, wherein the second control signal is in an inverse phase with the first control signal, and when the first control signal is at a first voltage level and the second control signal is at a second voltage level, the current-stage signal masking unit transmits a pulse signal to one of the plurality of scanning lines.

Therefore, according to the technical implementation manner of the present disclosure, embodiments of the present disclosure provide a signal masking unit, a signal masking method and a display panel, and more particularly, to a signal masking unit, a signal masking method and a display panel with low power consumption, so as to effectively reduce the power consumption of a display device without reducing the performance of the display device.

Drawings

In order to make the aforementioned and other objects, features, and advantages of the invention, as well as others which will become apparent, reference is made to the following description taken in conjunction with the accompanying drawings in which:

fig. 1 is a schematic diagram of a display panel according to some embodiments of the disclosure;

fig. 2 is a schematic diagram of a signal masking unit according to some embodiments of the disclosure;

fig. 3 is a detailed schematic diagram of a signal masking unit according to some embodiments of the disclosure; and

FIG. 4 is a schematic diagram of an operating waveform according to some embodiments of the disclosure;

FIG. 5 is a schematic diagram illustrating an operation of a signal masking unit according to the embodiment shown in FIG. 3;

FIG. 6 is a schematic diagram illustrating an operation of a signal masking unit according to the embodiment shown in FIG. 3;

FIG. 7 is a schematic diagram illustrating an operation of a signal masking unit according to the embodiment shown in FIG. 3;

FIG. 8 is a schematic diagram illustrating an operation of a signal masking unit according to the embodiment shown in FIG. 3;

FIG. 9 is a schematic diagram illustrating an operation of a signal masking unit according to the embodiment shown in FIG. 3;

FIG. 10 is a schematic diagram illustrating an operation of a signal masking unit according to the embodiment shown in FIG. 3;

FIG. 11 is a schematic diagram of an operating waveform according to some embodiments of the disclosure;

FIG. 12 is a schematic diagram illustrating an operation of a signal masking unit according to the embodiment shown in FIG. 3;

FIG. 13 is a schematic diagram illustrating an operation of a signal masking unit according to the embodiment shown in FIG. 3;

FIG. 14 is a schematic diagram illustrating an operation of a signal masking unit according to the embodiment shown in FIG. 3;

FIG. 15 is a schematic diagram illustrating an operation of a signal masking unit according to the embodiment shown in FIG. 3;

FIG. 16 is a schematic diagram illustrating an operation of a signal masking unit according to the embodiment shown in FIG. 3;

FIG. 17 is a schematic diagram illustrating an operation of a signal masking unit according to the embodiment shown in FIG. 3; and

fig. 18 is a flow chart of a signal masking method according to some embodiments of the disclosure.

Description of reference numerals:

100: display panel

110A to 110N: signal generator

120A to 120N: signal mask unit

120: signal mask unit

130: active region

GA-GN: scanning line

En: drive signal

Vrst: reset voltage

VDD: operating voltage

Vin_1、Vin_2：

RST 1: reset unit

T1、T2、T3、T4、T5、T6：

CLK: pulse signal

G [ n ]: scanning line voltage

BT, Q: node point

OUT: output end

400. 500: operating waveform

P1, P2, P3, P4, P5, P6: period of time

P7, P8, P9, P10, P11, P12: period of time

600: signal masking method

S610, S620, S630, S640, S650: step (ii) of

Detailed Description

The following disclosure provides many different embodiments or illustrations for implementing different features of the invention. Elements and configurations in the specific illustrations are used in the following discussion to simplify the present disclosure. Any examples discussed are intended for illustrative purposes only and do not limit the scope or meaning of the invention or its illustrations in any way. Moreover, the present disclosure may repeat reference numerals and/or letters in the various examples, which are for purposes of simplicity and clarity, and do not in themselves dictate a relationship between the various embodiments and/or configurations discussed below.

The term (terms) used throughout the specification and claims has the ordinary meaning as commonly understood in each term used in the art, in the disclosure herein, and in the specific context, unless otherwise indicated. Certain words used to describe the disclosure are discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art in describing the disclosure.

As used herein, coupled or connected means that two or more elements are in direct or indirect physical or electrical contact with each other, and coupled or connected means that two or more elements are in operation or act on each other.

The terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections. These elements, components, regions, layers and/or regions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention. As used herein, the word "and/or" includes any combination of one or more of the associated listed items. Reference to "and/or" in this document refers to any one, all, or any combination of at least one of the listed elements.

Please refer to fig. 1. Fig. 1 is a schematic diagram of a display panel 100 according to some embodiments of the disclosure. As shown in fig. 1, the display panel 100 includes a plurality of signal generators 110A to 110N, a plurality of signal masking units 120A to 120N, a plurality of scan lines GA to GN, and an active region 130. The signal masking units 120A-120N are respectively coupled between one of the scan lines GA-GN and one of the multi-stage signal generators 110A-110N. The active region 130 is coupled to a plurality of scan lines GA-GN. In some embodiments, each of the multi-stage signal generators 110A-110N generates the driving signal En, respectively, and transmits the driving signal En to a next-stage signal generator of the multi-stage signal generators 110A-110N. For example, as shown in fig. 1, the signal generator 110A transmits the driving signal En to the signal generator 110B, the signal generator 110B transmits the driving signal En to the signal generator 110C, and so on.

In some embodiments, for example, the scan line GA updates the active region 130 coupled to the scan line GA only when the scan line voltage G [ n ] output to the scan line GA is at a low voltage level, but the disclosure is not limited thereto. The rest of the scanning lines GB to GN are analogized. The operation between the elements will be described below with reference to fig. 2.

Please refer to fig. 2. Fig. 2 is a schematic diagram of a signal masking unit 120 according to some embodiments of the disclosure. In some embodiments, the signal masking unit 120 of fig. 2 is used to implement the signal masking units 120A, 120B, 120C …, or 120N of the first figure. The signal masking unit 120 receives a first control signal and a second control signal according to a driving signal transmitted by a coupled signal generator. The second control signal is inverted from the first control signal. When the first control signal is at the first voltage level and the second control signal is at the second voltage level, the signal masking unit 120 sends the pulse signal to one of the plurality of scanning lines GA to GN. For example, the signal masking unit 120A in fig. 1 receives the first control signal Vin _1 and the second control signal Vin _2 according to the driving signal En transmitted by the signal generator 110A coupled to the signal masking unit 120A. When the first control signal is at the first voltage level and the second control signal is at the second voltage level, the signal masking unit 120A sends the pulse signal CLK to the scan line GA. The rest of the signal mask units 120B-120N are repeated.

As shown in fig. 2, the signal masking unit 120 includes a reset unit RST1, a switch unit T1, a switch unit T2, and a switch unit T3. The switch unit T1 is electrically connected to the reset unit RST 1. The switch unit T2 is electrically connected to the reset unit RST 1. The switch unit T3 is electrically connected to the switch unit T1.

The reset unit RST1 receives the reset voltage Vrst and determines whether to receive the control signal Vin _1 according to the driving signal En. The switch unit T1 receives the pulse signal CLK and determines whether to receive the control signal Vin _2 according to the driving signal En. The control signal Vin _1 is inverted with respect to the control signal Vin _ 2. When the control signal Vin _1 is at the first voltage level and the control signal Vin _2 is at the second voltage level, the reset unit RST1 is not operated, and the control signal Vin _2 turns on the switch unit T1 to make the switch unit T1 output the pulse signal CLK to one of the plurality of scan lines G1-GN as shown in fig. 1. When the control signal Vin _1 is at the second voltage level and the control signal Vin _2 is at the first voltage level, the reset unit RST1 outputs the operating voltage VDD to the switch unit T1, and the operating voltage VDD and the control signal Vin _2 turn off the switch unit T1.

In some implementations, the switch unit T2 receives the control signal Vin _1 and turns on the control signal Vin _1 to the reset unit RST1 according to the driving signal En. The switch unit T3 receives the control signal Vin _2 and turns on the control signal Vin _2 to the switch unit T1 according to the driving signal En.

Please refer to fig. 3. Fig. 3 is a detailed schematic diagram of a signal masking unit 120 according to some embodiments of the disclosure. As shown in fig. 3, in some embodiments, the switch unit T1 has a control terminal and an output terminal. The control terminal is used for receiving the control signal Vin _2, and the output terminal is used for outputting the pulse signal CLK. The reset unit RST1 is electrically connected to the control terminal and the output terminal, respectively, for selectively outputting the operating voltage VDD to the control terminal and the output terminal of the switch unit T1 according to the control signal Vin _ 1.

As shown in fig. 3, in some embodiments, the reset unit RST1 includes a switch unit T4, a switch unit T5, a switch unit T6 and a capacitor C1. The switch unit T4 is used to receive a reset voltage Vrst. The switch unit T5 is used to receive a reset voltage Vrst. The control terminal of the switch unit T5 is used for receiving the control signal Vin _1 and is electrically connected to the switch unit T4 for receiving the reset voltage Vrst. The switch unit T6 receives the Vrst, the switch unit T6 has a control terminal and an output terminal, the control terminal of the switch unit T6 is electrically connected to the control terminal of the switch unit T5, and the output terminal of the switch unit T6 is electrically connected to the output terminal of the switch unit T1. The capacitor C1 is electrically connected to the control terminal of the switch unit T5 and is configured to receive a reset voltage Vrst.

In some embodiments, when the switch unit T4, the switch unit T5 and the switch unit T6 are turned on by the reset voltage Vrst and the control signal Vin _1, the operating voltage VDD is turned on to the control terminal and the output terminal of the switch unit T1 such that the control terminal and the output terminal of the switch unit T1 have the first voltage level.

As illustrated in FIG. 3, in some embodiments, the switch cells T1-T6 are P-type metal oxide semiconductor field effect transistors (PMOS). However, the present disclosure is not limited to the embodiment of fig. 3.

Please refer to fig. 4. Fig. 4 is a diagram illustrating an operation waveform 400 according to some embodiments of the disclosure. As shown in FIG. 4, during the period P1-P6, the control signal Vin _1 is at a high voltage level, and the control signal Vin _2 is at a low voltage level. Details of fig. 4 will be described below with reference to fig. 5 to 10.

Please refer to fig. 5. Fig. 5 is a schematic diagram illustrating an operation of the signal masking unit 120 according to the embodiment shown in fig. 3. Please refer to fig. 4 and fig. 5. In the period P1, the driving signal En is at a high voltage level, and therefore, neither the switch unit T2 nor the switch unit T3 is conductive. The switch unit T4 is turned on when the reset voltage Vrst is low, so that the node Q is low, and the switch unit T5 and the switch unit T6 are both turned on. Since the switch unit T5 and the switch unit T6 are both turned on, the operating voltage VDD is provided to the node BT and the output terminal OUT through the switch unit T5 and the switch unit T6, and the node BT is at a high voltage level, so the switch unit T1 is turned off. The signal masking unit 120 does not output the pulse signal CLK to one of the plurality of scan lines G1 GN, and the scan line voltage G [ n ] is at a high voltage level, so that the active region 130 coupled to one of the plurality of scan lines G1 GN is not updated by one of the plurality of scan lines G1 GN.

Please refer to fig. 6. Fig. 6 is a schematic diagram illustrating an operation of a signal masking unit 120 according to the embodiment shown in fig. 3. Please refer to fig. 4 and fig. 6. In the period P2, the driving signal En is at a low voltage level, and therefore the switch unit T2 and the switch unit T3 are both turned on. The control signal Vin _1 of the high voltage level is provided to the node Q through the switching unit T2, so the node Q is the high voltage level. The control signal Vin _2 of a low voltage level is provided to the node BT through the switching unit T3, so the node BT is a low voltage level. The reset voltage Vrst is a high voltage level, and thus the switching unit T4 is not conductive. Since the node Q is at a high voltage level and the node BT is at a low voltage level, the switch unit T5 and the switch unit T6 are not turned on, the switch unit T1 is turned on, and the signal masking unit 120 outputs the pulse signal CLK to one of the plurality of scan lines G1-GN. At this time, the pulse signal CLK is at a high voltage level, and thus, one of the plurality of scan lines G1 GN does not update the active region 130 coupled to the one of the plurality of scan lines G1 GN.

Please refer to fig. 7. Fig. 7 is a schematic diagram illustrating an operation of a signal masking unit 120 according to the embodiment shown in fig. 3. Please refer to fig. 4 and fig. 7 together. In the period P3, the driving signal En is at a high voltage level, and therefore, neither the switch unit T2 nor the switch unit T3 is conductive. The reset voltage Vrst is a high voltage level, and thus the switching unit T4 is not conductive. The operating voltage VDD is provided to the node Q through the capacitor C1, so that the node Q is at a high voltage level, and the switch unit T5 and the switch unit T6 are not conductive. Node BT is at a low voltage level and switching unit T1 is conducting. The signal masking unit 120 outputs the pulse signal CLK to one of the plurality of scan lines G1-GN. At this time, the pulse signal CLK is at a low voltage level, so one of the plurality of scan lines G1-GN updates the active region 130 coupled to the one of the plurality of scan lines G1-GN.

Please refer to fig. 8. Fig. 8 is a schematic diagram illustrating an operation of a signal masking unit 120 according to the embodiment shown in fig. 3. Please refer to fig. 4 and fig. 8. In the period P4, the driving signal En is at a high voltage level, and therefore, neither the switch unit T2 nor the switch unit T3 is conductive. The reset voltage Vrst is at a low voltage level, and thus the switching unit T4 is turned on. Since the switch unit T4 is turned on, the node Q is at a low voltage level, so that the switch units T5 and T6 are turned on. The operating voltage VDD is supplied to the node BT through the switching unit T5, and thus the node BT is at a high voltage level, so that the switching unit T1 is not conductive. The operating voltage VDD is supplied to the output terminal OUT through the switching unit T6, and thus the output terminal OUT is at a high voltage level. The signal masking unit 120 does not output the pulse signal CLK to one of the plurality of scan lines G1 GN, and the scan line voltage G [ n ] is at a high voltage level, so that the active region 130 coupled to one of the plurality of scan lines G1 GN is not updated by one of the plurality of scan lines G1 GN.

Please refer to fig. 9. Fig. 9 is a schematic diagram illustrating an operation of a signal masking unit 120 according to an embodiment shown in fig. 3. Please refer to fig. 4 and fig. 9. In the period P5, the driving signal En is at a high voltage level, and therefore, neither the switch unit T2 nor the switch unit T3 is conductive. The reset voltage Vrst is at a high voltage level, so the switch unit T4 is not turned on, the node Q is maintained at a low voltage level, so that the switch unit T5 and the switch unit T6 are turned on, the operating voltage VDD is provided to the node BT through the switch unit T5, and the node BT is at a high voltage level. Node BT is at a high voltage level and therefore the switching unit T1 is non-conductive. The operating voltage VDD is supplied to the output terminal OUT through the switching unit T6, and thus the output terminal OUT is at a high voltage level. The signal masking unit 120 does not output the pulse signal CLK to one of the plurality of scan lines G1 GN, and the scan line voltage G [ n ] is at a high voltage level, so that the active region 130 coupled to one of the plurality of scan lines G1 GN is not updated by one of the plurality of scan lines G1 GN.

Please refer to fig. 10. Fig. 10 is a schematic diagram illustrating an operation of a signal masking unit 120 according to the embodiment shown in fig. 3. Please refer to fig. 4 and fig. 10 together. In the period P6, the driving signal En is at a high voltage level, and therefore, neither the switch unit T2 nor the switch unit T3 is conductive. The reset voltage Vrst is at a high voltage level, and thus the switching unit T4 is not turned on, and the node Q is maintained at a low voltage level. The node Q is at a low voltage level, so the switch unit T5 and the switch unit T6 are turned on, and the operating voltage VDD is provided to the node BT through the switch unit T5, so the node BT is at a high voltage level, so that the switch unit T1 is turned off. The operating voltage VDD is supplied to the output terminal OUT through the switching unit T6, and thus the output terminal OUT is at a high voltage level. The signal masking unit 120 does not output the pulse signal CLK to one of the plurality of scan lines G1-GN. Therefore, even if the pulse signal CLK is at a low voltage level during the period P6, the active region 130 coupled to one of the scan lines G1 GN is not updated by one of the scan lines G1 GN because the signal masking unit 120 does not output the pulse signal CLK to one of the scan lines G1 GN and the scan line voltage G [ n ] is at a high voltage level.

Please refer to fig. 11. Fig. 11 is a diagram illustrating an operation waveform 500 according to some embodiments of the disclosure. As shown in FIG. 11, during the period P7-P12, the control signal Vin _1 is at a low voltage level and the control signal Vin _2 is at a high voltage level. Details of fig. 11 will be described below with reference to fig. 12 to 17.

Please refer to fig. 12. Fig. 12 is a schematic diagram illustrating an operation of a signal masking unit 120 according to the embodiment shown in fig. 3. Please refer to fig. 11 and fig. 12. In the period P7, the driving signal En is at a high voltage level, and therefore, neither the switch unit T2 nor the switch unit T3 is conductive. The reset voltage Vrst is at a low voltage level, so the switch unit T4 is turned on, the node Q is at a low voltage level, so that the switch unit T5 and the switch unit T6 are turned on, the operating voltage VDD is provided to the node BT through the switch unit T5, so the node BT is at a high voltage level, and therefore the switch unit T1 is not turned on. The operating voltage VDD is supplied to the output terminal OUT through the switching unit T6, and thus the output terminal OUT is at a high voltage level. The signal masking unit 120 does not output the pulse signal CLK to one of the plurality of scan lines G1 GN, and the scan line voltage G [ n ] is at a high voltage level, so that the active region 130 coupled to one of the plurality of scan lines G1 GN is not updated by one of the plurality of scan lines G1 GN.

Please refer to fig. 13. Fig. 13 is an operation diagram of a signal masking unit 120 according to the embodiment shown in fig. 3. Please refer to fig. 11 and fig. 13. In the period P8, the driving signal En is at a low voltage level, and therefore the switch unit T2 and the switch unit T3 are both turned on. The reset voltage Vrst is a high voltage level, and thus the switching unit T4 is not conductive. The control signal Vin _1 of a low voltage level is provided to the node Q through the switching unit T2, so the node Q is of a low voltage level. The control signal Vin _2 of the high voltage level is provided to the node BT through the switching unit T3, so the node BT is the high voltage level. Since the node Q is at a low voltage level and the node BT is at a high voltage level, the switch unit T5 and the switch unit T6 are conductive, and the switch unit T1 is non-conductive. The operating voltage VDD is supplied to the output terminal OUT through the switching unit T6, and thus the output terminal OUT is at a high voltage level. The signal masking unit 120 does not output the pulse signal CLK to one of the plurality of scan lines G1-GN. At this time, the scan line voltage G [ n ] is at a high voltage level, so that one of the plurality of scan lines G1-GN does not update the active region 130 coupled to the one of the plurality of scan lines G1-GN.

Please refer to fig. 14. Fig. 14 is an operation diagram of a signal masking unit 120 according to the embodiment shown in fig. 3. Please refer to fig. 11 and 14. In the period P9, the driving signal En is at a high voltage level, and therefore, neither the switch unit T2 nor the switch unit T3 is conductive. The reset voltage Vrst is at a high voltage level, so the switch unit T4 is not turned on, and the node Q is at a low voltage level, so that the switch units T5 and T6 are turned on. The operating voltage VDD is supplied to the node BT through the switching unit T5, and thus the node BT is at a high voltage level. Node BT is at a high voltage level and therefore the switching unit T1 is non-conductive. The operating voltage VDD is supplied to the output terminal OUT through the switching unit T6, and thus the output terminal OUT is at a high voltage level. The signal masking unit 120 does not output the pulse signal CLK to one of the plurality of scan lines G1-GN. Therefore, even if the pulse signal CLK is at a low voltage level during the period P12, the scan line voltage G [ n ] is at a high voltage level because the signal masking unit 120 does not output the pulse signal CLK to one of the scan lines G1 GN, and thus the active region 130 coupled to one of the scan lines G1 GN is not updated by one of the scan lines G1 GN.

Please refer to fig. 15. Fig. 15 is an operation diagram of a signal masking unit 120 according to the embodiment shown in fig. 3. Please refer to fig. 11 and fig. 15. In the period P10, the driving signal En is at a high voltage level, and therefore, neither the switch unit T2 nor the switch unit T3 is conductive. The reset voltage Vrst is at a low voltage level, and thus the switching unit T4 is turned on. The reset voltage Vrst is provided to the node Q through the switch unit T4, so the node Q is at a low voltage level, and the switch unit T5 and the switch unit T6 are turned on. The operating voltage VDD is supplied to the node BT through the switching unit T5, and thus the node BT is at a high voltage level. Node BT is at a high voltage level and therefore the switching unit T1 is non-conductive. The operating voltage VDD is supplied to the output terminal OUT through the switching unit T6, and thus the output terminal OUT is at a high voltage level. The signal masking unit 120 does not output the pulse signal CLK to one of the plurality of scan lines G1-GN. At this time, the scan line voltage G [ n ] is at a high voltage level, so that one of the plurality of scan lines G1-GN does not update the active region 130 coupled to the one of the plurality of scan lines G1-GN.

Please refer to fig. 16. Fig. 16 is an operation diagram of a signal masking unit 120 according to the embodiment shown in fig. 3. Please refer to fig. 11 and fig. 16. In the period P11, the driving signal En is at a high voltage level, and therefore, neither the switch unit T2 nor the switch unit T3 is conductive. The reset voltage Vrst is at a high voltage level, so the switch unit T4 is not turned on, and the node Q is at a low voltage level, so that the switch units T5 and T6 are turned on. The operating voltage VDD is supplied to the node BT through the switching unit T5, and thus the node BT is at a high voltage level, so that the switching unit T1 is not conductive. The operating voltage VDD is supplied to the output terminal OUT through the switching unit T6, and thus the output terminal OUT is at a high voltage level. The signal masking unit 120 does not output the pulse signal CLK to one of the plurality of scan lines G1-GN. At this time, the scan line voltage G [ n ] is at a high voltage level, so that one of the plurality of scan lines G1-GN does not update the active region 130 coupled to the one of the plurality of scan lines G1-GN.

Please refer to fig. 17. Fig. 17 is a schematic diagram illustrating an operation of a signal masking unit 120 according to the embodiment shown in fig. 3. Please refer to fig. 11 and 17. In the period P12, the driving signal En is at a high voltage level, and therefore, neither the switch unit T2 nor the switch unit T3 is conductive. The reset voltage Vrst is at a high voltage level, so the switch unit T4 is not turned on, and the node Q is at a low voltage level, so that the switch units T5 and T6 are turned on. The operating voltage VDD is supplied to the node BT through the switching unit T5, and thus the node BT is at a high voltage level. Node BT is at a high voltage level and therefore the switching unit T1 is non-conductive. The operating voltage VDD is supplied to the output terminal OUT through the switching unit T6, and thus the output terminal OUT is at a high voltage level. The signal masking unit 120 does not output the pulse signal CLK to one of the plurality of scan lines G1-GN. Therefore, even if the pulse signal CLK is at a low voltage level during the period P12, the scan line voltage G [ n ] is at a high voltage level because the signal masking unit 120 does not output the pulse signal CLK to one of the scan lines G1 GN, and thus the active region 130 coupled to one of the scan lines G1 GN is not updated by one of the scan lines G1 GN.

Please refer to fig. 18. Fig. 18 is a flow chart of a signal masking method 600 according to some embodiments of the disclosure. As shown in fig. 18, the signal masking method 600 comprises the following steps:

step S610: enabling the driving circuit to receive a first control signal and a second control signal according to the driving signal;

step S620: enabling the driving circuit to receive the pulse signal;

step S630: when the first control signal is at a first voltage level and the second control signal is at a second voltage level, enabling the driving circuit to output a pulse signal;

step S640: when the first control signal is at the second voltage level and the second control signal is at the first voltage level, stopping the driving circuit from outputting the pulse signal; and

step S650: and enabling the driving circuit to selectively receive the reset voltage according to the reset voltage and the first control signal, wherein the reset voltage has a second voltage level, and the reset voltage enables the driving circuit to stop outputting the pulse signal.

For the signal masking method 600 of the present embodiment to be easily understood, please refer to fig. 3 to 18 together.

In step S610, the driving circuit receives a first control signal and a second control signal according to the driving signal. In some embodiments, the driving circuit may be a signal masking unit 120 as illustrated in fig. 3. For example, in some embodiments, when the driving signal En is at a low voltage level, the switch units T2 and T3 are turned on, and the signal mask unit 120 receives the control signals Vin _1 and Vin _ 2.

In step S620, the driving circuit receives the pulse signal. In some embodiments, the pulse signal CLK is received by the switch unit T1 of the signal mask unit 120.

In step S630, when the first control signal is at the first voltage level and the second control signal is at the second voltage level, the driving circuit is enabled to output the pulse signal. For example, as shown in FIG. 7, when the control signal Vin _1 is at a high voltage level, the control signal Vin _2 is at a low voltage level. The node Q is at a high voltage level, so the switch units T5 and T6 are non-conductive. Node BT is at a low voltage level and switching unit T1 is conducting. The signal masking unit 120 outputs the pulse signal CLK to one of the plurality of scan lines G1-GN. At this time, the pulse signal CLK is at a low voltage level, so one of the plurality of scan lines G1-GN updates the active region 130 coupled to the one of the plurality of scan lines G1-GN.

In step S640, when the first control signal is at the second voltage level and the second control signal is at the first voltage level, the driving circuit stops outputting the pulse signal. For example, as shown in fig. 12 to 17, the control signal Vin _1 is at a low voltage level, the control signal Vin _2 is at a high voltage level, and none of the switch units T1 is turned on, so the signal masking unit 120 does not output the pulse signal CLK to one of the plurality of scan lines G1 to GN.

In step S650, the driving circuit selectively receives a reset voltage according to the reset voltage and the first control signal, wherein the reset voltage has a second voltage level, and the reset voltage stops the driving circuit from outputting the pulse signal. For example, referring to fig. 8, when the reset voltage Vrst is at a low voltage level, the switch unit T4 is turned on, and the node Q is at a low voltage level, so that the switch unit T5 and the switch unit T6 are turned on. At this time, the node BT is at a high voltage level, the switch unit T1 is turned off, and therefore the signal masking unit 120 does not output the pulse signal CLK to one of the plurality of scan lines G1 GN.

In some embodiments, the driving signal En is generated by the signal generator 110 as illustrated in fig. 1 and input to the signal masking unit 120. In some other embodiments, the driving signal En is generated by the previous stage signal masking unit 120 in the display panel 100 and is input to the current stage signal masking unit 120.

In some embodiments, the reset voltage Vrst and the pulse signal CLK shown in fig. 4 and 11 are periodically changed.

As shown in fig. 4 to 17, when the control signal Vin _1 is at a high voltage level and the control signal Vin _2 is at a low voltage level, the signal mask unit 120 outputs the pulse signal CLK to one of the plurality of scan lines G1 to GN. If the pulse signal CLK is at a low voltage level, the scan line voltage G [ n ] is at a low voltage level, such that one of the plurality of scan lines G1-GN updates the active region 130 coupled to the one of the plurality of scan lines G1-GN. On the other hand, when the control signal Vin _1 is at a low voltage level and the control signal Vin _2 is at a high voltage level, the pulse signal CLK is not output to one of the plurality of scan lines G1-GN by the signal masking unit 120, so that the active region 130 coupled to one of the plurality of scan lines G1-GN is not updated by one of the plurality of scan lines G1-GN. In this way, the embodiment of the present invention can only update a portion of the active region 130 that needs to be updated by controlling the control signal Vin _1 and the control signal Vin _2, so as to reduce the power consumption of the display panel 100.

In view of the foregoing, embodiments of the present disclosure provide a signal masking unit, a signal masking method and a display panel, and more particularly, to a signal masking unit, a signal masking method and a display panel with low power consumption, so as to effectively reduce the power consumption of a display device without reducing the performance of the display device.

Additionally, the above illustration includes exemplary steps in sequential order, but the steps need not be performed in the order shown. It is within the contemplation of the disclosure that the steps may be performed in a different order. Steps may be added, substituted, changed in order and/or omitted as appropriate within the spirit and scope of embodiments of the disclosure.

Although the present disclosure has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made by those skilled in the art without departing from the spirit and scope of the disclosure, and therefore, the scope of the disclosure is to be determined by that of the appended claims.

Claims (8)

1. A signal masking unit, comprising:

the reset unit is used for receiving a reset voltage and receiving a first control signal according to a driving signal; and

the first switch unit is electrically connected with the reset unit and used for receiving a pulse signal and receiving a second control signal according to the driving signal, wherein the second control signal is in phase opposition to the first control signal;

when the first control signal is at a first voltage level and the second control signal is at a second voltage level, the reset unit does not work, and the second control signal conducts the first switch unit to enable the first switch unit to output the pulse signal;

when the first control signal is at the second voltage level and the second control signal is at the first voltage level, the reset unit outputs a working voltage to the first switch unit, and the working voltage and the second control signal turn off the first switch unit.

2. The signal masking unit as claimed in claim 1, further comprising:

the second switch unit is electrically connected with the reset unit and used for receiving the first control signal and conducting the first control signal to the reset unit according to the driving signal.

3. The signal masking unit as claimed in claim 1, further comprising:

and the third switch unit is electrically connected with the first switch unit and used for receiving the second control signal and conducting the second control signal to the first switch unit according to the driving signal.

4. The signal masking unit as claimed in claim 1, wherein the first switch unit has a control terminal for receiving the second control signal and an output terminal for outputting the pulse signal, and the reset unit is electrically connected to the control terminal and the output terminal respectively for selectively outputting the operating voltage to the control terminal and the output terminal according to the first control signal.

5. The signal masking unit as claimed in claim 4, wherein the reset unit comprises:

a fourth switching unit for receiving the reset voltage;

the fifth switch unit is used for receiving the working voltage and is provided with a control end, wherein the control end of the fifth switch unit is used for receiving the first control signal and is electrically connected with the fourth switch unit;

a sixth switch unit for receiving the working voltage, the sixth switch unit having a control end and an output end, wherein the control end of the sixth switch unit is electrically connected to the control end of the fifth switch unit, and the output end of the sixth switch unit is electrically connected to the output end of the first switch unit; and

and the capacitor is electrically connected with the control end of the fifth switch unit.

6. The signal masking unit as claimed in claim 5, wherein when the fourth, fifth and sixth switching units are turned on by the reset voltage and the first control signal, the operating voltage is turned on to the control terminal and the output terminal of the first switching unit so that the control terminal and the output terminal of the first switching unit have the first voltage level.

7. A signal masking method for a driving circuit, comprising:

enabling the driving circuit to receive a first control signal and a second control signal according to a driving signal;

enabling the driving circuit to receive a pulse signal;

when the first control signal is at a first voltage level and the second control signal is at a second voltage level, the driving circuit is enabled to output the pulse signal; and

when the first control signal is at the second voltage level and the second control signal is at the first voltage level, the driving circuit stops outputting the pulse signal,

further comprising:

and enabling the driving circuit to selectively receive a working voltage according to a reset voltage and the first control signal, wherein the working voltage has the second voltage level, and the working voltage enables the driving circuit to stop outputting the pulse signal.

8. A display panel, comprising:

a plurality of scan lines;

the signal generator of each stage generates a driving signal and transmits the driving signal to the signal generator of the next stage;

a plurality of signal masking units respectively coupled between one of the plurality of scan lines and one of the plurality of signal generators, wherein the plurality of signal masking units of each stage receive a first control signal and a second control signal according to the driving signal transmitted by the coupled current stage signal generator, wherein the second control signal is inverted with respect to the first control signal, and when the first control signal is at a first voltage level and the second control signal is at a second voltage level, the current stage signal masking unit transmits a pulse signal to one of the plurality of scan lines,

wherein the plurality of signal masking units of each stage comprises:

the reset unit is used for receiving a reset voltage and receiving the first control signal according to the driving signal transmitted by the signal generator; and

the first switch unit is electrically connected with the reset unit and one of the plurality of scanning lines, receives the second control signal according to the driving signal transmitted by the signal generator, and is used for sending the pulse signal to one of the plurality of scanning lines when the first switch unit is conducted;

when the first control signal is at the second voltage level and the second control signal is at the first voltage level, the reset unit outputs a working voltage to the first switch unit, and the working voltage and the second control signal turn off the first switch unit.

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