TWI621267B - Semiconductor device - Google Patents

Abstract

The present invention provides a semiconductor device including: a field insulating layer on a top surface of the substrate, and the field insulating layer includes a trench defined therein in a first direction; and a fin active pattern from the substrate a top surface extending through the trench defined in the field insulating layer, the fin active pattern including a first lower pattern and a first upper pattern, the first lower pattern contacting the substrate, And the first upper pattern contacts the first lower pattern, and the first upper pattern is more convex from the substrate than the field insulating layer, the first upper pattern includes a different a lattice modifying material of a first lower pattern, and the fin active pattern includes a first fin portion and a second fin portion, the second fin portion being in the first fin portion in the first fin portion And the first gate electrode intersecting the fin active pattern and extending in a second direction different from the first direction.

Description

Semiconductor device [Related application cross-reference]

The present application claims priority to U.S. Patent Application Serial No. 61/970,615, filed on March 26, 2014, which is assigned to the The priority of the Korean Patent Application No. 2014-0101756, the entire disclosure of which is hereby incorporated by reference.

The present disclosure relates to a semiconductor device and a method of fabricating the same, and more particularly to a semiconductor device including a fin active pattern and a method of fabricating the same.

As a miniaturization technique for increasing the density of a semiconductor device, a multi-gate transistor has been proposed. The multi-gate transistor is obtained by forming a multi-channel active pattern (or a body) of a fin shape or a nanowire shape on a substrate and forming a gate on a surface of the multi-channel active pattern.

As the feature size of a metal oxide semiconductor (MOS) transistor decreases, the gate and the channel formed under the gate are Shorter in length. Shorter channel lengths increase charge dispersion and reduce charge mobility in the channel. A decrease in charge mobility can be an obstacle to improving the saturation current of the transistor. Therefore, various studies have been conducted to increase the charge mobility in a transistor having a shortened channel length.

Aspects of the inventive concept provide a semiconductor device in which the operational performance of the transistor is improved by using tantalum carbide in the channel layer of the transistor. Some embodiments of the inventive concept are directed to a semiconductor device including a field insulating layer on a top surface of a substrate and including a trench defined therein extending in a first direction and extending from a top surface of the substrate and passing through the field insulating layer A fin active pattern defined in the trench. The fin active pattern includes a first lower pattern contacting the substrate and a first upper pattern contacting the first lower pattern, and the first upper pattern is more convex from the substrate than the field insulating layer. The first upper pattern includes a lattice modifying material that is different from the first lower pattern. The fin active pattern includes a first fin portion and a second fin portion on both sides of the first fin portion in the first direction. The device includes a first gate electrode that intersects the fin active pattern and extends in a second direction that is different from the first direction.

Some embodiments include a first source region and a first drain region, the first source region and the first drain region including an impurity region and a first epitaxial layer, the impurity region being in the second fin portion and On both sides of the first gate electrode, the first epitaxial layer includes a lattice modifying material. In some embodiments, the first epitaxial layer is formed on sidewalls and a top surface of the second portion of the first upper pattern, and the first epitaxial layer contacts the field insulating layer. Some embodiments provide that the first epitaxial layer is formed on a sidewall of the second portion of the first upper pattern and The top surface is not in contact with the field insulation. Some embodiments include a first gate spacer on a sidewall of the first gate electrode and a first fin spacer on a sidewall of a portion of the second portion of the first upper pattern, and contacting the first epitaxial layer A gate spacer.

In some embodiments, the semiconductor device includes an n-channel metal oxide semiconductor (NMOS), the lattice modification material includes carbon, and the first upper pattern includes silicon carbide (SiC). Some embodiments include a first source region and a first drain region, the first source region and the first drain region including an impurity region and a first epitaxial layer, the impurity region being in the second fin portion and On both sides of the first gate electrode, the first epitaxial layer includes a lattice modifying material. In some embodiments, the carbon concentration in the first upper pattern does not exceed the carbon concentration in the first epitaxial layer. In some embodiments, the carbon concentration in the first upper pattern is in a range from about 0.5% to about 1.5%, and the carbon concentration in the first epitaxial layer is in a range from about 0.5% to about 3.0%.

Some embodiments provide that the semiconductor device comprises a p-channel metal oxide semiconductor (PMOS), the lattice modifying material comprises germanium, and the first upper pattern comprises silicon germanium (SiGe). Some embodiments include a first source region and a first drain region, the first source region and the first drain region including an impurity region and a first epitaxial layer, the impurity region being in the second fin portion and On both sides of the first gate electrode, the first epitaxial layer includes a lattice modifying material. Some embodiments provide that the concentration of germanium in the first upper pattern does not exceed the concentration of germanium in the first epitaxial layer. In some embodiments, the germanium concentration in the first upper pattern is in the range of from about 50% to about 70%, and the germanium concentration in the first epitaxial layer is in the range of from about 50% to about 90%.

In some embodiments, the top surface of the second fin portion relative to the substrate The face is more concave than the top surface of the first fin portion.

Some embodiments provide that the fin active pattern comprises a first fin active pattern and the lattice modifying material comprises a first lattice modifying material. Some embodiments further include a second fin active pattern extending from a top surface of the substrate and through a trench defined in the field insulating layer. The second fin active pattern includes a second lower pattern in contact with the substrate and a second upper pattern in contact with the second lower pattern, the second upper pattern being more convex from the substrate than the field insulating layer. The second upper pattern includes a second lattice modification material different from the second lower pattern. The fin active pattern includes a third fin portion and a fourth fin portion on both sides of the third fin portion in the first direction. Some embodiments include a second gate electrode that intersects the second fin active pattern and that extends in the second direction.

Some embodiments include a first source region and a first drain region and a second source region and a second drain region, the first source region and the first drain region including an impurity region and a first epitaxial layer The impurity region is in the second fin portion and on both sides of the first gate electrode, and the first epitaxial layer includes a lattice modification material. The second source region and the second drain region include an impurity region and a second epitaxial layer, the impurity region is in the fourth fin portion and on both sides of the second gate electrode, the second epitaxial layer A second lattice modifying material is included. In some embodiments, the first lattice modifying material and the second lattice modifying material are the same material. Some embodiments provide that the first lattice modifying material comprises carbon and the second lattice modifying material comprises ruthenium.

Some embodiments include a virtual gate electrode that is on the field insulating layer and that extends in a second direction between the first gate electrode and the second gate electrode.

Some embodiments include an oxide pattern formed on a substrate between the first fin active pattern and the second fin active pattern. Some embodiments include a virtual gate electrode on the oxide pattern. In some embodiments, the virtual gate electrode is at the first gate The electrode extends between the second gate electrode and in the second direction.

Some embodiments include a first dummy gate electrode and a second dummy gate electrode at least partially on the oxide pattern. Some embodiments provide that the first dummy gate electrode and the second dummy gate electrode are spaced apart in a first direction between the first gate electrode and the second gate electrode and extend in a second direction.

However, aspects of the inventive concept are not limited to those described herein. The above and other aspects of the inventive concept will become more apparent to those of ordinary skill in the art of the invention.

1, 2, 3, 2704, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22‧‧‧ ‧ semiconductor devices

100‧‧‧Substrate

101, 301‧‧‧Optoelectronics

105‧‧ ‧ field insulation

106‧‧‧First District

107‧‧‧Second District

110, 210, 310‧‧‧Fin active pattern

110a, 310a‧‧‧ part one

110b, 310b‧‧‧ Part II

110b-1, 310b-1‧‧‧ top surface

110b-2, 310b-2‧‧‧ side wall

111, 211, 311‧‧‧ lower pattern

112, 212, 312‧‧‧ upper pattern

112p‧‧‧ compound semiconductor layer

120, 220, 320‧‧ ‧ gate electrode

125, 225, 325‧‧ ‧ gate insulation

126‧‧‧virtual gate pattern

127, 165‧‧‧Virtual gate insulation

128, 160, 260‧‧‧ virtual gate electrode

130, 230, 330‧‧‧ source/bungee area

135, 235, 335‧‧ ‧ epitaxial layer

140, 340‧‧ ‧ brake spacer

145, 345 ‧ ‧ fin gap

150‧‧‧Interlayer insulating film

151, 152, 153, 156‧‧‧ Ditch

170‧‧‧Virtual gate spacer

1100‧‧‧Electronic system

1110‧‧‧ Controller

1120‧‧‧Input/output devices

1130‧‧‧ memory device

1140‧‧ interface

1150‧‧ ‧ busbar

2103, 2104‧‧‧ mask pattern

A-A, B-B, C-C, D-D, E-E, F-F‧‧ lines

H1, H2‧‧‧ height

I‧‧‧First District

II‧‧‧Second District

The above and other aspects and features of the present invention will become more apparent from the detailed description.

1 is a perspective view of a semiconductor device in accordance with a first embodiment of the inventive concept.

2 is a cross-sectional view taken along line A-A of FIG. 1.

FIG. 3 is a cross-sectional view taken along line B-B of FIG. 1.

4 is a cross-sectional view taken along line C-C of FIG. 1.

5 and 6 are views of a semiconductor device in accordance with a second embodiment of the inventive concept.

Figure 7 is a diagram of a semiconductor device in accordance with a third embodiment of the inventive concept.

FIG. 8 is a view of a semiconductor device in accordance with a fourth embodiment of the inventive concept.

9 and 10 are views of a semiconductor device in accordance with a fifth embodiment of the inventive concept.

Figure 11 is a diagram of a semiconductor device in accordance with a sixth embodiment of the inventive concept.

Figure 12 is a diagram of a semiconductor device in accordance with a seventh embodiment of the inventive concept.

13 and 14 are views of a semiconductor device in accordance with an eighth embodiment of the inventive concept.

Figure 15 is a diagram of a semiconductor device in accordance with a ninth embodiment of the inventive concept.

16A and 16B are respectively a perspective view and a plan view of a semiconductor device in accordance with a tenth embodiment of the inventive concept.

17 is a partial perspective view of the first fin active pattern and the second fin active pattern and the field insulating layer illustrated in FIG. 16A.

Figure 18 is a cross-sectional view taken along line D-D of Figure 16A.

19 and 20 are views of a semiconductor device in accordance with an eleventh embodiment of the inventive concept.

Figure 21 is a cross-sectional view of a semiconductor device in accordance with a twelfth embodiment of the inventive concept.

22 and 23 are views of a semiconductor device in accordance with a thirteenth embodiment of the inventive concept.

Figure 24 is a perspective view of a semiconductor device in accordance with a fourteenth embodiment of the inventive concept.

Figure 25 is a cross-sectional view taken along line A-A and line E-E of Figure 24.

26 and 27 are views of a semiconductor device in accordance with a fifteenth embodiment of the inventive concept.

Figure 28 is a diagram of a semiconductor device in accordance with a sixteenth embodiment of the inventive concept.

Figure 29 is a diagram of a semiconductor device in accordance with a seventeenth embodiment of the inventive concept.

30 and 31 are views of a semiconductor device in accordance with an eighteenth embodiment of the inventive concept.

Figure 32 is a view showing a semiconductor device in accordance with a nineteenth embodiment of the inventive concept.

Figure 33 is a diagram of a semiconductor device in accordance with a twentieth embodiment of the inventive concept.

34 and 35 are views of a semiconductor device in accordance with a twenty-first embodiment of the inventive concept.

Figure 36 is a diagram of a semiconductor device in accordance with a twenty-second embodiment of the inventive concept.

37 to 45 are operational diagrams illustrating a method of fabricating a semiconductor device in accordance with some embodiments of the inventive concept.

46 and 47 are operational diagrams illustrating a method of fabricating a semiconductor device in accordance with some embodiments of the inventive concept.

48 is a block diagram of an electronic system including a semiconductor device in accordance with some embodiments of the inventive concepts.

49 and 50 are diagrams showing an example of a semiconductor system to which a semiconductor device can be applied, according to some embodiments of the inventive concept.

The concept of the invention is described more fully hereinafter with reference to the accompanying drawings, in which FIG. However, the inventive concept may be embodied in many different forms and should not be construed as being limited by the embodiments set forth herein. Instead, the invention may be more thorough and complete, and The intellectual fully conveys the scope of the inventive concept. Throughout the specification, the same reference numerals indicate the same components. In the drawings, the thickness of layers and regions will be exaggerated for clarity.

It will be understood that when an element or layer is "connected" or "coupled" to another element or layer, it is meant that the element or layer can be directly connected or coupled to another Elements or layers may or may have intermediate elements or intermediate layers. Conversely, when referring to a component "directly connected" or "directly coupled" to another element In the case of a piece or layer, there are no intermediate elements or layers. Like reference numerals indicate like elements throughout. The term "and/or" used herein includes any and all combinations of one or more of the associated listed items.

It will also be understood that when a layer is referred to as being "on" another layer or substrate, it may be directly on another layer or substrate, or an intermediate layer may also be present. In contrast, when an element is referred to as being "directly on" another element, there is no intermediate element.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements are not limited by these words. These terms are only used to distinguish one element from another. Thus, for example, a first element, a first component, or a first region discussed below could be termed a second component, a second component, or a second region without departing from the teachings of the inventive concept.

The words "a" and "described" are used, as well as the description of the concept of the invention. Similar reference objects below (especially in the content of the following patent application) It is intended to be inclusive of the singular and plural, unless otherwise indicated herein or clearly contradicted by the context. Unless otherwise indicated, the terms "including", "having", "including" and "including" are interpreted as open words (ie, "including but not limited to").

Unless otherwise defined, all technical and scientific terms used herein have the same meaning meaning meanings It is to be noted that the use of any and all examples or exemplary voca 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 Furthermore, unless otherwise defined, all words defined in a common dictionary may not be overly interpreted.

A semiconductor device according to a first embodiment of the inventive concept will be described with reference to FIGS. 1 through 4.

1 is a perspective view of a semiconductor device 1 in accordance with a first embodiment of the inventive concept. 2 is a cross-sectional view taken along line A-A of FIG. 1. FIG. 3 is a cross-sectional view taken along line B-B of FIG. 1. 4 is a cross-sectional view taken along line C-C of FIG. 1. For convenience of description, the interlayer insulating film 150 is not illustrated in FIG.

Referring to FIGS. 1 through 4 , the semiconductor device 1 according to the first embodiment may include a substrate 100 , a first fin active pattern 110 , a first gate electrode 120 , and a first source/drain region 130 .

The substrate 100 can be a bulk germanium substrate and/or a silicon-on-insulator (SOI) substrate. Alternatively, the substrate 100 may be a germanium substrate and/or may be made of other materials (eg, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, and/or gallium antimonide). ) The resulting substrate. In some embodiments, the substrate 100 may be composed of a base substrate and an epitaxial layer formed on the base substrate. An embodiment of the inventive concept will be described on the premise that the substrate 100 is a germanium substrate.

A field insulating layer 105 may be formed on the substrate 100. The field insulating layer 105 can include one of an oxide layer, a nitride layer, an oxynitride layer, and combinations thereof.

The first fin active pattern 110 may protrude from the substrate 100. The field insulating layer 105 may partially cover sidewalls of the first fin active pattern 110. Therefore, the top surface of the first fin-shaped active pattern 110 may protrude more upward than the top surface of the field insulating layer 105. That is, the first fin active pattern 110 may be defined by the field insulating layer 105.

The first fin active pattern 110 includes a first lower pattern 111 and a first upper pattern 112 that are sequentially stacked on the substrate 100. The first lower pattern 111 protrudes from the substrate 100. The first upper pattern 112 is formed on the first lower pattern 111.

The first upper pattern 112 may be located on top of the first fin active pattern 110. That is, the top surface of the first fin active pattern 110 may be the top surface of the first upper pattern 112.

Since the top surface of the first fin active pattern 110 protrudes more upward than the top surface of the field insulating layer 105, at least a portion of the first upper pattern 112 may protrude more upward than the field insulating layer 105.

For example, if the semiconductor device 1 is a transistor, the first upper pattern 112 can serve as a channel region of the transistor.

The first upper pattern 112 is directly connected to the first lower pattern 111. That is, the first upper pattern 112 directly contacts the first lower pattern 111. For example, the first lower pattern 111 may be a base, the first upper pattern 112 is epitaxially grown on the base, and the first upper pattern 112 may be an epitaxial layer formed on the first lower pattern 111.

The first lower pattern 111 is a ruthenium pattern containing ruthenium. The first upper pattern 112 is a compound semiconductor pattern containing a material having a lattice constant different from that of the first lower pattern 111.

The first lower pattern 111 is directly connected to the substrate 100. Further, since the substrate 100 may be a germanium substrate and the first lower patterns 111 are germanium patterns, they include the same material. In other words, since the substrate 100 and the first lower pattern 111 include tantalum and are directly connected to each other, they may be an integral structure.

If the semiconductor device 1 according to the first embodiment of the present inventive concept is an n-channel metal oxide semiconductor (NMOS) transistor, the first upper pattern 112 may include a material having a lattice constant smaller than 矽. Material (for example, niobium carbide (SiC)). That is, the first upper pattern 112 may be a ruthenium carbide pattern.

On the other hand, if the semiconductor device 1 according to the first embodiment of the present inventive concept is a p-channel metal oxide semiconductor (PMOS) transistor, the first upper pattern 112 may include a lattice constant greater than矽 materials (such as germanium (SiGe)). That is, the first upper pattern 112 may be a meander pattern.

In FIGS. 1, 3, and 4, the contact surfaces of the first upper pattern 112 and the first lower pattern 111 are located in the same plane as the top surface of the field insulating layer 105. That is, the entire sidewall of the first lower pattern 111 contacts the field insulating layer 105, and the entire sidewall of the first upper pattern 112 does not contact the field insulating layer 105. However, the inventive concept is not limited thereto.

The first fin active pattern 110 may extend along the first direction X1. The first fin active pattern 110 includes a first portion 110a and a second portion 110b. The second portion 110b of the first fin active pattern 110 is disposed on both sides of the first portion 110a of the first fin active pattern 110 in the first direction X1.

In the semiconductor device 1 according to the first embodiment of the inventive concept, the top surface of the first portion 110a of the first fin-shaped active pattern 110 and the first fin-shaped active pattern 110 are compared to the top surface of the field insulating layer 105. The top surface of the two portions 110b protrudes upward. Further, the top surface of the first portion 110a of the first fin active pattern 110 is located in the same plane as the top surface of the second portion 110b of the first fin active pattern 110.

An interlayer insulating film 150 is formed on the field insulating layer 105. The interlayer insulating film 150 covers the first fin active pattern 110, the first source/drain region 130, and the like. Interlayer insulation The film 150 includes a first trench 151 that intersects the first fin active pattern 110 and extends along the second direction Y1.

The interlayer insulating film 150 may include at least one of a low dielectric constant material, an oxide layer, a nitride layer, and an oxynitride layer. The low dielectric constant material can be made of, but not limited to, Flowable Oxide (FOX), Tonen SilaZen (TOSZ), Undoped Silica Glass (USG) ), Borosilica Glass (BSG), PhosphoSilica Glass (PSG), BoroPhosphoSilica Glass (BPSG), Plasma-Enhanced Tetraethyl Nitrate (Plasma Enhanced Tetra Ethyl Ortho Silicate; PETEOS), Fluoride Silicate Glass (FSG), High Density Plasma (HDP) oxide, Plasma Enhanced Oxide (PEOX) ), flow CVD (FCVD) oxides and any combination thereof.

The first gate electrode 120 is formed on the first fin active pattern 110 and the field insulating layer 105. For example, the first gate electrode 120 is formed on the first portion 110a of the first fin active pattern 110.

More specifically, the first gate electrode 120 is formed on the sidewalls and the top surface of the first upper pattern 112. The first upper pattern 112 that protrudes more upward than the top surface of the field insulating layer 105 is covered by the first gate electrode 120.

The first gate electrode 120 is formed in the first trench 151 included in the interlayer insulating film 150. The first gate electrode 120 extends along the second direction Y1 and intersects the first fin active pattern 110.

The first gate electrode 120 may include a metal layer. The first gate electrode 120 may include a portion that controls a work function and a portion that fills the first trench 151. First gate electrode 120 At least one of tungsten (W), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), titanium carbide (TiC), and tantalum carbide (TaC) may be included. In some embodiments, the first gate electrode 120 can be made of, for example, germanium and/or germanium (SiGe). In the semiconductor device 1 according to the first embodiment of the inventive concept, the first gate electrode 120 can be formed by a replacement process.

A first gate insulating layer 125 may be formed between the first fin active pattern 110 and the first gate electrode 120. Further, a first gate insulating layer 125 may be formed between the interlayer insulating film 150 and the first gate electrode 120.

The first gate insulating layer 125 may be formed along a top surface and sidewalls of the first portion 110a of the first fin active pattern 110. The first gate insulating layer 125 may be formed along sidewalls and a top surface of the first upper pattern 112, which protrudes more upward than the top surface of the field insulating layer 105.

The first gate insulating layer 125 may be disposed between the first gate electrode 120 and the field insulating layer 105. In other words, the first gate insulating layer 125 may be formed along sidewalls and a bottom surface of the first trench 151.

The first gate insulating layer 125 may include a hafnium oxide layer and/or a high dielectric constant material having a dielectric constant greater than that of the hafnium oxide layer. For example, the first gate insulating layer 125 may include one or more of the following (but not limited to): hafnium oxide, hafnium silicon oxide, lanthanum oxide, oxidation Lanthanum aluminum oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium Titanium oxide), strontium titanium oxide, cerium oxide (yttrium oxide), alumina, lead scandium tantalum oxide, and lead zinc niobate.

The first gate spacers 140 may be formed on sidewalls of the first gate electrode 120 extending along the second direction Y1, respectively. The first gate spacer 140 may include one of tantalum nitride (SiN), hafnium oxynitride (SiON), hafnium oxide (SiO ₂ ), silicon oxycarbonitride (SiOCN), and combinations thereof. In the drawings, each of the first gate spacers 140 is shown as a single layer. However, the inventive concept is not limited thereto, and each of the first gate spacers 140 may have a multi-layered structure.

The first source/drain regions 130 are formed on both sides of the first gate electrode 120, respectively. In other words, each of the first source/drain regions 130 is formed in the second portion 110b of the first fin-shaped active pattern 110. Each of the first source/drain regions 130 may be formed in the first fin active pattern 110, that is, formed in the second portion 110b of the first fin active pattern 110.

In the drawing, each of the first source/drain regions 130 is formed in the first upper pattern 112 of the second portion 110b of the first fin-shaped active pattern 110. However, this is merely an example for convenience of description, and the inventive concept is not limited to this example.

If the semiconductor device 1 according to the first embodiment of the inventive concept is an NMOS transistor, the first source/drain region 130 may include an n-type impurity. The n-type impurity may be, but not limited to, phosphorus (P), arsenic (As), and/or antimony.

If the semiconductor device 1 according to the first embodiment of the inventive concept is a PMOS transistor, the first source/drain region 130 may include a p-type impurity. The p-type impurity may be, but not limited to, boron (B).

5 and 6 are views of a semiconductor device 2 in accordance with a second embodiment of the inventive concept. For the sake of simplicity, the present embodiment will be described hereinafter, mainly focusing on differences from the above-described embodiments with reference to FIGS. 1 to 4.

Referring to FIGS. 5 and 6 , the semiconductor device 2 according to the second embodiment further includes a first epitaxial layer 135 .

Each of the first source/drain regions 130 includes a first epitaxial layer 135. That is, each of the first source/drain regions 130 may include a first epitaxial layer 135 and an impurity region formed in the second portion 110b of the first fin-shaped active pattern 110.

The first epitaxial layer 135 is formed on the second portion 110b of the first fin active pattern 110. More specifically, in the semiconductor device 2 according to the second embodiment of the present inventive concept, the first epitaxial layer 135 is formed on all of the top surface 110b-1 and the sidewall 110b of the second portion 110b of the first fin-shaped active pattern 110. On -2, it protrudes more upward than the top surface of the field insulating layer 105. The first epitaxial layer 135 is formed to completely surround the second portion 110b of the first fin-shaped active pattern 110, which protrudes more upward than the top surface of the field insulating layer 105. The first epitaxial layer 135 may contact the field insulating layer 105.

The first epitaxial layer 135 is formed on sidewalls and a top surface of the first upper pattern 112 of the second portion 110b of the first fin active pattern 110. The first epitaxial layer 135 is formed around the first upper pattern 112.

Referring to FIG. 6, the outer peripheral surface of the first epitaxial layer 135 may have various shapes. For example, the outer peripheral surface of the first epitaxial layer 135 may be at least one of a diamond shape, a circular shape, and a rectangular shape. An octagon is illustrated in FIG.

If the semiconductor device 2 according to the second embodiment of the inventive concept is an NMOS transistor, the first epitaxial layer 135 (such as the first upper pattern 112) may include tantalum carbide.

Both the first upper pattern 112 and the first epitaxial layer 135 may include tantalum carbide. However, the proportion of carbon in the first epitaxial layer 135 may be greater than or equal to the ratio of carbon in the first upper pattern 112.

If the proportion of carbon in the first epitaxial layer 135 is greater than the ratio of carbon in the first upper pattern 112, the lattice constant of the first epitaxial layer 135 may be smaller than the lattice constant of the first upper pattern 112. Therefore, the first epitaxial layer 135 can enhance the mobility of the carrier by applying tensile stress to the channel region of the first fin active pattern 110.

If the semiconductor device 2 according to the second embodiment of the inventive concept is a PMOS transistor, the first epitaxial layer 135 (such as the first upper pattern 112) may include germanium.

Both the first upper pattern 112 and the first epitaxial layer 135 may include germanium. However, the proportion of germanium in the first epitaxial layer 135 may be greater than or equal to the ratio of germanium in the first upper pattern 112.

If the proportion of germanium in the first epitaxial layer 135 is greater than the proportion of germanium in the first upper pattern 112, the lattice constant of the first epitaxial layer 135 may be greater than the lattice constant of the first upper pattern 112. Therefore, the first epitaxial layer 135 can enhance the mobility of the carrier by applying a compressive stress to the channel region of the first fin active pattern 110.

A semiconductor device according to third and fourth embodiments of the inventive concept will be described with reference to FIGS. 7 and 8. For the sake of simplicity, the present embodiment will be described hereinafter, mainly focusing on differences from the above-described embodiments with reference to FIGS. 5 and 6.

FIG. 7 is a diagram of a semiconductor device 3 in accordance with a third embodiment of the inventive concept. FIG. 8 is a diagram of a semiconductor device 4 in accordance with a fourth embodiment of the inventive concept.

Referring to FIG. 7, in the semiconductor device 3 according to the third embodiment of the inventive concept, the first epitaxial layer 135 does not contact the field insulating layer 105.

The first epitaxial layer 135 is formed on the sidewall 110b-2 and the top surface 110b-1 of the portion of the second portion 110b of the first fin active pattern 110, which protrudes more upward than the top surface of the field insulating layer 105. That is, the first epitaxial layer 135 is formed around the second portion 110b of the portion of the first fin-shaped active pattern 110, which protrudes more upward than the top surface of the field insulating layer 105.

Referring to FIG. 8, a semiconductor device 4 according to a fourth embodiment of the inventive concept further includes a first fin spacer 145.

The first fin spacer 145 may be formed on the sidewall 110b-2 of the portion of the second portion 110b of the first fin-shaped active pattern 110, which protrudes more upward than the top surface of the field insulating layer 105. Therefore, the second portion 110b of the portion of the first fin-shaped active pattern 110 protrudes more upward than the first fin spacer 145. That is, the sidewall 110b-2 of the portion of the second portion 110b of the first fin active pattern 110 is not covered by the first fin spacer 145.

In view of FIG. 1, since the first fin spacer 145 is formed on the sidewall 110b-2 of the convex second portion 110b of the first fin-shaped active pattern 110, it extends along the first direction X1.

Further, the first fin spacer 145 is physically connected to the first gate spacer wall 140 formed on the sidewall of the first gate electrode 120. The first fin spacer 145 and the first gate spacer wall 140 are connected to each other (because they are formed at the same level). Here, the word "same level" means that the first fin spacer 145 and the first gate spacer 140 are formed by the same manufacturing process.

The first fin spacer 145 may include one of tantalum nitride, hafnium oxynitride, hafnium oxide, niobium oxynitride (SiOCN), and combinations thereof. In the schema, the first fin Each of the spacers 145 is depicted as a single layer. However, the inventive concept is not limited thereto, and each of the first fin spacers 145 may also have a multi-layered structure.

The first epitaxial layer 135 is formed on the top surface 110b-1 and the sidewall 110b-2 of the second portion 110b of the first fin-shaped active pattern 110, which protrudes upward more than the first fin spacer 145. That is, the first epitaxial layer 135 is formed around the second portion 110b of the first fin-shaped active pattern 110, which protrudes more upward than the first fin spacer 145.

The first epitaxial layer 135 may contact the first fin spacer 145.

9 and 10 are views of a semiconductor device 5 in accordance with a fifth embodiment of the inventive concept. For the sake of simplicity, the present embodiment will be described hereinafter, mainly focusing on differences from the above-described embodiments with reference to FIGS. 1 to 4.

Referring to FIG. 9 and FIG. 10, in the semiconductor device 5 according to the fifth embodiment of the inventive concept, the first fin active pattern 110 is compared with the top surface of the first portion 110a of the first fin active pattern 110. The top surface of the two portions 110b is relatively concave. Further, the semiconductor device 5 further includes a first epitaxial layer 135.

More specifically, the top surface of the first portion 110a of the first fin-shaped active pattern 110 and the top surface of the second portion 110b of the first fin-shaped active pattern 110 are more convex upward than the top surface of the field insulating layer 105. . However, the top surface of the first portion 110a of the first fin active pattern 110 and the top surface of the second portion 110b of the first fin active pattern 110 are not located in the same plane.

In the semiconductor device 5 according to the fifth embodiment of the inventive concept, the height from the top surface of the substrate 100 to the top surface of the second portion 110b of the first fin-shaped active pattern 110 is from the top surface of the substrate 100 to The height of the top surface of the first portion 110a of the first fin active pattern 110 is higher.

In addition, the sidewall 110b-2 of the portion of the second portion 110b of the first fin active pattern 110 is in contact with the field insulating layer 105, but the sidewall 110b-2 of the other portion of the second portion 110b of the first fin active pattern 110 is not Contact with the field insulating layer 105.

The first epitaxial layer 135 is formed on the recessed second portion 110b of the first fin active pattern 110. More specifically, in the semiconductor device 5 according to the fifth embodiment of the inventive concept, the first epitaxial layer 135 is formed on the top surface 110b-1 of the second portion 110b of the first fin-shaped active pattern 110, the ratio of which is The top surface of the field insulating layer 105 is more convex upward, but the first epitaxial layer 135 is not formed on the sidewall 110b-2 of the second portion 110b of the first fin active pattern 110.

If the first epitaxial layer 135 includes, for example, tantalum carbide, the proportion of carbon in the first epitaxial layer 135 may be, but is not limited to, greater than the proportion of carbon in the first upper pattern 112.

If the first epitaxial layer 135 includes, for example, germanium, the proportion of germanium in the first epitaxial layer 135 may be, but is not limited to, greater than the proportion of germanium in the first upper pattern 112.

Each of the first source/drain regions 130 may include a first epitaxial layer 135 and an impurity region formed in the recessed second portion 110b of the first fin active pattern 110.

A semiconductor device according to sixth and seventh embodiments of the inventive concept will be described with reference to FIGS. 11 and 12. For the sake of simplicity, the present embodiment will be described hereinafter, mainly focusing on differences from the above-described embodiments with reference to FIGS. 9 and 10.

Figure 11 is a diagram of a semiconductor device 6 in accordance with a sixth embodiment of the inventive concept. Figure 12 is a diagram of a semiconductor device 7 in accordance with a seventh embodiment of the inventive concept.

Referring to FIG. 11, in the semiconductor device 6 according to the sixth embodiment of the inventive concept, the first epitaxial layer 135 may contact the field insulating layer 105.

The first epitaxial layer 135 is formed on the sidewall 110b-2 and the top surface 110b-1 of the second portion 110b of the first fin active pattern 110, which protrudes more upward than the top surface of the field insulating layer 105. The first epitaxial layer 135 is formed around the second portion 110b of the first fin-shaped active pattern 110, which protrudes more upward than the top surface of the field insulating layer 105.

Referring to FIG. 12, a semiconductor device 7 according to a seventh embodiment of the inventive concept further includes a first fin spacer 145.

The first fin spacer 145 may be formed on the sidewall 110b-2 of the second portion 110b of the first fin-shaped active pattern 110, which protrudes more upward than the top surface of the field insulating layer 105. Therefore, the first fin spacer 145 may contact the first epitaxial layer 135.

In the drawing, the second portion 110b of the first fin-shaped active pattern 110 does not protrude more upward than the first fin spacer 145, but the inventive concept is not limited thereto.

13 and 14 are views of a semiconductor device 8 in accordance with an eighth embodiment of the inventive concept. For the sake of simplicity, the present embodiment will be described hereinafter, mainly focusing on differences from the above-described embodiments with reference to FIGS. 9 and 10.

Referring to FIGS. 13 and 14, in the semiconductor device 8 according to the eighth embodiment of the inventive concept, the entire sidewall 110b-2 of the second portion 110b of the first fin-shaped active pattern 110 may contact the field insulating layer 105.

The top surface 110b-1 of the second portion 110b of the first fin-shaped active pattern 110 may not protrude more upward than the top surface of the field insulating layer 105. That is, if the top surface of the field insulating layer 105 is illustrated as being flat, the top surface 110b-1 of the second portion 110b of the first fin active pattern 110 may be located on the top surface of the field insulating layer 105. In the same face.

Since the entire sidewall 110b-2 of the second portion 110b of the first fin active pattern 110 is covered by the field insulating layer 105, the first epitaxial layer 135 is formed on the top surface of the second portion 110b of the first fin active pattern 110. 110b-1, but not formed on the sidewall 110b-2 of the second portion 110b of the first fin active pattern 110.

Figure 15 is a diagram of a semiconductor device 9 in accordance with a ninth embodiment of the inventive concept. For the sake of simplicity, the present embodiment will be described hereinafter, mainly focusing on differences from the above-described embodiments with reference to FIGS. 1 to 4.

Referring to FIG. 15, in the semiconductor device 9 according to the ninth embodiment of the inventive concept, the first gate insulating layer 125 is formed along the bottom surface of the first trench 151 but not along the sidewall of the first trench 151.

The first gate insulating layer 125 is not formed along the sidewall of the first gate spacer 140. The first gate insulating layer 125 does not include a portion located in the same plane as the top surface of the first gate electrode 120.

Therefore, the first gate insulating layer 125 is interposed between the first gate electrode 120 and the first fin active pattern 110, but not between the first gate electrode 120 and the first gate spacer 140.

The first gate insulating layer 125 is not formed by a replacement process. The first gate electrode 120 may not be formed by a replacement process, but the inventive concept is not limited thereto.

A semiconductor device according to a tenth embodiment of the inventive concept will be described with reference to FIGS. 16A through 18.

16A and 16B are a perspective view and a plan view, respectively, of a semiconductor device 10 in accordance with a tenth embodiment of the inventive concept. 17 is a partial perspective view of the first fin active pattern 110 and the second fin active pattern 210 and the field insulating layer 105 illustrated in FIG. 16A. Figure 18 is a cross-sectional view taken along line D-D of Figure 16A.

Figure 18 is a cross-sectional view showing a semiconductor device 2 to a semiconductor device 4 according to second to fourth embodiments of the inventive concept. However, the inventive concept is not limited thereto. That is, the cross-sectional view of FIG. 18 may also be a cross-sectional view of any of the semiconductor device 1 to the semiconductor device 9 according to the first to ninth embodiments of the present invention.

Referring to FIG. 16A to FIG. 18 , a semiconductor device 10 according to a tenth embodiment of the present invention may include a field insulating layer 105 , a first fin active pattern 110 , a second fin active pattern 210 , a first gate electrode 120 , and a first The second gate electrode 220 and the first dummy gate electrode 160.

The first fin active pattern 110 and the second fin active pattern 210 are formed on the substrate 100. The first fin active pattern 110 and the second fin active pattern 210 protrude from the substrate 100.

The first fin active pattern 110 and the second fin active pattern 210 extend along the first direction X1. The first fin active pattern 110 and the second fin active pattern 210 are formed side by side along the length direction. The first fin active pattern 110 and the second fin active pattern 210 are formed adjacent to each other.

Since each of the first fin active pattern 110 and the second fin active pattern 210 extends along the first direction X1, it may include a long side extending along the first direction X1 and extending along the second direction Y1 Short side.

That is, if the first fin active pattern 110 and the second fin active pattern 210 extend side by side along the length direction, the short side of the first fin active pattern 110 faces the short side of the second fin active pattern 210. .

The first fin active pattern 110 includes a first lower pattern 111 and a first upper pattern 112 that are sequentially stacked on the substrate 100. The second fin active pattern 210 includes a second lower pattern 211 and a second upper pattern 212 that are sequentially stacked on the substrate 100.

Further, a top surface of the first fin active pattern 110 may be a top surface of the first upper pattern 112, and a top surface of the second fin active pattern 210 may be a top surface of the second upper pattern 212.

Similar to the first fin active pattern 110, the second upper pattern 212 is directly connected to the second lower pattern 211. Further, the second lower pattern 211 is directly connected to the substrate 100.

Similar to the first lower pattern 111, the second lower pattern 211 is a ruthenium pattern containing ruthenium. The second upper pattern 212 may be a ruthenium carbide pattern containing ruthenium carbide or a ruthenium pattern containing ruthenium.

The first upper pattern 112 and the second upper pattern 212 may comprise the same material. That is, the first upper pattern 112 and the second upper pattern 212 may be, but are not limited to, a tantalum carbide pattern or a tantalum pattern.

A field insulating layer 105 is formed on the substrate 100. The field insulating layer 105 is formed around the first fin active pattern 110 and the second fin active pattern 210. Therefore, the first fin active pattern 110 and the second fin active pattern 210 may be defined by the field insulating layer 105.

The field insulating layer 105 includes a first region 106 and a second region 107. The first region 106 of the field insulating layer 105 contacts the long side of the first fin active pattern 110 and the long side of the second fin active pattern 210. The first region 106 of the field insulating layer 105 may extend along the long side of the first fin active pattern 110 and the long side of the second fin active pattern 210 in the first direction X1.

The second region 107 of the field insulating layer 105 contacts the short side of the first fin active pattern 110 and the short side of the second fin active pattern 210. Second region of field insulating layer 105 107 is formed between the short side of the first fin active pattern 110 and the short side of the second fin active pattern 210 to extend along the second direction Y1.

In the semiconductor device 10 according to the tenth embodiment of the inventive concept, the top surface of the first region 106 of the field insulating layer 105 and the top surface of the second region 107 of the field insulating layer 105 may be located in the same plane. That is, the height H1 of the first region 106 of the field insulating layer 105 and the height H2 of the second region 107 of the field insulating layer 105 may be the same.

The first gate electrode 120 is formed on the first region 106 of the first fin active pattern 110 and the field insulating layer 105. The first gate electrode 120 intersects the first fin active pattern 110.

The second gate electrode 220 is formed on the first region 106 of the second fin active pattern 210 and the field insulating layer 105. The second gate electrode 220 intersects the second fin active pattern 210.

The first gate electrode 120 and the second gate electrode 220 may extend along the second direction Y1. In the drawing, one first gate electrode 120 is intersected with the first fin active pattern 110, and one second gate electrode 220 is intersected with the second fin active pattern 210. However, this is merely an example for convenience of description, and the inventive concept is not limited to this example.

At least a portion of the first dummy gate electrode 160 is formed on the second region 107 of the field insulating layer 105. The first dummy gate electrode 160 is formed side by side with the first gate electrode 120 and the second gate electrode 220. The first dummy gate electrode 160 is formed between the first gate electrode 120 and the second gate electrode 220. The first gate electrode 160 may extend along the second direction Y1.

In the semiconductor device 10 according to the tenth embodiment of the inventive concept, the entire first dummy gate electrode 160 is formed on the second region 107 of the field insulating layer 105. That is, the entire first dummy gate electrode 160 overlaps the second region 107 of the field insulating layer 105.

The first dummy gate electrode 160 is formed between the short side of the first fin active pattern 110 and the short side of the second fin active pattern 210. In other words, the first dummy gate electrode 160 is formed between the end of the first fin active pattern 110 and the end of the second fin active pattern 210. The first dummy gate electrode 160 may extend between an end of the first fin active pattern 110 and an end of the second fin active pattern 210 to be formed on the second region 107 of the field insulating layer 105.

In addition, one first dummy gate electrode 160 may be formed between the first fin active pattern 110 and the second fin active pattern 210. Since only one first dummy gate electrode 160 is formed instead of two or more than two first dummy gate electrodes between the first fin active pattern 110 and the second fin active pattern 210, the layout can be reduced. size.

Similar to the first gate electrode 120, the second gate electrode 220 may include at least one of tungsten, aluminum, titanium nitride, tantalum nitride, titanium carbide, and tantalum carbide. The second gate electrode 220 may be formed in the second trench 152 included in the interlayer insulating film 150.

The first dummy gate electrode 160 may have a structure similar to the first gate electrode 120 and the second gate electrode 220. The first dummy gate electrode 160 may include at least one of tungsten, aluminum, titanium nitride, tantalum nitride, titanium carbide, and tantalum carbide.

The first dummy gate electrode 160 may be formed in the third trench 153 included in the interlayer insulating film 150. The third trench 153 may extend along the second direction Y1 to overlap the second region 107 of the field insulating layer 105.

Similar to the first gate electrode 120 and the second gate electrode 220, the first dummy gate electrode 160 may be formed by a replacement process (or a post-last gate process), but is not limited thereto.

The second gate insulating layer 225 may be formed along a top surface and a sidewall of the second fin active pattern 210. The second gate insulating layer 225 may be formed along sidewalls and a bottom surface of the second trench 152.

The first dummy gate insulating layer 165 may be formed along sidewalls and a bottom surface of the third trench 153. In other words, the first dummy gate insulating layer 165 may be formed along the sidewall of the first dummy gate spacer 170 and the top surface of the second region 107 of the field insulating layer 105.

The second gate insulating layer 225 and the first dummy gate insulating layer 165 may include a hafnium oxide layer and/or a high dielectric constant material having a dielectric constant higher than that of the hafnium oxide layer.

In the drawing, the entire first dummy gate spacer 170 is formed on the second region 107 of the field insulating layer 105, and thus does not contact the first fin active pattern 110 and the second fin active pattern 210. However, the inventive concept is not limited thereto.

The second source/drain regions 230 are formed on both sides of the second gate electrode 220, respectively. Each of the second source/drain regions 230 may include a second epitaxial layer 235. The second epitaxial layer 235 may be the same as the first epitaxial layer 135 described above, and thus redundant description thereof is omitted.

A semiconductor device according to the eleventh and twelfth embodiments of the inventive concept will be described with reference to FIGS. 19 to 21. For the sake of simplicity, the present embodiment will be described hereinafter, mainly focusing on differences from the above-described embodiments with reference to Figs. 16 to 18.

19 and 20 are views of a semiconductor device 11 in accordance with an eleventh embodiment of the inventive concept. Figure 21 is a cross-sectional view of a semiconductor device 12 in accordance with a twelfth embodiment of the inventive concept.

Referring to FIG. 19 and FIG. 20, in the semiconductor device 11 according to the eleventh embodiment of the inventive concept, the top surface of the second region 107 of the field insulating layer 105 is higher than the top surface of the first region 106 of the field insulating layer 105. . However, the second of the field insulating layer 105 The top surface of the region 107 is lower than the top surface of the first fin active pattern 110 and the top surface of the second fin active pattern 210.

That is, the top surface of the first region 106 of the field insulating layer 105 and the top surface of the second region 107 of the field insulating layer 105 are not located in the same plane.

More specifically, the height H2 of the second region 107 of the field insulating layer 105 is greater than the height H1 of the first region 106 of the field insulating layer 105. However, the height H2 of the second region 107 of the field insulating layer 105 is smaller than the height of the first fin active pattern 110 and the height of the second fin active pattern 210. As shown, the height may refer to the relative distance from the surface of the substrate 100.

In the drawing, a portion of the first fin active pattern 110 and a portion of the second fin active pattern 210 overlap the first dummy gate spacer 170. However, the inventive concept is not limited thereto.

Referring to FIG. 21, in the semiconductor device 12 according to the twelfth embodiment of the present inventive concept, the top surface of the second region 107 of the field insulating layer 105 is higher than the top surface of the first region 106 of the field insulating layer 105.

In addition, the top surface of the second region 107 of the field insulating layer 105 may be at the same level as the top surface of the first fin active pattern 110 and the top surface of the second fin active pattern 210, or the second region of the field insulating layer 105. The top surface of the 107 may be higher than the top surface of the first fin active pattern 110 and the top surface of the second fin active pattern 210.

In the drawing, the top surface of the second region 107 of the field insulating layer 105 is located in the same plane as the top surface of the first fin active pattern 110 and the top surface of the second fin active pattern 210. However, the inventive concept is not limited thereto.

22 and 23 are views of a semiconductor device 13 according to a thirteenth embodiment of the inventive concept. For the sake of simplicity, the present embodiment will be described hereinafter, mainly focusing on differences from the above-described embodiments with reference to Figs. 16 to 18.

Referring to FIG. 22 and FIG. 23, the semiconductor device 13 according to the thirteenth embodiment of the inventive concept further includes a second dummy gate electrode 260.

The second dummy gate electrode 260 is formed side by side with the first gate electrode 120 and the second gate electrode 220. The second dummy gate electrode 260 is formed between the first gate electrode 120 and the second gate electrode 220. The second virtual gate electrode 260 may extend along the second direction Y1.

The second dummy gate electrode 260 may have a structure similar to that of the first dummy gate electrode 160, and thus description thereof will be omitted.

In the semiconductor device 13 according to the thirteenth embodiment of the inventive concept, a portion of the first dummy gate electrode 160 and a portion of the second dummy gate electrode 260 are formed on the second region 107 of the field insulating layer 105. That is, only a portion of the first dummy gate electrode 160 may overlap the second region 107 of the field insulating layer 105, and only a portion of the second dummy gate electrode 260 may overlap the second region 107 of the field insulating layer 105.

In other words, a portion of the first dummy gate electrode 160 is formed on the second region 107 of the field insulating layer 105, and other portions of the first dummy gate electrode 160 are formed in the first region 106 of the field insulating layer 105 and the first fin On the active pattern 110. Further, a portion of the second dummy gate electrode 260 is formed on the second region 107 of the field insulating layer 105, and other portions of the second dummy gate electrode 260 are formed in the first region 106 and the second fin active of the field insulating layer 105. On the pattern 210.

In FIG. 23, the height H1 of the first region 106 of the field insulating layer 105 is equal to the height H2 of the second region 107 of the field insulating layer 105. However, the inventive concept is not limited thereto.

That is, as shown in FIGS. 19 and 20, the top surface of the second region 107 of the field insulating layer 105 is higher than the top surface of the first region 106 of the field insulating layer 105. However, the top surface of the second region 107 of the field insulating layer 105 is lower than the top surface of the first fin active pattern 110 and the top surface of the second fin active pattern 210.

In some embodiments, the top surface of the second region 107 of the field insulating layer 105 is higher than the top surface of the first region 106 of the field insulating layer 105. In addition, the top surface of the second region 107 of the field insulating layer 105 may be at the same level as the top surface of the first fin active pattern 110 and the top surface of the second fin active pattern 210, or the second region of the field insulating layer 105. The top surface of the 107 may be higher than the top surface of the first fin active pattern 110 and the top surface of the second fin active pattern 210.

A semiconductor device according to the fourteenth to twenty-second embodiments of the inventive concept will be described with reference to FIGS. 24 to 36.

Figure 24 is a perspective view of a semiconductor device 14 in accordance with a fourteenth embodiment of the inventive concept. Figure 25 is a cross-sectional view taken along line A-A and line E-E of Figure 24.

26 and 27 are views of a semiconductor device 15 in accordance with a fifteenth embodiment of the inventive concept. Figure 28 is a diagram of a semiconductor device 16 in accordance with a sixteenth embodiment of the inventive concept.

Figure 29 is a diagram of a semiconductor device 17 in accordance with a seventeenth embodiment of the inventive concept. 30 and 31 are views of a semiconductor device 18 in accordance with an eighteenth embodiment of the inventive concept. Figure 32 is a diagram of a semiconductor device 19 in accordance with a nineteenth embodiment of the inventive concept.

Figure 33 is a diagram of a semiconductor device 20 in accordance with a twentieth embodiment of the inventive concept. 34 and 35 are diagrams of a semiconductor device 21 according to a twenty-first embodiment of the inventive concept. Figure 36 is a diagram of a semiconductor device 22 in accordance with a twenty-second embodiment of the inventive concept.

Specifically, FIGS. 26, 30, 34, and 36 are cross sections taken along line AA and line EE of FIG. 24 of the semiconductor device 14 to the semiconductor device 22 according to the fourteenth to twenty-second embodiments. Figure. 27 to 29, 31 to 33, and 35 are cross-sectional views of the semiconductor device 14 to the semiconductor device 22 according to the fourteenth to twenty-second embodiments taken along line CC and line FF of Fig. 24. .

In the semiconductor device 14 to the semiconductor device 22 according to the fourteenth to twenty-secondth embodiments of the inventive concept, the first transistor 101 formed in the first region I may be substantially described with reference to FIGS. 1 to 15 described above. Those of the same are the same, and thus the description thereof will be simply described or omitted.

Referring to FIG. 24 and FIG. 25, a semiconductor device 14 according to a fourteenth embodiment of the present invention may include a substrate 100, a first fin active pattern 110, a third fin active pattern 310, a first gate electrode 120, and a third The gate electrode 320, the first source/drain region 130, and the third source/drain region 330.

The substrate 100 may include a first region I and a second region II. The first zone I and the second zone II may be separated from each other or connected to each other. Further, the first region I and the second region II may include different types of transistor regions. For example, the first region I may be formed with an NMOS transistor, and the second region II may be formed with a PMOS transistor.

The first transistor 101 includes a first fin active pattern 110, a first gate electrode 120, and a first source/drain region 130.

In the semiconductor device 14 to the semiconductor device 22 according to the fourteenth to twenty-secondth embodiments of the inventive concept, the first upper pattern 112 of the first fin-shaped active pattern 110 may be a tantalum carbide pattern containing tantalum carbide. Further, the first source/drain region 130 may include an n-type impurity.

Other features of the first transistor 101 are the same as those described above with reference to FIGS. 1 to 4, and thus redundant description thereof will be omitted.

The second transistor 301 includes a third fin active pattern 310, a third gate electrode 320, and a third source/drain region 330.

The third fin active pattern 310 may protrude from the substrate 100. The field insulating layer 105 partially covers the sidewall of the third fin active pattern 310. Therefore, the top surface of the third fin-shaped active pattern 310 protrudes more upward than the top surface of the field insulating layer 105. The third fin active pattern 310 is defined by the field insulating layer 105.

The third fin active pattern 310 includes a third lower pattern 311 and a third upper pattern 312 which are sequentially stacked on the substrate 100. The third upper pattern 312 is formed on the third lower pattern 311. The third upper pattern 312 and the third lower pattern 311 are directly connected to each other.

The top surface of the third fin active pattern 310 may be the top surface of the third upper pattern 312. At least a portion of the third upper pattern 312 protrudes more upward than the field insulating layer 105. The third upper pattern 312 can be used as a channel region of the second transistor 301.

The third lower pattern 311 is a ruthenium pattern containing ruthenium. The third upper pattern 312 is a ruthenium pattern containing ruthenium.

The third lower pattern 311 is directly connected to the substrate 100. Since the substrate 100 may be a germanium substrate and the third lower pattern 311 is a meander pattern, they may be an integral structure.

In FIG. 24, the contact surfaces of the third upper pattern 312 and the third lower pattern 311 are located in the same plane as the top surface of the field insulating layer 105. That is, the entire sidewall of the third lower pattern 311 is in contact with the field insulating layer 105, and the entire sidewall of the third upper pattern 312 is not in contact with the field insulating layer 105. However, the inventive concept is not limited thereto.

The third fin active pattern 310 may extend along the third direction X2. The third fin active pattern 310 includes a first portion 310a and a second portion 310b. The second portion 310b of the third fin active pattern 310 is disposed on both sides of the first portion 310a of the third fin active pattern 310 in the third direction X2.

In the semiconductor device 14 according to the fourteenth embodiment of the inventive concept, the top surface of the first portion 310a of the third fin-shaped active pattern 310 and the third fin-shaped active pattern 310 are compared with the top surface of the field insulating layer 105. The top surface of the second portion 310b is more convex upward. Further, the top surface of the first portion 310a of the third fin active pattern 310 and the top surface of the second portion 310b of the third fin active pattern 310 are located in the same plane.

The third gate electrode 320 is formed on the third fin active pattern 310 and the field insulating layer 105. For example, the third gate electrode 320 is formed on the first portion 310a of the third fin active pattern 310. More specifically, the third gate electrode 320 is formed on the side walls and the top surface of the third upper pattern 312.

The third gate electrode 320 extends along the fourth direction Y2 to intersect the third fin active pattern 310.

The third gate electrode 320 may include a metal layer. The third gate electrode 320 may include a portion that controls a work function and a portion that fills the fourth trench 156. The third gate electrode 320 may include at least one of tungsten, aluminum, titanium nitride, tantalum nitride, titanium carbide, and tantalum carbide. In some embodiments, the third gate electrode 320 can be made of, for example, germanium and/or germanium.

The third gate insulating layer 325 may be formed between the third fin active pattern 310 and the third gate electrode 320. The third gate insulating layer 325 may be formed along a top surface and sidewalls of the first portion 310a of the third fin active pattern 310. The third gate insulating layer 325 may be formed along sidewalls and a top surface of the third upper pattern 312, which is greater than the field insulating layer 105 The top surface is more convex upwards. The third gate insulating layer 325 may be formed along sidewalls and a bottom surface of the fourth trench 156.

The third gate insulating layer 325 may include a hafnium oxide layer and/or a high dielectric constant material having a dielectric constant higher than that of the hafnium oxide layer.

The third source/drain regions 330 are formed on both sides of the third gate electrode 320, respectively. For example, each of the third source/drain regions 330 is formed in the second portion 310b of the third fin-shaped active pattern 310. Each of the third source/drain regions 330 may be formed in the third fin active pattern 310, that is, formed in the second portion 310b of the third fin active pattern 310.

The third source/drain region 330 may include a p-type impurity.

A semiconductor device 15 according to a fifteenth embodiment of the inventive concept will be described with reference to FIGS. 26 and 27. For the sake of simplicity, the present embodiment will be described hereinafter, mainly focusing on the differences from the above-described embodiments with reference to Figs. 24 and 25.

Referring to FIG. 26 and FIG. 27, the semiconductor device 15 according to the fifteenth embodiment of the present invention further includes a first epitaxial layer 135 and a third epitaxial layer 335.

In the semiconductor device 15 to the semiconductor device 21 according to the fifteenth to twenty-first embodiments of the inventive concept, the first epitaxial layer 135 may include tantalum carbide. The first upper pattern 112 and the first epitaxial layer 135 both include tantalum carbide. However, the proportion of carbon in the first epitaxial layer 135 may be greater than or equal to the ratio of carbon in the first upper pattern 112.

Other features of the first transistor 101 are the same as those described above with reference to FIGS. 5 and 6, and thus redundant description thereof will be omitted.

Each of the third source/drain regions 330 may include a third epitaxial layer 335 and an impurity region formed in the second portion 310b of the third fin active pattern 310.

The entire third epitaxial layer 335 is formed on the top surface 310b-1 and the sidewall 310b-2 of the second portion 310b of the third fin-shaped active pattern 310, which protrudes more upward than the top surface of the field insulating layer 105. The third epitaxial layer 335 may be in contact with the field insulating layer 105.

The third epitaxial layer 335 is formed on sidewalls and a top surface of the third upper pattern 312 of the second portion 310b of the third fin active pattern 310.

In FIG. 27, the outer peripheral surface of the third epitaxial layer 335 may be of various shapes. For example, the outer peripheral surface of the third epitaxial layer 335 may be at least one of a diamond shape, a circular shape, and a rectangular shape. An octagon is illustrated in FIG.

Similar to the third upper pattern 312, the third epitaxial layer 335 can include germanium.

That is, the third upper pattern 312 and the third epitaxial layer 335 all include germanium. However, the proportion of germanium in the third epitaxial layer 335 may be greater than or equal to the proportion of germanium in the third upper pattern 312.

The semiconductor device 16 and the semiconductor device 17 according to the sixteenth and seventeenth embodiments of the inventive concept will be described with reference to FIGS. 28 and 29. For the sake of simplicity, the present embodiment will be described hereinafter, mainly focusing on the differences from the above-described embodiments with reference to Figs. 26 and 27.

Referring to FIG. 28, in the semiconductor device 16 according to the sixteenth embodiment of the inventive concept, the first epitaxial layer 135 does not contact the field insulating layer 105, and the third epitaxial layer 335 does not contact the field insulating layer 105.

The third epitaxial layer 335 is formed on the sidewall 310b-2 and the top surface 310b-1 of the portion of the second portion 310b of the third fin active pattern 310, which protrudes more upward than the top surface of the field insulating layer 105. That is, the third epitaxial layer 335 is formed around the second portion 310b of the portion of the third fin-shaped active pattern 310, which protrudes more upward than the top surface of the field insulating layer 105.

Referring to FIG. 29, a semiconductor device 17 according to a seventeenth embodiment of the inventive concept further includes a first fin spacer 145 and a second fin spacer 345.

The second fin spacer 345 may be formed on the sidewall 310b-2 of the portion of the second portion 310b of the third fin-shaped active pattern 310, which protrudes more upward than the top surface of the field insulating layer 105. Therefore, the second portion 310b of the portion of the third fin-shaped active pattern 310 protrudes more upward than the second fin spacer 345. That is, the sidewall 310b-2 of the portion of the second portion 310b of the third fin active pattern 310 is not covered by the second fin spacer 345.

The third epitaxial layer 335 is formed on the top surface 310b-1 and the sidewall 310b-2 of the second portion 310b of the third fin active pattern 310, which protrudes more upward than the second fin spacer 345. That is, the third epitaxial layer 335 is formed around the second portion 310b of the third fin-shaped active pattern 310, which protrudes more upward than the second fin spacer 345.

The third epitaxial layer 335 may be in contact with the second fin spacer 345.

A semiconductor device 18 according to an eighteenth embodiment of the concept of the present invention will be described with reference to FIGS. 30 and 31. For the sake of simplicity, the present embodiment will be described hereinafter, mainly focusing on differences from the above-described embodiments with reference to Figs. 26 and 27.

Referring to FIG. 30 and FIG. 31, in the semiconductor device 18 according to the eighteenth embodiment of the present invention, the top surface of the second portion 110b of the first fin active pattern 110 is larger than the first portion 110a of the first fin active pattern 110. The top surface is sunken. Further, the top surface of the second portion 310b of the third fin active pattern 310 is recessed from the top surface of the first portion 310a of the third fin active pattern 310.

The top surface of the first portion 310a of the third fin-shaped active pattern 310 and the top surface of the second portion 310b of the third fin-shaped active pattern 310 protrude more upward than the top surface of the field insulating layer 105. However, the first of the third fin active pattern 310 The top surface of the portion 310a and the top surface of the second portion 310b of the third fin active pattern 310 are not located in the same plane.

The height from the top surface of the substrate 100 to the top surface of the first portion 310a of the third fin-shaped active pattern 310 is greater than the height from the top surface of the substrate 100 to the top surface of the second portion 310b of the third fin-shaped active pattern 310.

In addition, the sidewall 310b-2 of the portion of the second portion 310b of the third fin active pattern 310 is in contact with the field insulating layer 105, but the sidewall 310b-2 of the other portion of the second portion 310b of the third fin active pattern 310 is not It will be in contact with the field insulating layer 105.

The third epitaxial layer 335 is formed on the recessed second portion 310b of the third fin active pattern 310. More specifically, the third epitaxial layer 335 is formed on the top surface 310b-1 of the second portion 310b of the third fin active pattern 310 but is not formed on the second portion 310b of the third fin active pattern 310. On the side wall 310b-2, it protrudes more upward than the top surface of the field insulating layer 105.

The semiconductor device 19 and the semiconductor device 20 according to the nineteenth and twentieth embodiments of the inventive concept will be described with reference to FIGS. 32 and 33. For the sake of simplicity, the present embodiment will be described hereinafter, mainly focusing on differences from the above-described embodiments with reference to Figs. 30 and 31.

Referring to FIG. 32, in the semiconductor device 19 according to the nineteenth embodiment of the present invention, the first epitaxial layer 135 and the third epitaxial layer 335 may be in contact with the field insulating layer 105.

The third epitaxial layer 335 is formed on the sidewall 310b-2 and the top surface 310b-1 of the second portion 310b of the third fin active pattern 310, which is greater than the field insulating layer 105. The top surface is more convex upwards. The third epitaxial layer 335 is formed around the second portion 310b of the third fin-shaped active pattern 310, which protrudes more upward than the top surface of the field insulating layer 105.

Referring to FIG. 33, the semiconductor device 20 according to the twentieth embodiment of the present invention further includes a first fin spacer 145 and a second fin spacer 345.

The second fin spacer 345 may be formed on the sidewall 310b-2 of the second portion 310b of the third fin-shaped active pattern 310, which protrudes more upward than the top surface of the field insulating layer 105. Therefore, the second fin spacer 345 may be in contact with the third epitaxial layer 335.

In the drawing, the second portion 310b of the third fin active pattern 310 does not protrude more upward than the second fin spacer 345. However, the inventive concept is not limited thereto.

A semiconductor device 21 according to a twenty-first embodiment of the inventive concept will be described with reference to FIGS. 34 and 35. For the sake of simplicity, the present embodiment will be described hereinafter, mainly focusing on differences from the above-described embodiments with reference to Figs. 26 and 27.

Referring to FIG. 34 and FIG. 35, in the semiconductor device 21 according to the twenty-first embodiment of the inventive concept, the entire sidewall 110b-2 of the second portion 110b of the first fin active pattern 110 and the third fin active pattern The entire sidewall 310b-2 of the second portion 310b of the 310 may be in contact with the field insulating layer 105.

The top surface 310b-1 of the second portion 310b of the third fin-shaped active pattern 310 may not protrude more upward than the top surface of the field insulating layer 105. That is, if the top surface of the field insulating layer 105 is flat as shown in the drawing, the top surface 310b-1 of the second portion 310b of the third fin active pattern 310 may be the top surface of the field insulating layer 105. Located in the same face.

Since the entire sidewall 310b-2 of the second portion 310b of the third fin active pattern 310 is covered by the field insulating layer 105, the third epitaxial layer 335 is formed in the third The top surface 310b-1 of the second portion 310b of the fin active pattern 310 is formed on the sidewall 310b-2 of the second portion 310b of the third fin active pattern 310.

A semiconductor device 22 according to a twenty-second embodiment of the inventive concept will be described with reference to FIG. For the sake of simplicity, the present embodiment will be described hereinafter, mainly focusing on differences from the above-described embodiments with reference to Figs. 24 and 25.

Referring to FIG. 36, in the semiconductor device 22 according to the twenty-second embodiment of the inventive concept, the first gate insulating layer 125 is formed along the bottom surface of the first trench 151, but not along the sidewall of the first trench 151. . Further, the third gate insulating layer 325 is formed along the bottom surface of the fourth trench 156, but not along the sidewall of the fourth trench 156.

The third gate insulating layer 325 is not formed along the sidewall of the third gate spacer 340. The third gate insulating layer 325 does not include a portion located in the same plane as the top surface of the third gate electrode 320.

Therefore, the third gate insulating layer 325 is interposed between the third gate electrode 320 and the third fin active pattern 310, but not between the third gate electrode 320 and the third gate spacer 340.

In the above-described semiconductor device 14 to semiconductor device 22 of FIGS. 24 to 36, it is desirable that the first transistor 101 and the second transistor 301 have the same structure. However, this is merely an example for convenience of description, and the inventive concept is not limited to this example.

That is, the second transistor 301 illustrated in FIGS. 24 and 25 may have not only the structure described above with reference to FIGS. 1 to 4, but also the structure described above with reference to FIGS. 5 to 15.

A method of manufacturing a semiconductor device according to the inventive concept will be described with reference to FIGS. 37 to 45. The semiconductor device manufactured by the processes of FIGS. 37 to 45 may be the semiconductor device 8 described above with reference to FIGS. 13 and 14.

37 through 45 are operational diagrams illustrating a method of fabricating a semiconductor device in accordance with some embodiments of the inventive concept.

Referring to FIG. 37, a compound semiconductor layer 112p is formed on the substrate 100. The compound semiconductor layer 112p is formed to directly contact the substrate 100. The compound semiconductor layer 112p can be formed, for example, by an epitaxial growth process.

The compound semiconductor layer 112p includes a material having a lattice constant different from that of the material of the substrate 100. If the substrate 100 is a germanium substrate, the compound semiconductor layer 112p includes a material having a lattice constant greater than or less than germanium.

When used as a channel region of an NMOS, the compound semiconductor layer 112p may be a tantalum carbide layer.

On the other hand, when used as a channel region of a PMOS, the compound semiconductor layer 112p may be, for example, a germanium layer.

The compound semiconductor layer 112p formed on the substrate 100 can be completely strained. That is, the lattice constant of the compound semiconductor layer 112p may be equal to the lattice constant of the substrate 100. In order to completely strain the compound semiconductor layer 112p, the thickness of the compound semiconductor layer 112p formed on the substrate 100 may be less than or equal to a critical thickness.

A first mask pattern 2103 is formed on the compound semiconductor layer 112p. The first mask pattern 2103 may extend along the first direction X1.

The first mask pattern 2103 may include a material including at least one of a ruthenium oxide layer, a tantalum nitride layer, and a ruthenium oxynitride layer.

Referring to FIG. 38, the compound semiconductor layer 112p is patterned with a portion of the substrate 100 to form a first fin active pattern 110 on the substrate 100.

Specifically, the compound semiconductor layer 112p and a portion of the substrate 100 are etched using the first mask pattern 2103 formed on the compound semiconductor layer 112p as a mask. Therefore, the first fin active pattern 110 is formed on the substrate 100 to extend along the first direction X1.

The first upper pattern 112 is formed by patterning the compound semiconductor layer 112p, and the first lower pattern 111 is formed by patterning a portion of the substrate. That is, the first fin-shaped active pattern 110 protruding upward from the substrate 100 includes the first lower pattern 111 and the first upper pattern 112 sequentially stacked on the substrate 100.

Referring to FIG. 39, a field insulating layer 105 is formed on the substrate 100. The field insulating layer 105 may be made of a material including at least one of a hafnium oxide layer, a tantalum nitride layer, and a hafnium oxynitride layer.

For example, a field insulating layer 105 is formed on the substrate 100 to cover the first fin active pattern 110 and the first mask pattern 2103. Next, a planarization process is performed such that the top surface of the first fin active pattern 110 is on the same side as the top surface of the field insulating layer 105.

The first mask pattern 2103 may be removed in the planarization process, however, the inventive concept is not limited thereto. That is, the first mask pattern 2103 may be removed before the formation of the field insulating layer 105 or after the process of recessing the field insulating layer 105.

Next, a portion of the field insulating layer 105 is recessed. Therefore, the first fin active pattern 110 protrudes more upward than the top surface of the field insulating layer 105. That is, the field insulating layer 105 is formed as a sidewall that contacts a portion of the first fin-shaped active pattern 110. Therefore, the first fin active pattern 110 can be defined by the field insulating layer 105.

The removal of a portion of the field insulating layer 105 causes at least a portion of the first upper pattern 112 to protrude more upward than the field insulating layer 105.

Further, the first fin active pattern 110 may be doped with impurities for controlling the threshold voltage. In order to fabricate an NMOS fin transistor using the first fin active pattern 110, boron (B) may be used as an impurity for controlling a threshold voltage. In order to fabricate a PMOS fin transistor using the first fin active pattern 110, phosphorus (P) and/or arsenic (As) may be used as an impurity for controlling a threshold voltage. That is, the first upper pattern 112 serving as a channel region of the transistor may be doped with impurities for controlling the threshold voltage.

Referring to FIG. 40, an etching process is performed using the second mask pattern 2104, thereby forming a dummy gate pattern 126 that intersects the first fin active pattern 110 and extends along the second direction Y1.

A dummy gate pattern 126 is formed on the field insulating layer 105 and on the first fin active pattern 110 formed on the substrate 100. The dummy gate pattern 126 includes a dummy gate insulating layer 127 and a dummy gate electrode 128. For example, the dummy gate insulating layer 127 may be a hafnium oxide layer, and the dummy gate electrode 128 may be a polysilicon.

In the method of fabricating a semiconductor device according to the current embodiment, the dummy gate pattern 126 is formed to form a replacement gate electrode. However, the inventive concept is not limited thereto.

That is, a gate pattern (not the dummy gate pattern 126) may be formed on the first fin active pattern 110 using a material to be used as a gate insulating layer of the transistor and a gate electrode. Here, the gate pattern may include a high dielectric constant gate insulating layer having a dielectric constant higher than that of the tantalum oxide layer and/or the metal gate electrode.

Referring to FIG. 41, a first gate spacer wall 140 is formed on a sidewall of the dummy gate pattern 126. In other words, the first gate spacer wall 140 is formed on the side surface of the dummy gate electrode 128.

Specifically, a spacer layer is formed on the dummy gate pattern 126 and the first fin active pattern 110, and then etch-back to form the first gate spacer 140. The first gate spacer wall 140 may expose a top surface of the second mask pattern 2104 and a top surface of the fin active pattern 110 that does not overlap the dummy gate pattern 126.

Next, a recess is formed in the first fin active pattern 110 by partially removing the first fin active pattern 110 exposed on both sides of the dummy gate pattern 126. That is, a recess is formed on both sides of the dummy gate electrode 128 by partially removing the first fin active pattern 110 that does not overlap the dummy gate electrode 128.

Referring to FIG. 42, a first source/drain region 130 each including a first epitaxial layer 135 is formed on both sides of the dummy gate pattern 126.

The first epitaxial layer 135 fills the recesses formed on both sides of the dummy gate pattern 126. That is, the first epitaxial layer 135 is formed on the first fin active pattern 110.

The first epitaxial layer 135 can be formed using an epitaxial growth method. If necessary, the first epitaxial layer 135 may be doped in-situ with impurities in an epitaxial process.

In the drawings, the first epitaxial layer 135 is octagonal. However, the shape of the first epitaxial layer 135 is not limited to the octagon. That is, the first epitaxial layer can be formed into various shapes such as a rhombus, a rectangle, and/or a pentagon by controlling the conditions of the epitaxial process for forming the first epitaxial layer 135.

If the first upper pattern 112 used as the channel region is a tantalum carbide pattern, the first epitaxial layer 135 may include tantalum carbide.

If the first upper pattern 112 used as the channel region is a germanium pattern, the first epitaxial layer 135 may include germanium.

Referring to FIG. 43, an interlayer insulating film 150 is formed on the substrate 100 to cover the first source/drain regions 130 and the dummy gate patterns 126. The interlayer insulating film 150 may include at least one of an oxide layer, a nitride layer, and an oxynitride layer.

The interlayer insulating film 150 is planarized until the top surface of the dummy gate pattern 126 is exposed. Therefore, the second mask pattern 2104 is removed and the top surface of the dummy gate electrode 128 is exposed.

Referring to FIG. 44, the dummy gate pattern 126 is removed, that is, the dummy gate insulating layer 127 and the dummy gate electrode 128 are removed.

The removal of the dummy gate insulating layer 127 and the dummy gate electrode 128 results in the trench formation of the exposed field insulating layer 105 and a portion of the first fin active pattern 110. The first upper pattern 112 is exposed by the trench.

Referring to FIG. 45, a first gate insulating layer 125 and a first gate electrode 120 are formed in the trench.

The first gate insulating layer 125 may be formed substantially conformally along the sidewalls and the bottom surface of the trench. The first gate electrode 120 may fill the trench in which the first gate insulating layer 125 is formed.

A method of fabricating a semiconductor device according to some other embodiments of the inventive concept will be described with reference to FIGS. 37 to 40 and FIGS. 43 to 47. The semiconductor device manufactured by the processes of FIGS. 37 to 40 and FIGS. 43 to 47 may be the above-described semiconductor device 2 with reference to FIGS. 5 and 6.

46 and 47 are operational diagrams illustrating a method of fabricating a semiconductor device in accordance with other embodiments of the inventive concept.

Referring to FIG. 46, a first gate spacer wall 140 is formed on a sidewall of the dummy gate pattern 126. In the process of forming the first gate spacer 140, the first fin active pattern 110 that does not overlap the dummy gate pattern 126 is not etched.

More specifically, in the process of forming the first gate spacers 140, fin spacers may also be formed on the sidewalls of the first fin active pattern 110. By controlling the conditions of the etch back process for forming the first gate spacers 140, only the fin spacers formed on the sidewalls of the first fin active pattern 110 may be removed without etching the first fin active pattern 110.

That is, an etching material having an etch selectivity with respect to the first upper pattern 112 may be used to etch only the material forming the first gate spacer 140 and the fin spacer without etching the first upper pattern 112.

Therefore, the first fin active pattern 110 that does not overlap with the dummy gate pattern 126 and the first gate spacer wall 140 are still more convex upward than the field insulating layer 105.

Referring to FIG. 47, a first epitaxial layer 135 is formed on both sides of the dummy gate pattern 126.

The first epitaxial layer 135 is formed on sidewalls and a top surface of the first fin active pattern 110, which is more convex than the field insulating layer 105. For example, the first epitaxial layer 135 is formed on sidewalls and a top surface of the first upper pattern 112 that protrudes more upward than the field insulating layer 105. The first epitaxial layer 135 is formed around the first upper pattern 112 that protrudes more upward than the field insulating layer 105.

Accordingly, the first source/drain regions 130 each including the first epitaxial layer 135 and the impurity regions formed in the first fin-shaped active pattern 110 are formed.

FIG. 48 is a block diagram of an electronic system 1100 including a semiconductor device in accordance with some embodiments of the present inventive concepts.

Referring to FIG. 48, the electronic system 1100 can include a controller 1110, an input/output (I/O) device 1120, a memory device 1130, an interface 1140, and a bus bar 1150. The controller 1110, the I/O device 1120, the memory device 1130, and/or the interface 1140 may be connected to each other by a bus bar 1150. Bus 1150 can be used as a path for transferring data.

Controller 1110 can include at least one of a microprocessor, a digital signal processor, a microcontroller, and logic capable of performing functions similar to those of a microprocessor, digital signal processor, and/or microcontroller. The I/O device 1120 can include a keypad, a keyboard, and a display device. The memory device 1130 can store data and/or instructions. The interface 1140 can be used to transmit data to or receive data from a communication network. Interface 1140 can be a wired or wireless interface. In an example, interface 1140 can include an antenna and/or a wired and/or wireless transceiver. Although not shown in the drawings, the electronic system 1100 may be an operational memory for improving the operation of the controller 1110, and may further include a high speed dynamic access memory (DRAM) or a static access memory (SRAM). . Any of the semiconductor devices according to the above-described embodiments of the inventive concept may be disposed in the memory device 1130 and/or the controller 1110 and/or the I/O device 1120.

The electronic system 1100 can be applied to almost all types of electronic products capable of transmitting or receiving information in a wireless environment, such as a personal digital assistant (PDA), a portable computer, a web tablet, a wireless telephone, a mobile phone, Digital music player and / or memory card.

49 and 50 illustrate an example of a semiconductor system to which a semiconductor device can be applied, in accordance with some embodiments of the inventive concept. FIG. 49 illustrates a tablet personal computer (PC), and FIG. 50 illustrates a notebook computer. According to some embodiments of the inventive concept At least one of the semiconductor devices can be used in a tablet personal computer, a notebook computer, or the like. Semiconductor devices in accordance with some embodiments of the inventive concepts as described herein are also applicable to various integrated circuit devices other than those described herein.

While the present invention has been particularly shown and described with reference to the exemplary embodiments of the embodiments The spirit and scope of the inventive concept. Therefore, the present embodiments are to be considered in all respects

Claims (20)

A semiconductor device comprising: a field insulating layer on a top surface of a substrate, wherein the field insulating layer includes a trench defined therein in a first direction; and a fin active pattern extending from a top surface of the substrate And passing through the trench defined in the field insulating layer, the fin active pattern including a first lower pattern and a first upper pattern, the first lower pattern contacting the substrate, and the An upper pattern contacting the first lower pattern, and the first upper pattern is more convex from the substrate than the field insulating layer, the first upper pattern comprising different from the first lower a lattice-modifying material of the partial pattern, and the fin active pattern includes a first fin portion and a second fin portion, the second fin portion being on both sides of the first fin portion in the first direction The first lower pattern includes a semiconductor material; and a first gate electrode intersecting the fin active pattern and extending in a second direction different from the first direction. The semiconductor device of claim 1, further comprising a first source region and a first drain region, wherein the first source region and the first drain region comprise an impurity region and a first epitaxial layer, Wherein the impurity region is in the second fin portion and on both sides of the first gate electrode, and the first epitaxial layer includes the lattice modification material. The semiconductor device of claim 2, wherein the first epitaxial layer is formed on sidewalls and a top surface of the second fin portion of the first upper pattern, and wherein the first Lei A seed layer is in contact with the field insulating layer. The semiconductor device of claim 2, wherein the first epitaxial layer is formed on sidewalls and a top surface of the second fin portion of the first upper pattern without the field insulating layer contact. The semiconductor device of claim 4, further comprising: a first gate spacer on the sidewall of the first gate electrode; and a first fin spacer in the first upper pattern a sidewall of a portion of the second fin portion and in contact with the first epitaxial layer and the first gate spacer. The semiconductor device of claim 1, wherein the semiconductor device comprises an n-channel metal oxide semiconductor (NMOS), wherein the lattice modification material comprises carbon, and wherein the first upper pattern comprises carbonization矽 (SiC). The semiconductor device of claim 6, further comprising a first source region and a first drain region, wherein the first source region and the first drain region comprise an impurity region and a first epitaxial layer, Wherein the impurity region is in the second fin portion and on both sides of the first gate electrode, the first epitaxial layer includes the lattice modification material, wherein the first upper pattern The carbon concentration does not exceed the carbon concentration in the first epitaxial layer. The semiconductor device of claim 7, wherein the carbon concentration in the first upper pattern is in a range from about 0.5% to about 1.5%, and wherein the carbon concentration in the first epitaxial layer It is in the range of about 0.5% to about 3.0%. The semiconductor device of claim 1, wherein the semiconductor device comprises a p-type channel metal oxide semiconductor (PMOS), wherein the lattice modification material comprises germanium, and wherein the first upper pattern comprises germanium锗 (SiGe). The semiconductor device of claim 9, further comprising a first source region and a first drain region, wherein the first source region and the first drain region comprise an impurity region And a first epitaxial layer in the second fin portion and on both sides of the first gate electrode, the first epitaxial layer comprising the lattice modifying material, wherein The concentration of germanium in the first upper pattern does not exceed the concentration of germanium in the first epitaxial layer. The semiconductor device of claim 10, wherein a concentration of germanium in the first upper pattern is in a range from about 50% to about 70%, and wherein germanium concentration in the first epitaxial layer It is in the range of about 50% to about 90%. The semiconductor device of claim 1, wherein a top surface of the second fin portion is more recessed than a top surface of the first fin portion with respect to the substrate. A semiconductor device comprising: a field insulating layer on a top surface of a substrate, and wherein the field insulating layer includes a trench defined therein in a first direction; a fin active pattern extending from a top surface of the substrate and Passing through the trench defined in the field insulating layer, the fin active pattern includes a first lower pattern and a first upper pattern, the first lower pattern contacting the substrate, and the first The upper pattern contacts the first lower pattern, and the first upper pattern is more convex from the substrate than the field insulating layer, the first upper pattern comprising a different from the first lower portion a patterned lattice modifying material, and the fin active pattern includes a first fin portion and a second fin portion, the second fin portion being on both sides of the first fin portion in the first direction; And a first gate electrode intersecting the fin active pattern and extending in a second direction different from the first direction, wherein the fin active pattern includes a first fin active pattern, and Wherein the lattice modifying material comprises a first lattice modifying material, the semiconductor device further comprising: a second fin active pattern extending from a top surface of the substrate and passing through the field insulating layer a trench, the second fin active pattern includes a second lower pattern and a second upper pattern, the second lower pattern contacts the substrate, and the second upper pattern contacts the second lower pattern, and In the field insulating layer, the second upper pattern is more convex from the substrate, the second upper pattern includes a second lattice modifying material different from the second lower pattern, and the second fin The active pattern includes a third fin portion and a fourth fin portion on the two sides of the third fin portion in the first direction; and a second gate electrode, and the second The fin active patterns intersect and extend in the second direction. The semiconductor device of claim 13, further comprising: a first source region and a first drain region, wherein the first source region and the first drain region comprise an impurity region and a first epitaxial layer The impurity region is in the second fin portion and on both sides of the first gate electrode, the first epitaxial layer includes the first lattice modification material; and the second source region and a second drain region, the second source region and the second drain region including an impurity region and a second epitaxial layer, the impurity region being in the fourth fin portion and at the second gate electrode On both sides, the second epitaxial layer comprises the second lattice modifying material. The semiconductor device according to claim 14, wherein the first lattice modifying material and the second lattice modifying material are the same material. The semiconductor device of claim 14, wherein the first lattice modification material comprises carbon, and the second lattice modification material comprises ruthenium. The semiconductor device of claim 14, further comprising a dummy gate electrode on the field insulating layer and between the first gate electrode and the second gate electrode in the second direction extend. The semiconductor device of claim 14, further comprising an oxide pattern formed on the substrate between the first fin active pattern and the second fin active pattern. The semiconductor device of claim 18, further comprising a dummy gate electrode on the oxide pattern, wherein the dummy gate electrode is between the first gate electrode and the second gate electrode Extending in the second direction. The semiconductor device of claim 18, further comprising a first dummy gate electrode and a second dummy gate electrode at least partially on the oxide pattern, wherein the first dummy gate electrode and the second A dummy gate electrode is spaced apart in the first direction between the first gate electrode and the second gate electrode and extends in the second direction.