KR102388364B1 - Semiconductor device - Google Patents

Abstract

A semiconductor device is provided. The semiconductor device includes a substrate including first and second regions, first and second fin-shaped patterns formed in the first region, protruding from the substrate, and a first convex polygon on the first fin-shaped pattern; , the first convex polygon is formed as a second convex polygon on a first epitaxial pattern including a first interior angle and a second fin-shaped pattern, wherein the convex polygon includes a second interior angle equal to the first interior angle, , a second epitaxial pattern spaced apart from the first epitaxial pattern, third and fourth fin-shaped patterns formed in the second region and protruding from the substrate, and a third convex polygon on the third fin-shaped pattern and the third convex polygon is formed as a fourth convex polygon on a third epitaxial pattern including a third interior angle and a fourth fin-shaped pattern, wherein the fourth convex polygon is a fourth interior angle different from the third interior angle and a fourth epitaxial pattern in contact with the third epitaxial pattern.

Description

semiconductor device

The present invention relates to a semiconductor device.

As one of the scaling techniques for increasing the density of a semiconductor device, a multi-gate transistor (multi-gate transistor) in which a fin or nanowire-shaped silicon body is formed on a substrate and a gate is formed on the surface of the silicon body gate transistor) has been proposed.

Since such a multi-gate transistor uses a three-dimensional channel, it is easy to scale. In addition, the current control capability can be improved without increasing the gate length of the multi-gate transistor. In addition, it is possible to effectively suppress a short channel effect (SCE) in which the potential of the channel region is affected by the drain voltage.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having high integration and low contact resistance by merging sources/drains with each other only in some of a plurality of regions.

The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

A semiconductor device according to some embodiments of the present invention provides a substrate including first and second regions, first and second fin-shaped patterns formed in the first region and protruding from the substrate; A first convex polygon is formed on the first fin-shaped pattern, the first convex polygon is formed in a first epitaxial pattern including a first interior angle, and a second convex polygon is formed on the second fin-shaped pattern, the convex polygon The polygon includes a second inner angle equal to the first inner angle, a second epitaxial pattern spaced apart from the first epitaxial pattern, and third and fourth fin-shaped patterns formed in the second region and protruding from the substrate , is formed in a third convex polygon on the third fin-shaped pattern, wherein the third convex polygon is formed in a third epitaxial pattern including a third interior angle and a fourth convex polygon on the fourth fin-shaped pattern, wherein The fourth convex polygon includes a fourth interior angle different from the third interior angle, and includes a fourth epitaxial pattern in contact with the third epitaxial pattern.

The first and second convex polygons may be pentagons.

The first and second convex polygons may be symmetrical.

Heights of upper surfaces of the first and second fin-shaped patterns may be lower than heights of upper surfaces of the third and fourth fin-shaped patterns.

Widths of upper surfaces of the first and second fin-shaped patterns may be wider than widths of upper surfaces of the third and fourth fin-shaped patterns.

Here, a fifth fin formed in the first region, formed on one side of the first and second fin-shaped patterns, inclined in a direction away from the first and second fin-shaped patterns, and formed in the second region and a sixth fin formed on one side of the third and fourth fin-shaped patterns and inclined in a direction away from the third and fourth fin-shaped patterns.

Here, the substrate may further include a first trench defining the first and second regions.

It further includes a first shallow trench formed between the first and second fin-shaped patterns and a second shallow trench formed between the third and fourth fin-shaped patterns, wherein the depth of the first trench is between the first and fourth fin-shaped patterns. It may be deeper than or equal to the second shallow trench.

The heights of the lowermost portions of the third and fourth epitaxial patterns may be lower than the heights of upper surfaces of the third and fourth fin-shaped patterns.

The lower surfaces of the third and fourth epitaxial patterns are connected to the lower surfaces of the third and fourth fin-shaped patterns, the lower surfaces of which have a lower height, and the lower surfaces, and the upper surfaces of the third and fourth fin-shaped patterns are connected to the lower surfaces. It may include a rising part whose height increases as the distance from it increases.

The lower surfaces of the third and fourth epitaxial patterns include first and second protruding points where the lowering portion and the rising portion meet on both sides of the third and fourth epitaxial patterns, respectively, the first protruding point and A distance between the third and fourth epitaxial patterns and a distance between the second protrusion point and the third and fourth epitaxial patterns may be different from each other.

Here, the first to fourth fin-shaped patterns may further include a liner that is conformally formed on the side surface.

Here, a first interlayer insulating film formed on the side surfaces of the first to fourth fin-shaped patterns, and a second interlayer insulating film formed on the first interlayer insulating film on the side surfaces of the third and fourth fin-shaped patterns. can

The first interlayer insulating layer may include an oxide layer, and the second interlayer insulating layer may include a nitride layer.

A third interlayer insulating layer formed on the second interlayer insulating layer may be further included on side surfaces of the first and second fin-shaped patterns, and a thickness of the third interlayer insulating layer may be smaller than a thickness of the second interlayer insulating layer.

A semiconductor device according to some embodiments of the present invention for solving the above problems is a substrate including a first region, a second region, and a first trench defining the first and second regions, wherein the first trenches are mutually A substrate comprising opposing first and second side surfaces, wherein the first side is in contact with the first area, and the second side is in contact with the second area, and in the first area, protrudes from the substrate; A first fin-shaped pattern in contact with a first side and inclined toward the first side, a second fin-shaped pattern protruding from the substrate in the first region and positioned farther from the first trench than the first fin-shaped pattern; In region 2, a third fin-shaped pattern protruding from the substrate, in contact with the second side surface, inclined toward the second side surface, protruding from the substrate in the second region, and the first trench than the third fin-shaped pattern A fourth fin-shaped pattern located far from the first and second epitaxial patterns respectively formed on the first and second fin-shaped patterns, wherein lower surfaces of the first and second epitaxial patterns are formed at a first height first and second epitaxial patterns and third and fourth epitaxial patterns respectively formed on the third and fourth fin-shaped patterns, wherein lower surfaces of the third and fourth epitaxial patterns are higher than the first height and third and fourth epitaxial patterns formed at the second height.

Here, a first shallow trench formed between the first and second fin-shaped patterns and a second shallow trench formed between the third and fourth fin-shaped patterns are further included, wherein the width of the first trench is equal to the width of the first trench. It may be wider than the width of the first and second shallow trenches.

Here, the interlayer insulating layer may further include an interlayer insulating layer filling a portion of the first trench, and the interlayer insulating layer may have a tensile stress characteristic.

Here, an air gap formed between the third and fourth epitaxial patterns may be further included.

A lower surface of the air gap may be an interlayer insulating layer.

The first and second epitaxial patterns include a first lower region and a first upper region formed on the first lower region, and the width of the first lower region increases as the height increases, 1 The upper region may have a narrower width as the height increases.

The first upper region may include a first outer surface and a second outer surface that are symmetrical to each other, and a normal direction of the first outer surface may be the same in the first and second epitaxial patterns.

The third and fourth epitaxial patterns include a second lower region and a second upper region formed on the second lower region, and the second lower region increases in width as the height increases, 2 The upper region may become narrower as the height increases.

The second upper region may include a third outer surface and a fourth outer surface that are symmetrical to each other, and a normal direction of the third outer surface may be different from each other in the third and fourth epitaxial patterns.

A semiconductor device according to some embodiments of the present invention for solving the above problems is a substrate including a first region, a second region, and a first trench defining the first and second regions, wherein the first trenches are mutually A substrate comprising opposing first and second side surfaces, wherein the first side is in contact with the first area, and the second side is in contact with the second area, a first fin-type structure formed in the first area, A first fin-shaped structure including first and second fin-shaped patterns protruding from the substrate, and first and second epitaxial patterns respectively formed on the first and second fin-shaped patterns and spaced apart from each other; A second fin-shaped structure formed in the region, the third and fourth fin-shaped patterns protruding from the substrate, and third and fourth epitaxial patterns respectively formed on the third and fourth fin-shaped patterns and contacting each other; and a second fin-shaped structure including an air gap formed between the third and fourth fin-shaped patterns and the third and fourth epitaxial patterns.

Here, the first to fourth fin-shaped patterns extend in a first direction, are spaced apart from each other in a second direction intersecting the first direction, and the first to fourth fin-shaped patterns extend in the second direction on the first and second fin-shaped patterns. A first gate electrode and a second gate electrode extending in the second direction on the third and fourth fin-shaped patterns may be further included.

The first and second epitaxial patterns may include SiGe, and the third and fourth epitaxial patterns may include Si.

The first fin-type structure may be a PMOS, and the second fin-type structure may be an NMOS.

Here, a fifth fin-shaped pattern formed on one side of the fourth fin-shaped pattern, a fifth epitaxial pattern formed on the fifth fin-shaped pattern, and the fourth and fifth epitaxial patterns are interposed between the fourth and fifth epitaxial patterns 5 It may further include an interlayer insulating film spaced apart from each other epitaxial patterns.

A semiconductor device according to some embodiments of the present invention provides a first fin-shaped pattern having a first height and a second fin-shaped pattern having a second height higher than the first height, wherein the second fin-shaped pattern includes a lower portion and a lower portion of the semiconductor device. , a second fin-shaped pattern including an upper portion narrower in width than the lower portion, and a step defining the lower portion and upper portion, a first epi formed on the first fin-shaped pattern and not overlapping a side surface of the first fin-shaped pattern a taxial pattern and a second epitaxial pattern formed on the second fin-shaped pattern and overlapping a side surface of the second fin-shaped pattern.

A width of a surface contacting the first fin-shaped pattern and the first epitaxial pattern may be wider than a width of a surface contacting the second fin-shaped pattern and the second epitaxial pattern.

A slope of a lower side surface of the second fin-shaped pattern may be greater than a slope of an upper side surface of the second fin-shaped pattern.

Here, it may further include a first contact formed on the first epitaxial pattern and a second contact formed on the second epitaxial pattern.

The first fin-shaped pattern and the first epitaxial pattern may be plural, the second fin-shaped pattern and the second epitaxial pattern may be plural, and at least some of the second epitaxial patterns may be in contact with each other.

Here, it may further include an air gap formed under the second epitaxial patterns in contact with each other.

1 is a layout diagram illustrating a semiconductor device according to some embodiments of the present invention.
FIG. 2 is a cross-sectional view taken along line A - A' of FIG. 1 .
FIG. 3 is a cross-sectional view taken along line B - B' of FIG. 1 .
4 is a cross-sectional view taken along line C - C' of FIG. 1 .
FIG. 5 is an enlarged cross-sectional view of a second fin-shaped pattern and a second epitaxial pattern of FIG. 4 .
FIG. 6 is an enlarged cross-sectional view of a sixth fin-shaped pattern and a sixth epitaxial pattern of FIG. 4 .
7 is a cross-sectional view for explaining a semiconductor device according to some embodiments of the present invention.
8 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present invention.
9 is a cross-sectional view for explaining a semiconductor device according to some embodiments of the present invention.
10 is a cross-sectional view for explaining a semiconductor device according to some embodiments of the present invention.
11 is a cross-sectional view for explaining a semiconductor device according to some embodiments of the present invention.
12 is a cross-sectional view for explaining a semiconductor device according to some embodiments of the present invention.
13 is a block diagram of a SoC system including a semiconductor device according to a method for manufacturing a semiconductor device according to embodiments of the present invention.
14 is a block diagram of an electronic system including a semiconductor device according to a method of manufacturing a semiconductor device according to embodiments of the present invention.

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, and only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention belongs It is provided to fully inform the possessor of the scope of the invention, and the present invention is only defined by the scope of the claims. Relative sizes of layers and regions in the drawings may be exaggerated for clarity of description. Like reference numerals refer to like elements throughout.

When one element is referred to as “connected to” or “coupled to” with another element, it means that it is directly connected or coupled to another element, or with the other element intervening. including all cases. On the other hand, when one element is referred to as “directly connected to” or “directly coupled to” with another element, it indicates that another element is not interposed therebetween.

Like reference numerals refer to like elements throughout. “and/or” includes each and every combination of one or more of the recited items.

Reference to an element or layer “on” or “on” another element or layer includes not only directly on the other element or layer, but also with other layers or other elements intervening. include all On the other hand, reference to an element "directly on" or "directly on" indicates that no intervening element or layer is interposed.

It should be understood that although first, second, etc. are used to describe various elements, components, and/or sections, these elements, components, and/or sections are not limited by these terms. These terms are only used to distinguish one element, component, or sections from another. Accordingly, it goes without saying that the first element, the first element, or the first section mentioned below may be the second element, the second element, or the second section within the spirit of the present invention.

The terminology used herein is for the purpose of describing the embodiments and is not intended to limit the present invention. In this specification, the singular also includes the plural unless specifically stated otherwise in the phrase. As used herein, "comprises" and/or "comprising" refers to the presence of one or more other components, steps, operations and/or elements mentioned. or addition is not excluded.

Unless otherwise defined, all terms (including technical and scientific terms) used herein may be used with the meaning commonly understood by those of ordinary skill in the art to which the present invention belongs. In addition, terms defined in a commonly used dictionary are not to be interpreted ideally or excessively unless clearly defined in particular.

Hereinafter, a semiconductor device according to an exemplary embodiment of the present invention will be described with reference to FIGS. 1 to 6 .

1 is a layout view for explaining a semiconductor device according to some embodiments of the present invention, and FIG. 2 is a cross-sectional view taken along line A - A' of FIG. 1 . FIG. 3 is a cross-sectional view taken along line B - B' of FIG. 1 , and FIG. 4 is a cross-sectional view taken along line C - C' of FIG. 1 . FIG. 5 is an enlarged cross-sectional view of the second fin-shaped pattern and the second epitaxial pattern of FIG. 4 , and FIG. 6 is an enlarged cross-sectional view of the sixth fin-shaped pattern and the sixth epitaxial pattern of FIG. 4 . For convenience of description, the first interlayer insulating layer 20 and the second interlayer insulating layer 30 are not illustrated in FIGS. 5 and 6 .

1 to 6 , the semiconductor device according to some embodiments of the present invention includes a substrate 10 , first to eighth fin-shaped patterns F1 to F8 , and first to sixth shallow trenches ST1 to ST6 . , the first interlayer insulating film 20 , the second interlayer insulating film 30 , the first gate electrode 200 , the second gate electrode 201 , the gate insulating films 130 and 140 , the gate spacers 160 , and the first to The eighth epitaxial patterns E1 to E8 may be included.

The substrate 10 may be, for example, bulk silicon or silicon-on-insulator (SOI). Alternatively, the substrate 10 may be a silicon substrate, or may include other materials such as silicon germanium, indium antimonide, lead tellurium, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide. . Alternatively, the substrate 10 may have an epitaxial layer formed on the base substrate.

The substrate 10 may include a first region (I) and a second region (II). The first region (I) and the second region (II) may be adjacent to each other or spaced apart from each other. Accordingly, the first to fourth fin-shaped patterns F1 to F4 of the first region I and the fifth to eighth fin-shaped patterns F5 to F8 of the second region II may extend in different directions. . However, for convenience of description, the first to fourth fin-shaped patterns F1 to F4 of the first region (I) and the fifth to eighth fin-shaped patterns F5 to F8 of the second region (II) are in the same direction. described as being extended to

Transistors of different conductivity types may be formed in the first region (I) and the second region (II). For example, the first region (I) may be a region in which a PMOS is formed, and the second region (II) may be a region in which an NMOS is formed, but is not limited thereto.

The first region I and the second region II may be defined by a first trench T1 , a second trench T2 , and a third trench T3 . The first trench T1 may have first and second sides facing each other. The first trench T1 may contact the first region I from the first side surface and may contact the second region II from the second side surface.

The first region I may include a first active region ACT1 , and the second region II may include a second active region ACT2 . The first active area ACT1 and the second active area ACT2 may be adjacent to each other or may be spaced apart from each other.

The second trench T2 may be in contact with the first region I. That is, the first region I may be positioned between the first trench T1 and the second trench T2 . The third trench T3 may be in contact with the second region II. That is, the second region II may be positioned between the first trench T1 and the second trench T2 .

Referring to FIG. 1 , the first to eighth fin-shaped patterns F1 to F8 may extend long in the first direction (X). Although the first to eighth fin-shaped patterns F1 to F8 are illustrated in a rectangular shape in FIG. 1 , the present invention is not limited thereto. If the first to eighth fin-shaped patterns F1 to F8 have a rectangular shape, the first to eighth fin-shaped patterns F1 to F8 have a long side extending in the first direction (X) and a second direction (Y). It may include an extended short side. In this case, the second direction Y may be a direction that is not parallel to and intersects with the first direction X.

The first to eighth fin-shaped patterns F1 to F8 may be disposed to be spaced apart from each other in the second direction Y. In this case, the first to eighth fin-shaped patterns F1 to F8 may be disposed to be spaced apart from each other in the second direction Y.

The first to fourth fin-shaped patterns F1 to F4 may be defined by the first to third shallow trenches ST1 to ST3 . Also, the fifth to eighth fin-shaped patterns F5 to F8 may be defined by fourth to sixth shallow trenches ST4 to ST6. That is, in the first region I, the first to fourth fin-shaped patterns F1 to F4 are formed by the first trench T1, the second trench T2, and the first to third shallow trenches ST1 to ST3. In the second region II, the first to fourth fin-shaped patterns F1 to F4 are formed by the first trench T1, the third trench T3, and the fourth to sixth shallow trenches ST4 to ST6. This is defined

The depths of the first to sixth shallow trenches ST1 to ST6 may be less than or equal to the depths of the first to third trenches T1 to T3 . However, the widths of the first to sixth shallow trenches ST1 to ST6 may be narrower than the widths of the first to third trenches T1 to T3 . Accordingly, the volume of the first interlayer insulating film 20 formed in the first to third trenches T1 to T3 is equal to that of the first interlayer insulating film 20 formed in the first to sixth shallow trenches ST1 to ST6. may be larger than the volume.

Specifically, the first fin-shaped pattern F1 and the second fin-shaped pattern F2 may be spaced apart from each other by the first shallow trench ST1 . The second fin-shaped pattern F2 and the third fin-shaped pattern F3 may be spaced apart from each other by the second shallow trench ST2 . The third fin-shaped pattern F3 and the fourth fin-shaped pattern F4 may be spaced apart from each other by the third shallow trench ST3 .

The first shallow trench ST1 may be formed on a side surface of the first fin-shaped pattern F1 facing the second fin-shaped pattern F2 . The second trench T2 may be formed on a side surface that does not face the first shallow trench ST1 based on the first fin-shaped pattern F1 . The third shallow trench ST3 may be formed on a side surface of the third fin-shaped pattern F3 facing the fourth fin-shaped pattern F4 . The first trench T1 may be formed on a side surface of the fourth fin-shaped pattern F4 that does not contact the third shallow trench ST3 .

The fifth fin-shaped pattern F5 and the sixth fin-shaped pattern F6 may be spaced apart from each other by the fourth shallow trench ST4 . The sixth fin-shaped pattern F6 and the seventh fin-shaped pattern F7 may be spaced apart from each other by the fifth shallow trench ST5 . The seventh fin-shaped pattern F7 and the eighth fin-shaped pattern F8 may be spaced apart from each other by the sixth shallow trench ST6 .

The fourth shallow trench ST4 may be formed on a side surface of the fifth fin-shaped pattern F5 facing the sixth fin-shaped pattern F6 . The first trench T1 may be formed on a side surface that does not face the fourth shallow trench ST4 based on the fifth fin-shaped pattern F5 . The sixth shallow trench ST6 may be formed on a side surface of the seventh fin-shaped pattern F7 facing the eighth fin-shaped pattern F8. The third trench T3 may be formed on a side surface of the eighth fin-shaped pattern F8 that does not contact the sixth shallow trench ST6 .

The first to eighth fin-shaped patterns F1 to F8 may be formed by etching a portion of the substrate 10 , or may include an epitaxial layer grown from the substrate 10 . The first to eighth fin-shaped patterns F1 to F8 may include, for example, silicon or germanium, which is an elemental semiconductor material. Also, the first to eighth fin-shaped patterns F1 to F8 may include a compound semiconductor, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor.

For example, taking the group IV-IV compound semiconductor as an example, the first to eighth fin-shaped patterns F1 to F8 may include at least two selected from carbon (C), silicon (Si), germanium (Ge), and tin (Sn). It may be a binary compound including the above, a ternary compound, or a compound in which a group IV element is doped.

Taking the group III-V compound semiconductor as an example, the first to eighth fin-shaped patterns F1 to F8 may include at least one of aluminum (Al), gallium (Ga), and indium (In) as a group III element, and phosphorus as a group V element. (P), arsenic (As), and antimonium (Sb) may be one of a binary compound, a ternary compound, or a quaternary compound formed by bonding.

In the semiconductor device according to the embodiments of the present invention, the first to eighth fin-shaped patterns F1 to F8 will be described as including silicon.

The first interlayer insulating layer 20 may partially fill the first to sixth shallow trenches ST1 to ST6 and the first to third trenches T1 to T3 . The first interlayer insulating layer 20 may surround a portion of side surfaces of the first to eighth fin-shaped patterns F1 to F8.

The first interlayer insulating layer 20 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k material having a dielectric constant lower than that of silicon oxide. The low dielectric constant material is, for example, Flowable Oxide (FOX), Tonen SilaZene (TOSZ), Undoped Silica Glass (USG), Borosilica Glass (BSG), PhosphoSilica Glass (PSG), BoroPhosphoSilica Glass (BPSG), Plasma Enhanced Tetra (PETEOS). Ethyl Ortho Silicate), FSG(Fluoride Silicate Glass), CDO(Carbon Doped silicon Oxide), Xerogel, Aerogel, Amorphous Fluorinated Carbon, OSG(Organo Silicate Glass), Parylene, BCB(bis-benzocyclobutenes), SiLK, polyimide, porous polymeric material or a combination thereof, but is not limited thereto.

The first interlayer insulating layer 20 may have a specific stress characteristic. That is, after being deposited, the first interlayer insulating layer 20 may have a tensile stress characteristic by shrinking its volume by heat treatment. The slope of the first to eighth fin-shaped patterns F1 to F8 according to the volume of the first interlayer insulating layer 20 may be determined by the tensile stress characteristic of the first interlayer insulating layer 20 . That is, when the volumes of the first interlayer insulating layer 20 positioned on both side surfaces are different from each other, the slope of the fin-shaped pattern may increase as the difference between the volumes increases. This is because a shrinkage rate of the first interlayer insulating film 20 having a large volume is smaller than a shrinkage rate of the first interlayer insulating film 20 having a small volume.

Specifically, the external fin-shaped pattern, that is, the first fin-shaped pattern F1, the fourth fin-shaped pattern F4, the fifth fin-shaped pattern F5, and the eighth fin-shaped pattern F8 is formed in the first trench T1 and the second fin-shaped pattern F8, respectively. It may be inclined in the direction of the trench T2 and the third trench T3 .

That is, the first fin-shaped pattern F1 is inclined in the direction of the second trench T2, the fourth fin-shaped pattern F4 and the fifth fin-shaped pattern F5 are inclined in the direction of the first trench T1, and the eighth fin-shaped pattern F4 and F5 are inclined in the direction of the first trench T1. The fin-shaped pattern F8 may be inclined in the direction of the third trench T3 .

That is, the standing angle of the first fin-shaped pattern F1 in the direction of the second trench T2 is the first angle θ1, and the first trench T1 of the fourth fin-shaped pattern F4 and the fifth fin-shaped pattern F5. ) direction is a second angle θ2 and a third angle θ3, respectively, and the standing angle in the third trench T3 direction of the eighth fin-shaped pattern F8 is a fourth angle θ4. The first to fourth angles θ1 to θ4 may be acute angles. That is, the first fin-shaped pattern F1 , the fourth fin-shaped pattern F4 , the fifth fin-shaped pattern F5 , and the eighth fin-shaped pattern F8 may be inclined.

The first gate electrode 200 and the second gate electrode 201 may extend in the second direction. The first gate electrode 200 may cross the first to fourth fin-shaped patterns F1 to F4, respectively. That is, the first gate electrode 200 may include portions overlapping the first to fourth fin-shaped patterns F1 to F4 spaced apart from each other, respectively. The first to fourth fin-shaped patterns F1 to F4 may each include a portion overlapping the first gate electrode 200 and a portion not overlapping the first gate electrode 200 .

The second gate electrode 201 may cross the fifth to eighth fin-shaped patterns F5 to F8, respectively. That is, the second gate electrode 201 may include portions overlapping the fifth to eighth fin-shaped patterns F5 to F8 spaced apart from each other, respectively. The fifth to eighth fin-shaped patterns F5 to F8 may each include a portion overlapping the second gate electrode 201 and a portion not overlapping the second gate electrode 201 .

Specifically, the first fin-shaped pattern F1 includes a first portion F1-1 overlapping the first gate electrode 200 and a second portion F1-2 not overlapping the first gate electrode 200 . may include The second portions F1 - 2 of the first fin-shaped pattern F1 may be disposed on both sides in the first direction X with the first portion F1-1 of the first fin-shaped pattern F1 as a center. . The second to fourth fin-shaped patterns F2 to F4 may overlap the first gate electrode 200 like the first fin-shaped pattern F1 . The fifth to eighth fin-shaped patterns F5 to F8 may also overlap the second gate electrode 201 similarly to the relationship between the first fin-shaped pattern F1 and the first gate electrode 200 .

2 and 3 , the first gate electrode 200 may include a first work function metal 210 and a first fill metal 220 . The first work function metal 210 controls the work function, and the first fill metal 220 serves to fill a space formed by the first work function metal 210 . The first workfunction metal 210 may be, for example, an N-type workfunction metal, a P-type workfunction metal, or a combination thereof.

In some embodiments of the present invention, since the first region I may be a PMOS region, the first workfunction metal 210 may be a combination of an N-type workfunction metal and a P-type workfunction metal. For example, the first work function metal 210 may include, for example, at least one of TiN, WN, TiAl, TiAlN, TaN, TiC, TaC, TaCN, TaSiN, or a combination thereof, but is not limited thereto. it is not In addition, the first fill metal 220 may include, for example, at least one of W, Al, Cu, Co, Ti, Ta, poly-Si, SiGe, or a metal alloy, but is not limited thereto.

The second gate electrode 201 may include a second work function metal 211 and a second fill metal 221 . The second work function metal 211 controls the work function, and the second fill metal 221 serves to fill the space formed by the second work function metal 211 . The second workfunction metal 211 may be, for example, an N-type workfunction metal, a P-type workfunction metal, or a combination thereof.

In some embodiments of the present invention, since the second region II may be an NMOS region, the second workfunction metal 211 may be an N-type workfunction metal. For example, the second workfunction metal 211 may include, for example, at least one of TiN, WN, TiAl, TiAlN, TaN, TiC, TaC, TaCN, TaSiN, or a combination thereof, but is not limited thereto. it is not In addition, the second fill metal 221 may include, for example, at least one of W, Al, Cu, Co, Ti, Ta, poly-Si, SiGe, or a metal alloy, but is not limited thereto.

The first gate electrode 200 and the second gate electrode 201 may be formed through, for example, a replacement process or a gate last process), but are limited thereto. not.

The gate insulating layers 130 and 140 are formed between the first to eighth fin-shaped patterns F1 to F8 and the first and second gate electrodes 200 and 201 , and between the first interlayer insulating layer 20 and the first and second gate electrodes. It can be formed between (200, 201). The gate insulating layers 130 and 140 may include an interface layer 130 and a high-k layer 140 .

The interface layer 130 may be formed by oxidizing a portion of the first to eighth fin-shaped patterns F1 to F8. The interface layer 130 may be formed along the profile of the first to eighth fin-shaped patterns F1 to F8 protruding above the upper surface of the first interlayer insulating layer 20 . When the first to eighth fin-shaped patterns F1 to F8 are silicon fin-shaped patterns including silicon, the interface layer 130 may include a silicon oxide film.

In FIG. 3 , the interfacial layer 130 is not formed along the top surface of the first interlayer insulating layer 20 , but is not limited thereto. Depending on the method of forming the interfacial layer 130 , the interfacial layer 130 may be formed along the top surface of the first interlayer insulating layer 20 .

Alternatively, even when the first interlayer insulating layer 20 includes silicon oxide, when the physical properties of the silicon oxide included in the first interlayer insulating layer 20 and the silicon oxide layer included in the interface layer 130 are different from each other, the interface The layer 130 may be formed along the top surface of the first interlayer insulating layer 20 .

The high-k layer 140 may be formed between the interface layer 130 and the first and second gate electrodes 200 and 201 . It may be formed along the profile of the first to eighth fin-shaped patterns F1 to F8 protruding above the upper surface of the first interlayer insulating layer 20 . Also, the high-k layer 140 may be formed between the first and second gate electrodes 200 and 201 and the first interlayer insulating layer 20 .

The high-k layer 140 may include a high-k material having a higher dielectric constant than that of the silicon oxide layer. The high-k film 140 may include, for example, silicon oxynitride, silicon nitride, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate. However, the present invention is not limited thereto.

The gate spacer 160 may be disposed on sidewalls of the first and second gate electrodes 200 and 201 extending in the second direction Y. The gate spacer 160 may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO ₂ ), silicon oxycarbonitride (SiOCN), and combinations thereof.

Although the gate spacer 160 is exemplarily shown as a single layer in the drawings, it may be a multi-spacer in which a plurality of layers are stacked. The shape of the gate spacer 160 and the shape of each of the multiple spacers constituting the gate spacer 160 may be I or L-shaped or a combination thereof depending on a manufacturing process or use.

2 and 4 , first to fourth epitaxial patterns E1 to E4 are formed on both sides of the first gate electrode 200 in the first direction X, and first to fourth fin-shaped patterns F1 . ~F4) can be formed respectively. The first to fourth epitaxial patterns E1 to E4 may be source/drain regions of each transistor on the first to fourth fin-shaped patterns F1 to F4 .

The fifth to eighth epitaxial patterns E5 to E8 may be formed on both sides of the second gate electrode 201 in the first direction X and on the fifth to eighth fin-shaped patterns F5 to F8, respectively. there is. The fifth to eighth epitaxial patterns E5 to E8 may be source/drain regions of each transistor on the fifth to eighth fin-shaped patterns F5 to F8 .

For example, the first epitaxial pattern E1 may be formed on the second portion F1 - 2 of the first fin-shaped pattern F1 . Similarly, the second to eighth epitaxial patterns E2 to E8 may be respectively formed on the second to eighth fin-shaped patterns F2 to F8 .

The first to eighth epitaxial patterns E8 may include an epitaxial layer formed by an epitaxial process. Also, the first to eighth epitaxial patterns E8 may be raised source/drain. Since the first region may be a PMOS region and the second region II may be an NMOS region, the first to fourth epitaxial patterns E1 to E4 may be, for example, SiGe epitaxial layers. The fifth to eighth epitaxial patterns E5 to E8 may be, for example, Si epitaxial layers. That is, the first to fourth epitaxial patterns E1 to E4 of the first region I are SiGe epitaxial layers, and the fifth to eighth epitaxial patterns E5 to E8 of the second region II are It may be a Si epitaxial layer. However, the present invention is not limited thereto.

The first epitaxial pattern E1 may fill the recess F1r formed in the second portion F1 - 2 of the first fin-shaped pattern F1 . Similarly, the second to eighth epitaxial patterns E2 to E8 may fill the recesses of the second to eighth fin-shaped patterns F2 to F8, respectively.

The outer peripheral surfaces of the first to eighth epitaxial patterns E8 may have various shapes. For example, the outer peripheral surface of the first to eighth epitaxial patterns E8 may have at least one of a diamond shape, a circular shape, and a rectangular shape. 3 exemplarily illustrates a diamond shape (or a pentagonal shape or a hexagonal shape).

In the first region (I), since the semiconductor device according to the exemplary embodiment is a PMOS transistor, the first to fourth epitaxial patterns E1 to E4 may include a compressive stress material. For example, the compressive stress material may be a material having a larger lattice constant than Si, for example, SiGe. For example, the compressive stress material may improve the mobility of carriers in the channel region by applying compressive stress to the first to fourth fin-shaped patterns F1 to F4 .

In the second region II, when the semiconductor device according to the embodiment is an NMOS transistor, the fifth to eighth epitaxial patterns E5 to E8 may include a tensile stress material. For example, when the fifth to eighth fin-shaped patterns F5 to F8 are silicon, the fifth to eighth epitaxial patterns E5 to E8 are formed of a material (eg, SiC) having a smaller lattice constant than silicon. may include For example, the tensile stress material may apply tensile stress to the fifth to eighth fin-shaped patterns F5 to F8 to improve carrier mobility in the channel region.

4 and 5 , the first to fourth epitaxial patterns E1 to E4 of the first region I may have a convex polygonal shape. 4 and 5 , the convex polygon may be a pentagon.

The first to fourth epitaxial patterns E1 to E4 may have first to fourth convex polygonal shapes, respectively. In this case, the first to fourth convex polygons may have the same shape as each other. In this case, "the same" does not mean only the shapes that are completely identical to each other, but is a concept including those in which the interior angles of the convex polygons are identical to each other.

Also, each of the first to fourth epitaxial patterns E1 to E4 may be symmetric to each other. In addition, the first to fourth epitaxial patterns E1 to E4 include a lower region and an upper region formed on the lower region, and the lower region increases in width as the height increases, and the upper region includes As the height increases, the width may become narrower.

The upper region may include a first outer surface and a second outer surface that are symmetrical to each other, and a normal direction of the first and second outer surfaces may be the same in the first to fourth epitaxial patterns E1 to E4 .

Referring to FIG. 5 , the first to fourth epitaxial patterns E1 to E4 include five first interior angles a1 to a5 . In this case, for convenience, the second epitaxial pattern E2 will be described as an example.

The first to fourth epitaxial patterns E1 to E4 may have first interior angles a1 to a5 identical to each other. In some embodiments of the present invention, the first interior angles a1 to a5 may mean only three first interior angles a1 to a3 that do not come into contact with the second fin-shaped pattern F2. That is, the three first interior angles a1 to a3 of the second epitaxial pattern E2 inevitably have constant values depending on the crystal direction, but the remaining two first interior angles a4 and a5 have a second fin shape. The angle may vary depending on the recessed surface of the pattern F2.

Since the first region I is a PMOS region, the first to fourth epitaxial patterns E1 to E4 may include SiGe, and epitaxial growth thereof may be performed straight in the crystal direction. Accordingly, the first to fourth epitaxial patterns E1 to E4 may have the same shape.

4 and 6 , the fifth to eighth epitaxial patterns E5 to E8 of the second region II may have a convex polygonal shape. 4 and 6 , the convex polygon may be a pentagon. In this case, the term "convex polygon" does not necessarily mean only a figure having a flat surface other than an interior angle, but includes a shape having a plurality of greatly characterized interior angles, and connecting the plurality of interior angles to a curved surface. That is, as shown in FIG. 6 , the "convex polygon" of the present specification has the second interior angles b1 to b5 largely characterized, and may have other interior angles, and each of the second interior angles b1 to b5 ) may not be flat.

The fifth to eighth epitaxial patterns E5 to E8 may have different shapes. Specifically, the second interior angles b1 to b5 of the fifth to eighth epitaxial patterns E5 to E8 may be different from each other.

Since the second region II is an NMOS region, the fifth to eighth epitaxial patterns E5 to E8 may include Si, and the epitaxial growth thereof differs from the first region I in the crystal direction. may not be performed. Accordingly, the fifth to eighth epitaxial patterns E5 to E8 may have different shapes.

The height of the lowermost portion of the sixth epitaxial pattern E6 may be lower than the height of the upper surface of the sixth fin-shaped pattern F6 . That is, the height of the lowermost portion of the sixth epitaxial pattern E6 may be lower than the second level L2 .

The lower surface of the sixth epitaxial pattern E6 is connected to the descending portion k1 and the descending portion k1, the height of which decreases as the distance from the upper surface of the sixth fin-shaped pattern F6 increases, and the sixth fin-shaped pattern F6. It may include a rising part k2 whose height increases as it goes away from the upper surface of the . The descending part k1 and the rising part k2 may meet each other at the first protrusion point k3 - 1 and the second protrusion point k3 - 2 . The distance D1 from the first protruding point k3-1 to the sixth fin-shaped pattern F6 and the distance D2 from the second protruding point k3-2 to the sixth fin-shaped pattern F6 are different from each other. can

The fifth to eighth epitaxial patterns E5 to E8 include a lower region and an upper region formed on the lower region, and the lower region increases in width as the height increases, and the upper region increases in height. The higher the height, the narrower the width.

In the fifth to eighth epitaxial patterns E5 to E8, the upper region includes a third outer surface and a fourth outer surface that are symmetrical to each other, and a normal direction of the third and fourth outer surfaces is the third and fourth may be different from each other in the epitaxial pattern.

4 to 6 , the first level of the interface where the first to fourth epitaxial patterns E1 to E4 and the first to fourth fin-shaped patterns F1 to F4 meet in the first region I (L1) is lower than the second level L2 of the interface where the fifth to eighth epitaxial patterns E5 to E8 and the fifth to eighth fin-shaped patterns F5 to F8 in the second region (II) meet can That is, lower surfaces of the first to fourth epitaxial patterns E1 to E4 may be lower than lower surfaces of the fifth to eighth epitaxial patterns E5 to E8 .

This is because the recessed depths of the first to fourth fin-shaped patterns F1 to F4 in the first region I are greater. In the first region (I), since the first to fourth epitaxial patterns E1 to E4 have a uniform shape, recesses of the first to third fin-shaped patterns F3 (F1r in FIG. 2 ) Depending on the degree, the total volume of the first to fourth epitaxial patterns E1 to E4 may be determined. That is, the fin-shaped pattern may become narrower as it moves away from the substrate 10 . Accordingly, as the recess (F1r of FIG. 2 ) becomes deeper, the width of the upper surface of the recessed fin-shaped pattern may increase. Since the total volume of the first to fourth epitaxial patterns E1 to E4 is formed according to the crystal direction, it may be determined according to the width of the exposed upper surface of the fin-shaped pattern.

On the other hand, in the second region II, the fifth to eighth epitaxial patterns E5 to E8 have irregular shapes, so that the width of the upper surface of the exposed fin-shaped pattern is increased by the fifth to eighth epitaxial patterns E5. ~E8) does not affect the volume. However, the volume of the fifth to eighth epitaxial patterns E5 to E8 may be determined by how long the fifth to eighth epitaxial patterns E5 to E8 are grown. Accordingly, unlike in the first region (I), it is not necessary to form a deep recess of the fin-shaped pattern in the second region (II). Accordingly, the height of the interface between the fin-shaped pattern and the epitaxial pattern in the first region (I), that is, the first level (L1) is the height of the interface between the fin-shaped pattern and the epitaxial pattern in the second region (II), that is, the second level. It can be lower than (L2).

Since upper surfaces of the fifth to eighth fin-shaped patterns F5 to F8 of the second region II are formed at the second level L2, the first to eighth fin-shaped patterns F5 to F8 of the first region I formed in the first level L1 It may be higher than the upper surfaces of the fourth fin-shaped patterns F1 to F4. Accordingly, the width W2 of the upper surfaces of the fifth to eighth fin-shaped patterns F5 to F8 of the second region II is the upper surface of the first to fourth fin-shaped patterns F1 to F4 of the first region I. may be narrower than the width of

In addition, the fifth to eighth fin-shaped patterns F5 to F8 of the second region II may include a step S on the side surface. The step S of the fifth to eighth fin-shaped patterns F5 to F8 will be described with reference to FIG. 6 , but for convenience, the sixth fin-shaped pattern F6 will be described as an example. Not only the sixth fin-shaped pattern F6 but also the fifth fin-shaped pattern F5 , the seventh fin-shaped pattern and the eighth fin-shaped pattern F8 may include the same level difference S.

The sixth fin-shaped pattern F6 may include a lower portion, an upper portion, and a step S. Specifically, the sixth fin-shaped pattern F6 may be divided into a lower portion and an upper portion by the step S. That is, the lower portion of the sixth fin-shaped pattern F6 may be defined as a portion up to the step S of the sixth fin-shaped pattern F6 protruding from the substrate 10 . Similarly, the upper portion of the sixth fin-shaped pattern F6 may be defined as the uppermost portion of the sixth fin-shaped pattern F6 from the step S. The width W1 of the lower portion of the sixth fin-shaped pattern F6 may be greater than the width W2 of the upper portion of the sixth fin-shaped pattern F6.

"Step" as used herein refers to a point or region at which the slope of the surface decreases and then increases again, or refers to a point or region at which the slope of the surface increases and then decreases again. That is, the “step difference” may mean including a point of inflection of the profile of the surface. In other words, a “step” may be a point or region where the profile of the surface changes from an upward convex curve to a downward convex curve, or a point or region where the surface profile changes from a downward convex curve to an upward convex curve. That is, the "step difference" means a point or area at which the sign of the change amount of the slope of the profile changes.

Accordingly, the step S may be a point or region at which the sign of the change amount of the slope of the side profile of the sixth fin-shaped pattern F6 changes. That is, the step S may be a point or region at which the profile of the side surface of the sixth fin-shaped pattern F6 changes from an upward convex curve to a downward convex curve, or a point or region where the downward convex curve changes into an upwardly convex curve. .

The first to fourth fin-shaped patterns F1 to F4 of the first region I also include a step difference as shown in FIG. 3 , but FIG. 4 is a cross-section in which the first to fourth epitaxial patterns E1 to E4 are formed. The step difference is not seen in In this case, since the recesses (F1r in FIG. 2 ) of the first to fourth fin-shaped patterns F1 to F4 of the first region I are formed deeper, the step may not be visible.

Again, referring to FIG. 4 , the sixth epitaxial pattern E6 and the seventh epitaxial pattern E7 of the second region II may contact each other. That is, the sixth epitaxial pattern E6 and the seventh epitaxial pattern E7 may be merged with each other.

The first to fourth epitaxial patterns E1 to E4 of the first region I may not be in contact with each other but may be spaced apart from each other. In contrast, at least one of the fifth to eighth epitaxial patterns E5 to E8 may contact each other. This is because the width of the epitaxial pattern of the second region (II) grows larger than that of the epitaxial pattern of the first region (I).

As described above, the fifth fin-shaped pattern F5 and the eighth fin-shaped pattern F8 may be inclined in the directions of the first trench T1 and the third trench T3 , respectively. Accordingly, the distance between the fifth fin-shaped pattern F5 and the sixth fin-shaped pattern and the distance between the seventh fin-shaped pattern F7 and the eighth fin-shaped pattern F8 is the sixth fin-shaped pattern F6 and the seventh fin-shaped pattern ( F7) can be greater than the distance between them. Accordingly, the probability that the sixth epitaxial pattern E6 and the seventh epitaxial pattern E7 are in contact with each other is the probability that the fifth epitaxial pattern E5 and the sixth epitaxial pattern E6 are in contact with each other and the seventh epitaxial pattern E6 is in contact with each other. The probability that the taxial pattern E7 and the eighth epitaxial pattern E8 come into contact with each other may be higher. However, the present invention is not limited thereto. In the semiconductor device according to some embodiments of the present disclosure, the fifth epitaxial pattern E5 and the sixth epitaxial pattern E6 or the seventh epitaxial pattern E7 and the eighth epitaxial pattern E8 may contact each other. there is.

In the semiconductor device according to some embodiments of the present invention, as the sixth epitaxial pattern E6 and the seventh epitaxial pattern E7 contact each other in the second region II, an air gap G may be formed. there is.

The air gap G may be formed between the sixth fin-shaped pattern F6 and the seventh fin-shaped pattern F7 . The air gap G may be formed on the first interlayer insulating layer 20 . The air gap G may be covered with the sixth epitaxial pattern E6 and the seventh epitaxial pattern E7 .

In the semiconductor device according to some embodiments of the present invention, the degree of integration may be improved by growing an epitaxial pattern on a device having a very small scale. Furthermore, the semiconductor device according to some embodiments of the present invention selectively generates source/drain merge only in the NMOS region, unlike the PMOS region, thereby lowering the contact resistance of the NMOS region, and increasing the degree of integration in the PMOS region. can keep In addition, the simplification of the process can be achieved by forming these two regions at once.

Hereinafter, semiconductor devices according to some exemplary embodiments will be described with reference to FIGS. 1 to 3 and 7 . Parts overlapping with the above-described embodiments of FIGS. 1 to 6 will be simplified or omitted.

7 is a cross-sectional view for explaining a semiconductor device according to some embodiments of the present invention.

1 to 3 and 7 , the semiconductor device according to some embodiments of the present invention further includes a first residual layer 40 .

The first residual layer 40 may not be formed in the first region (I) but may be formed in the second region (II). The first residual layer 40 may be formed on both sides of the fifth to eighth fin-shaped patterns F5 to F8, respectively. The first residual layer 40 may be formed on the first interlayer insulating layer 20 .

The first residual layer 40 may be formed along a portion of the top surface of the first interlayer insulating layer 20 . The first residual layer 40 may expose a remaining portion of the top surface of the first interlayer insulating layer 20 . The first residual layer 40 may include, for example, a silicon nitride layer. However, the present invention is not limited thereto. The first residual layer 40 may be formed in the forming process of the semiconductor device according to some embodiments of the present invention or may have a remaining film quality that is not completely removed depending on the removal process.

Hereinafter, semiconductor devices according to some exemplary embodiments will be described with reference to FIGS. 1 to 3 and 8 . Parts overlapping with the above-described embodiments of FIGS. 1 to 7 will be simplified or omitted.

8 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present invention.

1 to 3 and 8 , the semiconductor device according to some embodiments of the present invention further includes a second residual layer 45 .

The second residual layer 45 may be formed in the first region (I). The second residual layer 45 may be formed on both sides of the first to fourth fin-shaped patterns F1 to F4, respectively. The second residual layer 45 may be formed on the first interlayer insulating layer 20 .

The second residual layer 45 may be formed along a portion of the top surface of the second interlayer insulating layer 30 . The second residual layer 45 may expose the remaining portion of the top surface of the first interlayer insulating layer 20 . The second residual layer 45 may include the same material as the first residual layer 40 . The second residual layer 45 may include, for example, a silicon nitride layer. However, the present invention is not limited thereto. The second residual layer 45 may be formed in the process of forming a semiconductor device according to some embodiments of the present invention or may have a film quality that remains without being completely removed depending on the removal process.

The thickness of the second residual layer 45 may be thinner than the thickness of the first residual layer 40 . The length of the second residual layer 45 may be thinner than the length of the first residual layer 40 . This is because the upper surfaces of the first to fourth fin-shaped patterns F1 to F4 of the first region (I) were recessed deeper than the upper surfaces of the fifth to eighth fin-shaped patterns F5 to F8 of the second region (II). Because.

Hereinafter, semiconductor devices according to some exemplary embodiments will be described with reference to FIGS. 1 to 3 and 9 . Parts overlapping with the above-described embodiments of FIGS. 1 to 8 will be simplified or omitted.

9 is a cross-sectional view for explaining a semiconductor device according to some embodiments of the present invention.

1 to 3 and 9 , the first to third trenches T1 to T3 of the semiconductor device according to some embodiments of the present invention include a protrusion P.

Lower surfaces of the first to third trenches T1 to T3 of the semiconductor device according to some exemplary embodiments may be formed to be deeper than lower surfaces of the first to sixth shallow trenches ST1 to ST6. That is, the first to third trenches T1 to T3 may be deep trenches.

According to an etching process for forming the deep trench, the protrusion P may be formed in the first to third trenches T1 to T3 . In the first trench T1 , trenches having different depths may be formed on both sides of the protrusion P based on the first trench T1 . In the first trench T1, a side closer to the fourth fin-shaped pattern F4 or the fifth fin-shaped pattern F5 based on the protrusion P has a depth similar to that of the first to sixth shallow trenches ST1 to ST6. In the first trench T1, on the far side to the fourth fin-shaped pattern F4 or the fifth fin-shaped pattern F5 based on the protrusion P, the first to sixth shallow trenches ST1 to ST6 are deeper than can have depth.

The second trench T2 and the third trench T3 also have a depth similar to that of the first to sixth shallow trenches ST1 to ST6 on the side closer to the first fin-shaped pattern F1 and the eighth fin-shaped pattern F8, respectively. and may have a deeper depth than the first to sixth shallow trenches ST1 to ST6 on the far side of each of the first fin-shaped pattern F1 and the eighth fin-shaped pattern F8 based on the protrusion P there is.

Hereinafter, semiconductor devices according to some exemplary embodiments will be described with reference to FIGS. 1 to 3 and 10 . Parts overlapping with the above-described embodiments of FIGS. 1 to 9 will be simplified or omitted.

10 is a cross-sectional view for explaining a semiconductor device according to some embodiments of the present invention.

1 to 3 and 10 , a semiconductor device according to some exemplary embodiments includes a liner 50 .

The liner 50 may be formed on side surfaces of the first to eighth fin-shaped patterns F1 to F8. The liner 50 may be conformally formed along the profile of the side surface of the first to eighth fin-shaped patterns F1 to F8. The liner 50 may be formed between the first to eighth fin-shaped patterns F1 to F8 and the first interlayer insulating layer 20 . The liner 50 may be formed on the upper surface of the substrate 10 as well as the surfaces of the first to eighth fin-shaped patterns F1 to F8 according to the material and manufacturing process thereof.

The liner 50 may be formed of a material that applies a first stress to the channel regions of the first to eighth fin-shaped patterns F1 to F8 . The liner 50 may serve to improve carrier mobility in the channel region by introducing a first stress into the channel region of the first to eighth fin-shaped patterns F1 to F8. In some embodiments of the present invention, in the case of the fifth to eighth fin-shaped patterns F5 to F8 in which the channel region is an N-type channel region, the liner 50 is formed of a material that applies a tensile stress to the channel region. can For example, the liner 50 may include silicon nitride (SiN), silicon oxynitride (SiON), silicon boronitride (SiBN), silicon carbide (SiC), SiC:H, SiCN, SiCN:H, SiOCN, SiOCN:H, SiOC (silicon oxycarbide), SiO2 (silicon dioxide), polysilicon, or a combination thereof. In some embodiments, the liner 50 may have a thickness of about 10-100 Å. Conversely, in the case of the first to fourth fin-shaped patterns F1 to F4 in which the channel region is a P-type channel region, the liner 50 may be made of a material that applies a compressive stress to the channel region.

Hereinafter, semiconductor devices according to some exemplary embodiments will be described with reference to FIGS. 1 to 3 and 11 . Parts overlapping with the above-described embodiments of FIGS. 1 to 10 will be simplified or omitted.

11 is a cross-sectional view for explaining a semiconductor device according to some embodiments of the present invention.

1 to 3 and 11 , the semiconductor device according to some embodiments of the present invention further includes an insulating liner 60 .

The insulating liner 60 may be formed between the liner 50 and the first to eighth fin-shaped patterns F1 to F8 .

The insulating liner 60 may be formed of an oxide film. For example, the insulating liner 60 may be formed of a native oxide film. In some embodiments, the oxide film constituting the insulating liner 60 may be obtained by performing a process of thermally oxidizing the surfaces of the first to eighth fin-shaped patterns F1 to F8 . In some embodiments, insulating liner 60 may have a thickness of about 10-100 Angstroms.

Hereinafter, semiconductor devices according to some exemplary embodiments will be described with reference to FIGS. 1 to 3 and 12 . Parts overlapping with the above-described embodiments of FIGS. 1 to 11 will be simplified or omitted.

12 is a cross-sectional view for explaining a semiconductor device according to some embodiments of the present invention.

1 to 3 and 12 , the semiconductor device according to some embodiments of the present invention further includes first to seventh contacts C1 to C7.

In the first region I, first to fourth contacts C1 to C4 may be formed on first to fourth epitaxial patterns E1 to E4 , respectively. The first to fourth contacts C1 to C4 may be electrically and physically connected to the first to fourth epitaxial patterns E1 to E4 .

In the second region II, the fifth contact C5 and the seventh contact C7 may be formed on the fifth epitaxial pattern E5 and the eighth epitaxial pattern E8, respectively. The fifth contact C5 and the seventh contact C7 may be electrically and physically connected to the fifth epitaxial pattern E5 and the eighth epitaxial pattern E8, respectively.

The sixth contact C6 may be formed on the fifth epitaxial pattern E5 and the sixth epitaxial pattern E6 . The sixth contact C6 may have a wider width than the first to fifth contacts C1 to C5 and the seventh contact C7 . However, the present invention is not limited thereto.

Since the sixth epitaxial pattern E6 and the seventh epitaxial pattern E7 are merged with each other, the sixth contact C6 has the sixth epitaxial pattern E6 and the seventh epitaxial pattern E7. may be formed together. The sixth epitaxial pattern E6 and the seventh epitaxial pattern E7 may be physically and electrically connected to the seventh contact C7 .

13 is a block diagram of an SoC system including a semiconductor device according to a method for manufacturing a semiconductor device according to embodiments of the present invention.

Referring to FIG. 13 , the SoC system 1000 includes an application processor 1001 and a DRAM 1060 .

The application processor 1001 may include a central processing unit 1010 , a multimedia system 1020 , a bus 1030 , a memory system 1040 , and a peripheral circuit 1050 .

The central processing unit 1010 may perform an operation necessary for driving the SoC system 1000 . In some embodiments of the present invention, the central processing unit 1010 may be configured as a multi-core environment including a plurality of cores.

The multimedia system 1020 may be used to perform various multimedia functions in the SoC system 1000 . The multimedia system 1020 may include a 3D engine module, a video codec, a display system, a camera system, a post-processor, and the like. .

The bus 1030 may be used for data communication between the central processing unit 1010 , the multimedia system 1020 , the memory system 1040 , and the peripheral circuit 1050 . In some embodiments of the present invention, such bus 1030 may have a multi-layer structure. Specifically, as an example of the bus 1030 , a multi-layer advanced high-performance bus (AHB) or a multi-layer advanced eXtensible interface (AXI) may be used, but the present invention is not limited thereto.

The memory system 1040 may provide an environment necessary for the application processor 1001 to be connected to an external memory (eg, the DRAM 1060) to operate at a high speed. In some embodiments of the present invention, the memory system 1040 may include a separate controller (eg, a DRAM controller) for controlling an external memory (eg, the DRAM 1060 ).

The peripheral circuit 1050 may provide an environment necessary for the SoC system 1000 to be smoothly connected to an external device (eg, a main board). Accordingly, the peripheral circuit 1050 may include various interfaces that allow an external device connected to the SoC system 1000 to be compatible.

The DRAM 1060 may function as a working memory required for the application processor 1001 to operate. In some embodiments of the present invention, the DRAM 1060 may be disposed outside the application processor 1001 as shown. Specifically, the DRAM 1060 may be packaged with the application processor 1001 in a package on package (PoP) format.

At least one of the components of the SoC system 1000 may include at least one of the semiconductor devices according to the embodiments of the present invention described above.

14 is a block diagram of an electronic system including a semiconductor device according to a method for manufacturing a semiconductor device according to embodiments of the present invention.

Referring to FIG. 14 , an electronic system 1100 according to an embodiment of the present invention includes a controller 1110, an input/output device 1120, I/O, a memory device 1130, a memory device, an interface 1140, and a bus ( 1150, bus). The controller 1110 , the input/output device 1120 , the memory device 1130 , and/or the interface 1140 may be coupled to each other through the bus 1150 . The bus 1150 corresponds to a path through which data is moved.

The controller 1110 may include at least one of a microprocessor, a digital signal processor, a microcontroller, and logic devices capable of performing functions similar thereto. The input/output device 1120 may include a keypad, a keyboard, and a display device. The storage device 1130 may store data and/or instructions. The interface 1140 may perform a function of transmitting data to or receiving data from a communication network. The interface 1140 may be in a wired or wireless form. For example, the interface 1140 may include an antenna or a wired/wireless transceiver.

Although not shown, the electronic system 1100 may further include a high-speed DRAM and/or SRAM as an operational memory for improving the operation of the controller 1110 .

The semiconductor device according to the embodiments of the present invention described above may be provided in the memory device 1130 , or may be provided as a part of the controller 1110 , the input/output device 1120 , I/O, and the like.

The electronic system 1100 includes a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, and a digital music player (digital). music player), a memory card, or any electronic product capable of transmitting and/or receiving information in a wireless environment.

Although embodiments of the present invention have been described with reference to the accompanying drawings, those of ordinary skill in the art to which the present invention pertains can realize that the present invention can be embodied in other specific forms without changing its technical spirit or essential features. you will be able to understand Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

10: substrates F1 to F8: first to eighth fin-shaped patterns
E1 to E8: first to eighth epitaxial patterns

Claims (20)

a substrate comprising first and second regions;
first and second fin-shaped patterns formed in the first region and protruding from the substrate;
a first epitaxial pattern formed in a first convex polygon on the first fin-shaped pattern, wherein the first convex polygon includes a first interior angle;
a second epitaxial pattern formed in a second convex polygon on the second fin-shaped pattern, the convex polygon having a second interior angle equal to the first interior angle, and spaced apart from the first epitaxial pattern;
third and fourth fin-shaped patterns formed in the second region and protruding from the substrate;
a third epitaxial pattern formed in a third convex polygon on the third fin-shaped pattern, wherein the third convex polygon includes a third interior angle; and
a fourth convex polygon is formed on the fourth fin-shaped pattern, the fourth convex polygon includes a fourth interior angle different from the third interior angle, and a fourth epitaxial pattern in contact with the third epitaxial pattern; ,
The third and fourth epitaxial patterns overlap each other in a depth direction. According to claim 1,
A height of upper surfaces of the first and second fin-shaped patterns is lower than a height of upper surfaces of the third and fourth fin-shaped patterns. According to claim 1,
A width of upper surfaces of the first and second fin-shaped patterns is wider than widths of upper surfaces of the third and fourth fin-shaped patterns. According to claim 1,
a fifth fin formed in the first region, formed on one side of the first and second fin-shaped patterns, and inclined in a direction away from the first and second fin-shaped patterns;
and a sixth fin formed in the second region, formed on one side of the third and fourth fin-shaped patterns, and inclined in a direction away from the third and fourth fin-shaped patterns. According to claim 1,
The semiconductor device further comprising a first trench defining the first and second regions on the substrate. 6. The method of claim 5,
a first shallow trench formed between the first and second fin-shaped patterns;
Further comprising a second shallow trench formed between the third and fourth fin-shaped pattern,
A depth of the first trench is equal to or greater than that of the first and second shallow trenches. According to claim 1,
A height of a lowermost portion of the third and fourth epitaxial patterns is lower than a height of an upper surface of the third and fourth fin-shaped patterns. 8. The method of claim 7,
Lower surfaces of the third and fourth epitaxial patterns include lowering portions whose heights are lowered as they move away from the upper surfaces of the third and fourth fin-shaped patterns;
and a rising part connected to the descending part and having a height increasing as the distance from the upper surfaces of the third and fourth fin-shaped patterns increases. According to claim 1,
The semiconductor device further comprising a liner conformally formed on side surfaces of the first to fourth fin-shaped patterns. According to claim 1,
a first field insulating film formed on side surfaces of the first to fourth fin-shaped patterns;
and a second field insulating layer formed on the first field insulating layer on side surfaces of the third and fourth fin-shaped patterns. 11. The method of claim 10,
The first field insulating film includes an oxide film,
The second field insulating layer includes a nitride layer. 11. The method of claim 10,
a third field insulating layer formed on the second field insulating layer on side surfaces of the first and second fin-shaped patterns;
A thickness of the third field insulating layer is smaller than a thickness of the second field insulating layer. A substrate comprising a first region, a second region, and a first trench defining the first and second regions, the first trench including first and second sides opposite to each other, the first side comprising: a substrate in contact with the first region, the second side surface being in contact with the second region;
a first fin-shaped pattern protruding from the substrate in the first region, in contact with the first side surface, and inclined toward the first side surface;
a second fin-shaped pattern protruding from the substrate in the first region and positioned farther from the first trench than the first fin-shaped pattern;
a third fin-shaped pattern protruding from the substrate in the second region, in contact with the second side surface, and inclined toward the second side surface;
a fourth fin-shaped pattern protruding from the substrate in the second region and positioned farther from the first trench than the third fin-shaped pattern;
first and second epitaxial patterns respectively formed on the first and second fin-shaped patterns, wherein lower surfaces of the first and second epitaxial patterns are first and second epitaxial patterns formed at a first height; and
Third and fourth epitaxial patterns respectively formed on the third and fourth fin-shaped patterns, wherein lower surfaces of the third and fourth epitaxial patterns are formed at a second height higher than the first height. a fourth epitaxial pattern;
The third and fourth epitaxial patterns overlap each other in a depth direction. 14. The method of claim 13,
a first shallow trench formed between the first and second fin-shaped patterns;
Further comprising a second shallow trench formed between the third and fourth fin-shaped pattern,
A width of the first trench is wider than a width of the first and second shallow trenches. 15. The method of claim 14,
Further comprising a field insulating film filling a part of the first trench,
The field insulating layer may have a tensile stress characteristic. 14. The method of claim 13,
The semiconductor device further comprising an air gap formed between the third and fourth epitaxial patterns. 14. The method of claim 13,
The first and second epitaxial patterns include a first lower region and a first upper region formed on the first lower region,
The width of the first lower region increases as the height increases,
A semiconductor device in which the width of the first upper region increases as the height increases. 18. The method of claim 17,
The first upper region includes a first outer surface and a second outer surface that are symmetrical to each other,
A normal direction of the first outer surface is the same in the first and second epitaxial patterns. 18. The method of claim 17,
the third and fourth epitaxial patterns include a second lower region and a second upper region formed on the second lower region;
The width of the second lower region increases as the height increases,
The width of the second upper region increases as the height increases. A substrate comprising a first region, a second region, and a first trench defining the first and second regions, the first trench including first and second sides opposite to each other, the first side comprising: a substrate in contact with the first region, the second side surface being in contact with the second region;
A first fin-shaped structure formed in the first region, first and second fin-shaped patterns protruding from the substrate, and first and second epi-types respectively formed on the first and second fin-shaped patterns and spaced apart from each other a first fin-type structure including a taxial pattern; and
A second fin-shaped structure formed in the second region, third and fourth fin-shaped patterns protruding from the substrate, and third and fourth epitaxial formed on the third and fourth fin-shaped patterns to contact each other, respectively a second fin-shaped structure including a pattern and an air gap formed between the third and fourth fin-shaped patterns and the third and fourth epitaxial patterns;
The third and fourth epitaxial patterns overlap each other in a depth direction.

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