CN105047698B

CN105047698B - Semiconductor device with a plurality of transistors

Info

Publication number: CN105047698B
Application number: CN201510136837.3A
Authority: CN
Inventors: 前田茂伸; 权兑勇; 金相秀; 朴在厚
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2014-03-26
Filing date: 2015-03-26
Publication date: 2020-09-22
Anticipated expiration: 2035-03-26
Also published as: KR102236560B1; TWI621267B; KR20150111807A; TW201543678A; CN105047698A

Abstract

The present disclosure provides a semiconductor device. The semiconductor device may include: a field insulating layer on a top surface of the substrate and including a trench extending in a first direction defined therein; a fin active pattern extending from the top surface of the substrate and through the trench defined in the field insulating layer, the fin active pattern including a first lower pattern contacting the substrate and a first upper pattern contacting the first lower pattern and protruding further from the substrate than the field insulating layer, the first upper pattern including a different lattice-changing material than the first lower pattern, the fin active pattern including a first fin portion and second fin portions on both sides of the first fin portion in the first direction; and a first gate electrode crossing the fin-type active pattern and extending in a second direction different from the first direction.

Description

Semiconductor device with a plurality of transistors

Technical Field

Embodiments of the inventive concepts relate to semiconductor devices and methods of fabricating the same.

Background

Multi-gate transistors have been proposed as one of the scaling techniques to increase the density of semiconductor devices. The multi-gate transistor is obtained by forming a fin-shaped or nanowire-shaped multi-channel active pattern (or silicon body) on a substrate and forming a gate on a surface of the multi-channel active pattern.

As the feature size of Metal Oxide Semiconductor (MOS) transistors decreases, the gate and the channel formed under the gate become shorter and shorter in length. The reduced length of the channel increases scattering of charge and reduces mobility of charge in the channel. The reduced mobility of the charges can be an obstacle to improving the saturation current of the transistor.

Accordingly, various studies are being conducted to increase the mobility of charges in a transistor having a reduced channel length.

Disclosure of Invention

Aspects of the inventive concept provide a semiconductor device in which the operational performance of a transistor is improved by using silicon carbide in a channel layer of the transistor. Some embodiments of the inventive concept are directed to a semiconductor device, comprising: a field insulating layer on a top surface of the substrate and including a trench defined therein extending in a first direction; and a fin-type active pattern extending from a top surface of the substrate and through the trench defined in the field insulating layer. The fin-type active pattern includes a first lower pattern contacting the substrate and a first upper pattern contacting the first lower pattern and protruding farther from the substrate than the field insulating layer. The first upper pattern includes a lattice-changing material different from that of the first lower pattern. The fin-type active pattern includes a first fin portion and second fin portions on both sides of the first fin portion in a first direction. The device includes a first gate electrode crossing the fin-type active pattern and extending in a second direction different from the first direction.

Some embodiments include first source and drain regions including impurity regions in the second fin portion and on both sides of the first gate electrode and a first epitaxial layer including a lattice-change material. In some embodiments, the first epitaxial layer is formed on sidewalls and a top surface of the second fin portion of the first upper pattern, and the first epitaxial layer contacts the field insulating layer. Some embodiments provide that the first epitaxial layer is formed on sidewalls and a top surface of the second fin portion of the first upper pattern without contacting the field insulating layer. Some embodiments include: a first gate spacer on a sidewall of the first gate electrode; and a first fin spacer on a portion of a sidewall of the second fin portion of the first upper pattern and contacting the first epitaxial layer and the first gate spacer.

In some embodiments, the semiconductor device includes an n-channel metal oxide semiconductor (NMOS) transistor, the lattice change material includes carbon, and the first upper pattern includes silicon carbide (SiC). Some embodiments include first source and drain regions including impurity regions in the second fin portion and on both sides of the first gate electrode and a first epitaxial layer including a lattice-change material. In some embodiments, the concentration of carbon in the first upper pattern does not exceed the concentration of carbon in the first epitaxial layer. In some embodiments, the concentration of carbon in the first upper pattern is in the range of about 0.5% to about 1.5%, and the concentration of carbon in the first epitaxial layer is in the range of about 0.5% to about 3.0%.

Some embodiments provide that the semiconductor device includes a p-channel metal oxide semiconductor (PMOS) transistor, the lattice-change material includes germanium, and the first upper pattern includes silicon germanium (SiGe). Some embodiments include first source and drain regions including impurity regions in the second fin portion and on both sides of the first gate electrode and a first epitaxial layer including a lattice-change material. Some embodiments provide that a concentration of germanium in the first upper pattern does not exceed a concentration of germanium in the first epitaxial layer. In some embodiments, the concentration of germanium in the first upper pattern is in the range of about 50% to about 70%, and the concentration of germanium in the first epitaxial layer is in the range of about 50% to about 90%.

In some embodiments, a top surface of the second fin portion is recessed more relative to the substrate than a top surface of the first fin portion.

Some embodiments provide that the fin active pattern is a first fin active pattern and the lattice change material comprises a first lattice change material. Some embodiments further include a second fin-type active pattern extending from the top surface of the substrate and through another trench defined in the field insulating layer. The second fin-type active pattern includes a second lower pattern contacting the substrate and a second upper pattern contacting the second lower pattern and protruding farther from the substrate than the field insulating layer. The second upper pattern includes a second lattice change material different from the second lower pattern. The second fin-type active pattern includes third fin portions and fourth fin portions on both sides of the third fin portions in the first direction. Some embodiments include a second gate electrode crossing the second fin-type active pattern and extending in the second direction.

Some embodiments include: first source and drain regions including impurity regions in the second fin portion and on both sides of the first gate electrode and a first epitaxial layer including a lattice-change material; and second source and drain regions including impurity regions in the fourth fin portion and on both sides of the second gate electrode and a second epitaxial layer including a second lattice change material. In some embodiments, the first lattice-changing material and the second lattice-changing material are the same material. Some embodiments provide that the first lattice changing material comprises carbon and the second lattice changing material comprises germanium.

Some embodiments include a dummy gate electrode on the field insulating layer and between the first gate electrode and the second gate electrode and extending in the second direction.

Some embodiments include an oxide pattern formed on the substrate and between the first and second fin-type active patterns. Some embodiments include a dummy gate electrode on the oxide pattern. In some embodiments, the dummy gate electrode extends between the first gate electrode and the second gate electrode and in the second direction.

Some embodiments include first and second dummy gate electrodes at least partially on the oxide pattern. Some embodiments provide that the first and second dummy gate electrodes are spaced apart between the first gate electrode and the second gate electrode in the first direction and extend in the second direction.

However, aspects of the inventive concept are not limited to the one set forth herein. The above and other aspects of the inventive concept will become more apparent to those of ordinary skill in the art to which the inventive concept pertains by referencing the detailed description of the inventive concept given below.

Drawings

The above and other aspects and features of the present inventive concept will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.

Fig. 1 is a perspective view of a semiconductor device according to a first embodiment of the inventive concept.

Fig. 2 is a sectional view taken along line a-a of fig. 1.

Fig. 3 is a sectional view taken along line B-B of fig. 1.

Fig. 4 is a sectional view taken along line C-C of fig. 1.

Fig. 5 and 6 are views of a semiconductor device according to a second embodiment of the inventive concept.

Fig. 7 is a view of a semiconductor device according to a third embodiment of the inventive concept.

Fig. 8 is a view of a semiconductor device according to a fourth embodiment of the inventive concept.

Fig. 9 and 10 are views of a semiconductor device according to a fifth embodiment of the inventive concept.

Fig. 11 is a view of a semiconductor device according to a sixth embodiment of the inventive concept.

Fig. 12 is a view of a semiconductor device according to a seventh embodiment of the inventive concept.

Fig. 13 and 14 are views of a semiconductor device according to an eighth embodiment of the inventive concept.

Fig. 15 is a view of a semiconductor device according to a ninth embodiment of the inventive concept.

Fig. 16A and 16B are a perspective view and a plan view, respectively, of a semiconductor device according to a tenth embodiment of the inventive concept.

Fig. 17 is a partial perspective view of the first and second fin-type active patterns and the field insulating layer shown in fig. 16A.

Fig. 18 is a sectional view taken along line D-D of fig. 16A.

Fig. 19 and 20 are views of a semiconductor device according to an eleventh embodiment of the inventive concept.

Fig. 21 is a cross-sectional view of a semiconductor device according to a twelfth embodiment of the inventive concept.

Fig. 22 and 23 are views of a semiconductor device according to a thirteenth embodiment of the inventive concept.

Fig. 24 is a perspective view of a semiconductor device according to a fourteenth embodiment of the inventive concept.

Fig. 25 is a sectional view taken along lines a-a and E-E of fig. 24.

Fig. 26 and 27 are views of a semiconductor device according to a fifteenth embodiment of the inventive concept.

Fig. 28 is a view of a semiconductor device according to a sixteenth embodiment of the inventive concept.

Fig. 29 is a view of a semiconductor device according to a seventeenth embodiment of the inventive concept.

Fig. 30 and 31 are views of a semiconductor device according to an eighteenth embodiment of the inventive concept.

Fig. 32 is a view of a semiconductor device according to a nineteenth embodiment of the inventive concept.

Fig. 33 is a view of a semiconductor device according to a twentieth embodiment of the inventive concept.

Fig. 34 and 35 are views of a semiconductor device according to a twenty-first embodiment of the inventive concept.

Fig. 36 is a view of a semiconductor device according to a twenty-second embodiment of the inventive concept.

Fig. 37 to 45 are views illustrating operations of methods for manufacturing a semiconductor device according to some embodiments of the inventive concept.

Fig. 46 and 47 are views illustrating operations of methods of manufacturing a semiconductor device according to some embodiments of the inventive concept.

Fig. 48 is a block diagram of an electronic system including a semiconductor device according to some embodiments of the inventive concept.

Fig. 49 and 50 are diagrams illustrating examples of semiconductor systems to which semiconductor devices according to some embodiments of the inventive concepts can be applied.

Detailed Description

The present inventive concept will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the inventive concept are shown. The inventive concept may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art. Like reference numerals refer to like parts throughout the specification. In the drawings, the thickness of layers and regions are exaggerated for clarity.

It will be understood that when an element or layer is referred to as being "connected to" or "coupled to" another element or layer, it can be directly connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. Like reference numerals refer to like elements throughout. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It will also be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, for example, a first element, component, or section discussed below could be termed a second element, component, or section without departing from the teachings of the present inventive concept.

The use of the terms "a" and "an" and "the" and similar referents in the context of describing the inventive concept (especially in the context of the following claims) are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. The terms "comprising," "having," "including," and the like, are to be construed as open-ended terms (i.e., meaning "including, but not limited to,") unless otherwise noted.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concepts belong. It is noted that the use of any and all examples, or exemplary terms, provided herein is intended merely to better illuminate the inventive concept and does not pose a limitation on the scope of the inventive concept unless otherwise specified. Furthermore, unless otherwise defined, all terms defined in the general dictionary should not be excessively interpreted.

A semiconductor device according to a first embodiment of the inventive concept will now be described with reference to fig. 1 to 4.

Fig. 1 is a perspective view of a semiconductor device 1 according to a first embodiment of the inventive concept. Fig. 2 is a sectional view taken along line a-a of fig. 1. Fig. 3 is a sectional view taken along line B-B of fig. 1. Fig. 4 is a sectional view taken along line C-C of fig. 1. For convenience of description, the interlayer insulating film 150 is not shown in fig. 1.

Referring to fig. 1 to 4, a semiconductor device 1 according to the first embodiment may include a substrate 100, a first fin-type active pattern 110, a first gate electrode 120, and a first source/drain region 130.

The substrate 100 may be a bulk silicon substrate and/or a silicon-on-insulator (SOI) substrate. Additionally, the substrate 100 may be a silicon substrate, and/or may be a substrate made of other materials such as silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, and/or gallium antimonide. In some embodiments, the substrate 100 may be composed of a base substrate and an epitaxial layer formed on the base substrate. Embodiments of the inventive concept will be described on the assumption that the substrate 100 is a silicon substrate.

A field insulating layer 105 may be formed on the substrate 100. The field insulating layer 105 may include one of an oxide layer, a nitride layer, an oxynitride layer, and/or a combination thereof.

The first fin-type active pattern 110 may protrude from the substrate 100. The field insulating layer 105 may partially cover sidewalls of the first fin-type active patterns 110. Accordingly, the top surface of the first fin-type active pattern 110 may protrude further upward than the top surface of the field insulating layer 105. That is, the first fin-type active pattern 110 may be defined by the field insulating layer 105.

The first fin-type active pattern 110 includes a first lower pattern 111 and a first upper pattern 112 sequentially stacked on the substrate 100. The first lower pattern 111 protrudes from the substrate 100. The first upper pattern 112 is formed on the first lower pattern 111.

The first upper pattern 112 may be positioned on top of the first fin-type active pattern 110. That is, the top surface of the first fin-type active pattern 110 may be the top surface of the first upper pattern 112.

Since the top surface of the first fin-type active pattern 110 protrudes further upward than the top surface of the field insulating layer 105, at least a portion of the first upper pattern 112 may protrude further upward than the field insulating layer 105.

For example, if the semiconductor device 1 is a transistor, the first upper pattern 112 may serve as a channel region of the transistor.

The first upper pattern 112 is directly connected to the first lower pattern 111. That is, the first upper pattern 112 directly contacts the first lower pattern 111. For example, the first lower pattern 111 may be a substrate on which the first upper pattern 112 is epitaxially grown, and the first upper pattern 112 may be an epitaxial layer formed on the first lower pattern 111.

The first lower pattern 111 is a silicon pattern including silicon. The first upper pattern 112 is a compound semiconductor pattern including a material having a lattice constant different from that of the first lower pattern 111.

The first lower pattern 111 is directly connected to the substrate 100. In addition, since the substrate 100 may be a silicon substrate and the first lower pattern 111 is a silicon pattern, they include the same material. In other words, since the substrate 100 and the first lower pattern 111 include silicon and are directly connected to each other, they may be a unitary structure.

If the semiconductor device 1 according to the first embodiment of the inventive concept is an n-channel metal oxide semiconductor (NMOS) transistor, the first upper pattern 112 may include a material having a smaller lattice constant than silicon (e.g., silicon carbide (SiC)). That is, the first upper pattern 112 may be a silicon carbide pattern.

On the other hand, if the semiconductor device 1 according to the first embodiment of the inventive concept is a p-channel metal oxide semiconductor (PMOS) transistor, the first upper pattern 112 may include a material having a larger lattice constant than silicon (e.g., silicon germanium (SiGe)). That is, the first upper pattern 112 may be a silicon germanium pattern.

In fig. 1, 3 and 4, the contact surfaces of the first upper pattern 112 and the first lower pattern 111 are located in the same plane as the top surface of the field insulating layer 105. That is, the entire sidewall of the first lower pattern 111 contacts the field insulating layer 105, and the entire sidewall of the first upper pattern 112 does not contact the field insulating layer 105. However, the inventive concept is not limited thereto.

The first fin-type active pattern 110 may extend along a first direction X1. The first fin-type active pattern 110 includes a first portion 110a and a second portion 110 b. The second portion 110b of the first fin-type active pattern 110 is disposed at both sides of the first portion 110a of the first fin-type active pattern 110 in the first direction X1.

In the semiconductor device 1 according to the first embodiment of the inventive concept, the top surfaces of the first portion 110a of the first fin-type active pattern 110 and the second portion 110b of the first fin-type active pattern 110 protrude further upward than the top surface of the field insulating layer 105. In addition, the top surfaces of the first portion 110a of the first fin-type active pattern 110 and the second portion 110b of the first fin-type active pattern 110 are located in the same plane.

An interlayer insulating film 150 is formed on the field insulating layer 105. The interlayer insulating film 150 covers the first fin-type active pattern 110, the first source/drain region 130, and the like. The interlayer insulating film 150 includes first trenches 151 crossing the first fin-type active patterns 110 and extending along the second direction Y1.

The interlayer insulating film 150 may include at least one of a low-k material, an oxide layer, a nitride layer, and/or an oxynitride layer. The low-k material may be formed of, but is not limited to, Flowable Oxide (FOX), Tonen SilaZen (TOSZ), Undoped Silica Glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), plasma enhanced orthosilicate (PETEOS), fluorosilicate glass (FSG), High Density Plasma (HDP) oxide, Plasma Enhanced Oxide (PEOX), flow cvd (fcvd), and/or any combination thereof.

The first gate electrode 120 is formed on the first fin-type active pattern 110 and the field insulation layer 105. For example, the first gate electrode 120 is formed on the first portion 110a of the first fin-type active pattern 110.

More specifically, the first gate electrode 120 is formed on sidewalls and a top surface of the first upper pattern 112. The first upper pattern 112 protruding further upward than the top surface of the field insulating layer 105 is covered by the first gate electrode 120.

The first gate electrode 120 is formed in a first trench 151 included in the interlayer insulating film 150. The first gate electrode 120 extends along the second direction Y1 and crosses the first fin-type active pattern 110.

The first gate electrode 120 may include a metal layer. The first gate electrode 120 may include a portion to control a work function and a portion to fill the first trench 151. The first gate electrode 120 may include at least one of W, Al, TiN, TaN, TiC, and/or TaC. In some embodiments, the first gate electrode 120 may be made of, for example, Si and/or SiGe. In the semiconductor device 1 according to the first embodiment of the inventive concept, the first gate electrode 120 may be formed through a replacement process.

A first gate insulating layer 125 may be formed between the first fin-type active pattern 110 and the first gate electrode 120. In addition, a first gate insulating layer 125 may be formed between the interlayer insulating film 150 and the first gate electrode 120.

The first gate insulating layer 125 may be formed along the top surface and sidewalls of the first portion 110a of the first fin-type active pattern 110. The first gate insulating layer 125 may be formed along sidewalls and a top surface of the first upper pattern 112 protruding further upward than the top surface of the field insulating layer 105.

The first gate insulating layer 125 may be disposed between the first gate electrode 120 and the field insulating layer 105. In other words, the first gate insulating layer 125 may be formed along the sidewalls and the bottom surface of the first trench 151.

The first gate insulating layer 125 may include a silicon oxide layer and/or a high-k material having a higher dielectric constant than the silicon oxide layer. For example, the first gate insulating layer 125 may include one or more of hafnium oxide, hafnium silicon oxide, lanthanum aluminum oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and/or lead zinc niobate, but is not limited thereto.

The first gate spacers 140 may be respectively formed on sidewalls of the first gate electrode 120 extending along the second direction Y1. The first gate spacer 140 may include silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO)₂) At least one of silicon oxygen carbonitride (SiOCN), and/or combinations thereof. In the drawings, each first gate spacer 140 is illustrated as a single layer. However, the inventive concept is not limited thereto, and each of the first gate spacers 140 may also have a multi-layer structure.

The first source/drain regions 130 are formed at both sides of the first gate electrode 120, respectively. In other words, each of the first source/drain regions 130 is formed in the second portion 110b of the first fin-type active pattern 110. Each of the first source/drain regions 130 may be formed in the first fin-shaped active pattern 110, that is, in the second portion 110b of the first fin-shaped active pattern 110.

In the drawing, each of the first source/drain regions 130 is formed in the first upper pattern 112 of the second portion 110b of the first fin-type active pattern 110. However, this is only an example for ease of description, and the inventive concept is not limited to this example.

If the semiconductor device 1 according to the first embodiment of the inventive concept is an NMOS transistor, the first source/drain region 130 may include n-type impurities. The n-type impurity may be, but is not limited to, phosphorus (P), arsenic (As), and/or antimony (Sb), among others.

If the semiconductor device 1 according to the first embodiment of the inventive concept is a PMOS transistor, the first source/drain region 130 may include p-type impurities. The p-type impurity may be, but is not limited to, boron (B), among others.

Fig. 5 and 6 are views of a semiconductor device 2 according to a second embodiment of the inventive concept. For simplicity, the present embodiment will be described below, focusing mainly on the differences from the embodiment described above with reference to fig. 1 to 4.

Referring to fig. 5 and 6, the semiconductor device 2 according to the second embodiment further includes a first epitaxial layer 135.

Each first source/drain region 130 includes a first epitaxial layer 135. That is, each of the first source/drain regions 130 may include the first epitaxial layer 135 and an impurity region formed in the second portion 110b of the first fin-type active pattern 110.

The first epitaxial layer 135 is formed on the second portion 110b of the first fin-type active pattern 110. More specifically, in the semiconductor device 2 according to the second embodiment of the inventive concept, the first epitaxial layer 135 is formed on all of the top surface 110b-1 and the sidewalls 110b-2 of the second portion 110b of the first fin-type active pattern 110 protruding further upward than the top surface of the field insulating layer 105. The first epitaxial layer 135 is formed around the entire second portion 110b of the first fin-type active pattern 110 protruding further upward than the top surface of the field insulating layer 105. The first epitaxial layer 135 may contact the field insulating layer 105.

The first epitaxial layer 135 is formed on sidewalls and a top surface of the first upper pattern 112 of the second portion 110b of the first fin-type active pattern 110. The first epitaxial layer 135 is formed around the first upper pattern 112.

Referring to fig. 6, the outer peripheral surface of the first epitaxial layer 135 may have various shapes. For example, the outer peripheral surface of the first epitaxial layer 135 may be at least one of a diamond shape, a circular shape, and a rectangular shape. In fig. 6, an octagonal shape is shown.

If the semiconductor device 2 according to the second embodiment of the inventive concept is an NMOS transistor, the first epitaxial layer 135 may include silicon carbide, like the first upper pattern 112.

Both the first upper pattern 112 and the first epitaxial layer 135 may include silicon carbide. However, the proportion of carbon in the first epitaxial layer 135 may be equal to or greater than the proportion of carbon in the first upper pattern 112.

If the proportion of carbon in the first epitaxial layer 135 is greater than the proportion of carbon in the first upper pattern 112, the lattice constant of the first epitaxial layer 135 is smaller than the lattice constant of the first upper pattern 112. Accordingly, the first epitaxial layer 135 may improve mobility of carriers by applying tensile stress to the channel region of the first fin-type active pattern 110.

If the semiconductor device 2 according to the second embodiment of the inventive concept is a PMOS transistor, the first epitaxial layer 135 may include silicon germanium like the first upper pattern 112.

Both the first upper pattern 112 and the first epitaxial layer 135 may include silicon germanium. However, the ratio of germanium in the first epitaxial layer 135 may be equal to or greater than the ratio of germanium in the first upper pattern 112.

If the proportion of germanium in the first epitaxial layer 135 is greater than the proportion of germanium in the first upper pattern 112, the lattice constant of the first epitaxial layer 135 is greater than the lattice constant of the first upper pattern 112. Accordingly, the first epitaxial layer 135 may improve mobility of carriers by applying a compressive stress to the channel region of the first fin-type active pattern 110.

Semiconductor devices according to third and fourth embodiments of the inventive concept will now be described with reference to fig. 7 and 8. For simplicity, the current embodiment will be described below, focusing mainly on the differences from the embodiment described above with reference to fig. 5 to 6.

Fig. 7 is a view of a semiconductor device 3 according to a third embodiment of the inventive concept. Fig. 8 is a view of a semiconductor device 4 according to a fourth embodiment of the inventive concept.

Referring to fig. 7, in the semiconductor device 3 according to the third embodiment of the inventive concept, the first epitaxial layer 135 does not contact the field insulating layer 105.

The first epitaxial layer 135 is formed on the top surface 110b-1 and the portion of the sidewall 110b-2 of the second portion 110b of the first fin-type active pattern 110 protruding further upward than the top surface of the field insulating layer 105. That is, the first epitaxial layer 135 is formed around the portion of the second portion 110b of the first fin-type active pattern 110 protruding further upward than the top surface of the field insulating layer 105.

Referring to fig. 8, the semiconductor device 4 according to the fourth embodiment of the inventive concept further includes a first fin spacer 145.

The first fin spacer 145 may be formed on a portion of the sidewall 110b-2 of the second portion 110b of the first fin-type active pattern 110 protruding further upward than the top surface of the field insulating layer 105. Accordingly, a portion of the second portion 110b of the first fin-type active pattern 110 protrudes further upward than the first fin spacer 145. That is, a portion of the sidewalls 110b-2 of the second portion 110b of the first fin-type active pattern 110 is not covered by the first fin spacers 145.

Considering fig. 1, since the first fin spacers 145 are formed on the sidewalls 110b-2 of the protruding second portions 110b of the first fin-type active patterns 110, they extend along the first direction X1.

In addition, the first fin spacer 145 is physically connected to the first gate spacer 140 formed on the sidewall of the first gate electrode 120. The first fin spacer 145 and the first gate spacer 140 are connected to each other because they are formed at the same horizontal plane. Here, the term "the same horizontal plane" means that the first fin spacer 145 and the first gate spacer 140 are formed by the same manufacturing process.

The first fin spacer 145 may include SiN, SiON, SiO₂At least one of SiOCN and/or combinations thereof. In the figures, each first fin spacer 145 is shown as a single layer. However, the inventive concept is not limited thereto, and each of the first fin spacers 145 may also have a multi-layer structure.

The first epitaxial layer 135 is formed on the top surface 110b-1 and the sidewalls 110b-2 of the second portion 110b of the first fin-type active pattern 110 protruding further upward than the first fin spacers 145. That is, the first epitaxial layer 135 is formed around the second portion 110b of the first fin-type active pattern 110 protruding further upward than the first fin spacers 145.

The first epitaxial layer 135 may contact the first fin spacer 145.

Fig. 9 and 10 are views of a semiconductor device 5 according to a fifth embodiment of the inventive concept. For simplicity, the present embodiment will be described below, focusing mainly on the differences from the embodiment described above with reference to fig. 1 to 4.

Referring to fig. 9 and 10, in the semiconductor device 5 according to the fifth embodiment of the inventive concept, the top surfaces of the second portions 110b of the first fin-type active patterns 110 are more recessed than the top surfaces of the first portions 110a of the first fin-type active patterns 110. Furthermore, the semiconductor device 5 comprises a first epitaxial layer 135.

More specifically, the top surfaces of the first portion 110a of the first fin-type active pattern 110 and the second portion 110b of the first fin-type active pattern 110 protrude further upward than the top surface of the field insulating layer 105. However, the top surfaces of the first portion 110a of the first fin-type active pattern 110 and the second portion 110b of the first fin-type active pattern 110 do not lie in the same plane.

In the semiconductor device 5 according to the fifth embodiment of the inventive concept, a height from the top surface of the substrate 100 to the top surface of the first portion 110a of the first fin-type active pattern 110 is greater than a height from the top surface of the substrate 100 to the top surface of the second portion 110b of the first fin-type active pattern 110.

In addition, a portion of the sidewall 110b-2 of the second portion 110b of the first fin-type active pattern 110 contacts the field insulating layer 105, but other portions of the sidewall 110b-2 of the second portion 110b of the first fin-type active pattern 110 do not contact the field insulating layer 105.

The first epitaxial layer 135 is formed on the recessed second portion 110b of the first fin-type active pattern 110. More specifically, in the semiconductor device 5 according to the fifth embodiment of the inventive concept, the first epitaxial layer 135 is formed on the top surface 110b-1 of the second portion 110b of the first fin-type active pattern 110 protruding further upward than the top surface of the field insulating layer 105, but is not formed on the sidewall 110b-2 of the second portion 110b of the first fin-type active pattern 110.

If the first epitaxial layer 135 includes, for example, silicon carbide, the proportion of carbon in the first epitaxial layer 135 may be greater than the proportion of carbon in the first upper pattern 112, but is not limited thereto.

If the first epitaxial layer 135 includes, for example, silicon germanium, the proportion of germanium in the first epitaxial layer 135 may be greater than the proportion of germanium in the first upper pattern 112, but is not limited thereto.

Each of the first source/drain regions 130 may include a first epitaxial layer 135 and an impurity region formed in the recessed second portion 110b of the first fin-type active pattern 110.

Semiconductor devices according to sixth and seventh embodiments of the inventive concept will now be described with reference to fig. 11 and 12. For simplicity, the current embodiment will be described below, focusing mainly on differences from the embodiment described above with reference to fig. 9 to 10.

Fig. 11 is a view of a semiconductor device 6 according to a sixth embodiment of the inventive concept. Fig. 12 is a view of a semiconductor device 7 according to a seventh embodiment of the inventive concept.

Referring to fig. 11, in the semiconductor device 6 according to the sixth embodiment of the inventive concept, the first epitaxial layer 135 may contact the field insulating layer 105.

The first epitaxial layer 135 is formed on the sidewalls 110b-2 and the top surface 110b-1 of the second portion 110b of the first fin-type active pattern 110 protruding further upward than the top surface of the field insulating layer 105. The first epitaxial layer 135 is formed around the second portion 110b of the first fin-type active pattern 110 protruding further upward than the top surface of the field insulating layer 105.

Referring to fig. 12, the semiconductor device 7 according to the seventh embodiment of the inventive concept further includes a first fin spacer 145.

The first fin spacers 145 may be formed on sidewalls 110b-2 of the second portion 110b of the first fin-type active pattern 110 protruding further upward than the top surface of the field insulating layer 105. Accordingly, the first fin spacer 145 may contact the first epitaxial layer 135.

In the drawings, the second portion 110b of the first fin-type active pattern 110 does not protrude further upward than the first fin spacer 145, but the inventive concept is not limited thereto.

Fig. 13 and 14 are views of a semiconductor device 8 according to an eighth embodiment of the inventive concept. For simplicity, the current embodiment will be described below, focusing mainly on the differences from the embodiment described above with reference to fig. 9 and 10.

Referring to fig. 13 and 14, in the semiconductor device 8 according to the eighth embodiment of the inventive concept, the entire sidewall 110b-2 of the second portion 110b of the first fin-type active pattern 110 may contact the field insulating layer 105.

The top surface 110b-1 of the second portion 110b of the first fin-type active pattern 110 may not protrude further upward than the top surface of the field insulating layer 105. That is, if the top surface of the field insulating layer 105 is flat as shown in the drawing, the top surface 110b-1 of the second portion 110b of the first fin-type active pattern 110 may be located in the same plane as the top surface of the field insulating layer 105.

Since the entire sidewall 110b-2 of the second portion 110b of the first fin-type active pattern 110 is covered by the field insulation layer 105, the first epitaxial layer 135 is formed on the top surface 110b-1 of the second portion 110b of the first fin-type active pattern 110, and is not formed on the sidewall 110b-2 of the second portion 110b of the first fin-type active pattern 110.

Fig. 15 is a view of a semiconductor device 9 according to a ninth embodiment of the inventive concept. For simplicity, the present embodiment will be described below, focusing mainly on the differences from the embodiment described above with reference to fig. 1 to 4.

Referring to fig. 15, in the semiconductor device 9 according to the ninth embodiment of the inventive concept, the first gate insulating layer 125 is formed along the bottom surface of the first trench 151 and not along the sidewalls of the first trench 151.

The first gate insulating layer 125 is not formed along sidewalls of the first gate spacers 140. The first gate insulating layer 125 does not include a portion located in the same plane as the first gate electrode 120.

Accordingly, the first gate insulating layer 125 is interposed between the first gate electrode 120 and the first fin-type active pattern 110 without between the first gate electrode 120 and the first gate spacer 140.

The first gate insulating layer 125 is not formed through a replacement process. The first gate electrode 120 may not be formed through the replacement process, but the inventive concept is not limited thereto.

A semiconductor device according to a tenth embodiment of the inventive concept will now be described with reference to fig. 16A to 18.

Fig. 16A and 16B are a perspective view and a plan view of a semiconductor device 10 according to a tenth embodiment of the inventive concept, respectively. Fig. 17 is a partial perspective view of the field insulating layer 105 and the first and second fin-type

active patterns

110 and 210 shown in fig. 16A. Fig. 18 is a sectional view taken along line D-D of fig. 16A.

Fig. 18 is a sectional view related to semiconductor devices 2 to 4 according to second to fourth embodiments of the inventive concept. However, the inventive concept is not limited thereto. That is, the sectional view of fig. 18 may also be a sectional view of any one of the semiconductor devices 1 to 9 according to the first to ninth embodiments of the inventive concept.

Referring to fig. 16A through 18, the semiconductor device 10 according to the tenth embodiment of the inventive concept may include a field insulating layer 105, a first fin-type active pattern 110, a second fin-type active pattern 210, a first gate electrode 120, a second gate electrode 220, and a first dummy gate electrode 160.

The first and second fin

active patterns

110 and 210 are formed on the substrate 100. The first and second fin

active patterns

110 and 210 protrude from the substrate 100.

The first and second fin-type

active patterns

110 and 210 extend along a first direction X1. The first fin-type active pattern 110 and the second fin-type active pattern 210 are formed side by side along a longitudinal direction. The first fin-type active pattern 110 and the second fin-type active pattern 210 are formed adjacent to each other.

Since each of the first and second fin-type

active patterns

110 and 210 extends along the first direction X1, it may include a long side extending along the first direction X1 and a short side extending along the second direction Y1.

That is, if the first fin-type active pattern 110 and the second fin-type active pattern 210 extend side by side along the longitudinal direction, it means that a short side of the first fin-type active pattern 110 faces a short side of the second fin-type active pattern 210.

The first fin-type active pattern 110 includes a first lower pattern 111 and a first upper pattern 112 sequentially stacked on the substrate 100. The second fin-type active pattern 210 includes a second lower pattern 211 and a second upper pattern 212 sequentially stacked on the substrate 100.

In addition, a top surface of the first fin-type active pattern 110 may be a top surface of the first upper pattern 112, and a top surface of the second fin-type active pattern 210 may be a top surface of the second upper pattern 212.

Like the first fin-type active pattern 110, the second upper pattern 212 is directly connected to the second lower pattern 211. In addition, the second lower pattern 211 is directly connected to the substrate 100.

Like the first lower pattern 111, the second lower pattern 211 is a silicon pattern including silicon. The second upper pattern 212 may be a silicon carbide pattern including silicon carbide or a silicon germanium pattern including silicon germanium.

The first upper pattern 112 and the second upper pattern 212 may include the same material. That is, the first and second

upper patterns

112 and 212 may be, but are not limited to, a silicon carbide pattern or a silicon germanium pattern.

A field insulating layer 105 is formed on the substrate 100. The field insulating layer 105 is formed around the first and second fin-type

active patterns

110 and 210. Accordingly, the first and second fin-type

active patterns

110 and 210 may be defined by the field insulating layer 105.

The field insulating layer 105 includes a first region 106 and a second region 107. The first region 106 of the field insulating layer 105 contacts the long sides of the first fin-type active pattern 110 and the long sides of the second fin-type active pattern 210. The first region 106 of the field insulating layer 105 may extend in the first direction X1 along a long side of the first fin-type active pattern 110 and a long side of the second fin-type active pattern 210.

The second region 107 of the field insulating layer 105 contacts the short side of the first fin-type active pattern 110 and the short side of the second fin-type active pattern 210. The second region 107 of the field insulating layer 105 is formed between the short side of the first fin-type active pattern 110 and the short side of the second fin-type active pattern 210 to extend along the second direction Y1.

In the semiconductor device 10 according to the tenth embodiment of the inventive concept, the top surface of the first region 106 of the field insulating layer 105 and the top surface of the second region 107 of the field insulating layer 105 may be located in the same plane. That is, the height H1 of the first region 106 of the field insulating layer 105 may be equal to the height H2 of the second region 107 of the field insulating layer 105.

The first gate electrode 120 is formed on the first fin-type active pattern 110 and the first region 106 of the field insulation layer 105. The first gate electrode 120 crosses the first fin-type active pattern 110.

The second gate electrode 220 is formed on the second fin-type active pattern 210 and the first region 106 of the field insulating layer 105. The second gate electrode 220 crosses the second fin-type active pattern 210.

The first gate electrode 120 and the second gate electrode 220 may extend along the second direction Y1. In the drawing, one first gate electrode 120 crossing the first fin-type active pattern 110 and one second gate electrode 220 crossing the second fin-type active pattern 210 are shown. However, this is only an example for ease of description, and the inventive concept is not limited to this example.

At least part of the first dummy gate electrode 160 is formed on the second region 107 of the field insulating layer 105. The first dummy gate electrode 160 is formed side by side with the first gate electrode 120 and the second gate electrode 220. The first dummy gate electrode 160 is formed between the first gate electrode 120 and the second gate electrode 220. The first gate electrode 160 extends along the second direction Y1.

In the semiconductor device 10 according to the tenth embodiment of the inventive concept, the entire first dummy gate electrode 160 is formed on the second region 107 of the field insulating layer 105. That is, the entire first dummy gate electrode 160 overlaps the second region 107 of the field insulating layer 105.

The first dummy gate electrode 160 is formed between a short side of the first fin-type active pattern 110 and a short side of the second fin-type active pattern 210. In other words, the first dummy gate electrode 160 is formed between one end of the first fin-type active pattern 110 and one end of the second fin-type active pattern 210. The first dummy gate electrode 160 may extend between the one end of the first fin-type active pattern 110 and the one end of the second fin-type active pattern 210 to be formed on the second region 107 of the field insulating layer 105.

In addition, one first dummy gate electrode 160 may be formed between the first fin-type active pattern 110 and the second fin-type active pattern 210. Since only one first dummy gate electrode 160 is formed between the first and second fin-type

active patterns

110 and 210 instead of two or more first dummy gate electrodes, the layout size can be reduced.

Like first gate electrode 120, second gate electrode 220 may include at least one of W, Al, TiN, TaN, TiC, and/or TaC. The second gate electrode 220 may be formed in the second trench 152 included in the interlayer insulating film 150.

The first dummy gate electrode 160 may have a similar structure to the first gate electrode 120 and the second gate electrode 220. The first dummy gate electrode 160 may include at least one of W, Al, TiN, TaN, TiC, and/or TaC.

The first dummy gate electrode 160 may be formed in the third trench 153 included in the interlayer insulating film 150. The third trench 153 may extend along the second direction Y1 to overlap the second region 107 of the field insulating layer 105.

Like the first gate electrode 120 and the second gate electrode 220, the first dummy gate electrode 160 may be formed through (but not limited to) a replacement process (or a gate-last process).

The second gate insulating layer 225 may be formed along the top surface and sidewalls of the second fin-type active pattern 210. The second gate insulating layer 225 may be formed along sidewalls and a bottom surface of the second trench 152.

The first dummy gate insulating layer 165 may be formed along sidewalls and a bottom surface of the third trench 153. In other words, the first dummy gate insulating layer 165 may be formed along sidewalls of the first dummy gate spacers 170 and a top surface of the second region 107 of the field insulating layer 105.

The second gate insulating layer 225 and the first dummy gate insulating layer 165 may include a silicon oxide layer and/or a high-k material having a higher dielectric constant than the silicon oxide layer.

In the drawing, the entire first dummy gate spacer 170 is formed on the second region 107 of the field insulating layer 105, and thus does not contact the first and second fin-type

active patterns

110 and 210. However, the inventive concept is not limited thereto.

The second source/drain regions 230 are formed at both sides of the second gate electrode 220, respectively. Each second source/drain region 230 may include a second epitaxial layer 235. The second epitaxial layer 235 may be the same as the first epitaxial layer 135 described above, and thus a repeated description thereof is omitted.

Now, semiconductor devices according to eleventh and twelfth embodiments of the inventive concept will be described with reference to fig. 19 to 21. For simplicity, the current embodiment will be described below, focusing mainly on differences from the embodiment described above with reference to fig. 16 to 18.

Fig. 19 and 20 are views of a semiconductor device 11 according to an eleventh embodiment of the inventive concept. Fig. 21 is a cross-sectional view of a semiconductor device 12 according to a twelfth embodiment of the inventive concept.

Referring to fig. 19 and 20, in the semiconductor device 11 according to the eleventh embodiment of the inventive concept, the top surface of the second region 107 of the field insulating layer 105 is higher than the top surface of the first region 106 of the field insulating layer 105. However, the top surface of the second region 107 of the field insulation layer 105 is lower than the top surfaces of the first and second fin-type

active patterns

110 and 210.

That is, the top surface of the first region 106 of the field insulating layer 105 and the top surface of the second region 107 of the field insulating layer 105 do not lie in the same plane.

More specifically, the height H2 of the second region 107 of the field insulating layer 105 is larger than the height H1 of the first region 106 of the field insulating layer 105. However, the height H2 of the second region 107 of the field insulation layer 105 is less than the height of the first fin-type active pattern 110 and the height of the second fin-type active pattern 210. As shown, height may refer to a relative distance from the surface of the substrate 100.

In the drawing, a portion of the first fin-type active pattern 110 and a portion of the second fin-type active pattern 210 overlap the first dummy gate spacer 170. However, the inventive concept is not limited thereto.

Referring to fig. 21, in the semiconductor device 12 according to the twelfth embodiment of the inventive concept, the top surface of the second region 107 of the field insulating layer 105 is higher than the top surface of the first region 106 of the field insulating layer 105.

In addition, the top surface of the second region 107 of the field insulation layer 105 may be at the same level as the top surfaces of the first and second fin-type

active patterns

110 and 210, or may be higher than the top surfaces of the first and second fin-type

active patterns

110 and 210.

In the drawing, the top surface of the second region 107 of the field insulating layer 105 is located in the same plane as the top surface of the first fin-type active pattern 110 and the top surface of the second fin-type active pattern 210. However, the inventive concept is not limited thereto.

Fig. 22 and 23 are views of a semiconductor device 13 according to a thirteenth embodiment of the inventive concept. For simplicity, the current embodiment will be described below, focusing mainly on differences from the embodiment described above with reference to fig. 16 to 18.

Referring to fig. 22 and 23, the semiconductor device 13 according to the thirteenth embodiment of the inventive concept further includes a second dummy gate electrode 260.

The second dummy gate electrode 260 is formed side by side with the first gate electrode 120 and the second gate electrode 220. The second dummy gate electrode 260 is formed between the first gate electrode 120 and the second gate electrode 220. The second dummy gate electrode 260 may extend along the second direction Y1.

The second dummy gate electrode 260 may have a similar structure to the first dummy gate electrode 160, and thus a description thereof is omitted.

In the semiconductor device 13 according to the thirteenth embodiment of the inventive concept, a portion of the first dummy gate electrode 160 and a portion of the second dummy gate electrode 260 are formed on the second region 107 of the field insulating layer 105. That is, only a portion of the first dummy gate electrode 160 may overlap the second region 107 of the field insulating layer 105, and only a portion of the second dummy gate electrode 260 may overlap the second region 107 of the field insulating layer 105.

In other words, a portion of the first dummy gate electrode 160 is formed on the second region 107 of the field insulating layer 105, and the other portion of the first dummy gate electrode 160 is formed on the first region 106 of the field insulating layer 105 and the first fin-type active pattern 110. In addition, a portion of the second dummy gate electrode 260 is formed on the second region 107 of the field insulating layer 105, and the other portion of the second dummy gate electrode 260 is formed on the first region 106 of the field insulating layer 105 and the second fin-type active pattern 210.

In fig. 23, the height H1 of the first region 106 of the field insulating layer 105 is equal to the height H2 of the second region 107 of the field insulating layer 105. However, the inventive concept is not limited thereto.

That is, as shown in fig. 19 and 20, the top surface of the second region 107 of the field insulating layer 105 is higher than the top surface of the first region 106 of the field insulating layer 105. However, the top surface of the second region 107 of the field insulation layer 105 is lower than the top surfaces of the first and second fin-type

active patterns

110 and 210.

In some embodiments, the top surface of the second region 107 of the field insulating layer 105 is higher than the top surface of the first region 106 of the field insulating layer 105. In addition, the top surface of the second region 107 of the field insulation layer 105 may be at the same level as the top surfaces of the first and second fin-type

active patterns

110 and 210 or may be higher than the top surfaces of the first and second fin-type

active patterns

110 and 210.

A semiconductor device according to fourteenth to twenty-second embodiments of the inventive concept will now be described with reference to fig. 24 to 36.

Fig. 24 is a perspective view of a semiconductor device 14 according to a fourteenth embodiment of the inventive concept. Fig. 25 is a sectional view taken along lines a-a and E-E of fig. 24. Fig. 26 and 27 are views of a semiconductor device 15 according to a fifteenth embodiment of the inventive concept. Fig. 28 is a view of a semiconductor device 16 according to a sixteenth embodiment of the inventive concept. Fig. 29 is a view of a semiconductor device 17 according to a seventeenth embodiment of the inventive concept. Fig. 30 and 31 are views of a semiconductor device 18 according to an eighteenth embodiment of the inventive concept. Fig. 32 is a view of a semiconductor device 19 according to a nineteenth embodiment of the inventive concept. Fig. 33 is a view of a semiconductor device 20 according to a twentieth embodiment of the inventive concept. Fig. 34 and 35 are views of a semiconductor device 21 according to a twenty-first embodiment of the inventive concept. Fig. 36 is a view of a semiconductor device 22 according to a twenty-second embodiment of the inventive concept.

Specifically, fig. 26, 30, 34, and 36 are sectional views of the semiconductor devices 14 to 22 according to the fourteenth to twenty-second embodiments, taken along lines a-a and E-E of fig. 24. Fig. 27 to 29, 31 to 33, and 35 are sectional views of the semiconductor devices 14 to 22 according to the fourteenth to twenty-second embodiments taken along lines C-C and F-F of fig. 24.

In the semiconductor devices 14 to 22 according to the fourteenth to twenty-second embodiments of the inventive concept, the first transistor 101 formed in the first region I may be substantially the same as those described above with reference to fig. 1 to 15, and thus a description thereof will be briefly given or omitted.

Referring to fig. 24 and 25, a semiconductor device 14 according to a fourteenth embodiment of the inventive concept may include a substrate 100, a first fin-type active pattern 110, a third fin-type active pattern 310, a first gate electrode 120, a third gate electrode 320, a first source/drain region 130, and a third source/drain region 330.

The substrate 100 may include a first region I and a second region II. The first region I and the second region II may be separated from each other or may be connected to each other. Further, the first region I and the second region II may include different types of transistor regions. For example, the first region I may be where NMOS transistors are formed, and the second region II may be where PMOS transistors are formed.

The first transistor 101 includes a first fin-type active pattern 110, a first gate electrode 120, and a first source/drain region 130.

In the semiconductor devices 14 to 22 according to the fourteenth to twenty-second embodiments of the inventive concept, the first upper pattern 112 of the first fin-type active pattern 110 may be a silicon carbide pattern including silicon carbide. In addition, the first source/drain region 130 may include n-type impurities.

Other features of the first transistor 101 are the same as those described above with reference to fig. 1 to 4, and thus a repetitive description thereof is omitted.

The second transistor 301 includes a third fin-type active pattern 310, a third gate electrode 320, and a third source/drain region 330.

The third fin active pattern 310 may protrude from the substrate 100. The field insulating layer 105 partially covers sidewalls of the third fin-type active patterns 310. Accordingly, the top surface of the third fin-type active pattern 310 protrudes further upward than the top surface of the field insulation layer 105. The third fin-type active pattern 310 is defined by the field insulating layer 105.

The third fin-type active pattern 310 includes a third lower pattern 311 and a third upper pattern 312 sequentially stacked on the substrate 100. The third upper pattern 312 is formed on the third lower pattern 311. The third upper pattern 312 and the third lower pattern 311 are directly connected to each other.

A top surface of the third fin-type active pattern 310 may be a top surface of the third upper pattern 312. At least part of the third upper pattern 312 protrudes further upward than the field insulating layer 105. The third upper pattern 312 may serve as a channel region of the second transistor 301.

The third lower pattern 311 is a silicon pattern including silicon. The third upper pattern 312 is a silicon germanium pattern including silicon germanium.

The third lower pattern 311 is directly connected to the substrate 100. Since the substrate 100 may be a silicon substrate and the third lower pattern 311 is a silicon pattern, they may be a unitary structure.

In fig. 24, the contact surfaces of the third upper pattern 312 and the third lower pattern 311 are located in the same plane as the top surface of the field insulating layer 105. That is, the entire sidewall of the third lower pattern 311 contacts the field insulating layer 105, and the entire sidewall of the third upper pattern 312 does not contact the field insulating layer 105. However, the inventive concept is not limited thereto.

The third fin-type active pattern 310 may extend along the third direction X2. The third fin active pattern 310 includes a first portion 310a and a second portion 310 b. The second portion 310b of the third fin-type active pattern 310 is disposed at both sides of the first portion 310a of the third fin-type active pattern 310 in the third direction X2.

In the semiconductor device 14 according to the fourteenth embodiment of the inventive concept, the top surfaces of the first portion 310a of the third fin-type active pattern 310 and the second portion 310b of the third fin-type active pattern 310 protrude further upward than the top surface of the field insulating layer 105. In addition, the top surfaces of the first portion 310a of the third fin-type active pattern 310 and the second portion 310b of the third fin-type active pattern 310 are located in the same plane.

The third gate electrode 320 is formed on the third fin-type active pattern 310 and the field insulation layer 105. For example, the third gate electrode 320 is formed on the first portion 310a of the third fin-type active pattern 310. More specifically, the third gate electrode 320 is formed on sidewalls and a top surface of the third upper pattern 312.

The third gate electrode 320 extends along the fourth direction Y2 to cross the third fin-type active pattern 310.

The third gate electrode 320 may include a metal layer. The third gate electrode 320 may include a portion that controls a work function and a portion that fills the fourth trench 156. The third gate electrode 320 may include at least one of W, Al, TiN, TaN, TiC, and/or TaC. In some embodiments, the third gate electrode 320 may be made of, for example, Si and/or SiGe.

A third gate insulating layer 325 may be formed between the third fin-type active pattern 310 and the third gate electrode 320. The third gate insulating layer 325 may be formed along the top surface and sidewalls of the first portion 310a of the third fin-type active pattern 310. The third gate insulating layer 325 may be formed along sidewalls and a top surface of the third upper pattern 312 protruding further upward than the top surface of the field insulating layer 105. The third gate insulating layer 325 may be formed along sidewalls and a bottom surface of the fourth trench 156.

The third gate insulating layer 325 may include a silicon oxide layer and/or a high-k material having a higher dielectric constant than the silicon oxide layer.

The third source/drain regions 330 are formed at both sides of the third gate electrode 320, respectively. For example, each of the third source/drain regions 330 is formed in the second portion 310b of the third fin-type active pattern 310. Each of the third source/drain regions 330 may be formed in the third fin-shaped active pattern 310, that is, in the second portion 310b of the third fin-shaped active pattern 310.

The third source/drain region 330 may include p-type impurities.

A semiconductor device 15 according to a fifteenth embodiment of the inventive concept will now be described with reference to fig. 26 and 27. For simplicity, the current embodiment will be described below, focusing mainly on differences from the embodiment described above with reference to fig. 24 to 25.

Referring to fig. 26 and 27, the semiconductor device 15 according to the fifteenth embodiment of the inventive concept further includes a first epitaxial layer 135 and a third epitaxial layer 335.

In the semiconductor devices 15 to 21 according to the fifteenth to twenty-first embodiments of the inventive concept, the first epitaxial layer 135 may include silicon carbide. Both the first upper pattern 112 and the first epitaxial layer 135 include silicon carbide. However, the proportion of carbon in the first epitaxial layer 135 may be equal to or greater than the proportion of carbon in the first upper pattern 112.

Other features of the first transistor 101 are the same as those described above with reference to fig. 5 and 6, and thus a repetitive description thereof is omitted.

Each of the third source/drain regions 330 may include a third epitaxial layer 335 and an impurity region formed in the second portion 310b of the third fin-type active pattern 310.

The entire third epitaxial layer 335 is formed on the top surface 310b-1 and the sidewall 310b-2 of the second portion 310b of the third fin-type active pattern 310 protruding further upward than the top surface of the field insulating layer 105. The third epitaxial layer 335 may contact the field insulating layer 105.

The third epitaxial layer 335 is formed on sidewalls and a top surface of the third upper pattern 312 of the second portion 310b of the third fin-type active pattern 310.

In fig. 27, the outer peripheral surface of the third epitaxial layer 335 may have various shapes. For example, the outer peripheral surface of the third epitaxial layer 335 can be at least one of diamond-shaped, circular-shaped, and/or rectangular-shaped. In fig. 27, an octagonal shape is shown.

Like the third upper pattern 312, the third epitaxial layer 335 may include silicon germanium.

That is, both the third upper pattern 312 and the third epitaxial layer 335 include silicon germanium. However, the ratio of germanium in the third epitaxial layer 335 may be equal to or greater than the ratio of germanium in the third upper pattern 312.

Semiconductor devices

16 and 17 according to sixteenth and seventeenth embodiments of the inventive concept will now be described with reference to fig. 28 and 29. For simplicity, the present embodiment will be described below, focusing mainly on differences from the embodiment described above with reference to fig. 26 to 27.

Referring to fig. 28, in the semiconductor device 16 according to the sixteenth embodiment of the inventive concept, the first epitaxial layer 135 does not contact the field insulating layer 105 and the third epitaxial layer 335 does not contact the field insulating layer 105.

The third epitaxial layer 335 is formed on the top surface 310b-1 and portions of the sidewalls 310b-2 of the second portions 310b of the third fin-type active patterns 310 protruding further upward than the top surface of the field insulating layer 105. That is, the third epitaxial layer 335 is formed around the portion of the second portion 310b of the third fin-type active pattern 310 protruding further upward than the top surface of the field insulating layer 105.

Referring to fig. 29, the semiconductor device 17 according to the seventeenth embodiment of the inventive concept further includes a first fin spacer 145 and a second fin spacer 345.

The second fin spacer 345 may be formed on a portion of the sidewall 310b-2 of the second portion 310b of the third fin-type active pattern 310 protruding further upward than the top surface of the field insulating layer 105. Accordingly, a portion of the second portion 310b of the third fin-type active pattern 310 protrudes further upward than the second fin spacer 345. That is, a portion of the sidewalls 310b-2 of the second portion 310b of the third fin-type active pattern 310 is not covered by the second fin spacers 345.

The third epitaxial layer 335 is formed on the top surface 310b-1 and the sidewalls 310b-2 of the second portion 310b of the third fin-type active pattern 310 protruding further upward than the second fin spacers 345. That is, the third epitaxial layer 335 is formed around the second portion 310b of the third fin-type active pattern 310 protruding further upward than the second fin spacer 345.

Third epitaxial layer 335 may contact second fin spacer 345.

A semiconductor device 18 according to an eighteenth embodiment of the inventive concept will now be described with reference to fig. 30 and 31. For simplicity, the present embodiment will be described below, focusing mainly on differences from the embodiment described above with reference to fig. 26 to 27.

Referring to fig. 30 and 31, in the semiconductor device 18 according to the eighteenth embodiment of the inventive concept, the top surfaces of the second portions 110b of the first fin-type active patterns 110 are more recessed than the top surfaces of the first portions 110a of the first fin-type active patterns 110. In addition, the top surfaces of the second portions 310b of the third fin-type active patterns 310 are more recessed than the top surfaces of the first portions 310a of the third fin-type active patterns 310.

The top surfaces of the first portion 310a of the third fin-type active pattern 310 and the second portion 310b of the third fin-type active pattern 310 protrude further upward than the top surface of the field insulating layer 105. However, the top surfaces of the first portion 310a of the third fin-type active pattern 310 and the second portion 310b of the third fin-type active pattern 310 do not lie in the same plane.

A height from the top surface of the substrate 100 to the top surface of the first portion 310a of the third fin-type active pattern 310 is greater than a height from the top surface of the substrate 100 to the top surface of the second portion 310b of the third fin-type active pattern 310.

In addition, a portion of the sidewall 310b-2 of the second portion 310b of the third fin-type active pattern 310 contacts the field insulating layer 105, but other portions of the sidewall 310b-2 of the second portion 310b of the third fin-type active pattern 310 do not contact the field insulating layer 105.

The third epitaxial layer 335 is formed on the recessed second portion 310b of the third fin-type active pattern 310. More specifically, the third epitaxial layer 335 is formed on the top surface 310b-1 of the second portion 310b of the third fin-type active pattern 310 protruding further upward than the top surface of the field insulation layer 105, and is not formed on the sidewall 310b-2 of the second portion 310b of the third fin-type active pattern 310.

Semiconductor devices

19 and 20 according to nineteenth and twentieth embodiments of the inventive concept will now be described with reference to fig. 32 and 33. For simplicity, the current embodiment will be described below, focusing mainly on differences from the embodiment described above with reference to fig. 30 and 31.

Referring to fig. 32, in the semiconductor device 19 according to the nineteenth embodiment of the inventive concept, the first epitaxial layer 135 and the third epitaxial layer 335 may contact the field insulating layer 105.

The third epitaxial layer 335 is formed on the sidewalls 310b-2 and the top surface 310b-1 of the second portion 310 of the third fin-type active pattern 310 protruding further upward than the top surface of the field insulating layer 105. The third epitaxial layer 335 is formed around the second portion 310b of the third fin-type active pattern 310 protruding further upward than the top surface of the field insulating layer 105.

Referring to fig. 33, the semiconductor device 20 according to the twentieth embodiment of the inventive concept further includes first and

second fin spacers

145 and 345.

The second fin spacer 345 may be formed on the sidewall 310b-2 of the second portion 310b of the third fin-type active pattern 310 protruding further upward than the top surface of the field insulating layer 105. Thus, second fin spacer 345 may contact third epitaxial layer 335.

In the drawing, the second portion 310b of the third fin-type active pattern 310 does not protrude further upward than the second fin spacers 345. However, the inventive concept is not limited thereto.

A semiconductor device 21 according to a twenty-first embodiment of the inventive concept will now be described with reference to fig. 34 and 35. For simplicity, the current embodiment will be described below, focusing mainly on differences from the embodiment described above with reference to fig. 26 and 27.

Referring to fig. 34 and 35, in the semiconductor device 21 according to the twenty-first embodiment of the inventive concept, the entire sidewall 110b-2 of the second portion 110b of the first fin-type active pattern 110 and the entire sidewall 310b-2 of the second portion 310b of the third fin-type active pattern 310 may contact the field insulating layer 105.

A top surface 310b-1 of the second portion 310b of the third fin-type active pattern 310 may not protrude further upward than a top surface of the field insulating layer 105. That is, if the top surface of the field insulating layer 105 is flat as shown in the drawing, the top surface 310b-2 of the second portion 310b of the third fin-type active pattern 310 may be located in the same plane as the top surface of the field insulating layer 105.

Since the entire sidewall 310b-2 of the second portion 310b of the third fin-type active pattern 310 is covered with the field insulation layer 105, the third epitaxial layer 335 is formed on the top surface 310b-1 of the second portion 310b of the third fin-type active pattern 310 and not on the sidewall 310b-2 of the third portion 310b of the third fin-type active pattern 310.

A semiconductor device 22 according to a twenty-second embodiment of the inventive concept will now be described with reference to fig. 36. For simplicity, the current embodiment will be described below, focusing mainly on differences from the embodiment described above with reference to fig. 24 and 25.

Referring to fig. 36, in the semiconductor device 22 according to the twenty-second embodiment of the inventive concept, the first gate insulating layer 125 is formed along the bottom surface of the first trench 151 without along the sidewalls of the first trench 151. In addition, the third gate insulating layer 325 is formed along the bottom surface of the fourth trench 156 and not along the sidewalls of the fourth trench 156.

The third gate insulating layer 325 is not formed along sidewalls of the third gate spacer 340. The third gate insulating layer 325 does not include a portion located in the same plane as the third gate electrode 320.

Accordingly, the third gate insulating layer 325 is interposed between the third gate electrode 320 and the third fin-type active pattern 310 without between the third gate electrode 320 and the third gate spacer 340.

In the semiconductor devices 14 to 22 described above with reference to fig. 24 to 36, the first transistor 101 and the second transistor 301 are formed. However, this is only an example for ease of description, and the inventive concept is not limited to this example.

That is, the second transistor 301 illustrated in fig. 24 and 25 may have not only the structure described above with reference to fig. 1 to 4 but also the structure described above with reference to fig. 5 to 15.

A method of manufacturing a semiconductor device according to an embodiment of the inventive concept will now be described with reference to fig. 37 to 45. The semiconductor device manufactured by the processes of fig. 37 to 45 may be the semiconductor device 8 described above with reference to fig. 13 and 14.

Fig. 37 to 45 are views illustrating operations of methods of manufacturing a semiconductor device according to some embodiments of the inventive concept.

Referring to fig. 37, a compound semiconductor layer 112p is formed on a substrate 100. The compound semiconductor layer 112p is formed to directly contact the substrate 100. The compound semiconductor layer 112p may be formed by, for example, an epitaxial growth process.

The compound semiconductor layer 112p includes a material having a lattice constant different from that of the material of the substrate 100. If the substrate 100 is a silicon substrate, the compound semiconductor layer 112p includes a material having a larger or smaller lattice constant than silicon.

When used as a channel region of an NMOS transistor, the compound semiconductor layer 112p may be a silicon carbide layer.

On the other hand, when used as a channel region of a PMOS transistor, the compound semiconductor layer 112p may be, for example, a silicon germanium layer.

The compound semiconductor layer 112p formed on the substrate 100 may be fully strained. That is, the lattice constant of the compound semiconductor layer 112p may be equal to the lattice constant of the substrate 100. In order to completely strain the compound semiconductor layer 112p, the thickness of the compound semiconductor layer 112p formed on the substrate 100 may be equal to or less than a critical thickness.

A first mask pattern 2103 is formed on the compound semiconductor layer 112 p. The first mask pattern 2103 may extend in the first direction X1.

The first mask pattern 2103 may include a material including at least one of a silicon oxide layer, a silicon nitride layer, and/or a silicon oxynitride layer.

Referring to fig. 38, the compound semiconductor layer 112p and a portion of the substrate 100 are patterned to form first fin-type active patterns 110 on the substrate 100.

Specifically, the compound semiconductor layer 112p and a part of the substrate 100 are etched using the first mask pattern 2103 formed on the compound semiconductor layer 112p as a mask. As a result, the first fin-type active pattern 110 is formed on the substrate 100 to extend along the first direction X1.

The first upper pattern 112 is formed by patterning the compound semiconductor layer 112p, and the first lower pattern 111 is formed by patterning a portion of the substrate 100. That is, the first fin-type active pattern 110 protruding upward from the substrate 100 includes a first lower pattern 111 and a first upper pattern 112 sequentially stacked on the substrate 100.

Referring to fig. 39, a field insulating layer 105 is formed on a substrate 100. The field insulating layer 105 may be made of a material including at least one of a silicon oxide layer, a silicon nitride layer, and/or a silicon oxynitride layer.

For example, a field insulating layer 105 is formed on the substrate 100 to cover the first fin-type active pattern 110 and the first mask pattern 2103. Then, a planarization process is performed to make the top surface of the first fin-type active pattern 110 and the top surface of the field insulating layer 105 lie in the same plane.

The first mask pattern 2103 may be removed in the planarization process, but the inventive concept is not limited thereto. That is, the first mask pattern 2103 may be removed before forming the field insulating layer 105 or after a process of recessing the field insulating layer 105.

Next, a portion of the field insulating layer 105 is recessed. As a result, the first fin-type active pattern 110 protrudes further upward than the top surface of the field insulating layer 105. That is, the field insulating layer 105 is formed to contact a portion of sidewalls of the first fin-type active pattern 110. Thus, the first fin-type active pattern 110 may be defined by the field insulating layer 105.

The partial removal of the field insulating layer 105 causes at least a portion of the first upper pattern 112 to protrude further upward than the field insulating layer 105.

In addition, the first fin-type active pattern 110 may be doped with impurities to control a threshold voltage. In order to fabricate the NMOS fin transistor using the first fin active pattern 110, boron (B) may be used as an impurity for controlling a threshold voltage. In order to manufacture a PMOS fin transistor using the first fin active pattern 110, phosphorus (P) and/or arsenic (As) may be used As impurities for controlling a threshold voltage. That is, the first upper pattern 112, which is used as a channel region of a transistor, may be doped with impurities to control a threshold voltage.

Referring to fig. 40, an etching process is performed using the second mask pattern 2104, thereby forming a dummy gate pattern 126 crossing the first fin-type active patterns 110 and extending along the second direction Y1.

The dummy gate pattern 126 is formed on the field insulating layer 105 and the first fin-type active pattern 110 formed on the substrate 100. The dummy gate pattern 126 includes a dummy gate insulating layer 127 and a dummy gate electrode 128. For example, the dummy gate insulating layer 127 may be a silicon oxide layer, and the dummy gate electrode 128 may be polysilicon.

In the method of manufacturing the semiconductor device according to the current embodiment, the dummy gate pattern 126 is formed to form the replacement gate electrode. However, the inventive concept is not limited thereto.

That is, the gate pattern instead of the dummy gate pattern 126 can be formed on the first fin-type active pattern 110 using a material to be used as a gate insulating layer and a gate electrode of a transistor. Here, the gate pattern may include a high-k gate insulating layer and/or a metal gate electrode having a higher dielectric constant than the silicon oxide layer.

Referring to fig. 41, first gate spacers 140 are formed on sidewalls of the dummy gate pattern 126. In other words, the first gate spacers 140 are formed on the side surfaces of the dummy gate electrode 128.

Specifically, a spacer layer is formed on the dummy gate pattern 126 and the first fin-type active pattern 110 and then etched back to form the first gate spacers 140. The first gate spacers 140 may expose a top surface of the second mask pattern 2104 and a top surface of the non-overlapping dummy gate pattern 126 of the fin-type active pattern 110.

Next, recesses are formed in the first fin-type active patterns 110 by partially removing the first fin-type active patterns 110 exposed at both sides of the dummy gate pattern 126. That is, recesses are formed at both sides of the dummy gate electrode 128 by partially removing the first fin-type active patterns 110 that do not overlap the dummy gate electrode 128.

Referring to fig. 42, first source/drain regions 130 are formed at both sides of the dummy gate pattern 126, each of the first source/drain regions 130 including a first epitaxial layer 135.

The first epitaxial layer 135 fills recesses formed at both sides of the dummy gate pattern 126. That is, the first epitaxial layer 135 is formed on the first fin-type active pattern 110.

The first epitaxial layer 135 may be formed using an epitaxial growth method. The first epitaxial layer 135 may be doped in-situ with impurities in an epitaxial process, if desired.

In the figure, the first epitaxial layer 135 is octagonal. However, the shape of the first epitaxial layer 135 is not limited to the octagonal shape. That is, the first epitaxial layer can be formed to have various shapes such as a diamond shape, a rectangular shape, and/or a pentagonal shape by controlling conditions of an epitaxial process for forming the first epitaxial layer 135.

If the first upper pattern 112 used as the channel region is a silicon carbide pattern, the first epitaxial layer 135 may include silicon carbide.

If the first upper pattern 112 used as the channel region is a silicon germanium pattern, the first epitaxial layer 135 may include silicon germanium.

Referring to fig. 43, an interlayer insulating film 150 is formed on the substrate 100 to cover the first source/drain region 130 and the dummy gate pattern 126. The interlayer insulating film 150 may include at least one of an oxide layer, a nitride layer, and/or an oxynitride layer.

The interlayer insulating film 150 is planarized until the top surface of the dummy gate pattern 126 is exposed. As a result, the second mask pattern 2104 is removed, and the top surface of the dummy gate electrode 128 is exposed.

Referring to fig. 44, the dummy gate pattern 126 (i.e., the dummy gate insulating layer 127 and the dummy gate electrode 128) is removed.

The removal of the dummy gate insulating layer 127 and the dummy gate electrode 128 results in the formation of a trench exposing the field insulating layer 105 and a portion of the first fin-type active pattern 110. The first upper pattern 112 is exposed by the trench.

Referring to fig. 45, a first gate insulating layer 125 and a first gate electrode 120 are formed in the trench.

The first gate insulating layer 125 may be formed substantially conformally along the sidewalls and bottom surface of the trench. The first gate electrode 120 may fill a trench in which the first gate insulating layer 125 is formed.

Methods of manufacturing semiconductor devices according to further embodiments of the inventive concept will now be described with reference to fig. 37 to 40 and fig. 43 to 47. The semiconductor device manufactured by the processes of fig. 37 to 40 and 43 to 47 may be the semiconductor device 2 described above with reference to fig. 5 and 6.

Fig. 46 and 47 are views illustrating operations of methods of manufacturing semiconductor devices according to further embodiments of the inventive concept.

Referring to fig. 46, first gate spacers 140 are formed on sidewalls of the dummy gate pattern 126. The first fin-type active pattern 110, which does not overlap the dummy gate pattern 126, is not etched during the formation of the first gate spacers 140.

More specifically, in the process of forming the first gate spacer 140, fin spacers may also be formed on sidewalls of the first fin-type active pattern 110. By controlling the conditions of the etch-back process for forming the first gate spacers 140, only the fin spacers formed on the sidewalls of the first fin-type active pattern 110 may be removed, while the first fin-type active pattern 110 is not etched.

That is, an etching material having an etching selectivity with respect to the first upper pattern 112 may be used to etch only the material forming the first gate spacers 140 and the fin spacers without etching the first upper pattern 112.

As a result, the first fin-type active patterns 110 that do not overlap the dummy gate patterns 126 and the first gate spacers 140 still protrude further upward than the field insulating layer 105.

Referring to fig. 47, first epitaxial layers 135 are formed at both sides of the dummy gate pattern 126.

The first epitaxial layer 135 is formed on sidewalls and a top surface of the first fin-type active pattern 110 protruding further than the field insulating layer 105. For example, the first epitaxial layer 135 is formed on the sidewalls and the top surface of the first upper pattern 112 protruding further upward than the field insulating layer 105. The first epitaxial layer 135 is formed around the first upper pattern 112 protruding further upward than the field insulating layer 105.

As a result, first source/drain regions 130 are formed, each of the first source/drain regions 130 including the first epitaxial layer 135 and an impurity region formed in the first fin-type active pattern 110.

Fig. 48 is a block diagram of an electronic system 1100 including a semiconductor device according to some embodiments of the inventive concepts.

Referring to fig. 48, an electronic system 1100 may include a controller 1110, an input/output (I/O) device 1120, a memory device 1130, an interface 1140, and a bus 1150. The controller 1110, the I/O device 1120, the memory device 1130, and/or the interface 1140 may be connected to each other via a bus 1150. The bus 1150 may serve as a path for transferring data.

The controller 1110 may include at least one of a microprocessor, a digital signal processor, a microcontroller, and/or a logic device capable of performing functions similar to those of the microprocessor, the digital signal processor, and/or the microcontroller. I/O devices 1120 may include a keypad, a keyboard, and a display device. The memory device 1130 may store data and/or commands. The interface 1140 may be used to transmit data to and receive data from a communication network. The interface 1140 may be a wired or wireless interface. In an example, the interface 1140 may include an antenna and/or a wired and/or wireless transceiver. Although not shown in the drawings, the electronic system 1100 may further include a high-speed DRAM or an SRAM as an operation memory for improving the operation of the controller 1110. Any of the semiconductor devices according to the above-described embodiments of the inventive concept may be provided in the memory device 1130 and/or in the controller 1110 and/or the I/O device 1120.

Electronic system 1100 may be applied to almost any type of electronic product capable of sending or receiving information in a wireless environment, such as a Personal Data Assistant (PDA), a portable computer, a netbook, a wireless telephone, a mobile telephone, a digital music player, and/or a memory card, among others.

Fig. 49 and 50 are diagrams illustrating examples of semiconductor systems to which semiconductor devices according to some embodiments of the inventive concepts can be applied. Fig. 49 shows a tablet Personal Computer (PC), and fig. 50 shows a notebook computer. At least one of the semiconductor devices according to some embodiments of the inventive concept may be used in a tablet PC, a notebook computer, or the like. Semiconductor devices according to some embodiments of the inventive concepts, as set forth herein, may also be applied to various IC arrangements other than those set forth herein.

While the present inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present inventive concept as defined by the following claims. Therefore, it is intended that the present embodiments be considered in all respects as illustrative and not restrictive, reference being made to the appended claims rather than to the foregoing description to indicate the scope of the inventive concept.

This application claims priority from U.S. patent application No.61/970615 filed on 26/3/2014 and korean patent application No.10-2014-0101756 filed on 7/8/2014 on the korean intellectual property office, the disclosures of which are incorporated herein by reference in their entireties.

Claims

1. A semiconductor device, comprising:

a field insulating layer on a top surface of the substrate and including a trench extending in a first direction defined therein;

a fin active pattern extending from the top surface of the substrate and through the trench defined in the field insulating layer, the fin active pattern including a first lower pattern contacting the substrate and a first upper pattern contacting the first lower pattern and protruding further from the substrate than the field insulating layer, the first upper pattern including a different lattice-changing material than the first lower pattern, the fin active pattern including a first fin portion and second fin portions on both sides of the first fin portion in the first direction, and the first lower pattern including a semiconductor material; and

a first gate electrode crossing the fin-type active pattern and extending in a second direction different from the first direction, the first gate electrode being formed on the first fin portion of the first upper pattern,

wherein contact faces of the first upper pattern and the first lower pattern are located in the same plane as a top surface of the field insulating layer such that an entire sidewall of the first upper pattern of the second fin portion does not contact the field insulating layer,

wherein the semiconductor device further includes first source and drain regions including impurity regions in the second fin portion of the fin-type active pattern and on both sides of the first gate electrode.

2. The semiconductor device of claim 1, wherein the first source and drain regions further comprise a first epitaxial layer comprising the lattice-change material.

3. The semiconductor device as set forth in claim 2,

wherein the first epitaxial layer is formed on sidewalls and a top surface of the second fin portion of the first upper pattern, an

Wherein the first epitaxial layer contacts the field insulating layer.

4. The semiconductor device of claim 2, wherein the first epitaxial layer is formed on sidewalls and a top surface of the second fin portion of the first upper pattern without contacting the field insulating layer.

5. The semiconductor device of claim 4, further comprising:

a first gate spacer on a sidewall of the first gate electrode; and

a first fin spacer on a portion of the sidewalls of the second fin portion of the first upper pattern and contacting the first epitaxial layer and the first gate spacer.

6. The semiconductor device as set forth in claim 1,

wherein the semiconductor device comprises an n-channel metal oxide semiconductor (NMOS) transistor,

wherein the lattice change material comprises carbon, an

Wherein the first upper pattern comprises silicon carbide (SiC).

7. The semiconductor device of claim 6, wherein the first source and drain regions further comprise a first epitaxial layer comprising the lattice-change material,

wherein a concentration of carbon in the first upper pattern does not exceed a concentration of carbon in the first epitaxial layer.

8. The semiconductor device as set forth in claim 7,

wherein a concentration of carbon in the first upper pattern is in a range of 0.5% to 1.5%, and

wherein the concentration of carbon in the first epitaxial layer is in the range of 0.5% to 3.0%.

9. The semiconductor device of claim 1, wherein the semiconductor device comprises a p-channel metal-oxide-semiconductor (PMOS) transistor,

wherein the lattice change material comprises germanium, and

wherein the first upper pattern includes silicon germanium (SiGe).

10. The semiconductor device of claim 9, wherein the first source and drain regions further comprise a first epitaxial layer comprising the lattice change material,

wherein a concentration of germanium in the first upper pattern does not exceed a concentration of germanium in the first epitaxial layer.

11. The semiconductor device as set forth in claim 10,

wherein a concentration of germanium in the first upper pattern is in a range of 50% to 70%, an

Wherein the concentration of germanium in the first epitaxial layer is in the range of 50% to 90%.

12. The semiconductor device of claim 1, wherein a top surface of the second fin portion is recessed more relative to the substrate than a top surface of the first fin portion.

13. A semiconductor device, comprising:

a field insulating layer on a top surface of the substrate and including a first trench defined therein and extending in a first direction;

a fin-type active pattern extending from the top surface of the substrate and through the first trench defined in the field insulating layer, the fin-type active pattern including a first lower pattern contacting the substrate and a first upper pattern contacting the first lower pattern and protruding farther from the substrate than the field insulating layer, the first upper pattern including a different lattice-changing material than the first lower pattern, the fin-type active pattern including a first fin portion and second fin portions on both sides of the first fin portion in the first direction, and the first lower pattern including a semiconductor material; and

wherein the fin active pattern is a first fin active pattern, an

Wherein the lattice change material comprises a first lattice change material, the semiconductor device further comprising:

a second fin-type active pattern extending from a top surface of the substrate and passing through a second trench defined in the field insulating layer, the second fin-type active pattern including a second lower pattern contacting the substrate and a second upper pattern contacting the second lower pattern and protruding farther from the substrate than the field insulating layer, the first upper pattern including a second lattice change material different from the second lower pattern, and the second fin-type active pattern including a third fin portion and fourth fin portions at both sides of the third fin portion in the first direction, wherein the first fin-type active pattern and the second fin-type active pattern extend side by side along a longitudinal direction such that a short side of the first fin-type active pattern faces a short side of the second fin-type active pattern; and

and a second gate electrode crossing the second fin-type active pattern and extending in the second direction.

14. The semiconductor device of claim 13, further comprising:

first source and drain regions including an impurity region in the second fin portion and on both sides of the first gate electrode and a first epitaxial layer including the lattice-change material; and

second source and drain regions including an impurity region in the fourth fin portion and on either side of the second gate electrode and a second epitaxial layer including the second lattice change material.

15. The semiconductor device of claim 14, wherein the first lattice change material and the second lattice change material are the same material.

16. The semiconductor device of claim 14, wherein the first lattice change material comprises carbon and the second lattice change material comprises germanium.

17. The semiconductor device of claim 14, further comprising a dummy gate electrode on the field insulating layer and between the first and second gate electrodes and extending in the second direction.

18. The semiconductor device of claim 14, further comprising an oxide pattern formed on the substrate between the first fin-type active pattern and the second fin-type active pattern.

19. The semiconductor device of claim 18, further comprising a dummy gate electrode on the oxide pattern, wherein the dummy gate electrode extends between the first gate electrode and the second gate electrode and in the second direction.

20. The semiconductor device of claim 18, further comprising first and second dummy gate electrodes at least partially on the oxide pattern, wherein the first and second dummy gate electrodes are spaced apart between the first and second gate electrodes in the first direction and extend in the second direction.