TWI620256B - Semiconductor package and manufacturing method thereof - Google Patents
Semiconductor package and manufacturing method thereof Download PDFInfo
- Publication number
- TWI620256B TWI620256B TW105129920A TW105129920A TWI620256B TW I620256 B TWI620256 B TW I620256B TW 105129920 A TW105129920 A TW 105129920A TW 105129920 A TW105129920 A TW 105129920A TW I620256 B TWI620256 B TW I620256B
- Authority
- TW
- Taiwan
- Prior art keywords
- carrier
- semiconductor package
- support
- wafers
- setting
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 53
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 235000012431 wafers Nutrition 0.000 claims abstract description 56
- 239000000084 colloidal system Substances 0.000 claims abstract description 23
- 238000004806 packaging method and process Methods 0.000 claims abstract description 20
- 230000002093 peripheral effect Effects 0.000 claims abstract description 4
- 239000010410 layer Substances 0.000 claims description 42
- 238000000034 method Methods 0.000 claims description 19
- 239000008393 encapsulating agent Substances 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 12
- 239000012790 adhesive layer Substances 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 6
- 238000005538 encapsulation Methods 0.000 claims description 4
- 239000000499 gel Substances 0.000 description 14
- 238000010586 diagram Methods 0.000 description 13
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 4
- 238000009434 installation Methods 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
一種半導體封裝件及其製法，該製法包含：準備一承載件，該承載件包含有相對的第一設置面與第二設置面，該第一設置面設有複數晶片；形成一封裝膠體以包覆該等晶片的外周面；在該第二設置面設置一支撐件，其中該支撐件的熱膨脹係數大於該承載件的熱膨脹係數；在該等晶片與該封裝膠體的表面形成一線路重佈結構層，完成半導體封裝件；其中，該支撐件可有效降低該承載件與該封裝膠體的翹曲形變。 A semiconductor package and a manufacturing method thereof. The manufacturing method includes: preparing a carrier, the carrier includes a first setting surface and a second setting surface opposite to each other, and the first setting surface is provided with a plurality of wafers; Covering the peripheral surfaces of the wafers; providing a support on the second setting surface, wherein the thermal expansion coefficient of the support is greater than the thermal expansion coefficient of the carrier; forming a circuit redistribution structure on the surfaces of the wafers and the packaging colloid Layer to complete the semiconductor package; wherein the support can effectively reduce the warpage and deformation of the carrier and the packaging gel.
Description
本創作係有關一種半導體封裝件及其製法，特別是指可減少翹曲變形的半導體封裝件及其製法。 The present invention relates to a semiconductor package and a manufacturing method thereof, particularly to a semiconductor package and a manufacturing method capable of reducing warpage and deformation.
隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。為了滿足半導體封裝件微型化的封裝需求，係發展出晶圓級封裝技術(Wafer Level Packaging,WLP)。 With the vigorous development of the electronics industry, electronic products are gradually moving towards the trend of multifunctional and high performance. In order to meet the packaging needs of semiconductor package miniaturization, Wafer Level Packaging (WLP) technology has been developed.
圖1至圖5揭示習知晶圓級半導體封裝件之製法。請參考圖1，準備一承載件10，以將複數晶片11藉由離型膠層12固定於該承載件10的一表面，其中，各該晶片11的表面為一主動面110，該主動面110形成有複數電極墊111。 FIG. 1 to FIG. 5 disclose a conventional method for manufacturing a wafer-level semiconductor package. Referring to FIG. 1, a carrier 10 is prepared to fix a plurality of wafers 11 to a surface of the carrier 10 through a release adhesive layer 12, wherein the surface of each of the wafers 11 is an active surface 110. 110 is formed with a plurality of electrode pads 111.
請參考圖2，在該承載件10上形成一包覆膠體13，該包覆膠體13包覆該等晶片11。請參考圖3，可透過研磨輪去除多餘的該包覆膠體以形成一封裝膠體130，使各該晶片11的主動面110與電極墊111露出封裝膠體130。請參考圖4，進行線路重佈層製程，以形成一線路重佈結構層(Re-Distribution Layer,RDL)14於該封裝膠體130的表面與該等晶片11之主動面110，完成習知的半導體封裝件15，其中，該線路重佈結構層14包含有絕緣基材140、複數中介電連接部141與複數導電塊142，該等中介電連接部141形成在該絕緣基材140內且分別電性連接該等晶片11的電極墊111，該等導電塊142分別電性連接該等中介電連接部141。 Referring to FIG. 2, a covering colloid 13 is formed on the carrier 10, and the covering colloid 13 covers the wafers 11. Referring to FIG. 3, an excess of the coating gel can be removed through a grinding wheel to form a packaging gel 130, so that the active surface 110 and the electrode pad 111 of each of the wafers 11 expose the packaging gel 130. Please refer to FIG. 4, a circuit redistribution layer process is performed to form a circuit redistribution layer (RDL) 14 on the surface of the encapsulant 130 and the active surfaces 110 of the wafers 11, and the conventional process is completed. The semiconductor package 15, wherein the circuit redistribution structure layer 14 includes an insulating substrate 140, a plurality of inter-dielectric connection portions 141, and a plurality of conductive blocks 142, and the inter-dielectric connection portions 141 are formed in the insulating substrate 140 and are respectively The electrode pads 111 of the wafers 11 are electrically connected, and the conductive blocks 142 are electrically connected to the dielectric connection portions 141 respectively.
然而，因為該封裝膠體130、該承載件10與該等晶片11的熱膨脹係數(coefficient of thermal expansion,CTE)彼此不同，在形成該線路重佈結構層14的步驟中，該封裝膠體130在製程溫度的影響下體積熱脹而發生翹曲形變，如圖5之示意圖所示。如此一來，該線路重佈結構層14的中介電連接部141與該等晶片11之電極墊111之間的相對位置將會產生偏差，造成電性連接異常，衍生良率過低及產品可靠度不佳等問題。 However, because the coefficient of thermal expansion (CTE) of the encapsulant 130, the carrier 10, and the wafers 11 are different from each other, in the step of forming the circuit redistribution structure layer 14, the encapsulant 130 is in the manufacturing process. The thermal expansion of the volume under the influence of temperature causes warping deformation, as shown in the schematic diagram of FIG. 5. As a result, the relative position between the dielectric connection portion 141 of the circuit redistribution structure layer 14 and the electrode pads 111 of the wafers 11 will cause deviations, resulting in abnormal electrical connections, too low derivative yields, and reliable products. Poor degree and other issues.
有鑒於此，本創作的主要目的是提供一種半導體封裝件及其製法，可有效抑制該封裝膠體的翹曲幅度，避免線路重佈結構層與晶片之電極墊之間的相對位置產生偏移。 In view of this, the main purpose of this creation is to provide a semiconductor package and a manufacturing method thereof, which can effectively suppress the warping amplitude of the packaging colloid and prevent the relative position between the circuit redistribution structure layer and the electrode pads of the wafer from shifting.
本創作半導體封裝件，包含：一承載件，具有相對的一第一設置面與一第二設置面；一支撐件，設置於該承載件的該第二設置面，該支撐件的熱膨脹係數大於該承載件的熱膨脹係數；複數晶片，分離設置於該承載件的該第一設置面；封裝膠體，形成在該承載件的該第一設置面且包覆該等晶片的外周面；及一線路重佈結構層，形成於該封裝膠體的表面與該等晶片之主動面，且電性連接各該晶片。 The creative semiconductor package includes: a carrier having a first setting surface and a second setting surface opposite to each other; a support member disposed on the second setting surface of the carrier, and the thermal expansion coefficient of the support is greater than A thermal expansion coefficient of the carrier; a plurality of wafers separated and disposed on the first installation surface of the carrier; a sealing gel formed on the first installation surface of the carrier and covering an outer peripheral surface of the wafers; and a circuit The redistribution structure layer is formed on the surface of the encapsulant and the active surfaces of the chips, and is electrically connected to each of the chips.
本創作半導體封裝件的製法包含：準備一承載件，該承載件具有相對的一第一設置面與一第二設置面，該第一設置面設有分離設置的複數晶片，各該晶片具有一主動面，該主動面形成有複數電極墊；在該承載件的該第一設置面形成一封裝膠體，各該晶片的該主動面與該等電極墊外露於該封裝膠體； 在該承載件的該第二設置面設置一支撐件，該支撐件的熱膨脹係數大於該承載件的熱膨脹係數；以及形成一線路重佈結構層於該封裝膠體的表面與該等晶片之該等主動面，完成所述半導體封裝件。 The method for manufacturing a semiconductor package includes: preparing a carrier, the carrier having a first setting surface and a second setting surface opposite to each other, the first setting surface being provided with a plurality of wafers separately disposed, each of the wafers having a An active surface with a plurality of electrode pads formed on the active surface; an encapsulating gel is formed on the first setting surface of the carrier, and the active surfaces of the wafers and the electrode pads are exposed to the encapsulating gel; A support is provided on the second setting surface of the carrier, and the thermal expansion coefficient of the support is greater than the thermal expansion coefficient of the carrier; and a circuit redistribution structure layer is formed on the surface of the packaging colloid and the wafers. The active surface completes the semiconductor package.
根據本創作的製法，因為在形成該線路重佈結構層的步驟之前，係將該支撐件結合於該承載件，且該支撐件的熱膨脹係數大於該承載件的熱膨脹係數，故在形成該線路重佈結構層的步驟中，該支撐件的體積也在製程溫度的影響下往該承載件翹曲方向之反向形變，進而有效抑制該承載件與該封裝膠體的翹曲形變，讓該封裝膠體保持整體平整性，以利該線路重佈結構層結合於該封裝膠體的表面與該等晶片之該等主動面，確保本創作之晶片與線路重佈結構層的連線品質。 According to the production method of the present invention, because the supporting member is bonded to the bearing member before the step of forming the structural layer of the circuit, and the thermal expansion coefficient of the supporting member is greater than that of the bearing member, the circuit is being formed. In the step of redeploying the structure layer, the volume of the support member is also deformed in the reverse direction of the warping direction of the carrier under the influence of the process temperature, thereby effectively suppressing the warpage deformation of the carrier and the packaging colloid, so that the package The colloid maintains the overall flatness, so that the circuit redistribution structure layer is combined with the surface of the packaging colloid and the active surfaces of the wafers to ensure the quality of the connection between the created wafer and the circuit redistribution structure layer.
10‧‧‧承載件 10‧‧‧ Carrier
11‧‧‧晶片 11‧‧‧Chip
110‧‧‧主動面 110‧‧‧ active face
111‧‧‧電極墊 111‧‧‧electrode pad
12‧‧‧離型膠層 12‧‧‧ release adhesive layer
13‧‧‧包覆膠體 13‧‧‧ coated colloid
14‧‧‧線路重佈結構層 14‧‧‧ Line redistribution structure layer
140‧‧‧絕緣基材 140‧‧‧ insulating substrate
141‧‧‧中介電連接部 141‧‧‧Intermediary electrical connection
142‧‧‧導電塊 142‧‧‧Conductive block
15‧‧‧半導體封裝件 15‧‧‧semiconductor package
20‧‧‧承載件 20‧‧‧carrying parts
200‧‧‧第一設置面 200‧‧‧first setting surface
201‧‧‧第二設置面 201‧‧‧Second setting surface
21‧‧‧晶片 21‧‧‧Chip
210‧‧‧主動面 210‧‧‧ Active face
211‧‧‧電極墊 211‧‧‧electrode pad
22‧‧‧離型膠層 22‧‧‧Release adhesive layer
23‧‧‧包覆膠體 23‧‧‧ coated colloid
24‧‧‧封裝膠體 24‧‧‧ encapsulated colloid
25‧‧‧支撐件 25‧‧‧ support
26‧‧‧線路重佈結構層 26‧‧‧Line redistribution structure layer
260‧‧‧絕緣基材 260‧‧‧ insulating substrate
261‧‧‧中介電連接部 261‧‧‧Intermediary electrical connection
262‧‧‧導電塊 262‧‧‧Conductive block
27‧‧‧半導體封裝件 27‧‧‧Semiconductor package
28‧‧‧結合層 28‧‧‧Combination layer
29‧‧‧半導體封裝件 29‧‧‧semiconductor package
圖1：習知半導體封裝件之製法所提供的承載墊與晶片的示意圖。 FIG. 1 is a schematic diagram of a carrier pad and a wafer provided by a conventional method for manufacturing a semiconductor package.
圖2：習知半導體封裝件之製法形成一包覆膠體的示意圖。 FIG. 2 is a schematic diagram of forming a coating colloid according to a conventional method for manufacturing a semiconductor package.
圖3：習知半導體封裝件之製法形成一封裝膠體的示意圖。 FIG. 3 is a schematic diagram of forming a packaging gel by a conventional method for manufacturing a semiconductor package.
圖4：習知半導體封裝件之製法形成一線路重佈結構層後所完成習知半導體封裝件的示意圖。 FIG. 4 is a schematic diagram of a conventional semiconductor package completed after a conventional redistribution structure layer is formed by a conventional semiconductor package manufacturing method.
圖5：習知半導體封裝件之翹曲型態示意圖。 FIG. 5 is a schematic diagram of a warped shape of a conventional semiconductor package.
圖6：本創作半導體封裝件之製法所提供的承載墊與晶片的示意圖。 FIG. 6 is a schematic diagram of a carrier pad and a wafer provided by the method for manufacturing a semiconductor package.
圖7：本創作半導體封裝件之製法形成一包覆膠體的示意圖。 FIG. 7 is a schematic diagram of forming a coating colloid according to the method for manufacturing a semiconductor package.
圖8：本創作半導體封裝件之製法形成一封裝膠體的示意圖。 FIG. 8 is a schematic diagram of forming a packaging colloid according to the method for manufacturing a semiconductor package.
圖9：本創作半導體封裝件之製法形成一支撐件的示意圖。 FIG. 9 is a schematic diagram of forming a supporting member according to the method for manufacturing a semiconductor package.
圖10：本創作半導體封裝件之製法形成一線路重佈結構層後所完成本創作半導體封裝件的示意圖。 FIG. 10 is a schematic diagram of the completed semiconductor package after a circuit redistribution structure layer is formed by the manufacturing method of the creative semiconductor package.
圖11：本創作半導體封裝件之製法的另一實施例在該承載件與該支撐件之間形成一結合層的示意圖。 FIG. 11 is a schematic diagram of forming a bonding layer between the carrier and the support according to another embodiment of the method for manufacturing a semiconductor package.
圖12：本創作半導體封裝件另一實施例的示意圖。 FIG. 12 is a schematic diagram of another embodiment of the inventive semiconductor package.
請參考圖6，本創作半導體封裝件的製法的第一實施例係準備一承載件20，該承載件20可為一片體，如：圓形片體或方形片體，但不以此為限。該承載件20具有相對的一第一設置面200與一第二設置面201，且該第一設置面200與該第二設置面201位於相異的平面，例如該第一設置面200為頂面而該第二設置面201為底面，但不以此為限。該第一設置面200設有分離設置的複數晶片21，各該晶片21包含有相對的一第一表面與一第二表面，各該晶片21係以其第一表面透過一膠層22固定於該承載件20的第一設置面200，各該晶片21的第二表面為一主動面210，該主動面210形成有複數電極墊211。其中，該膠層22可為熱化離型膠層，但不以此為限。 Please refer to FIG. 6. In the first embodiment of the method for manufacturing a semiconductor package, a carrier 20 is prepared. The carrier 20 may be a single piece, such as a circular piece or a square piece, but not limited thereto. . The carrier 20 has a first setting surface 200 and a second setting surface 201 opposite to each other, and the first setting surface 200 and the second setting surface 201 are located on different planes. For example, the first setting surface 200 is a top. The second setting surface 201 is a bottom surface, but is not limited thereto. The first setting surface 200 is provided with a plurality of wafers 21 separated from each other. Each of the wafers 21 includes a first surface and a second surface opposite to each other. Each of the wafers 21 is fixed to the first surface through an adhesive layer 22. A first setting surface 200 of the carrier 20, and a second surface of each of the wafers 21 are an active surface 210, and the active surface 210 is formed with a plurality of electrode pads 211. The adhesive layer 22 may be a thermal release adhesive layer, but is not limited thereto.
請參考圖7，在該承載件20的第一設置面200上形成一包覆膠體23，該包覆膠體23包覆該等晶片21及其主動面210與電極墊211。請配合參考圖8，移除部分的該包覆膠體以形成一封裝膠體24，該封裝膠體24的表面以及各該晶片21的主動面210與電極墊211的表面位於同一平面，各該晶片21的主動面210與電極墊211露出該封裝膠體24。 Referring to FIG. 7, a covering colloid 23 is formed on the first setting surface 200 of the carrier 20, and the covering colloid 23 covers the wafers 21 and their active surfaces 210 and electrode pads 211. With reference to FIG. 8, a part of the coating gel is removed to form a packaging gel 24. The surface of the packaging gel 24 and the active surface 210 of each of the wafers 21 and the surface of the electrode pad 211 are located on the same plane, and each of the wafers 21 The active surface 210 and the electrode pad 211 expose the encapsulant 24.
請參考圖9，在該承載件20的第二設置面201設置一支撐件25，該支撐件25可為一片體，且該支撐件25的熱膨脹係數(coefficient of thermal expansion,CTE)大於該承載件20的熱膨脹係數，熱膨脹係數的單位是ppm/℃，其中ppm是百萬分率(parts per million)。 Please refer to FIG. 9, a supporting member 25 is provided on the second setting surface 201 of the supporting member 20. The supporting member 25 may be a piece of body, and the coefficient of thermal expansion (CTE) of the supporting member 25 is greater than the bearing. The coefficient of thermal expansion of the component 20 is in ppm / ° C, where ppm is parts per million.
請參考圖10，於該封裝膠體24的表面與該等晶片21之主動面210進行線路重佈層製程，以形成一線路重佈結構層(Re-Distribution Layer,RDL)26，完成本創作的半導體封裝件27。其中，該線路重佈結構層26包含有絕緣基材260、複數中介電連接部261與複數導電塊262，該絕緣基材260形成於該封裝膠體24的表面與該等晶片21之主動面210，該等中介電連接部261形成在該絕緣基材260內且分別電性連接該等晶片21的電極墊211，各該中介電連接部261外露該絕緣基材260的表面，該等導電塊262分別形成於該等中介電連接部261外露於該絕緣基材260之表面以分別電性連接該等中介電連接部261。 Please refer to FIG. 10, a circuit redistribution layer process is performed on the surface of the encapsulant 24 and the active surfaces 210 of the chips 21 to form a circuit redistribution layer (RDL) 26. Semiconductor package 27. The circuit redistribution structure layer 26 includes an insulating substrate 260, a plurality of inter-dielectric connection portions 261, and a plurality of conductive blocks 262. The insulating substrate 260 is formed on the surface of the encapsulant 24 and the active surface 210 of the wafers 21. The dielectric connecting portions 261 are formed in the insulating substrate 260 and are electrically connected to the electrode pads 211 of the wafers 21 respectively. Each of the dielectric connecting portions 261 exposes the surface of the insulating substrate 260, and the conductive blocks 262 are respectively formed on the dielectric connection portions 261 exposed on the surface of the insulating base material 260 to electrically connect the dielectric connection portions 261 respectively.
於該承載件20的第二設置面201設置該支撐件25的步驟中，請參考圖11，本創作第二實施例可先在該第二設置面201設置一結合層28，該結合層28可為熱解膠膜層(thermal release tape)或可由UV光照射的膠膜，接著在將該支撐件25設置在該結合層28上，換言之，本創作第二實施例的該支撐件25係透過該結合層28設置在該承載件20的該第二設置面201。本創作第二實施例透過該結合層28的設置，可使該支撐件25與該承載件20更為穩固結合。請參考圖12，為本創作第二實施例包含有該結合層28的半導體封裝件29，其中該結合層28位於該承載件20與該支撐件25之間。 In the step of setting the support member 25 on the second setting surface 201 of the carrier 20, please refer to FIG. 11. In the second embodiment of the present invention, a bonding layer 28 may be set on the second setting surface 201 first. The bonding layer 28 It can be a thermal release tape or a film that can be irradiated with UV light, and then the support member 25 is disposed on the bonding layer 28. In other words, the support member 25 of the second embodiment of the present invention is The bonding layer 28 is disposed on the second setting surface 201 of the carrier 20. In the second embodiment of the present invention, the supporting member 25 and the supporting member 20 can be more firmly combined through the setting of the bonding layer 28. Please refer to FIG. 12, a semiconductor package 29 including the bonding layer 28 in the second embodiment of the present invention, wherein the bonding layer 28 is located between the carrier 20 and the supporting member 25.
請參考圖10，本創作第一實施例的半導體封裝件27包含有一承載件20、一支撐件25、複數晶片21、封裝膠體24與一線路重佈結構層26。該承載件20具有相對的第一設置面200與第二設置面201，該支撐件25設置於該第二設置面201。該等晶片21分離設置於該第一設置面200，其中，各該晶片21包含有相對的一第一表面與一第二表面，各該晶片21係以其第一表面透過一膠層22固定於該承載件20，各該晶片21的第二表面為一主動面210，該主動面210形成有複數電極墊211，該主動面210與該等電極墊211的表面位於同一平面。該封裝膠體24形成在該承載件20的第一設置面200且包覆該等晶片21的外周面，該 封裝膠體24的表面以及該等晶片21的主動面210與電極墊211的表面位於同一平面，各該晶片21的主動面210與電極墊211外露於該封裝膠體24的表面，該支撐件25的分布區域可涵蓋該封裝膠體24。該線路重佈結構層26形成於該封裝膠體24的表面與該等晶片21之主動面210，該線路重佈結構層26包含有一絕緣基材260、複數中介電連接部261與複數導電塊262，該等中介電連接部261形成在該絕緣基材260內且分別電性連接該等晶片21的電極墊211，該等導電塊262可為焊球或金屬柱，其分別形成於該等中介電連接部261外露於該絕緣基材260之表面以電性連接該等中介電連接部261。 Referring to FIG. 10, the semiconductor package 27 of the first embodiment of the present invention includes a carrier 20, a support 25, a plurality of wafers 21, a packaging gel 24, and a circuit redistribution structure layer 26. The supporting member 20 has a first setting surface 200 and a second setting surface 201 opposite to each other. The supporting member 25 is disposed on the second setting surface 201. The wafers 21 are separately disposed on the first setting surface 200, wherein each of the wafers 21 includes a first surface and a second surface opposite to each other, and each of the wafers 21 is fixed by a first surface thereof through an adhesive layer 22 On the carrier 20, the second surface of each of the wafers 21 is an active surface 210. The active surface 210 is formed with a plurality of electrode pads 211, and the active surface 210 is located on the same plane as the surfaces of the electrode pads 211. The encapsulant 24 is formed on the first installation surface 200 of the carrier 20 and covers the outer peripheral surfaces of the wafers 21. The surface of the packaging gel 24 and the active surfaces 210 of the wafers 21 and the electrode pads 211 are on the same plane. The active surface 210 and the electrode pads 211 of the wafers 21 are exposed on the surface of the packaging gels 24. The distribution area may cover the encapsulant 24. The circuit redistribution structure layer 26 is formed on the surface of the encapsulation gel 24 and the active surfaces 210 of the wafers 21. The circuit redistribution structure layer 26 includes an insulating substrate 260, a plurality of inter-dielectric connection portions 261, and a plurality of conductive blocks 262. The dielectric connection portions 261 are formed in the insulating base material 260 and are electrically connected to the electrode pads 211 of the wafers 21 respectively. The conductive blocks 262 may be solder balls or metal pillars, which are respectively formed in the intermediaries. The electrical connection portion 261 is exposed on the surface of the insulating substrate 260 to electrically connect the dielectric connection portions 261.
請參考圖12，本創作第二實施例的半導體封裝件29進一步包含有結合層28，該結合層28位於該承載件20與該支撐件25之間。 Please refer to FIG. 12. The semiconductor package 29 according to the second embodiment of the present invention further includes a bonding layer 28. The bonding layer 28 is located between the carrier 20 and the support 25.
本創作的承載件20與支撐件25分別具有相異的熱膨脹係數，舉例來說，該承載件20的熱膨脹係數可小於8ppm/℃，該支撐件25的熱膨脹係數可大於或等於8ppm/℃，具體來說，該支撐件25的熱膨脹係數較佳為大於或等於8ppm/℃以及小於或等於10ppm/℃。該承載件20與該支撐件25可為相同材質或不同材質製成的構件，例如為玻璃、陶瓷或矽製成的構件。該承載件20的厚度小於該支撐件25的厚度，例如該承載件20的厚度可為該支撐件25的厚度的二分之一，於一實施例中，該承載件20的厚度可為1微米，該支撐件25的厚度可為2微米。 The carrier 20 and the support 25 have different thermal expansion coefficients. For example, the thermal expansion coefficient of the carrier 20 may be less than 8 ppm / ° C, and the thermal expansion coefficient of the support 25 may be greater than or equal to 8 ppm / ° C. Specifically, the thermal expansion coefficient of the support member 25 is preferably 8 ppm / ° C or more and 10 ppm / ° C or less. The supporting member 20 and the supporting member 25 may be members made of the same material or different materials, for example, members made of glass, ceramic, or silicon. The thickness of the supporting member 20 is smaller than the thickness of the supporting member 25. For example, the thickness of the supporting member 20 may be a half of the thickness of the supporting member 25. In one embodiment, the thickness of the supporting member 20 may be 1 The thickness of the supporting member 25 can be 2 microns.
根據本創作之該承載件20與該支撐件25的結合結構，因為該支撐件25的熱膨脹係數大於該承載件20的熱膨脹係數，因此在形成該線路重佈結構層26的步驟中，該支撐件25也在製程溫度的影響下其體積因熱脹而往該承載件20翹曲方向之反向形變，故該支撐件25的形變方式能有效抑制該承載件20與該封裝膠體24的翹曲形變，避免該線路重佈結構層26的中介電連接部261與該等晶片21之電極墊211之間的相對位置產生偏差，進而確保連線品質。 According to the combined structure of the supporting member 20 and the supporting member 25 according to the present creation, because the thermal expansion coefficient of the supporting member 25 is greater than the thermal expansion coefficient of the supporting member 20, in the step of forming the circuit redistribution structural layer 26, the support The component 25 is also deformed in the direction of warpage of the carrier 20 due to thermal expansion due to thermal expansion. Therefore, the deformation of the support member 25 can effectively suppress the warpage of the carrier 20 and the encapsulant 24. The bending deformation prevents the relative position between the dielectric connection portion 261 of the circuit redistribution structure layer 26 and the electrode pads 211 of the wafers 21 from deviating, thereby ensuring the connection quality.
Claims (18)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW105129920A TWI620256B (en) | 2016-09-14 | 2016-09-14 | Semiconductor package and manufacturing method thereof |
| CN201610913497.5A CN107818953A (en) | 2016-09-14 | 2016-10-20 | Semiconductor package and fabrication method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW105129920A TWI620256B (en) | 2016-09-14 | 2016-09-14 | Semiconductor package and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201810456A TW201810456A (en) | 2018-03-16 |
| TWI620256B true TWI620256B (en) | 2018-04-01 |
Family
ID=61600835
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW105129920A TWI620256B (en) | 2016-09-14 | 2016-09-14 | Semiconductor package and manufacturing method thereof |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN107818953A (en) |
| TW (1) | TWI620256B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20220181167A1 (en) * | 2020-12-07 | 2022-06-09 | Innolux Corporation | Manufacturing method of package structure |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201419394A (en) * | 2012-11-07 | 2014-05-16 | Taiwan Semiconductor Mfg | Carrier wafer and method for fabricating the same, method of packaging semiconductor device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8723185B2 (en) * | 2010-11-30 | 2014-05-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reducing wafer distortion through a high CTE layer |
| US9502360B2 (en) * | 2012-01-11 | 2016-11-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stress compensation layer for 3D packaging |
| TWI524437B (en) * | 2013-11-06 | 2016-03-01 | 矽品精密工業股份有限公司 | Method of fabricating semiconductor package |
| CN105225974A (en) * | 2015-11-05 | 2016-01-06 | 南通富士通微电子股份有限公司 | Method for packing |
-
2016
- 2016-09-14 TW TW105129920A patent/TWI620256B/en active
- 2016-10-20 CN CN201610913497.5A patent/CN107818953A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201419394A (en) * | 2012-11-07 | 2014-05-16 | Taiwan Semiconductor Mfg | Carrier wafer and method for fabricating the same, method of packaging semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201810456A (en) | 2018-03-16 |
| CN107818953A (en) | 2018-03-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI420640B (en) | Semiconductor package device, semiconductor package structure, and method for fabricating the same | |
| TWI643307B (en) | Electronic package and method for fabricating the same | |
| KR101605600B1 (en) | Manufacturing method of semiconductor device and semiconductor device thereof | |
| US20140042638A1 (en) | Semiconductor package and method of fabricating the same | |
| TWI463619B (en) | Semiconductor package and method of forming the same | |
| KR102391517B1 (en) | semiconductor device package and method of fabricating the same | |
| TWI652774B (en) | Electronic package manufacturing method | |
| TW201903992A (en) | Package structure and manufacturing method thereof | |
| TW201436161A (en) | Semiconductor package and method of manufacture | |
| TW201507075A (en) | Semiconductor package and manufacturing method thereof | |
| TW201812932A (en) | Electronic package and method for fabricating the same | |
| TW201901908A (en) | Electronic package and its manufacturing method | |
| TWI514484B (en) | Semicondutor device and method for manufacturing same | |
| TWI488270B (en) | Semiconductor package and method of forming the same | |
| WO2018133057A1 (en) | Packaging method for wafer-level chip, and package | |
| TW201903980A (en) | Electronic package and its manufacturing method | |
| TWI620256B (en) | Semiconductor package and manufacturing method thereof | |
| TWI717896B (en) | High heat dissipation stacked semiconductor package structure and packing method of the same | |
| TW201904011A (en) | Electronic package and method of manufacture thereof | |
| TW201515161A (en) | Package assembly and manufacturing method thereof | |
| TWI621223B (en) | Electronic package and the manufacture thereof | |
| TWI492344B (en) | Semiconductor package and method of manufacture | |
| JPH11214448A (en) | Semiconductor device and method for manufacturing semiconductor device | |
| TW201810546A (en) | Electronic package structure and the manufacture thereof | |
| TWI736736B (en) | Electronic package and method of manufacture |