TWI615956B - Radiation sensor and method for fabricating the same - Google Patents
Radiation sensor and method for fabricating the same Download PDFInfo
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- TWI615956B TWI615956B TW104135939A TW104135939A TWI615956B TW I615956 B TWI615956 B TW I615956B TW 104135939 A TW104135939 A TW 104135939A TW 104135939 A TW104135939 A TW 104135939A TW I615956 B TWI615956 B TW I615956B
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
- H01L27/14605—Structural or functional details relating to the position of the pixel elements, e.g. smaller pixel elements in the center of the imager compared to pixel elements at the periphery
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1462—Coatings
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01T—MEASUREMENT OF NUCLEAR OR X-RADIATION
- G01T1/00—Measuring X-radiation, gamma radiation, corpuscular radiation, or cosmic radiation
- G01T1/16—Measuring radiation intensity
- G01T1/20—Measuring radiation intensity with scintillation detectors
- G01T1/208—Circuits specially adapted for scintillation detectors, e.g. for the photo-multiplier section
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01T—MEASUREMENT OF NUCLEAR OR X-RADIATION
- G01T1/00—Measuring X-radiation, gamma radiation, corpuscular radiation, or cosmic radiation
- G01T1/16—Measuring radiation intensity
- G01T1/20—Measuring radiation intensity with scintillation detectors
- G01T1/2018—Scintillation-photodiode combinations
- G01T1/20184—Detector read-out circuitry, e.g. for clearing of traps, compensating for traps or compensating for direct hits
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01T—MEASUREMENT OF NUCLEAR OR X-RADIATION
- G01T1/00—Measuring X-radiation, gamma radiation, corpuscular radiation, or cosmic radiation
- G01T1/16—Measuring radiation intensity
- G01T1/24—Measuring radiation intensity with semiconductor detectors
- G01T1/241—Electrode arrangements, e.g. continuous or parallel strips or the like
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14632—Wafer-level processed structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
- H01L27/14658—X-ray, gamma-ray or corpuscular radiation imagers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
- H01L27/14658—X-ray, gamma-ray or corpuscular radiation imagers
- H01L27/14663—Indirect radiation imagers, e.g. using luminescent members
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
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Abstract
一種輻射感測器包括:一閃爍層,該閃爍層經組態以在與電離輻射相互作用時發射光子;及一光偵測器,其按次序包括一第一電極、一感光層,及接近於該閃爍層而安置之一可透射光子之第二電極。該感光層經組態以在與該等光子之一部分相互作用時產生電子電洞對。該輻射感測器包括:像素電路,其電連接至該第一電極且經組態以量測指示在該感光層中所產生之該等電子電洞對之一成像信號;及一平坦化層,其安置於該像素電路上在該第一電極與該像素電路之間,以使得該第一電極高於包括該像素電路之一平面。該第一電極及該第二電極中之至少一者之一表面至少部分地重疊於該像素電路,且具有高於該像素電路之特徵之一表面反曲。該表面反曲具有大於1/2微米之曲率半徑。 A radiation sensor includes: a scintillation layer configured to emit photons when interacting with ionizing radiation; and a photodetector including a first electrode, a photosensitive layer, and close in order A second electrode capable of transmitting photons is disposed in the scintillation layer. The photosensitive layer is configured to create an electron hole pair when interacting with a portion of the photons. The radiation sensor includes: a pixel circuit electrically coupled to the first electrode and configured to measure an imaging signal indicative of one of the pairs of electron holes generated in the photosensitive layer; and a planarization layer And disposed between the first electrode and the pixel circuit on the pixel circuit such that the first electrode is higher than a plane including the pixel circuit. A surface of at least one of the first electrode and the second electrode at least partially overlaps the pixel circuit and has a surface recursion higher than one of the features of the pixel circuit. The surface recursion has a radius of curvature greater than 1/2 micron.
Description
本發明大體而言係關於經設計以偵測入射電離輻射以便形成影像的裝置。 The present invention generally relates to devices designed to detect incident ionizing radiation to form an image.
本申請案與以下申請案有關且依據35 U.S.C.119的規定主張以下申請案之優先權:2009年6月17日申請之題為「PHOTODIODE AND OTHER SENSOR STRUCTURES IN FLAT-PANEL X-RAY IMAGERS AND METHOD FOR IMPROVING TOPOLOGICAL UNIFORMITY OF THE PHOTODIODE AND OTHER SENSOR STRUCTURES IN FLAT-PANEL X-RAY IMAGERS BASED ON THIN-FILM ELECTRONICS」之美國臨時專利申請案61/213,530,該案之全部揭示內容藉此以引用的方式併入本文中。 This application is related to the following application and claims the priority of the following application in accordance with the provisions of 35 USC119: "PHOTODIODE AND OTHER SENSOR STRUCTURES IN FLAT-PANEL X-RAY IMAGERS AND METHOD FOR" IMPROVING TOPOLOGICAL UNIFORMITY OF THE PHOTODIODE AND OTHER SENSOR STRUCTURES IN FLAT-PANEL X-RAY IMAGERS BASED ON THIN-FILM ELECTRONICS, US Provisional Patent Application No. 61/213, 530, the entire disclosure of which is hereby incorporated by reference. in.
本發明係依據由美國國家衛生研究院授予之EB000558在政府支持下做出。美國政府對本發明具有特定權利。 This invention was made with government support under EB000558 awarded by the National Institutes of Health . The U.S. Government has certain rights in the invention.
在x光成像領域中,基於主動式矩陣成像陣列之成像器常用於眾多醫療及非醫療應用中。除非本文中另有指示,否則術語「主動式矩陣」將用以指代憑藉開關來定址成像像素之二維柵格之原理,其中每一像素中有一定址開關。基於主動式矩陣成像陣列之成像器將稱作 「主動式矩陣平面板成像器」(AMFPI)或,更簡明地,稱作「主動式矩陣成像器」。另外,將可互換地使用術語「主動式矩陣陣列」與「主動式矩陣成像陣列」。 In the field of x-ray imaging, imagers based on active matrix imaging arrays are commonly used in many medical and non-medical applications. Unless otherwise indicated herein, the term " active matrix " will be used to refer to the principle of addressing a two-dimensional grid of imaging pixels by means of switches, with a positional switch in each pixel. An imager based on an active matrix imaging array will be referred to as an " active matrix planar panel imager " (AMFPI) or, more simply, as an " active matrix imager. " In addition, the terms " active matrix array " and " active matrix imaging array " will be used interchangeably.
AMFPI通常併有一單一陣列,包括對電離輻射之效應具高度抵抗力之材料。然而,AMFPI有時包括並列排列之兩個鄰近陣列,或排列成正方形或矩形之四個鄰近陣列。主動式矩陣成像器具有普遍性及有用性的一原因為:可以可接受之良率及以合理之成本、以顯著超出用習知晶態矽(c-Si)技術可能達成之大小的大小來製造陣列。在c-Si技術之狀況下,像素化成像陣列(諸如,電荷耦合裝置(CCD)、CMOS感測器、主動式像素感測器,及被動式像素感測器)最終受用於製造之矽晶圓之大小(目前直至約300mm)限制。由晶態矽製成之CCD、CMOS感測器及主動式像素感測器及被動式像素感測器通常被製造成具有小於約4cm×4cm之尺寸。雖然已將此等裝置製造成具有大至約20cm×20cm之尺寸,但此等裝置難以生產且生產成本高。又,雖然可藉由平鋪小面積c-Si陣列來製造大面積裝置,但此方法引入了額外顯著的工程問題、挑戰及成本。在AMFPI之狀況下,雖然可使主動式矩陣陣列小至兩個像素×兩個像素(其將小於1cm×1cm),但用於AMFPI之主動式矩陣陣列通常以在約10cm×10cm直至約43cm×43cm之範圍內之大小來製造,此範圍大大超過像素化c-Si成像陣列之範圍。此外,不存在禁止產生甚至更大的主動式矩陣成像陣列(例如,相當於最大的主動式矩陣液晶顯示器(AMLCD)之大小,最大主動式矩陣液晶顯示器已被製造成在對角線上大至約108吋)之技術原因。 AMFPI usually has a single array, including materials that are highly resistant to the effects of ionizing radiation. However, AMFPI sometimes includes two adjacent arrays arranged side by side, or four adjacent arrays arranged in a square or rectangular shape. One reason for the versatility and usefulness of active matrix imagers is that they can be manufactured with acceptable yields and at reasonable cost, significantly beyond the size that can be achieved with conventional crystalline 矽 (c-Si) technology. . In the case of c-Si technology, pixelated imaging arrays (such as charge-coupled devices (CCDs), CMOS sensors, active pixel sensors, and passive pixel sensors) are ultimately used in manufacturing wafers. The size (currently up to about 300mm) is limited. CCDs, CMOS sensors and active pixel sensors and passive pixel sensors made of crystalline germanium are typically fabricated to have dimensions of less than about 4 cm x 4 cm. While these devices have been fabricated to have dimensions up to about 20 cm x 20 cm, such devices are difficult to produce and costly to produce. Also, while large area devices can be fabricated by tiling small area c-Si arrays, this approach introduces additional significant engineering issues, challenges, and costs. In the case of AMFPI, although the active matrix array can be as small as two pixels x two pixels (which will be less than 1 cm x 1 cm), the active matrix array for AMFPI typically ranges from about 10 cm x 10 cm up to about 43 cm. Manufactured in the range of ×43 cm, which greatly exceeds the range of pixelated c-Si imaging arrays. In addition, there is no ban on the generation of even larger active matrix imaging arrays (eg, equivalent to the largest active matrix liquid crystal display (AMLCD) size, the largest active matrix liquid crystal display has been fabricated to be on the diagonal up to about 108吋) Technical reasons.
在主動式矩陣成像陣列中,憑藉薄膜開關來定址成像像素之二維柵格。該陣列包括一薄基板,在該薄基板上製造成像像素。每一像素併有一電路,在該電路中,一定址開關連接至某形式之像素儲存電容器。每一開關通常採取薄膜電晶體(TFT)之形式,但亦可採取薄膜 二極體或兩個或兩個以上薄膜二極體之組合的形式。雖然簡單的陣列設計對每一像素僅併有單一開關以用於定址之目的,但更複雜的設計可在像素中包括額外電路元件,該等額外電路元件用以改良效能及/或擴展成像器能力。此外,可在該等像素外部在陣列基板上併有其他電路元件。此等元件可經組態以執行諸如以下各項之功能:控制閘極位址線上之電壓,多工來自資料線之信號,或用於與陣列之操作有關之其他目的。 In an active matrix imaging array, a two-dimensional grid of imaging pixels is addressed by means of a membrane switch. The array includes a thin substrate on which imaging pixels are fabricated. Each pixel has a circuit in which the address switch is connected to some form of pixel storage capacitor. Each switch is usually in the form of a thin film transistor (TFT), but can also be used as a thin film. A form of a diode or a combination of two or more thin film diodes. While a simple array design has only a single switch per pixel for addressing purposes, a more complex design can include additional circuit components in the pixel to improve performance and/or extend the imager. ability. In addition, other circuit components can be placed on the array substrate outside of the pixels. These components can be configured to perform functions such as controlling the voltage on the gate address line, multiplexing the signal from the data line, or for other purposes related to the operation of the array.
用於陣列製造中之材料包括用以形成諸如以下各項之特徵的各種金屬:位址線、至位址線之接點、跡線、介層孔、電極表面及阻光表面,以及TFT之源極、汲極及閘極。可使用諸如鋁、銅、鉻、鉬、鉭、鈦、鎢之金屬、氧化銦錫及金,以及此等材料之合金,諸如TiW、MoCr及AlCu。在製造期間沈積至陣列上之給定金屬層之厚度可在約10nm至若干μm之範圍內。鈍化層可包括諸如氮氧化矽(Si2N2O)、氮化矽(Si3N4)、聚醯亞胺及苯并環丁烯聚合物(BCB)之材料。在製造期間沈積至陣列表面上之給定鈍化層之厚度可在約100nm直至10μm之範圍內。裝置(諸如,TFT及電容器)中之介電質可包括諸如氮化矽(Si3N4)、二氧化矽(SiO2)、非晶矽及非晶矽氮化物(a-Si3N4:H)之材料。在製造期間沈積至陣列表面上之給定介電層之厚度可在約1nm至若干μm之範圍內。通常,使用多個金屬層、鈍化層及介電層來製造一陣列中之各種電路元件。 Materials used in array fabrication include various metals used to form features such as address lines, contacts to address lines, traces, via holes, electrode surfaces and light blocking surfaces, and TFTs. Source, drain and gate. Metals such as aluminum, copper, chromium, molybdenum, niobium, titanium, tungsten, indium tin oxide, and gold, and alloys of such materials, such as TiW, MoCr, and AlCu, can be used. The thickness of a given metal layer deposited onto the array during fabrication can range from about 10 nm to several μm. The passivation layer may include materials such as bismuth oxynitride (Si 2 N 2 O), cerium nitride (Si 3 N 4 ), polyimine, and benzocyclobutene polymer (BCB). The thickness of a given passivation layer deposited onto the surface of the array during fabrication can range from about 100 nm up to 10 μm. Dielectrics in devices such as TFTs and capacitors may include, for example, tantalum nitride (Si 3 N 4 ), hafnium oxide (SiO 2 ), amorphous germanium, and amorphous germanium nitride (a-Si 3 N 4 ). :H) Material. The thickness of a given dielectric layer deposited onto the surface of the array during fabrication can range from about 1 nm to several μm. Typically, multiple metal layers, passivation layers, and dielectric layers are used to fabricate the various circuit elements in an array.
用於TFT(及二極體開關)之半導體材料最通常為氫化非晶矽(a-Si),但亦可為微晶矽、多晶矽(多晶-Si)、硫族化物或硒化鎘(CdSe),所有此等材料適合於大面積處理,從而允許製造大面積陣列。在此狀況下,基板可由諸如以下各項之材料製成:玻璃(諸如,康寧(Corning)7059、1737F、1737G,約1mm厚),或石英(約1mm厚),或不鏽鋼薄片(約25至500μm厚)。陣列電路之製造涉及以下操作:使用 區域沈積技術在基板上沈積連續材料層(諸如,半導體層、金屬層、介電層及鈍化層),區域沈積技術諸如電漿增強化學氣相沈積(PECVD)、低壓化學氣相沈積(LPCVD)、化學氣相沈積(CVD)、物理氣相沈積(PVD)、濺鍍及旋塗。在多晶-Si之狀況下,一用於生產此半導體之常見方法為:憑藉準分子雷射使先前所沈積之a-Si材料結晶。另外,使用光微影與蝕刻技術之組合形成電路之特徵(諸如TFT、二極體、光電二極體、電容器、跡線、介層孔、位址線,及至位址線之接點的彼等特徵)。 The semiconductor material used for TFT (and diode switching) is most usually hydrogenated amorphous germanium (a-Si), but may also be microcrystalline germanium, polycrystalline germanium (polycrystalline-Si), chalcogenide or cadmium selenide ( CdSe), all of these materials are suitable for large area processing, allowing for the fabrication of large area arrays. In this case, the substrate may be made of a material such as glass (such as Corning 7059, 1737F, 1737G, about 1 mm thick), or quartz (about 1 mm thick), or stainless steel sheet (about 25 to 500 μm thick). The manufacture of array circuits involves the following operations: use Area deposition techniques deposit a continuous layer of material (such as a semiconductor layer, a metal layer, a dielectric layer, and a passivation layer) on a substrate, and regional deposition techniques such as plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD) , chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering and spin coating. In the case of poly-Si, a common method for producing such a semiconductor is to crystallize the previously deposited a-Si material by means of an excimer laser. In addition, the combination of photolithography and etching techniques is used to form features of the circuit (such as TFTs, diodes, photodiodes, capacitors, traces, vias, address lines, and contacts to the address lines). And other features).
或者,用於此等開關之半導體材料可採取適合於大面積沈積之其他材料之形式,諸如低溫a-Si、有機小分子或聚合物半導體。低溫a-Si係使用PECVD、LPCVD及PVD來沈積,而有機小分子及聚合物半導體可使用區域沈積技術或印刷技術來沈積。對於此等半導體材料,基板可為薄的及可撓性的(由諸如聚醯亞胺(PI)或聚萘二甲酸乙二酯(PEM,約25至200μm厚)之材料薄片製成)。或者,可使用玻璃、石英或不鏽鋼基板。可使用光微影、蝕刻、減色印刷及加色印刷技術中之一者或其組合來形成陣列電路之特徵。可用於TFT與其他裝置兩者之其他半導體材料包括碳奈米管及石墨薄膜。可用於TFT與其他裝置兩者之其他半導體材料包括氧化物半導體,包括(但不限於)ZnO、InGaZnO、InZnO、ZnSnO(及任何其他含Zn的氧化物)、SnO2、TiO2、Ga2O3、InGaO、In2O3及InSnO。已知此等氧化物半導體以非晶系或多晶存在,且在可用時適合於本發明。對於所有類型之半導體,材料係以其純質形式加以使用,以及以摻雜形式加以使用以提供p-型摻雜或n-型摻雜半導體材料。 Alternatively, the semiconductor materials used for such switches may take the form of other materials suitable for large area deposition, such as low temperature a-Si, organic small molecules or polymer semiconductors. Low temperature a-Si is deposited using PECVD, LPCVD, and PVD, while organic small molecules and polymer semiconductors can be deposited using either regional deposition techniques or printing techniques. For such semiconductor materials, the substrate can be thin and flexible (made of a sheet of material such as polyimine (PI) or polyethylene naphthalate (PEM, about 25 to 200 μm thick)). Alternatively, a glass, quartz or stainless steel substrate can be used. One or a combination of photolithography, etching, subtractive printing, and additive printing techniques can be used to form the features of the array circuitry. Other semiconductor materials that can be used for both TFTs and other devices include carbon nanotubes and graphite films. Other semiconductor materials that can be used for both TFTs and other devices include oxide semiconductors including, but not limited to, ZnO, InGaZnO, InZnO, ZnSnO (and any other Zn-containing oxide), SnO 2 , TiO 2 , Ga 2 O 3 , InGaO, In 2 O 3 and InSnO. These oxide semiconductors are known to exist as amorphous or polycrystalline and are suitable for use in the present invention when available. For all types of semiconductors, materials are used in their pure form and in doped form to provide p-type doped or n-type doped semiconductor materials.
TFT具有閘極、源極及汲極。在源極與汲極之間流經TFT之半導體通道之電流的量值受多種因素控制,該等因素諸如TFT通道之寬度及長度、用於通道中之半導體之遷移率、施加於閘極與源極之間的電 壓之量值及極性,及源極與汲極之間的電壓差。對施加於閘極之電壓的操縱允許使電晶體高度傳導(描述為「接通」)或高度非傳導(描述為「斷開」)。 The TFT has a gate, a source, and a drain. The magnitude of the current flowing between the source and the drain through the TFT's semiconductor channel is controlled by a number of factors such as the width and length of the TFT channel, the mobility of the semiconductor used in the channel, and the application to the gate. Electricity between sources The magnitude and polarity of the voltage, and the voltage difference between the source and the drain. Manipulation of the voltage applied to the gate allows the transistor to be highly conductive (described as "on") or highly non-conductive (depicted as "off").
圖1至圖4展示a-Si及多晶-Si TFT之實例。圖1為說明a-Si TFT之一形式之結構的示意圖式。圖2為對應於由圖1中之線框指示之平面的位置的示意性橫截面圖。此a-Si TFT之結構之對稱性使得對於線框之沿著電晶體之寬度的任何位置,此橫截面圖很大程度上將保持不變。圖3為說明多晶-Si TFT之一形式之結構的示意圖式。所展示之版本具有單一閘極,但兩個或兩個以上閘極亦係可能的。圖4為對應於由圖3中之線框指示之平面的位置的示意性橫截面圖。與圖1及圖2中所說明之a-Si TFT相比較,圖3及圖4中所說明之多晶-Si TFT由於介層孔之存在而具有較低程度之對稱性,以致對於線框之沿著電晶體之寬度的其他位置,電晶體之橫截面圖將顯著地變化。 1 to 4 show examples of a-Si and poly-Si TFTs. Fig. 1 is a schematic view showing the structure of one form of an a-Si TFT. Figure 2 is a schematic cross-sectional view corresponding to the position of the plane indicated by the wire frame in Figure 1. The symmetry of the structure of the a-Si TFT is such that the cross-sectional view will remain largely unchanged for any position of the wireframe along the width of the transistor. Fig. 3 is a schematic view showing the structure of one form of a polycrystalline-Si TFT. The version shown has a single gate, but two or more gates are also possible. Figure 4 is a schematic cross-sectional view corresponding to the position of the plane indicated by the wire frame in Figure 3. Compared with the a-Si TFTs illustrated in FIGS. 1 and 2, the poly-Si TFTs illustrated in FIGS. 3 and 4 have a lower degree of symmetry due to the presence of via holes, so that for the wire frame At other locations along the width of the transistor, the cross-sectional view of the transistor will vary significantly.
主動式矩陣成像器通常包括:(a)主動式矩陣成像陣列;(b)上覆該陣列之材料層,其用作x光轉換器;(c)外部電子器件,其憑藉定位於資料位址線及閘極位址線之末端的接觸墊而連接至該陣列。此等電子器件中之一些電子器件極接近於陣列之周邊而定位,且提供數位邏輯,該數位邏輯用以輔助控制操作陣列所必要之電壓及時序,以及放大、多工及數位化沿著資料位址線自像素所提取之類比信號。此等電子器件亦包括操作陣列及周邊電子器件所需之電壓供應器,以及用以允許該等電子器件與一或多個電腦之間的通信的數位電子介面;(d)一或多個電腦,其用以將控制資訊發送至該等電子器件,自該等電子器件接收數位像素資訊,使陣列之操作與來自x光源之輻射之遞送同步,且處理、顯示並儲存此成像資訊;及(e)軟體、韌體及其他編碼指令,其用於該等電腦中及該等電子器件之數位邏輯中。 An active matrix imager typically includes: (a) an active matrix imaging array; (b) a layer of material overlying the array for use as an x-ray converter; (c) an external electronic device that is positioned by a data address The contact pads at the ends of the line and gate address lines are connected to the array. Some of these electronic devices are positioned in close proximity to the perimeter of the array and provide digital logic that assists in controlling the voltage and timing necessary to operate the array, as well as amplification, multiplexing, and digitization along the data. The analog signal extracted from the pixel by the address line. The electronic devices also include voltage supplies required to operate the array and peripheral electronics, and digital electronic interfaces to allow communication between the electronic devices and one or more computers; (d) one or more computers Transmitting control information to the electronic devices, receiving digital pixel information from the electronic devices, synchronizing the operation of the array with the delivery of radiation from the x-ray source, and processing, displaying, and storing the imaging information; e) software, firmware and other coded instructions for use in the digital logic of such computers and of such electronic devices.
陣列基板、薄膜電子器件及x光轉換器均相對較薄,組合厚度為 小於1cm。此允許將此等元件連同周邊電子器件組態成一封裝,該封裝具有約1cm之緊密厚度,類似於標準x光膜片匣或電腦放射攝影(CR)片匣之厚度。具有此等輪廓之電子x光成像器常常稱為平面板成像器(FPI),此無關於成像器所基於之技術。為了與根據其他技術(諸如,平鋪式CMOS感測器)產生之平面板成像器區別,廣泛地與基於薄膜電子器件之成像器有關之描述性術語為「薄膜平面板成像器」。在使用主動式矩陣陣列之成像器之特定狀況下,術語「主動式矩陣平面板成像器(AMFPI)」係適當的。 The array substrate, the thin film electronic device, and the x-ray converter are all relatively thin, and the combined thickness is less than 1 cm. This allows these components to be configured in a package along with peripheral electronics having a compact thickness of about 1 cm, similar to the thickness of a standard x-ray film cassette or computer radiography (CR) sheet. Electronic x-ray imagers with such contours are often referred to as planar panel imagers (FPIs), regardless of the technology on which the imager is based. In contrast to planar panel imagers produced in accordance with other technologies, such as tiled CMOS sensors, the descriptive term broadly associated with film-based electronic device-based imagers is the " film flat panel imager. " In the specific case of an imager using an active matrix array, the term " active matrix flat panel imager (AMFPI) " is appropriate.
用於主動式矩陣成像陣列之像素排列成列及行。對於使用TFT開關之陣列,且對於給定像素列,沿著彼列之所有定址TFT之閘極皆連接至共同閘極位址線,其中每一像素列有一閘極線。對施加至每一閘極位址線之電壓之外部操縱因此允許控制沿著彼列之所有定址TFT之傳導性。對於給定像素行,沿著彼行之所有定址TFT之汲極連接至共同資料位址線,其中每一像素行有一資料位址線。 The pixels used in the active matrix imaging array are arranged in columns and rows. For arrays using TFT switches, and for a given column of pixels, the gates of all of the addressed TFTs along the column are connected to a common gate address line, with each pixel column having a gate line. External manipulation of the voltage applied to each gate address line thus allows control of the conductivity of all of the addressed TFTs along the column. For a given row of pixels, the drains of all of the addressed TFTs along the row are connected to a common data address line, with each pixel row having a data address line.
在AMFPI之操作期間,在x光之遞送期間,所有定址TFT皆保持非傳導,以便允許將成像信號收集於像素儲存電容器中。通常每次一像素列地藉由使列中之定址TFT傳導而讀出儲存於此等電容器中之成像信號。此允許以陣列之完全空間解析度自對應資料位址線取樣成像信號。對於給定資料位址線,每一取樣之信號由一前置放大器放大且由一類比至數位轉換器數位化,該前置放大器與該類比至數位轉換器兩者均定位於陣列外部。當然,可每次自兩個或兩個以上相繼列取樣成像信號,此減少讀出時間,但以減小之空間解析度為代價。 During operation of the AMFPI, all of the addressed TFTs remain non-conducting during x-ray delivery to allow imaging signals to be collected in the pixel storage capacitor. The imaging signals stored in these capacitors are typically read out one pixel column at a time by conducting the addressed TFTs in the columns. This allows the imaging signal to be sampled from the corresponding data address line with full spatial resolution of the array. For a given data address line, each sampled signal is amplified by a preamplifier and digitized by an analog to digital converter, both preamplifiers and analog to digital converters being positioned external to the array. Of course, the imaging signal can be sampled from two or more consecutive columns at a time, which reduces readout time, but at the expense of reduced spatial resolution.
主動式矩陣成像器最通常結合x光源操作,但其亦可與其他形式之電離輻射源一起操作,諸如伽瑪射線、電子、質子、中子、阿伐粒子及重離子。陣列之像素間距(其等於一個像素之寬度)及大小、陣列及成像器之圖框率能力、及x光源之射束能量、濾波及時間特性全都 被選擇以匹配成像應用之需要。對於許多形式之乳房成像應用(包括乳腺成像、乳房斷層組合式攝影、乳房電腦斷層攝影,及影像導引組織切片),可用具有約25μm直至約200μm之像素間距的陣列及約15至40kVp之x光射束來執行診斷性及介入性醫療成像。對於許多形式之放射攝影、螢光鏡及斷層攝影應用(包括胸部成像、胸部斷層組合式攝影、雙能量成像、血管攝影法、介入性療法、組織切片法、四肢之成像、兒科成像、心臟成像、腹部、胸部、頭部、頸部、牙齒之錐形射束電腦斷層攝影,以及放射治療中之模擬、定位、確證及品質確保),亦可用具有約75μm直至約1000μm之像素間距的陣列及約50至150kVp之x光射束來執行診斷性及介入性醫療成像。另外,可用約300μm直至約1000μm之像素間距及用於體外放射治療(external beam radiation therapy)之治療射束來執行醫療成像。在此狀況下,放射源可為Co-60源(平均能量為約1.25MeV),或來自線性加速器或產生在約3直至50MV之範圍內的百萬伏輻射的任何其他類型之加速器的輸出。亦可用近接治療源(brachytherapy source)來執行使用主動式矩陣成像器之醫療成像,諸如銫-137(137Cs)、碘-125(125I)、銥-192(192Ir)、鈀-103(103Pd)、鍶-90(90Sr)及釔-90(90Y)。另外,非醫療應用(諸如,工業放射攝影)結合上文所描述之所有放射源以及提供在幾kVp直至約15kVp之範圍內的x光能量的源來使用主動式矩陣成像器。平面板成像器之x光轉換器及相關聯之電子器件的設計及能力與陣列之設計、操作方式及各種非醫療應用之需要匹配。 Active matrix imagers are most commonly operated in conjunction with x-ray sources, but they can also operate with other forms of ionizing radiation sources such as gamma rays, electrons, protons, neutrons, Alpha particles, and heavy ions. The pixel pitch of the array (which is equal to the width of one pixel) and the size, the frame rate of the array and imager, and the beam energy, filtering, and time characteristics of the x-ray source are all selected to match the needs of the imaging application. For many forms of breast imaging applications (including mammography, breast tomosynthesis, mammography, and image-guided tissue sectioning), arrays with pixel pitches of from about 25 [mu]m up to about 200 [mu]m and x of about 15 to 40 kVp can be used. Light beams are used to perform diagnostic and interventional medical imaging. For many forms of radiography, fluoroscopy and tomography applications (including chest imaging, chest tomosynthesis, dual energy imaging, angiography, interventional therapy, tissue sectioning, limb imaging, pediatric imaging, cardiac imaging) , abdomen, chest, head, neck, conical beam computed tomography of the teeth, and simulation, positioning, confirmation and quality assurance in radiotherapy), and arrays having a pixel pitch of about 75 μm up to about 1000 μm and Diagnostic and interventional medical imaging is performed with an x-ray beam of approximately 50 to 150 kVp. In addition, medical imaging can be performed with a pixel pitch of about 300 [mu]m up to about 1000 [mu]m and a therapeutic beam for external beam radiation therapy. In this case, the source may be a Co-60 source (average energy of about 1.25 MeV), or an output from a linear accelerator or any other type of accelerator that produces millions of volts of radiation in the range of about 3 up to 50 MV. Medical imaging using an active matrix imager, such as cesium-137 ( 137 Cs), iodine-125 ( 125I ), cesium-192 ( 192 Ir), palladium-103 (can also be performed with a brachytherapy source) 103 Pd), 锶-90 ( 90 Sr) and 钇-90 ( 90 Y). Additionally, non-medical applications, such as industrial radiography, use active matrix imagers in conjunction with all of the sources described above and sources that provide x-ray energy in the range of a few kVp up to about 15 kVp. The design and capabilities of the x-ray converters and associated electronics of the planar panel imager are matched to the array design, mode of operation, and the needs of various non-medical applications.
基於轉換器偵測x光之方式,基於主動式矩陣陣列之成像器大體上可劃分成兩種類別:稱作間接偵測與直接偵測。對於間接偵測成像器,與轉換器相互作用之一些入射x光能量首先被轉換成可見光子,且此等光子之一部分隨後被轉換成儲存於陣列之像素儲存電容器中之電信號。對於直接偵測成像器,與轉換器相互作用之一些入射x光能 量直接被轉換成儲存於像素儲存電容器中之電信號。 Based on the way the converter detects x-rays, imagers based on active matrix arrays can be roughly divided into two categories: indirect detection and direct detection . For an indirect detection imager , some of the incident x-ray energy that interacts with the converter is first converted to visible light, and a portion of the photons are then converted into electrical signals stored in a pixel storage capacitor of the array. For direct detection of the imager , some of the incident x-ray energy that interacts with the converter is directly converted into an electrical signal stored in the pixel storage capacitor.
對於間接偵測成像器,轉換器採取閃爍器之形式。對於許多應用,使用摻雜鉈之碘化銫(寫作CsI:Tl或CsI:Tl+,通常經生長以便形成具有對準之針狀晶體之結構),或摻雜鋱之釓氧硫化物(寫作Gd2O2S:Tb或Gd2O2S:Tb3+,亦稱為GOS,通常為粉末磷光體屏幕之形式)。然而,其他閃爍器亦係可能的,諸如摻雜鈉之碘化銫(寫作CsI:Na或CsI:Na+)、摻雜鉈之碘化鈉(寫作NaI:Tl或NaI:Tl+)、鎢酸鈣(CaWO4)、鎢酸鋅(ZnWO4)、鎢酸鎘(CdWO4)、鍺酸鉍(Bi4Ge3O12,亦稱為BGO)、摻雜鈰之鑥釔正矽酸鹽(寫作Lu1.8Yb0.2SiO5:Ce或Lu1.8Yb0.2SiO5:Ce3+,亦稱為LYSO),及摻雜鈰之矽酸釓(寫作Gd2SiO5:Ce或Gd2SiO5:Ce3+,亦稱為GSO)。其他閃爍器係可能的,諸如BaFCl:Eu2+、BaSO4:Eu2+、BaFBr:Eu2+、LaOBr:Tb3+、LaOBr:Tm3+、La2O2S:Tb3+、Y2O2S:Tb3+、YTaO4、YTaO4:Nb、ZnS:Ag、(Zn,Cd)S:Ag、ZnSiO4:Mn2+、CsI、LiI:Eu2+、PbWO4、Bi4Si3O12、Lu2SiO5:Ce3+、YAlO3:Ce3+、CsF、CaF2:Eu2+、BaF2、CeF3、Y1.34Gd0.6O3:Eu3+、Pr、Gd2O2S:Pr3+、Ce、SCGl、HFG:Ce3+(5%)及C14H10。對於許多類型之閃爍器材料(諸如,CsI:Tl、BGO及LYSO),轉換器可採取分段偵測器之形式,在分段偵測器中,閃爍器材料之小的個別元件(每一個別元件具有一大致等於或小於成像陣列之像素間距(或陣列之像素間距之倍數)的橫截面面積)與中隔壁材料組裝在一起,該中隔壁材料分離該等元件以形成一區域偵測器,該中隔壁材料提供元件之間的光學隔離,藉此保持空間解析度。 For indirect detection of an imager, the converter takes the form of a scintillator. For many applications, doped yttrium iodide (written as CsI:Tl or CsI:Tl + , usually grown to form structures with aligned needle crystals), or doped yttrium oxysulfide (writing) Gd 2 O 2 S: Tb or Gd 2 O 2 S: Tb 3+ , also known as GOS, usually in the form of a powder phosphor screen). However, other scintillators are also possible, such as sodium-doped cesium iodide (written as CsI:Na or CsI:Na + ), cesium iodide (written as NaI:Tl or NaI:Tl + ), tungsten Calcium acid (CaWO 4 ), zinc tungstate (ZnWO 4 ), cadmium tungstate (CdWO 4 ), bismuth ruthenate (Bi 4 Ge 3 O 12 , also known as BGO), yttrium yttrium orthosilicate (Writing Lu 1.8 Yb 0.2 SiO 5 :Ce or Lu 1.8 Yb 0.2 SiO 5 :Ce 3+ , also known as LYSO), and ytterbium ytterbium ytterbium (written as Gd 2 SiO 5 :Ce or Gd 2 SiO 5 : Ce 3+ , also known as GSO). Other scintillators are possible, such as BaFCl:Eu 2+ , BaSO 4 :Eu 2+ , BaFBr:Eu 2+ , LaOBr:Tb 3+ , LaOBr:Tm 3+ ,La 2 O 2 S:Tb 3+ ,Y 2 O 2 S: Tb 3+ , YTaO 4 , YTaO 4 : Nb, ZnS: Ag, (Zn, Cd) S: Ag, ZnSiO 4 : Mn 2+ , CsI, LiI: Eu 2+ , PbWO 4 , Bi 4 Si 3 O 12 , Lu 2 SiO 5 :Ce 3+ , YAlO 3 :Ce 3+ , CsF, CaF 2 :Eu 2+ , BaF 2 , CeF 3 , Y 1.34 Gd 0.6 O 3 :Eu 3+ , Pr, Gd 2 O 2 S: Pr 3+ , Ce, SCG1, HFG: Ce 3+ (5%) and C 14 H 10 . For many types of scintillator materials (such as CsI:Tl, BGO, and LYSO), the converter can take the form of a segmented detector, in the segmented detector, the individual components of the scintillator material (each The individual components have a cross-sectional area substantially equal to or less than the pixel pitch of the imaging array (or a multiple of the pixel pitch of the array) assembled with the intermediate partition material that separates the components to form a region detector The medial wall material provides optical isolation between the elements, thereby maintaining spatial resolution.
可沈積一材料層(稱作囊封或囊封層)以形成閃爍器之頂層,以便以機械方式及以化學方式保護閃爍器。 A layer of material (referred to as an encapsulation or encapsulation layer) can be deposited to form the top layer of the scintillator to mechanically and chemically protect the scintillator.
對於間接偵測AMFPI,像素儲存電容器採取光學感測器之形式,諸如光電二極體或金屬絕緣半導體(MIS)結構。此等光學感測器通常 併有a-Si半導體-其為由於以下事實而極適合於電離輻射之成像之材料:a-Si感測器之信號、雜訊及暗電流性質僅極微弱地受極高輻射劑量影響。基於a-Si及多晶-Si之TFT之性質亦僅微弱地受極高輻射劑量影響,使得此等TFT極適合於電離輻射之成像。 For indirect detection of AMFPI, the pixel storage capacitor takes the form of an optical sensor, such as a photodiode or a metal-insulated semiconductor (MIS) structure. These optical sensors are usually There is also an a-Si semiconductor, which is a material that is well suited for imaging of ionizing radiation due to the fact that the signal, noise and dark current properties of the a-Si sensor are only very weakly affected by extremely high radiation doses. The properties of TFTs based on a-Si and poly-Si are also only weakly affected by extremely high radiation doses, making these TFTs extremely suitable for imaging of ionizing radiation.
a-Si光電二極體之結構之一形式包括底部電極(其連接至定址TFT之源極)、摻雜層(n+型摻雜a-Si,約10至500nm厚且較佳約50至100nm厚)、純質a-Si層(較佳約0.5至2.0μm厚)、第二摻雜層(p+型摻雜a-Si,約10至500nm厚且較佳約5至20nm厚),及由對可見光透明之材料(諸如,氧化銦錫,ITO)製成的頂部電極。在此a-Si光電二極體結構之一替代形式中,上部a-Si層與下部a-Si層之摻雜可互換。將頂部摻雜a-Si層之厚度最小化減少了在此層中吸收之可見光子之分率,從而有助於將記錄於像素中之成像信號最大化。 One form of the structure of the a-Si photodiode includes a bottom electrode (which is connected to the source of the addressed TFT), a doped layer (n + type doped a-Si, about 10 to 500 nm thick and preferably about 50 to 100 nm thick), pure a-Si layer (preferably about 0.5 to 2.0 μm thick), second doped layer (p + type doped a-Si, about 10 to 500 nm thick and preferably about 5 to 20 nm thick) And a top electrode made of a material that is transparent to visible light, such as indium tin oxide, ITO. In an alternative form of the a-Si photodiode structure, the doping of the upper a-Si layer and the lower a-Si layer are interchangeable. Minimizing the thickness of the top doped a-Si layer reduces the fraction of visible light absorbed in this layer, thereby helping to maximize the imaging signal recorded in the pixel.
在圖5中示意性地說明用於間接偵測、主動式矩陣成像陣列之像素電路之實例。此圖中所描繪之電路元件包括光電二極體(PD)及像素定址電晶體(TFT)。標記了由虛線橢圓環繞的TFT之源極、汲極及閘極。第二虛線橢圓強調:光電二極體(其為像素之光學感測器)亦用作具有電容CPD之像素儲存電容器。亦展示分別對應於所描繪之像素之列及行的閘極位址線及資料位址線。施加至光電二極體之頂部電極之反向偏壓電壓的量值為VBIAS。此電壓由外部電壓供應器來提供。VBIAS通常設定為在約1V至8V之範圍內的值。 An example of a pixel circuit for an indirect detection, active matrix imaging array is schematically illustrated in FIG. The circuit components depicted in this figure include a photodiode (PD) and a pixel addressed transistor (TFT). The source, drain and gate of the TFT surrounded by the dashed oval are marked. The second dashed oval emphasizes that the photodiode, which is an optical sensor of a pixel, is also used as a pixel storage capacitor having a capacitance C PD . Gate address lines and data address lines corresponding to the columns and rows of pixels depicted are also shown. The magnitude of the reverse bias voltage applied to the top electrode of the photodiode is V BIAS . This voltage is provided by an external voltage supply. V BIAS is typically set to a value in the range of about 1V to 8V.
圖6為對應於圖5中之像素電路之像素設計的一結構實施的示意性橫截面說明,該結構實施稱作基線架構。在此實施中,定址TFT與若干其他元件共用像素之表面積,該等若干其他元件包括具有堆疊結構之離散a-Si光電二極體、位址線,及位址線、光電二極體與TFT之間的間隙。 6 is a schematic cross-sectional illustration of a structural implementation of a pixel design corresponding to the pixel circuit of FIG. 5, the implementation of which is referred to as a baseline architecture . In this implementation, the addressed TFT shares the surface area of the pixel with a number of other components, including discrete a-Si photodiodes having a stacked structure, address lines, and address lines, photodiodes, and TFTs. The gap between them.
在圖6中,藉由虛線橢圓來指示a-Si定址電晶體(TFT)之大體位置 (僅說明汲極、源極及閘極)。光電二極體之底部閘極由用以形成TFT之源極之金屬的延伸部分形成。將光電二極體之剩餘層(其並不與TFT重疊)圖案化,以使得其與底部電極之邊緣對準且以此方式形成一堆疊結構。此等層包括n+型摻雜a-Si層、純質a-Si層、p+型摻雜a-Si層,及用作光學透明頂部電極之ITO層。憑藉偏壓線將量值為VBIAS之反向偏壓電壓施加至光電二極體之頂部電極,從而產生跨越光電二極體之電場。憑藉金屬介層孔而連接至TFT之汲極的資料位址線及偏壓線之方向與圖式平面正交。藉由陰影示意性地指示鈍化材料之大致位置。此包括沈積於陣列之整個頂面上以便囊封陣列之鈍化材料,從而以機械方式保護陣列且防止與偏壓線及資料位址線的非意欲之電接觸。亦描繪閃爍器之形式的x光轉換器,該閃爍器在整個陣列之上延伸。入射x光(波狀箭頭)在閃爍器中產生可見光子(筆直的、暗淡箭頭)。一些可見光子進入光電二極體之純質層中,產生由於電場而朝向電極漂移之電子及電洞,藉此產生儲存於像素中且最終自像素讀出之成像信號。 In Fig. 6, the general position of the a-Si addressed transistor (TFT) is indicated by a dashed oval (only the drain, source and gate are illustrated). The bottom gate of the photodiode is formed by an extension of the metal used to form the source of the TFT. The remaining layers of the photodiode (which do not overlap the TFT) are patterned such that they align with the edges of the bottom electrode and form a stacked structure in this manner. These layers include an n + -type doped a-Si layer, a pure a-Si layer, a p + -type doped a-Si layer, and an ITO layer used as an optically transparent top electrode. Applying a reverse bias voltage of V BIAS to the top electrode of the photodiode by means of a bias line, thereby generating an electric field across the photodiode . The direction of the data address line and the bias line connected to the drain of the TFT by the via hole is orthogonal to the plane of the drawing. The approximate location of the passivation material is schematically indicated by the shading. This includes depositing a passivation material over the entire top surface of the array to encapsulate the array, thereby mechanically protecting the array and preventing unintended electrical contact with bias lines and data address lines. An x-ray converter in the form of a scintillator is also depicted that extends over the entire array. Incident x-rays (wavy arrows) produce visible light (straight, dim arrows) in the scintillator. Some of the visible light ions enter the pure layer of the photodiode, producing electrons and holes that drift toward the electrode due to the electric field, thereby producing an imaging signal that is stored in the pixel and ultimately read out from the pixel.
對於直接偵測、主動式矩陣平面板成像器,轉換器可採取光導材料層之形式,該光導材料層具有足以使大部分入射x光停止之厚度。一合適的光導材料為非晶硒a-Se,其可製造為直至約2000μm厚,且較佳製造為具有在約200至1000μm之範圍內的厚度。適合於作為直接偵測轉換器之其他光導材料包括單晶及多晶系式之碘化鉛(PbI2)、碘化汞(HgI2)、氧化鉛(PbO)、碲化鎘鋅(CdZnTe)、碲化鎘(CdTe)、Bi2S3、Bi2Se3、BiI3、BiBr3、CdS、CdSe、HgS、Cd2P3、InAs、InP、In2S3、In2Se3、Ag2S、PbI4 -2及Pb2I7 -3。光導體之厚度之選擇隨著x光能量之增加而增加,以便達成合理的較大分率之x光的轉換,該分率可為約10%至90%(在診斷能量下)及約1%至10%(在放射治療能量下)之範圍內的任何值。 For a direct detection, active matrix planar panel imager, the transducer can take the form of a layer of photoconductive material having a thickness sufficient to stop most of the incident x-rays. A suitable photoconductive material is amorphous selenium a-Se, which can be fabricated up to about 2000 [mu]m thick, and is preferably fabricated to have a thickness in the range of from about 200 to 1000 [mu]m. Other photoconductive materials suitable as direct detection converters include single crystal and polycrystalline lead iodide (PbI 2 ), mercury iodide (HgI 2 ), lead oxide (PbO), and cadmium zinc telluride (CdZnTe). , cadmium telluride (CdTe), Bi 2 S 3 , Bi 2 Se 3 , BiI 3 , BiBr 3 , CdS, CdSe, HgS, Cd 2 P 3 , InAs, InP, In 2 S 3 , In 2 Se 3 , Ag 2 S, PbI 4 -2 and Pb 2 I 7 -3 . The choice of the thickness of the photoconductor increases as the x-ray energy increases to achieve a reasonably large fraction of x-ray conversion, which may be between about 10% and 90% (at diagnostic energy) and about 1%. Any value within the range of 10% (under radiotherapy energy).
在使用百萬伏輻射進行成像之狀況下(例如,體外放射治療成像或工業放射攝影,包括用於安全應用之掃描),通常將一薄(約1mm)金屬板定位於轉換器之上(對於間接偵測,直接在閃爍器上,或對於直接偵測,直接在覆蓋光導體之頂部電極之上的囊封上)。此板之組合物可採取許多形式,包括銅、鋼、鎢及鉛。在圖7中示意性地說明用於直接偵測、主動式矩陣成像陣列之像素電路之實例。此圖中所描繪之電路元件包括光導體(PC)、像素定址電晶體(TFT),及具有電容CSTORAGE之像素儲存電容器(如由虛線橢圓指示)。標記了由另一虛線橢圓環繞的TFT之源極、汲極及閘極。第三虛線橢圓強調:光導體具有電容CPC且亦類似於電路中的電阻為RPC之大電阻器而起作用。亦展示對應於所描繪之像素之列及行的閘極位址線及資料位址線。施加至光導體之頂部電極之偏壓電壓的量值為VBIAS。此電壓由外部電壓供應器來提供。所使用之VBIAS值取決於光導體材料之類型,且大體上與彼材料之層厚度成比例地增加。對於a-Se,VBIAS通常為每一微米厚度約10V。因此,對於1000μm之a-Se層,VBIAS將為約10,000V。對於HgI2,VBIAS通常在每一微米約0.5至2.0V之範圍內。因此,對於500μm之HgI2層,VBIAS將為約250至1,000V。光導層亦可以突崩模式操作,其中跨越彼層之VBIAS之值通常較高-對於a-Se之實例,在每一微米約50V至100V之範圍內。在此狀況下,可使突崩層足夠厚,以本身使大部分x光停止,或可使突崩層較薄,而將一光導體或閃爍器層(諸如,分別具有足夠厚度以使大部分入射x光停止之a-Se或CsI:Tl)沈積於突崩層之上。在此狀況下,突崩層之用途在於放大來自上覆轉換器之信號。 In the case of imaging with millions of volts of radiation (eg, extracorporeal radiotherapy imaging or industrial radiography, including scanning for safety applications), a thin (about 1 mm) metal plate is typically positioned over the transducer (for Indirect detection, directly on the scintillator, or for direct detection, directly on the envelope overlying the top electrode of the photoconductor). The composition of the board can take many forms including copper, steel, tungsten and lead. An example of a pixel circuit for a direct detection, active matrix imaging array is schematically illustrated in FIG. The circuit components depicted in this figure include a photoconductor (PC), a pixel addressed transistor (TFT), and a pixel storage capacitor having a capacitance C STORAGE (as indicated by the dashed oval). The source, drain and gate of the TFT surrounded by another dashed ellipse are marked. The third dashed ellipse emphasizes that the photoconductor has a capacitance C PC and also acts like a large resistor in the circuit that is a large resistor of R PC . Gate address lines and data address lines corresponding to the columns and rows of pixels depicted are also shown. The magnitude of the bias voltage applied to the top electrode of the photoconductor is V BIAS . This voltage is provided by an external voltage supply. The V BIAS value used depends on the type of photoconductor material and generally increases in proportion to the layer thickness of the material. For a-Se, V BIAS is typically about 10V per micron thickness. Thus, for a 1000 μm a-Se layer, V BIAS will be about 10,000V. For HgI 2 , V BIAS is typically in the range of about 0.5 to 2.0 V per micron. Thus, for a 500 μm HgI 2 layer, V BIAS will be about 250 to 1,000V. The photoconductive layer can also operate in a collapse mode in which the value of V BIAS across the other layer is generally higher - for the example of a-Se, in the range of about 50V to 100V per micron. In this case, the sag layer can be made thick enough to stop most of the x-rays themselves, or the sag layer can be made thinner, and a photoconductor or scintillator layer (such as having a sufficient thickness to make it large) Part of the incident x-light stopped a-Se or CsI:Tl) is deposited on the avalanche layer. In this case, the purpose of the sag layer is to amplify the signal from the overlying converter.
圖8為對應於圖7中之像素電路之像素設計的一結構實施的示意性橫截面說明。在此實施中,定址TFT與以下各項共用像素之表面積:像素儲存電容器、位址線,及位址線、儲存電容器與TFT之間的 間隙。光導體結構(包括底部電極、光導材料層,及頂部電極)駐留於定址TFT之平面上方(亦即,水平面上方)。 Figure 8 is a schematic cross-sectional illustration of a structural implementation of a pixel design corresponding to the pixel circuit of Figure 7. In this implementation, the addressed TFT shares the surface area of the pixel with: a pixel storage capacitor, an address line, and an address line, between the storage capacitor and the TFT. gap. The photoconductor structure (including the bottom electrode, the layer of photoconductive material, and the top electrode) resides above the plane of the addressed TFT (ie, above the horizontal plane).
在圖8中,藉由虛線橢圓來指示a-Si定址電晶體(TFT)之大體位置(僅說明汲極、源極及閘極)。對於像素儲存電容器(其位置由第二虛線橢圓指示),僅說明了頂部電極及底部電極。像素儲存電容器之頂部電極由後部接點形成,該後部接點為用以形成TFT之源極之金屬的延伸部分。光導體之底部電極憑藉至後部接點之介層孔(藉由第三橢圓指示)而連接至TFT,且並不在TFT之上延伸。跨越整個陣列沈積一厚的連續光導體材料層(其充當x光轉換器),從而使彼材料與底部電極接觸。在整個光導體表面之上沈積一連續頂部電極。將量值為VBIAS之偏壓電壓施加至頂部電極,以便建立一跨越光導體之電場。將一材料層(稱作囊封或囊封層)沈積於整個頂部電極之上以便囊封陣列,從而以機械方式及以化學方式保護陣列,且防止與頂部電極的非意欲之電接觸。憑藉金屬介層孔而連接至TFT之汲極的資料位址線之方向與圖式平面正交。大致藉由陰影來指示鈍化材料之位置。注意,在直接偵測像素及陣列之替代組態中,可在底部電極與光導體之間或在頂部電極與光導體之間沈積一薄材料層(通常為約1至10微米厚,充當障壁、介電或摻雜層)。或者,可在兩個位置中都沈積此薄材料層,且在每一位置中此薄材料層之類型及厚度可不同。 In Fig. 8, the general position of the a-Si addressed transistor (TFT) is indicated by a dashed oval (only the drain, source and gate are illustrated). For pixel storage capacitors whose position is indicated by a second dashed oval, only the top and bottom electrodes are illustrated. The top electrode of the pixel storage capacitor is formed by a rear contact which is an extension of the metal used to form the source of the TFT. The bottom electrode of the photoconductor is connected to the TFT by means of a via hole to the back contact (indicated by a third ellipse) and does not extend over the TFT. A thick layer of continuous layer of photoconductor material (which acts as an x-ray converter) is deposited across the entire array to bring the material into contact with the bottom electrode. A continuous top electrode is deposited over the entire surface of the photoconductor. A bias voltage of magnitude V BIAS is applied to the top electrode to establish an electric field across the photoconductor. A layer of material (referred to as an encapsulation or encapsulation layer) is deposited over the entire top electrode to encapsulate the array to mechanically and chemically protect the array and prevent unintended electrical contact with the top electrode. The direction of the data address line connected to the drain of the TFT by the via hole is orthogonal to the plane of the drawing. The position of the passivation material is indicated by a shadow. Note that in an alternative configuration for directly detecting pixels and arrays, a thin layer of material (typically about 1 to 10 microns thick) can be deposited between the bottom electrode and the photoconductor or between the top electrode and the photoconductor, acting as a barrier , dielectric or doped layer). Alternatively, the thin material layer can be deposited in both locations, and the type and thickness of the thin material layer can be different in each location.
對於具有圖6中所說明之基線架構的間接偵測主動式矩陣成像陣列,定址TFT與光電二極體彼此直接競爭及與其他像素元件競爭像素中之區域。此在圖6中以及在顯現於圖9中之四個像素之對應示意性呈現中顯而易見。其在圖10中進一步顯而易見,在圖10中展示自一對間接偵測主動式矩陣陣列所獲得之像素之顯微照片。大體而言,設計間接偵測主動式矩陣陣列以便使光電二極體之面積儘可能地大。另外,對於偏壓線在光電二極體之頂面之上延伸的陣列設計,使此等線及相 關聯之介層孔(兩者均為光學不透明的且阻擋光到達光電二極體)之面積儘可能地小。對於給定陣列設計,像素區域之被光電二極體表面(其對來自上方之入射光開放)佔據之分率稱作光學填充因子。 For an indirect-detect active matrix imaging array having the baseline architecture illustrated in FIG. 6, the addressed TFT and the photodiode compete directly with each other and compete with other pixel elements for regions in the pixel. This is apparent in Figure 6 and in the corresponding schematic representation of the four pixels appearing in Figure 9. It is further apparent in Figure 10, which shows a photomicrograph of a pixel obtained from a pair of indirect detection active matrix arrays. In general, the design indirectly detects the active matrix array so that the area of the photodiode is as large as possible. In addition, for an array design in which the bias lines extend over the top surface of the photodiode, the lines and associated vias (both are optically opaque and block light from reaching the photodiode) The area is as small as possible. For a given array design, the fraction of the pixel area that is occupied by the surface of the photodiode (which is open to incident light from above) is called the optical fill factor .
光學填充因子之最大化受以下事實推動:對來自上覆閃爍器之入射光之更有效使用增加了像素信號大小,及因此增加成像器之信雜比,從而導致改良之影像品質。對於用於需要小像素間距(例如,在約100μm以下)之應用或成像器以低曝光(諸如,螢光鏡檢查法之低曝光區,其中每一圖框之曝光小於約1μR)操作之應用的陣列設計而言,將光學填充因子最大化特別重要。 The maximization of the optical fill factor is driven by the fact that more efficient use of incident light from the overlying scintillator increases the pixel signal size and thus increases the imager's signal to noise ratio, resulting in improved image quality. For applications requiring small pixel pitch (eg, below about 100 μm) or imager for low exposure (such as low exposure areas for fluoroscopy, where each frame exposure is less than about 1 μR) In terms of array design, it is especially important to maximize the optical fill factor.
高的光學填充因子激勵以下各項之最小化:定址TFT之大小、位址線之寬度、偏壓線之寬度,及光電二極體、TFT與位址線之間的間隙。然而,製造過程對設計之每個元件強加了最小特徵大小。此外,位址線及偏壓線必須足夠寬,以限制沿著此等線之電阻(因為高電阻將負面地影響陣列之時間及/或電操作,以及可能減小信號對雜訊效能)。另外,間隙不得窄到導致像素元件之間的非意欲之接觸(及因此的電短路)或導致寄生電容之高位準(其可使信雜比及時間效能降級)。最後,TFT通道之寬度對長度比(稱為縱橫比)必須足夠大,以便提供所要的陣列讀出速度所需之TFT接通電流之量值(因為具有較高縱橫比之TFT在其傳導模式中提供較高位準之電流)。圖10說明此等考慮之實際實例,其中經由間隙、位址線及TFT之大小之減小(由最小特徵大小之減小輔助),早先陣列設計之光學填充因子(圖10(a)中所展示)在稍後設計中顯著增加(圖10(b)中所展示)。隨著像素間距減小,維持大的光學填充因子之挑戰變得更為困難,此係因為被位址線、間隙及定址TFT佔據之區域消耗了像素區域之更大分率。 The high optical fill factor excites the minimization of the size of the addressed TFT, the width of the address line, the width of the bias line, and the gap between the photodiode, the TFT, and the address line. However, the manufacturing process imposes a minimum feature size on each component of the design. In addition, the address and bias lines must be wide enough to limit the resistance along these lines (because high resistance will negatively impact the time and/or electrical operation of the array, and may reduce signal-to-noise performance). In addition, the gap must not be narrow enough to cause unintended contact (and thus electrical shorting) between pixel elements or to cause high levels of parasitic capacitance (which can degrade signal-to-noise ratio and time performance). Finally, the width-to-length ratio (referred to as the aspect ratio) of the TFT channel must be large enough to provide the amount of TFT turn-on current required for the desired array read speed (because the TFT with a higher aspect ratio is in its conduction mode) Provide a higher level of current). Figure 10 illustrates a practical example of such considerations in which the optical fill factor of the earlier array design (assisted by the reduction of the minimum feature size) via the gap, the address line, and the size of the TFT (Figure 10(a) Showcase) has increased significantly in later designs (shown in Figure 10(b)). As the pixel pitch decreases, the challenge of maintaining a large optical fill factor becomes more difficult because the area occupied by the address lines, gaps, and addressed TFTs consumes a larger fraction of the pixel area.
回避上述關於光學填充因子之限制的高度有效之方法為:實施光電二極體結構位於定址TFT之平面上方(亦即,水平面上方)的像素 架構。多種此等平面外架構係可能的,且圖11及圖12中展示兩個此等架構。在此等說明中,平面外光電二極體結構與定址TFT之一部分或全部重疊,以便將光學填充因子最大化。 A highly efficient method of avoiding the above limitation on the optical fill factor is to implement a pixel in which the photodiode structure is located above the plane of the addressed TFT (ie, above the horizontal plane). Architecture. A variety of such out-of-plane architectures are possible, and two such architectures are shown in Figures 11 and 12. In these illustrations, the out-of-plane photodiode structure partially or completely overlaps one of the addressed TFTs to maximize the optical fill factor.
圖11中之光電二極體包括與底部電極對準的一離散之堆疊結構。如圖6中,單一定址TFT連接至離散a-Si光電二極體,該離散a-Si光電二極體具有三個a-Si層以及頂部電極及底部電極。然而,在此像素架構中,光電二極體之底部電極定位於定址TFT之平面上方。底部電極憑藉至後部接點之介層孔(其位置藉由虛線橢圓指示)而連接至TFT,該後部接點為用以形成TFT之源極之金屬的延伸部分。光電二極體之該等a-Si層及該頂部電極經圖案化以形成與底部電極對準之一堆疊。資料位址線(其位置藉由實線橢圓指示)與偏壓線兩者之方向與圖式平面正交。 The photodiode of Figure 11 includes a discrete stack of structures aligned with the bottom electrode. As shown in FIG. 6, a single address TFT is connected to a discrete a-Si photodiode having three a-Si layers and a top electrode and a bottom electrode. However, in this pixel architecture, the bottom electrode of the photodiode is positioned above the plane of the addressed TFT. The bottom electrode is connected to the TFT by means of a via hole to the back contact whose position is indicated by a dashed oval, which is an extension of the metal used to form the source of the TFT. The a-Si layers of the photodiode and the top electrode are patterned to form a stack aligned with the bottom electrode. The direction of the data address line (whose position is indicated by the solid ellipse) and the bias line are orthogonal to the plane of the drawing.
圖12中之光電二極體具有一結構,在該結構中,一些層為連續的。如圖11中,單一定址TFT連接至定位於TFT之平面上方的a-Si光電二極體。然而,在此像素架構中,p+型摻雜層及純質層未經圖案化,而是跨越陣列為連續的以輔助將光學填充因子最大化。n+型摻雜a-Si層經圖案化以與光電二極體之底部電極對準,以抑制相鄰像素之間的電荷共用。底部電極憑藉至後部接點之介層孔(其位置藉由虛線橢圓指示)而連接至TFT,該後部接點為用以形成TFT之源極之金屬的延伸部分。資料位址線(其位置藉由實線橢圓指示)之方向與圖式平面正文。 The photodiode of Figure 12 has a structure in which some of the layers are continuous. As shown in Figure 11, a single address TFT is connected to an a-Si photodiode positioned above the plane of the TFT. However, in this pixel architecture, the p + doped layer and the pure layer are unpatterned, but are continuous across the array to aid in maximizing the optical fill factor. The n + -type doped a-Si layer is patterned to align with the bottom electrode of the photodiode to suppress charge sharing between adjacent pixels. The bottom electrode is connected to the TFT by means of a via hole to the back contact whose position is indicated by a dashed oval, which is an extension of the metal used to form the source of the TFT. The direction of the data address line (the position of which is indicated by the solid ellipse) and the body of the graphic plane.
圖13及圖14對應於具有圖12中所描繪之像素架構之間接偵測主動式矩陣陣列設計的實際實現。圖13為四個像素之示意性呈現而圖14為來自一陣列之像素之顯微照片。 13 and 14 correspond to an actual implementation having an inter-pixel detection active matrix array design of the pixel architecture depicted in FIG. Figure 13 is a schematic representation of four pixels and Figure 14 is a photomicrograph of pixels from an array.
在本發明之一實施例中,提供一種輻射感測器,其包括:一閃 爍層,該閃爍層經組態以在與電離輻射相互作用時發射光子;及一光偵測器,其按次序包括一第一電極、一感光層,及接近於該閃爍層而安置之一可透射光子之第二電極。該感光層經組態以在與該等光子之一部分相互作用時產生電子電洞對。該輻射感測器包括:像素電路,其電連接至該第一電極且經組態以量測指示在該感光層中所產生之該等電子電洞對之一成像信號;及一平坦化層,其安置於該像素電路上在該第一電極與該像素電路之間,以使得該第一電極高於包括該像素電路之一平面。該第一電極及該第二電極中之至少一者之一表面至少部分地重疊於該像素電路且具有高於該像素電路之特徵之一表面反曲。該表面反曲具有大於1/2微米之一曲率半徑。 In an embodiment of the invention, a radiation sensor is provided, comprising: a flash a scintillation layer configured to emit photons when interacting with ionizing radiation; and a photodetector comprising, in order, a first electrode, a photosensitive layer, and one of the photoluminescent layers disposed adjacent to the scintillation layer A second electrode that transmits photons. The photosensitive layer is configured to create an electron hole pair when interacting with a portion of the photons. The radiation sensor includes: a pixel circuit electrically coupled to the first electrode and configured to measure an imaging signal indicative of one of the pairs of electron holes generated in the photosensitive layer; and a planarization layer And disposed between the first electrode and the pixel circuit on the pixel circuit such that the first electrode is higher than a plane including the pixel circuit. A surface of at least one of the first electrode and the second electrode at least partially overlaps the pixel circuit and has a surface recursion higher than one of the features of the pixel circuit. The surface recursion has a radius of curvature greater than one of 1/2 microns.
在本發明之另一實施例中,提供一種輻射感測器,其包括一光導體偵測器,該光導體偵測器按次序包括一第一電極、一光導層,及一可透射電離輻射之第二電極。該光導層經組態以在與電離輻射相互作用時產生電子電洞對。該輻射感測器包括:像素電路,其電連接至該第一電極且經組態以量測指示在該光導層中所產生之電子電洞對之一成像信號;及一平坦化層,其安置於該像素電路上在該第一電極與該像素電路之間,以使得該第一電極高於包括該像素電路之一平面。該第一電極及該第二電極中之至少一者之一表面至少部分地重疊於該像素電路且具有高於該像素電路之特徵之一表面反曲。該表面反曲具有大於1/2微米之一曲率半徑。 In another embodiment of the present invention, a radiation sensor is provided, comprising: a photoconductor detector comprising a first electrode, a photoconductive layer, and a transmissive ionizing radiation in order The second electrode. The photoconductive layer is configured to create an electron hole pair upon interaction with ionizing radiation. The radiation sensor includes: a pixel circuit electrically coupled to the first electrode and configured to measure an imaging signal indicative of one of an electron hole pair generated in the light guiding layer; and a planarization layer Disposed on the pixel circuit between the first electrode and the pixel circuit such that the first electrode is higher than a plane including the pixel circuit. A surface of at least one of the first electrode and the second electrode at least partially overlaps the pixel circuit and has a surface recursion higher than one of the features of the pixel circuit. The surface recursion has a radius of curvature greater than one of 1/2 microns.
在本發明之又一實施例中,提供一種用於製造一輻射感測器之方法。該方法包括:在一基底基板上形成像素電路元件,在該等像素電路元件之上形成一平坦化層,在該平坦化層中形成一孔洞以曝露至該等像素電路元件之一連接件,使該圖案化之孔洞金屬化,形成與該金屬化孔洞電接觸之一第一電極,及在該第一電極上形成對光或電離輻射敏感之層。形成該平坦化層在該至少部分地重疊於該像素電路之 第一電極之一表面上提供一表面反曲,該表面反曲高於該像素電路之特徵、具有大於1/2微米之一曲率半徑。 In yet another embodiment of the invention, a method for fabricating a radiation sensor is provided. The method includes: forming a pixel circuit component on a base substrate, forming a planarization layer on the pixel circuit component, and forming a hole in the planarization layer to expose to a connector of the pixel circuit component, The patterned holes are metallized to form a first electrode in electrical contact with the metallized holes, and a layer sensitive to light or ionizing radiation is formed on the first electrode. Forming the planarization layer at least partially overlapping the pixel circuit A surface reversal is provided on one of the surfaces of the first electrode, the surface being recurved above the features of the pixel circuit, having a radius of curvature greater than one-half micron.
應理解,本發明之上述一般描述與以下詳細描述兩者均為例示性的,且並非限制本發明。 The above general description of the present invention is intended to be illustrative and not restrictive.
PC‧‧‧光導體 PC‧‧‧Light Conductor
PD‧‧‧光電二極體 PD‧‧‧Photoelectric diode
TFT‧‧‧像素定址電晶體 TFT‧‧‧pixel addressed transistor
TFTADDR‧‧‧定址TFT TFT ADDR ‧‧‧ Addressing TFT
TFTAL‧‧‧有效負載TFT TFT AL ‧‧‧ payload TFT
TFTCSA‧‧‧共源極放大器TFT TFT CSA ‧‧‧ Common source amplifier TFT
TFTRST‧‧‧重設TFT TFT RST ‧‧‧Reset TFT
TFTSF‧‧‧源極隨耦器TFT TFT SF ‧‧‧Source follower TFT
圖1為a-Si薄膜電晶體(TFT)之一形式之示意性三維圖,其展示自斜角檢視的TFT之頂部;圖2為圖1中所展示之a-Si TFT的示意性橫截面圖;圖3為多晶-Si TFT之一形式之示意性三維圖,其展示自斜角檢視的TFT之頂部;圖4為圖3中所展示之多晶-Si TFT的示意性橫截面圖;圖5為來自主動式矩陣成像陣列之像素的示意性電路圖,該主動式矩陣成像陣列使用入射輻射之間接偵測;圖6為具有離散光電二極體之間接偵測像素設計之一形式的橫截面圖的示意性圖式,該間接偵測像素設計對應於圖5之像素電路之一特定結構實施且稱作基線架構;圖7為來自主動式矩陣成像陣列之像素的示意性電路圖,該主動式矩陣成像陣列使用入射輻射之直接偵測;圖8為直接偵測像素設計之一形式的橫截面圖的示意性圖式;圖9為間接偵測主動式矩陣陣列之四個鄰近像素之示意性呈現,其對應於分別在圖5及圖6中所展示之像素電路及基線架構的實施;圖10為一對間接偵測主動式矩陣陣列之在單一像素區中之頂面的顯微照片集合,其對應於圖6中之基線架構之實施;圖11為具有離散的平面外光電二極體結構之間接偵測像素設計的橫截面圖的示意性圖式;圖12為具有連續的平面外光電二極體結構之間接偵測像素設計 的橫截面圖的示意性圖式;圖13為間接偵測主動式矩陣陣列之四個鄰近像素之示意性呈現,其對應於分別在圖5及圖12中所展示之像素電路及架構的實施;圖14為間接偵測主動式矩陣陣列之在單一像素區中之頂面的顯微照片,其對應於圖12中之像素架構之實施及圖13中之呈現;圖15為來自基於主動式像素設計之間接偵測陣列的像素的示意性電路圖,該主動式像素設計具有單級像素內放大器;圖16為基於主動式像素設計之間接偵測陣列的四個鄰近像素的示意性呈現,該主動式像素設計使用多晶-Si TFT,該示意性呈現對應於圖15中之像素電路及類似於圖12中之結構之光電二極體結構的實施;圖17為間接偵測陣列之在單一像素區中之頂面的顯微照片,其對應於圖15中之像素電路之實施及圖16中之呈現;圖18為來自基於主動式像素設計之間接偵測陣列的像素的示意性電路圖,該主動式像素設計具有兩級像素內放大器;圖19為基於主動式像素設計之間接偵測陣列的四個鄰近像素的示意性呈現,該主動式像素設計使用多晶-Si TFT,該示意性呈現對應於圖18中之像素電路及類似於圖12中之結構之光電二極體結構的實施;圖20為間接偵測陣列之在單一像素區中之頂面的顯微照片,其對應於圖18中之像素電路之實施及圖19中之呈現;圖21為基於單級像素內放大器設計之間接偵測陣列的計算之橫截面圖,該單級像素內放大器設計使用多晶-Si TFT,該橫截面圖對應於圖16及圖17且展示各種特徵及材料之原生拓撲;圖22(a)為基於兩級像素內放大器設計之間接偵測陣列的計算之橫截面圖,該兩級像素內放大器設計使用多晶-Si TFT,該橫截面圖 對應於圖19及圖20且展示各種特徵及材料之原生拓撲;圖22(b)對應於圖22(a)之一部分;圖23(a)為單級像素內放大器陣列的在單一像素區中之俯視圖,該圖係根據用於圖21之相同計算獲得,該圖對應於圖16及圖17且展示連續光電二極體結構之頂部的原生拓撲;圖23(b)為自圖17獲得之顯微照片,其經展示以用於與圖23(a)中的計算之俯視圖相比較之目的;圖24(a)為兩級像素內放大器陣列的在單一像素區中之俯視圖,該圖係根據用於圖22之相同計算獲得,該圖對應於圖19及圖20且展示連續光電二極體結構之頂部的原生拓撲;圖24(b)為自圖20獲得之顯微照片,其經展示以用於與圖24(a)中的計算之俯視圖相比較之目的;圖25為說明曲率半徑之一般概念的一對圖式,曲率半徑可應用於表面之平坦度之改變的特性化;圖26(a)為間接偵測陣列之計算之橫截面圖,其對應於圖21,但具有經由鈍化#2之完全平坦化而達成的更一致之拓撲;圖26(b)為間接偵測陣列之計算之橫截面圖,其對應於圖21,但具有經由鈍化#2之部分平坦化而達成的更一致之拓撲;圖27(a)為間接偵測陣列之計算之橫截面圖,其對應於圖22(a),但具有經由鈍化#2之完全平坦化而達成的更一致之拓撲;圖27(b)對應於圖27(a)之一部分;圖28為間接偵測陣列之計算之橫截面圖,其對應於圖26(a),但具有經由光電二極體之底部電極之周邊邊緣的平滑化而達成的更一致之拓撲;圖29為間接偵測陣列之計算之橫截面圖,其對應於圖27(a),但具有經由光電二極體之底部電極之周邊邊緣的平滑化而達成的更一致 之拓撲;圖30為間接偵測陣列之計算之橫截面圖,其對應於圖28,但具有經由介層孔之窄化及用金屬填充彼等介層孔而達成的更一致之拓撲,該等介層孔連接光電二極體之底部電極與後部接點;圖31(a)為單級像素內放大器陣列的在單一像素區中之俯視圖,該圖係自計算獲得且完全對應於圖23(a),該圖展示頂部連續光電二極體結構之原生拓撲,且經包括以用於與此圖31中之剩餘視圖相比較之目的;圖31(b)展示經由鈍化#2之完全平坦化而達成的相對於圖31(a)的表面拓撲之改良,該圖係自用於圖26(a)之相同計算獲得;圖31(c)展示經由光電二極體之底部電極之周邊邊緣的平滑化而達成的相對於圖31(b)的表面拓撲之改良,該圖係自用於圖28之相同計算獲得;圖31(d)展示經由介層孔之窄化及用金屬填充彼等介層孔而達成的相對於圖31(c)的表面拓撲之改良,該介層孔連接光電二極體之底部電極與後部接點,該圖係自用於圖30之相同計算獲得;圖32(a)為兩級像素內放大器陣列的在單一像素區中之俯視圖,該圖係自計算獲得且完全對應於圖24(a),該圖展示頂部連續光電二極體結構之原生拓撲,且經包括以用於與此圖32中之剩餘視圖相比較之目的;圖32(b)展示經由鈍化#2之完全平坦化而達成的相對於圖32(a)的表面拓撲之改良,該圖係自用於圖27之相同計算獲得;圖32(c)展示經由光電二極體之底部電極之周邊邊緣的平滑化而達成的相對於圖32(b)的表面拓撲之改良,該圖係自用於圖29之相同計算獲得;圖32(d)展示經由介層孔之窄化及用金屬填充彼等介層孔而達成 的相對於圖32(c)的表面拓撲之改良,該介層孔連接光電二極體之底部電極與後部接點,該圖係自計算獲得;圖33(a)為間接偵測陣列之計算之橫截面圖,其對應於圖21,但具有經由光電二極體中之純質a-Si層之完全平坦化而達成的更一致之拓撲;圖33(b)為間接偵測陣列之計算之橫截面圖,其對應於圖21,但具有經由光電二極體中之純質a-Si層之部分平坦化而達成的更一致之拓撲;圖34(a)為單級像素內放大器陣列的在單一像素區中之俯視圖,該圖係自計算獲得且完全對應於圖23(a),該圖展示頂部連續光電二極體結構之原生拓撲,且經包括以用於與此圖34中之剩餘視圖相比較之目的;圖34(b)展示經由光電二極體中之純質a-Si層之部分平坦化而達成的相對於圖34(a)的表面拓撲之改良,該圖係自用於圖33(b)之相同計算獲得;及圖34(c)展示經由光電二極體中之純質a-Si層之完全平坦化而達成的相對於圖34(a)的表面拓撲之改良,該圖係自用於圖33(a)之相同計算獲得。 1 is a schematic three-dimensional view of one form of an a-Si thin film transistor (TFT) showing the top of a TFT from a bevel view; FIG. 2 is a schematic cross section of the a-Si TFT shown in FIG. Figure 3 is a schematic three-dimensional view of one of the poly-Si TFTs, showing the top of the TFT from the oblique angle view; Figure 4 is a schematic cross-sectional view of the poly-Si TFT shown in Figure 3. Figure 5 is a schematic circuit diagram of a pixel from an active matrix imaging array using incident radiation inter-connect detection; Figure 6 is in the form of an inter-connected detection pixel design with discrete photodiodes A schematic diagram of a cross-sectional view of the indirect detection pixel design corresponding to one of the pixel structures of FIG. 5 and referred to as a baseline architecture; FIG. 7 is a schematic circuit diagram of pixels from an active matrix imaging array, Active matrix imaging arrays use direct detection of incident radiation; Figure 8 is a schematic diagram of a cross-sectional view of one form of direct detection pixel design; Figure 9 is an indirect detection of four adjacent pixels of an active matrix array Schematic representation, which corresponds to The implementation of the pixel circuit and the baseline architecture shown in FIGS. 5 and 6; FIG. 10 is a photomicrograph collection of a pair of indirect detection active matrix arrays in a single pixel region, corresponding to the map Implementation of a baseline architecture in Figure 6; Figure 11 is a schematic diagram of a cross-sectional view of an inter-detected pixel design with discrete out-of-plane photodiode structures; Figure 12 is a continuous out-of-plane photodiode structure Interconnect detection pixel design Schematic diagram of a cross-sectional view; FIG. 13 is a schematic representation of indirect detection of four adjacent pixels of an active matrix array, corresponding to the implementation of the pixel circuits and architecture shown in FIGS. 5 and 12, respectively Figure 14 is a photomicrograph of the top surface of the active matrix array in a single pixel region, which corresponds to the implementation of the pixel architecture in Figure 12 and the presentation in Figure 13; Figure 15 is from active-based A schematic circuit diagram of a pixel design inter-detecting a pixel of the array having a single-stage in-pixel amplifier; FIG. 16 is a schematic representation of four adjacent pixels based on an active pixel design inter-detection array, The active pixel design uses a poly-Si TFT, which schematically represents the implementation of the pixel circuit of FIG. 15 and a photodiode structure similar to the structure of FIG. 12; FIG. 17 shows that the indirect detection array is single. A photomicrograph of the top surface in the pixel region, which corresponds to the implementation of the pixel circuit of FIG. 15 and the representation of FIG. 16; FIG. 18 is a schematic diagram of the pixel from the interferometric detection array based on the active pixel design The active pixel design has a two-stage in-pixel amplifier; FIG. 19 is a schematic representation of four adjacent pixels based on an active pixel design inter-connected detection array using a poly-Si TFT, The schematic representation corresponds to the implementation of the pixel circuit of FIG. 18 and a photodiode structure similar to the structure of FIG. 12; FIG. 20 is a photomicrograph of the top surface of the indirect detection array in a single pixel region, Corresponding to the implementation of the pixel circuit in FIG. 18 and the presentation in FIG. 19; FIG. 21 is a cross-sectional view of the calculation of the inter-connected detection array based on a single-stage in-pixel amplifier design using polycrystalline -Si TFT, the cross-sectional view corresponding to Figures 16 and 17 and showing the native topology of various features and materials; Figure 22 (a) is a cross-sectional view of the calculation based on the inter-detection array of the two-stage in-pixel amplifier design, The two-stage in-pixel amplifier design uses a poly-Si TFT, the cross-sectional view Corresponding to Figures 19 and 20 and showing the native topology of various features and materials; Figure 22 (b) corresponds to a portion of Figure 22 (a); Figure 23 (a) is a single-pixel in-pixel amplifier array in a single pixel region In the top view, the figure is obtained according to the same calculations used in FIG. 21, which corresponds to FIGS. 16 and 17 and shows the native topology of the top of the continuous photodiode structure; FIG. 23(b) is obtained from FIG. A photomicrograph, which is shown for comparison with the top view of the calculation in Figure 23(a); Figure 24(a) is a top view of the two-stage in-pixel amplifier array in a single pixel region, the graph Obtained according to the same calculations used in FIG. 22, which corresponds to FIGS. 19 and 20 and shows the native topology of the top of the continuous photodiode structure; FIG. 24(b) is a photomicrograph obtained from FIG. Shown for comparison with the top view of the calculation in Figure 24(a); Figure 25 is a pair of diagrams illustrating the general concept of radius of curvature, which can be applied to the characterization of the change in the flatness of the surface; Figure 26 (a) is a cross-sectional view of the calculation of the indirect detection array, which corresponds to Figure 21, but with A more consistent topology achieved by complete planarization of passivation #2; Figure 26(b) is a cross-sectional view of the calculation of the indirect detection array, corresponding to Figure 21, but with partial planarization via passivation #2 A more consistent topology is achieved; Figure 27(a) is a cross-sectional view of the calculation of the indirect detection array, which corresponds to Figure 22(a) but with a more consistent topology achieved by complete planarization of passivation #2 Figure 27(b) corresponds to a portion of Figure 27(a); Figure 28 is a cross-sectional view of the indirect detection array, which corresponds to Figure 26(a) but with a bottom electrode via a photodiode A more consistent topology achieved by smoothing the peripheral edges; Figure 29 is a cross-sectional view of the indirect detection array, corresponding to Figure 27(a) but with peripheral edges of the bottom electrode via the photodiode Smoother and more consistent Topology; Figure 30 is a cross-sectional view of the indirect detection array, corresponding to Figure 28, but with a more consistent topology achieved by narrowing the via holes and filling their via holes with metal. The interlayer hole is connected to the bottom electrode and the rear contact of the photodiode; FIG. 31(a) is a top view of the single-stage in-pixel amplifier array in a single pixel region, which is obtained by calculation and corresponds completely to FIG. (a), the figure shows the native topology of the top continuous photodiode structure and is included for comparison with the remaining views in this Figure 31; Figure 31 (b) shows complete flatness via passivation #2 The improvement of the surface topology with respect to Fig. 31(a) is obtained from the same calculation used for Fig. 26(a); Fig. 31(c) shows the peripheral edge of the bottom electrode via the photodiode The improvement of the surface topology with respect to Fig. 31(b) achieved by smoothing, the figure is obtained from the same calculation used in Fig. 28; Fig. 31(d) shows the narrowing through the via holes and filling them with metal Improvement of the surface topology achieved by the layer hole relative to the surface of FIG. 31(c) The bottom electrode and the back contact of the electric diode are obtained from the same calculation used in FIG. 30; FIG. 32(a) is a top view of the two-stage pixel in-amplifier array in a single pixel region, which is self-calculating Obtained and fully corresponds to Figure 24(a), which shows the native topology of the top continuous photodiode structure and is included for purposes of comparison with the remaining views in this Figure 32; Figure 32(b) shows Improvements to the surface topology of Figure 32(a) achieved by complete planarization of passivation #2, which is obtained from the same calculations used in Figure 27; Figure 32(c) shows the bottom electrode via the photodiode The improvement of the surface topology with respect to FIG. 32(b) achieved by the smoothing of the peripheral edge, which is obtained from the same calculation used in FIG. 29; FIG. 32(d) shows the narrowing and metal through the via hole. Filled with their mesopores Compared with the improvement of the surface topology of FIG. 32(c), the via hole is connected to the bottom electrode and the rear contact of the photodiode, and the figure is obtained by calculation; FIG. 33(a) is the calculation of the indirect detection array. A cross-sectional view corresponding to Figure 21, but with a more consistent topology achieved by complete planarization of the pure a-Si layer in the photodiode; Figure 33(b) is an indirect detection array calculation A cross-sectional view corresponding to Figure 21, but with a more consistent topology achieved by partial planarization of the pure a-Si layer in the photodiode; Figure 34 (a) is a single-stage in-pixel amplifier array a top view in a single pixel region, obtained from calculations and fully corresponding to Figure 23(a), which shows the native topology of the top continuous photodiode structure, and is included for use in this Figure 34 The remaining views are compared for the purpose; FIG. 34(b) shows an improvement over the surface topology of FIG. 34(a) achieved by partial planarization of the pure a-Si layer in the photodiode, the figure Obtained from the same calculation used in Figure 33(b); and Figure 34(c) shows the completion of the pure a-Si layer in the photodiode The improvement of the surface topology with respect to Fig. 34(a) achieved by full planarization is obtained from the same calculations used for Fig. 33(a).
藉由參考結合隨附圖式考慮之以下詳細描述,對本發明之更完全的瞭解及其許多附帶優點將容易得到,且其將變得更好理解。 A more complete understanding of the present invention, together with the <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt;
將平面外光電二極體結構併入於間接偵測主動式矩陣陣列之像素設計中提供了一種用於顯著改良光學填充因子之機制。在實施連續光電二極體結構之狀況下,可能實現對應於整個像素區域的大至1之光學填充因子。此等光學填充因子改良起因於消除了光電二極體與其他像素元件(諸如,定址TFT、位址線及間隙)之間的對像素區域之競 爭。 Incorporating an out-of-plane photodiode structure into a pixel design of an indirect detection active matrix array provides a mechanism for significantly improving the optical fill factor. In the case of implementing a continuous photodiode structure, it is possible to achieve an optical fill factor of up to 1 corresponding to the entire pixel area. These optical fill factor improvements result from the elimination of the pixel area between the photodiode and other pixel elements (such as addressed TFTs, address lines and gaps). Fight.
平面外光電二極體結構亦使得有可能將額外元件引入像素(諸如,TFT、二極體、電容器及電阻器,以及介層孔、跡線、控制線、位址線及接地平面),藉此使得有可能實現更複雜的像素電路。如在主動式矩陣陣列之狀況下,此等額外元件將駐留於與光電二極體之平面分離之平面中,且因此將不與光電二極體競爭像素區域。經由在像素設計中及在陣列設計中之其他地方引入更複雜電路,與每一像素僅具有單一TFT(充當像素定址開關)的主動式矩陣平面板成像陣列之效能相比較,可達成相當大的效能改良。雖然用於此等額外TFT及二極體之半導體材料之類型可為上文所描述之彼等類型中之任一者,但下文所描述之更複雜電路之實例涉及多晶-Si TFT。另外,雖然以下實例與間接偵測陣列設計(其中成像信號經收集且在讀出之前儲存於像素儲存電容器中)有關,但平面外光電二極體結構亦使得有可能產生允許偵測及計數個別x光(通常稱作單一光子計數之能力)之像素電路,而不使此等電路與光電二極體競爭區域。此等單一光子計數像素將包括偵測器(諸如,平面外光電二極體結構),以及用於放大器、鑑別器(視需要而具有脈衝整形電路)及事件計數器(例如,線性回饋移位暫存器之形式)以及用於定址及像素重設之電路。單一光子計數陣列提供許多優點,諸如基於x光光譜之選定部分產生高對比度影像之能力(稱作能量鑑別或能量窗限(energy windowing)之技術)。 The out-of-plane photodiode structure also makes it possible to introduce additional components into the pixel (such as TFTs, diodes, capacitors and resistors, as well as vias, traces, control lines, address lines, and ground planes). This makes it possible to implement more complex pixel circuits. As in the case of an active matrix array, such additional components will reside in a plane separate from the plane of the photodiode and will therefore not compete with the photodiode for the pixel region. By introducing more complex circuitry in pixel design and elsewhere in the array design, considerable performance can be achieved compared to the performance of an active matrix planar panel imaging array with only a single TFT (acting as a pixel addressing switch) per pixel. Performance improvement. While the types of semiconductor materials used for such additional TFTs and diodes can be any of the types described above, examples of more complex circuits described below relate to poly-Si TFTs. In addition, although the following examples relate to indirect detection array designs in which imaging signals are collected and stored in pixel storage capacitors prior to reading, the out-of-plane photodiode structure also makes it possible to detect and count individual A pixel circuit of x-ray (usually referred to as the ability to count a single photon) without competing such circuits with the photodiode. Such single photon counting pixels will include detectors (such as out-of-plane photodiode structures), as well as amplifiers, discriminators (with pulse shaping circuitry as needed), and event counters (eg, linear feedback shifts) The form of the register) and the circuitry for addressing and pixel resetting. A single photon counting array provides a number of advantages, such as the ability to generate high contrast images based on selected portions of the x-ray spectrum (a technique known as energy discrimination or energy windowing).
對於基於入射輻射之間接偵測以及直接偵測之陣列設計,增加的複雜性均可改良成像器之信雜比。在間接偵測之狀況下,較大複雜性亦可有助於限制與光電二極體中之a-Si之處於介穩態電子狀態(亦稱為捕集狀態)中的電荷之捕集及釋放相關聯的不合需要之效應。 For array designs based on incident detection of incident radiation and direct detection, the added complexity improves the imager's signal-to-noise ratio. In the case of indirect detection, greater complexity may also help to limit the trapping of charge in the metastable electron state (also known as the trapping state) of a-Si in the photodiode. Release the associated undesirable effects.
現參看諸圖式,其中相似參考數字指定貫穿若干視圖之相同或對應部分,且更特定言之,參看圖5,對於具有圖5中所展示之一般形 式之主動式矩陣陣列像素電路,在給定像素列之讀出期間,跨越對應光電二極體之電場增加回至最大值,該最大值藉由VBIAS之量值及光電二極體中之a-Si之厚度來定義。因此,像素讀出導致對成像信號進行取樣以及將像素初始化。在每一像素儲存電容器中之成像信號之收集期間,電場減小。對於給定像素,若成像信號足夠大,則電場之量值將幾乎減小至零,儲存電容器將不能夠進一步儲存電荷,且像素飽和。光電二極體中之電荷捕集之機率通常隨著電場強度減小而增加,且在接近像素飽和之條件時變得非常高。在放射攝影成像(其通常涉及大的x光曝光)中,所捕集電荷之高位準導致成像信號之實質損失。此減小成像器之信雜比且可使影像品質降級。在螢光鏡成像中,在早先影像之擷取期間所捕集的電荷將在稍後影像中釋放。此可導致來自較早影像之影像資訊顯現於稍後影像中-其為一種稱作延滯或影像延滯的一般不合需要之效應。另外,若使用成像器產生具有大的x光曝光之放射攝影影像,且若在短時間以後使用彼成像器產生螢光影像,則來自放射攝影影像之影像資訊可顯現於螢光影像中-其為一種稱作重像(ghosting)之不合需要之效應。延滯及重像為造成影像假影的原因,該等影像假影可使影像中之重要資訊不清楚,因此使得影像之有用性降級,且此等假影通常在使用基於主動式矩陣陣列之成像器的情況下遇到。然而,併有具有比主動式矩陣陣列之複雜性更大之複雜性的電路的陣列設計可克服信號對雜訊限制且減少影像假影,同時保持緊密性、大面積及輻射傷害抗性之重要優點。 Referring now to the drawings, wherein like reference numerals refer to the same or corresponding parts throughout the several, and more particularly, referring to FIG. 5, for the active matrix array pixel circuit having the general form shown in FIG. During readout of the pixel column, the electric field across the corresponding photodiode is increased back to a maximum value defined by the magnitude of V BIAS and the thickness of a-Si in the photodiode. Thus, pixel readout results in sampling of the imaging signal and initialization of the pixel. During the collection of imaging signals in each pixel storage capacitor, the electric field is reduced. For a given pixel, if the imaging signal is large enough, the magnitude of the electric field will be reduced to almost zero, the storage capacitor will not be able to store further charge, and the pixel will be saturated. The probability of charge trapping in a photodiode generally increases as the electric field strength decreases, and becomes very high near the condition of pixel saturation. In radiographic imaging, which typically involves large x-ray exposures, the high level of trapped charge results in substantial loss of imaging signal. This reduces the signal to noise ratio of the imager and can degrade image quality. In fluoroscopic imaging, the charge trapped during the capture of the previous image will be released in later images. This can result in image information from earlier images appearing in later images - a generally undesirable effect known as lag or image lag. In addition, if an imager is used to generate a radiographic image with a large x-ray exposure, and if the image is generated by using the imager after a short time, the image information from the radiographic image can be displayed in the fluorescent image - It is an undesirable effect called ghosting. Delay and ghosting are the causes of image artifacts. These image artifacts can make important information in the image unclear, thus degrading the usefulness of the image, and these artifacts are usually based on active matrix arrays. Encountered in the case of an imager. However, array designs with circuits that have greater complexity than the complexity of active matrix arrays can overcome signal-to-noise limitations and reduce image artifacts while maintaining tightness, large area, and resistance to radiation damage. advantage.
在圖15中示意性地說明用於間接偵測陣列之更複雜像素電路之實例。此電路設計包括三個TFT,該等TFT經組態以提供單級像素內放大器、定址TFT及重設TFT。由於像素內放大器之存在,此設計稱作主動式像素設計。在併有此設計之陣列之操作期間,收集成像信號且將其儲存於充當像素儲存電容器之光電二極體中。如在主動式矩陣 陣列之狀況下,每次可對一像素列執行讀出(若最大空間解析度為所要的),但像素信號之取樣與像素初始化不再同時進行。當經由使用定址TFT來取樣給定像素儲存電容器中之成像信號時,像素內放大器將該信號放大一量,該量等於資料位址線之電容與光電二極體之電容CPD的比率。因為此放大在來自定址TFT及來自外部前置放大器(其為主動式矩陣成像器中之兩個主要雜訊源)之雜訊影響之前發生於成像器電路中,所以此像素電路設計可提供成像器之信雜比之實質增加。另外,對於此像素電路,對成像信號進行取樣並不會初始化像素。實情為,成像信號繼續駐留於像素儲存電容器中,直至經由使用重設TFT初始化像素為止。因此,可對成像信號進行多次取樣且接著將其進行平均,從而導致成像器之信雜比的進一步改良。圖16及圖17對應於具有單級像素內放大器設計之間接偵測陣列之實際實現,其表示圖15之像素電路之實施。圖16為四個像素之示意性呈現,而圖17為來自實際陣列之像素之顯微照片。 An example of a more complex pixel circuit for indirectly detecting an array is schematically illustrated in FIG. This circuit design includes three TFTs that are configured to provide a single-stage in-pixel amplifier, address TFT, and reset TFT. This design is called active pixel design due to the presence of an in-pixel amplifier. During operation of the array with this design, the imaging signal is collected and stored in a photodiode that acts as a pixel storage capacitor. As in the case of an active matrix array, readout can be performed on one pixel column at a time (if the maximum spatial resolution is desired), but the sampling of the pixel signals and pixel initialization are no longer performed simultaneously. When an imaging signal in a given pixel storage capacitor is sampled by using an addressed TFT, the in-pixel amplifier amplifies the signal by an amount equal to the ratio of the capacitance of the data address line to the capacitance C PD of the photodiode. Because this amplification occurs in the imager circuit before the noise effects from the addressed TFT and from the external preamplifier, which is the two main sources of noise in the active matrix imager, this pixel circuit design provides imaging The signal-to-noise ratio of the device has increased substantially. Additionally, for this pixel circuit, sampling the imaging signal does not initialize the pixels. The reality is that the imaging signal continues to reside in the pixel storage capacitor until the pixel is initialized via the use of the reset TFT. Thus, the imaging signal can be sampled multiple times and then averaged, resulting in a further improvement in the imager's signal to noise ratio. 16 and 17 correspond to an actual implementation of an inter-connected detection array having a single-stage in-pixel amplifier design, which represents the implementation of the pixel circuit of FIG. Figure 16 is a schematic representation of four pixels, and Figure 17 is a photomicrograph of pixels from an actual array.
在圖18中示意性地說明用於間接偵測陣列之甚至更複雜像素電路之另一實例。此電路設計包括五個TFT及一回饋電容器,該五個TFT及該回饋電容器經組態以提供兩級像素內放大器、定址TFT及重設TFT。此為主動式像素設計之另一實例。在併有此設計之陣列之操作期間,收集成像信號且將其儲存於充當像素儲存電容器之回饋電容器中。此設計之操作及優點類似於上文所描述之單級像素內放大器設計之操作及優點-由於對成像信號之像素內放大以及由於對成像信號之多次取樣及平均而提供成像器之信雜比之實質增加。另外,在此設計中,在成像信號之收集及儲存期間,跨越光電二極體之電場僅極輕微地減小-與主動式矩陣像素設計或先前所描述之單級像素內放大器設計之情形形成鮮明對比。 Another example of an even more complex pixel circuit for indirectly detecting an array is schematically illustrated in FIG. The circuit design includes five TFTs and a feedback capacitor configured to provide a two-stage in-pixel amplifier, an addressable TFT, and a reset TFT. This is another example of an active pixel design. During operation of the array with this design, the imaging signal is collected and stored in a feedback capacitor that acts as a pixel storage capacitor. The operation and advantages of this design are similar to the operation and advantages of the single-stage in-pixel amplifier design described above - due to the in-pixel amplification of the imaging signal and the availability of the imager due to multiple sampling and averaging of the imaging signal. Increased in substance. In addition, in this design, the electric field across the photodiode is only slightly reduced during the collection and storage of the imaging signal - in the case of an active matrix pixel design or the previously described single-stage in-pixel amplifier design. sharp contrast.
因此,光電二極體中之電荷捕集之量得以減少且延滯及重像假 影得以減輕,甚至在非常高之x光曝光下亦如此。此兩級像素內放大器設計之另一優點在於:與單級設計之情況相比較,此設計允許對放大器之增益(定義為放大器增大成像信號所藉由之乘法因子)之更大程度的控制。在兩級設計中,像素內放大器將成像信號放大一量,該量等於資料位址線之電容與像素回饋電容器之電容CFB的比率。因此,對於單級設計與兩級設計兩者而言,對於給定像素間距及像素儲存電容器電容,像素內放大器增益之量值隨著資料線電容增加而增加。因此,若基於給定像素設計製造較大的陣列(亦即,沿著資料線方向具有較大數目個像素的陣列),則放大之量將增加。此係由於資料線電容將與沿著資料位址線之像素數目成比例地增加。在單級設計之狀況下,在不變更光電二極體之厚度或面積(其規格需要針對最大光偵測效率獨立地進行最佳化)之情況下,像素內放大器增益對陣列大小之此相依性(其一般為不合需要的)無法被抵銷。然而,對於兩級設計,可調整CFB之量值(例如,藉由調整電容器介電質之厚度或電容器之面積),以抵銷資料線電容之改變。此允許針對各種陣列大小實施給定兩級設計,而不必改變自陣列提取之成像信號之量值的範圍-因而簡化了成像器操作所需之外部前置放大電子器件之設計。圖19及圖20對應於具有兩級像素內放大器之間接偵測陣列之實際實現,其表示圖18之像素電路之實施。圖19為四個像素之示意性呈現,而圖20為來自實際陣列之像素之顯微照片。 As a result, the amount of charge trapping in the photodiode is reduced and the lag and ghosting artifacts are alleviated, even under very high x-ray exposures. Another advantage of this two-stage in-pixel amplifier design is that it allows for a greater degree of control over the gain of the amplifier (defined as the multiplication factor by which the amplifier increases the imaging signal) compared to the single-stage design. . In a two-stage design, the in-pixel amplifier amplifies the imaging signal by an amount equal to the ratio of the capacitance of the data address line to the capacitance C FB of the pixel feedback capacitor. Thus, for both a single-stage design and a two-stage design, for a given pixel pitch and pixel storage capacitor capacitance, the magnitude of the amplifier gain in the pixel increases as the data line capacitance increases. Thus, if a larger array is fabricated based on a given pixel design (i.e., an array having a larger number of pixels along the direction of the data line), the amount of amplification will increase. This is because the data line capacitance will increase in proportion to the number of pixels along the data address line. In the case of a single-stage design, the amplifier gain in the pixel depends on the array size without changing the thickness or area of the photodiode (the specification needs to be optimized independently for maximum photodetection efficiency). Sex (which is generally undesirable) cannot be offset. However, for a two-stage design, the magnitude of C FB can be adjusted (eg, by adjusting the thickness of the capacitor dielectric or the area of the capacitor) to offset the change in data line capacitance. This allows a given two-stage design to be implemented for various array sizes without having to change the range of magnitudes of the imaging signals extracted from the array - thus simplifying the design of external preamplifier electronics required for imager operation. 19 and 20 correspond to an actual implementation of an inter-pixel in-detection detection array having two levels of pixels, which represents the implementation of the pixel circuit of FIG. Figure 19 is a schematic representation of four pixels, and Figure 20 is a photomicrograph of pixels from an actual array.
如上文所描述,平面外光電二極體結構使得實質效能改良成為可能。此等改良為增加之光學填充因子之直接結果,以及係由此等光電二極體結構促進的增加之像素電路複雜性的結果。然而,對於此等益處之實際實現,平面外光電二極體結構不應引入使效能降級之其他因素。就此而言,發明者已發現了使效能降級之顯著問題,如下文所解釋。 As described above, the out-of-plane photodiode structure enables substantial performance improvement. These improvements are a direct result of the increased optical fill factor and are the result of increased pixel circuit complexity facilitated by such photodiode structures. However, for practical implementation of such benefits, the out-of-plane photodiode structure should not introduce other factors that degrade performance. In this regard, the inventors have discovered significant problems that degrade performance, as explained below.
圖21及圖22分別為對應於圖17及圖20中之顯微照片的單級像素內放大器設計及兩級像素內放大器設計的計算之橫截面圖。此等橫截面圖說明存在於像素設計中之各種特徵及材料。舉例而言,存在四個鈍化層:緩衝鈍化、鈍化#1、鈍化#2,及頂部鈍化。另外,存在四個金屬層:分流金屬(用於諸如重設電壓線及閘極位址線之元件);金屬#1(用於諸如後部接點、資料位址線及介層孔之元件);金屬#2(用於諸如光電二極體之底部電極之元件);及ITO(用於光電二極體之頂部電極)。圖21及圖22中所展示之其他層及特徵包括:用於TFT通道之多晶-Si(標記為活性多晶-Si);TFT閘極(由多晶-Si形成);及用於光電二極體之n+型摻雜、純質及p+型摻雜a-Si。在此等橫截面中顯而易見的光電二極體結構之拓撲不一致性表示對應的已製造之陣列中的拓撲不一致性,圖17及圖20中之顯微照片係自該等對應的已製造之陣列獲得。舉例而言,在圖23及圖24中,像素之俯視圖(自用以產生圖21及圖22中之橫截面圖之相同計算獲得)與對應陣列之實際實現的顯微照片之間的緊密對應係顯而易見的。 21 and 22 are cross-sectional views showing the calculation of the single-stage in-pixel amplifier design and the two-stage in-pixel amplifier design corresponding to the photomicrographs in FIGS. 17 and 20, respectively. These cross-sectional views illustrate the various features and materials present in the pixel design. For example, there are four passivation layers: buffer passivation, passivation #1, passivation #2, and top passivation. In addition, there are four metal layers: shunt metal (for components such as reset voltage lines and gate address lines); metal #1 (for components such as back contacts, data address lines, and vias) Metal #2 (for elements such as the bottom electrode of a photodiode); and ITO (for the top electrode of a photodiode). Other layers and features shown in Figures 21 and 22 include poly-Si (labeled as active poly-Si) for TFT channels; TFT gates (formed by poly-Si); and for optoelectronics The n + type doped, pure and p + type doped a-Si of the diode. The topological inconsistency of the photodiode structures apparent in such cross-sections represents topological inconsistencies in the corresponding fabricated arrays, and the photomicrographs in Figures 17 and 20 are from the corresponding fabricated arrays. obtain. For example, in Figures 23 and 24, the close view of the top view of the pixel (obtained from the same calculation used to generate the cross-sectional views of Figures 21 and 22) and the actual realized photomicrograph of the corresponding array Obvious.
圖21至圖24中所說明之光電二極體結構示範了其拓撲之極高不一致性程度。此拓撲不一致性係由於像素設計中的定位於光電二極體下方或為光電二極體之部分的特徵之存在。對於所展示之像素設計之實例,此等特徵包括TFT、電容器、位址線、跡線及介層孔(包括將光電二極體之底部電極連接至後部接點之介層孔)。此等特徵在平面外光電二極體結構中產生不一致性,而不管結構為連續的(如在此等實例中)抑或離散的(亦即,具有圖11中所展示之光電二極體結構)。注意,在直接偵測陣列之狀況下,在光導體結構下方或為光導體結構之部分的特徵(諸如,TFT、電容器、位址線、跡線及介層孔)之存在亦在彼結構中產生類似程度之拓撲不一致性。對於具有連續平面外光電二極體結構之間接偵測陣列,以及對於直接偵測陣列,沿著底部電極 之整個周邊且在將底部電極連接至後部接點之介層孔之區中產生拓撲不一致性,如在圖14、圖21及圖22(a)中顯而易見的。 The photodiode structure illustrated in Figures 21 through 24 demonstrates the extremely high degree of inconsistency in its topology. This topological inconsistency is due to the presence of features in the pixel design that are positioned below the photodiode or part of the photodiode. For the example of pixel design shown, these features include TFTs, capacitors, address lines, traces, and vias (including vias that connect the bottom electrode of the photodiode to the back contact). These features create inconsistencies in the out-of-plane photodiode structure, whether the structure is continuous (as in such examples) or discrete (i.e., has the photodiode structure shown in Figure 11). . Note that in the case of direct detection of the array, the presence of features under the photoconductor structure or portions of the photoconductor structure (such as TFTs, capacitors, address lines, traces, and via holes) is also present in the structure. A similar degree of topological inconsistency is produced. For an in-line detection array with a continuous out-of-plane photodiode structure, and for a direct detection array, along the bottom electrode Topological inconsistencies are created throughout the perimeter and in the region of the via hole connecting the bottom electrode to the back contact, as is evident in Figures 14, 21 and 22(a).
比較起來,對於使用基線架構之間接偵測陣列,離散光電二極體結構示範了其拓撲之極高程度的一致性。此拓撲一致性係由於在像素設計中不存在定位於光電二極體下方或為光電二極體之部分的任何特徵,如在圖6及圖9中顯而易見的。在此狀況下,當在陣列基板之平滑、平面表面之上執行用以製造光電二極體結構之各種層之處理步驟時,對於每一層皆達成平滑且平坦表面以及厚度一致性。因此,光電二極體結構之頂部將為平滑的且平坦的,如在圖10中所觀測。此平滑性及平坦性僅受起源於用於陣列之製造的處理步驟的隨機的局部變化(大約幾百埃)限制。注意,在製造期間,其他處理變化可跨越陣列產生給定材料層之厚度的多達百分之幾十的系統變化(例如,增加或減少)。 In comparison, for an in-line detection array using a baseline architecture, the discrete photodiode structure demonstrates a very high degree of consistency in its topology. This topological consistency is due to the absence of any features in the pixel design that are positioned below the photodiode or part of the photodiode, as is evident in Figures 6 and 9. In this case, when the processing steps for fabricating the various layers of the photodiode structure are performed over the smooth, planar surface of the array substrate, a smooth and flat surface and thickness uniformity is achieved for each layer. Therefore, the top of the photodiode structure will be smooth and flat, as observed in FIG. This smoothness and flatness is only limited by random local variations (approximately a few hundred angstroms) that originate from the processing steps used for the fabrication of the array. Note that during processing, other process variations can produce up to tens of percent system variation (eg, increase or decrease) across the thickness of a given layer of material across the array.
在使用基線架構之間接偵測陣列的狀況下,光電二極體展現極佳性質,包括感測可見光子及收集所得信號的高效率,及暗電流、電荷捕集、電荷釋放及延滯之有利的低位準-既無干擾此等極佳性質的歸因於製造過程的平滑性及平坦性之隨機局部變化,亦無干擾此等極佳性質的歸因於製造過程的材料厚度之系統變化。展現此等極佳性質之光電二極體結構(不管包含離散的基線架構設計,抑或連續的或離散的平面外設計)稱作具有高品質。對於給定成像陣列,此等性質中之每一者可經由量測個別像素之信號性質來獲得,且來自個別像素之結果或來自許多像素之結果之平均的結果可以以下方式來表達。每一像素之暗電流的此有利位準的量值(正規化至單位光電二極體面積)小於約1pA/mm2。每一像素之電荷捕集之此有利位準的量值(藉由在單一放射攝影圖框期間由於捕集而損失的成像信號之量來定量,且表達為在電荷捕集與電荷釋放處於平衡之條件下獲得的成像信號之百分 比)小於約20%。每一像素之電荷釋放之此有利位準的量值(藉由在具有輻射之情況下且在電荷捕集與電荷釋放處於平衡之條件下獲取的一系列圖框之後的在不存在輻射之情況下獲取的第一圖框期間自捕集狀態釋放的成像信號之量來定量,且表達為在電荷捕集與釋放處於平衡之條件下獲得的成像信號之百分比)小於約15%。每一像素之延滯之此有利位準的量值(藉由在具有輻射之情況下獲取的一個圖框或一系列圖框之後的在不存在輻射之情況下獲取的第一圖框期間自捕集狀態釋放之成像信號(其起源於在一或多個先前圖框中所捕集的電荷)之量來定量,且表達為來自先前圖框之成像信號之百分比)小於約15%。此等量測之結果通常亦稱作第一域延滯,或者,稱作第一圖框延滯。對於將光導材料用於轉換器之直接偵測主動式矩陣陣列,暗電流(正規化至單位光導體面積)、電荷捕集、電荷釋放及延滯之有利位準之量值類似於上文針對間接偵測陣列所描述之位準。 The photodiode exhibits excellent properties, including the high efficiency of sensing the visible light and collecting the resulting signal, and the benefits of dark current, charge trapping, charge release and delay, in the case of using an inter-connected detection array with a baseline architecture. The low level - there is no random local variation due to the smoothness and flatness of the manufacturing process that interferes with these excellent properties, nor the systematic variation of the material thickness attributed to the manufacturing process that interferes with such excellent properties. Photodiode structures that exhibit these excellent properties (whether including discrete baseline architecture designs or continuous or discrete out-of-plane designs) are said to be of high quality. For a given imaging array, each of these properties can be obtained by measuring the signal properties of the individual pixels, and the results from the individual pixels or the average of the results from many pixels can be expressed in the following manner. The magnitude of this favorable level of dark current per pixel (normalized to unit photodiode area) is less than about 1 pA/mm 2 . The magnitude of this favorable level of charge trapping per pixel (quantized by the amount of imaging signal lost due to trapping during a single radiographic frame, and expressed as being in equilibrium between charge trapping and charge release) The percentage of imaging signal obtained under conditions is less than about 20%. The magnitude of this favorable level of charge release per pixel (in the absence of radiation after a series of frames acquired with radiation and under conditions of charge trapping and charge release being balanced) The amount of imaging signal released from the capture state during the first frame acquired is quantified and expressed as a percentage of the imaging signal obtained under conditions in which charge trapping and release are in equilibrium) less than about 15%. The magnitude of this advantageous level of delay for each pixel (by the frame after a frame or series of frames acquired with radiation, during the first frame acquired in the absence of radiation) The amount of imaging signal released by the capture state (which originates from the charge trapped in one or more previous frames) is quantified and expressed as a percentage of the imaging signal from the previous frame) of less than about 15%. The result of these measurements is also commonly referred to as the first domain delay, or, referred to as the first frame delay. For direct detection of active matrix arrays using photoconductive materials for converters, the magnitudes of dark current (normalized to unit photoconductor area), charge trapping, charge release, and lag are similar to those described above. Indirectly detect the level described by the array.
對於使用基線架構之間接偵測陣列中的高品質光電二極體結構,一有助於上文所描述之極佳性質之因素為拓撲之一致性之程度。在先前所描述的表面平滑性、表面平坦性及厚度一致性的限度內,光電二極體中之個別n+型摻雜、純質及p+型摻雜a-Si層中之每一者具有一致厚度,頂部電極與底部電極均為平坦的,且此等電極平行於彼此。因此,電場強度隨跨越純質層之厚度之距離而變化的方式在光電二極體之區域上保持相對不變,且此為造成高品質光電二極體中之暗電流、電荷捕集、電荷釋放及延滯之有利位準的原因。 For the use of a high quality photodiode structure in the inter-connected detection array of the baseline architecture, one of the factors contributing to the excellent properties described above is the degree of topological consistency. Each of the individual n + -type doped, pure and p + -type doped a-Si layers in the photodiode within the limits of surface smoothness, surface flatness, and thickness uniformity previously described With a uniform thickness, both the top and bottom electrodes are flat and the electrodes are parallel to each other. Therefore, the manner in which the electric field strength varies with the distance across the thickness of the pure layer remains relatively constant over the area of the photodiode, and this causes dark current, charge trapping, and charge in the high quality photodiode. Reasons for the favorable level of release and delay.
相反地,在具有不一致拓撲之光電二極體結構中,在光電二極體之a-Si材料中產生極高及極低電場強度之區。在頂部電極或底部電極展現與平坦性的急劇的(亦即,突然的)偏離的光電二極體之區中,純質a-Si中之電場將顯著大於頂部電極與底部電極平行之區中的電場。在此等高電場區附近,電場強度將顯著低於頂部電極與底部電極 平行之區中的電場。平坦性之改變愈急劇(亦即,愈突然),電場強度之偏差將愈大。因為暗電流隨電場強度之增加而增加,所以電場強度顯著增加之區將導致暗電流之不利位準。類似地,因為電荷捕集隨電場強度之減小而增加,所以電場強度顯著減小之區將導致電荷捕集、電荷釋放及延滯之不利位準。 Conversely, in a photodiode structure having an inconsistent topology, regions of extremely high and very low electric field strength are produced in the a-Si material of the photodiode. In the region of the photodiode where the top or bottom electrode exhibits a sharp (ie, abrupt) deviation from flatness, the electric field in the pure a-Si will be significantly larger than in the region where the top electrode is parallel to the bottom electrode. Electric field. In the vicinity of this high electric field, the electric field strength will be significantly lower than the top and bottom electrodes The electric field in the parallel zone. The sharper the change in flatness (i.e., the more sudden), the greater the deviation in electric field strength. Since the dark current increases as the electric field strength increases, a region where the electric field strength is significantly increased will result in an unfavorable level of dark current. Similarly, because charge trapping increases with decreasing electric field strength, regions of significantly reduced electric field strength will result in undesirable levels of charge trapping, charge release, and retardation.
對於上文所描述的具有連續平面外光電二極體結構之像素設計的該三個實例(亦即,具有主動式矩陣設計(圖14)、具有單級像素內放大器設計(圖21及圖23),及具有兩級像素內放大器設計(圖22及圖24)),每一設計中的光電二極體之延伸的拓撲不一致性導致具有顯著增加之電場強度之延伸區,以及具有顯著減小之電場強度之延伸區。電極平坦性之急劇改變亦可實質上減小頂部電極與底部電極之間的最小距離(如在圖21中之深介層孔之區中顯而易見),從而進一步有助於電場強度之顯著增加。如發明者已發現,此等區之存在導致暗電流、電荷捕集、電荷釋放及延滯之不利的高位準且因此妨礙實現高品質光電二極體。 The three examples of pixel designs with continuous out-of-plane photodiode structures described above (ie, with active matrix design (Figure 14), with a single-stage in-pixel amplifier design (Figure 21 and Figure 23) ), and with a two-stage in-pixel amplifier design (Figures 22 and 24), the topological inconsistency of the extension of the photodiode in each design results in an extended region with significantly increased electric field strength, and a significant reduction The extension of the electric field strength. A sharp change in electrode flatness can also substantially reduce the minimum distance between the top and bottom electrodes (as is evident in the region of the deep via holes in Figure 21), further contributing to a significant increase in electric field strength. As the inventors have discovered, the presence of such zones results in unfavorably high levels of dark current, charge trapping, charge release and retardation and thus hinders the achievement of high quality photodiodes.
由於若干原因,高光電二極體暗電流係不合需要的。因為暗信號(由暗電流產生)在成像期間儲存於像素儲存電容器中,所以高暗電流顯著減小像素在飽和之前可操作的曝光之範圍。另外,因為暗電流產生稱作散粒雜訊之雜訊源,所以高暗電流導致高散粒雜訊。因為成像器中之散粒雜訊之此影響發生於來自像素內放大器(諸如,在圖15及圖18之像素電路設計中)之增益之效應之前,所以減小了成像器之信雜比之改良(與預期改良相比較)。類似地,高散粒雜訊減小了併有具有平面外光電二極體結構之AMFPI陣列之成像器的信雜比的意欲之改良(諸如,在圖11及圖12中所說明之像素設計中)。由於若干原因,電荷捕集之高位準係不合需要的。在放射攝影成像中,由於捕集狀態之信號損失減少了自像素取樣之成像信號,藉此減小了成像器之信雜 比。另外,電荷捕集之高位準導致電荷釋放及延滯之高位準,從而增加了影像假影之不合需要之後果。 High photodiode dark currents are undesirable for several reasons. Because dark signals (generated by dark current) are stored in the pixel storage capacitor during imaging, the high dark current significantly reduces the range of exposures that the pixel can operate before saturation. In addition, because dark current produces a noise source called shot noise, high dark currents cause high shot noise. Since the effect of the shot noise in the imager occurs before the gain from the in-pixel amplifier (such as in the pixel circuit design of Figures 15 and 18), the imager's signal-to-noise ratio is reduced. Improvement (compared to expected improvement). Similarly, high-volume noise reduces the intended improvement in the signal-to-noise ratio of an imager having an AMFPI array with an out-of-plane photodiode structure (such as the pixel design illustrated in Figures 11 and 12). in). The high level of charge trapping is undesirable for several reasons. In radiographic imaging, the signal loss due to the captured state reduces the imaging signal sampled from the pixel, thereby reducing the messenger of the imager. ratio. In addition, the high level of charge trapping leads to a high level of charge release and lag, which increases the undesirableness of image artifacts.
表面之平坦性(諸如,如圖21至圖24中所展示之光電二極體中的電極之拓撲)之改變的急劇性(亦即,突然性)可藉由曲率半徑r來定量,如圖25中所說明。平坦性之較急劇之改變因此藉由r之較小值來表示。電極平坦性之急劇改變(如藉由r來參數化)對光電二極體結構(表示連續及離散平面外設計中之彼等結構)之純質a-Si層中之電場強度的影響的計算判定指示了減小光電二極體結構中之此等急劇改變之重要性。 The sharpness (i.e., suddenness) of the change in the flatness of the surface (such as the topology of the electrodes in the photodiode as shown in Figures 21 to 24) can be quantified by the radius of curvature r , as shown in the figure. As explained in 25. The sharper change in flatness is therefore represented by the smaller value of r . Calculation of the effect of sharp changes in electrode flatness (as parameterized by r ) on the electric field strength in a pure a-Si layer of a photodiode structure (representing their structure in continuous and discrete out-of-plane designs) The decision indicates the importance of reducing such sharp changes in the photodiode structure.
在接近平坦性之改變(由為0.1μm或0.1μm以下之r值來特性化)之區中,電場之最大偏差可能非常大,比一對平行電極之電場之量值高300%以上(在最接近平坦性之改變之彼等區中)、比一對平行電極之電場之量值低60%以上(在彼等區附近)。在接近平坦性之改變(由為約0.5μm之r值來特性化)之區中,電場之偏差可比一對平行電極之電場之量值高多達約300%(在最接近平坦性之改變之彼等區中)、比一對平行電極之電場之量值低多達約60%(在彼等區附近)。 In the region close to the change in flatness (characterized by an r value of 0.1 μm or less), the maximum deviation of the electric field may be very large, which is more than 300% higher than the magnitude of the electric field of a pair of parallel electrodes (in The area closest to the change in flatness) is 60% or more lower than the magnitude of the electric field of a pair of parallel electrodes (near the zones). In a region close to the change in flatness (characterized by an r value of about 0.5 μm), the deviation of the electric field can be as much as about 300% higher than the magnitude of the electric field of a pair of parallel electrodes (the change in the closest flatness) In their respective zones, the magnitude of the electric field is less than about 60% (near the zone) than the magnitude of the electric field of a pair of parallel electrodes.
在接近平坦性之改變(由為約1μm之r值來特性化)之區中,電場之偏差可比一對平行電極之電場之量值高多達約200%(在最接近平坦性之改變之彼等區中)、比一對平行電極之電場之量值低多達約50%(在彼等區附近)。在接近平坦性之改變(由為約2μm之r值來特性化)之區中,電場之偏差可比一對平行電極之電場之量值高多達約50%(在最接近平坦性之改變之彼等區中)、比一對平行電極之電場之量值低多達約30%(在彼等區附近)。在接近平坦性之改變(由為約5μm之r值來特性化)之區中,電場之偏差可比一對平行電極之電場之量值高多達約20%(在最接近平坦性之改變之彼等區中)、比一對平行電極之電場之量值低多達約15%(在彼等區附近)。在接近平坦性之改變(由 為約10μm之r值來特性化)之區中,電場之偏差可比一對平行電極之電場之量值高多達約10%(在最接近平坦性之改變之彼等區中)、比一對平行電極之電場之量值低多達約10%(在彼等區附近)。 In a region close to the change in flatness (characterized by an r value of about 1 μm), the deviation of the electric field can be as much as about 200% higher than the magnitude of the electric field of a pair of parallel electrodes (in the closest change to flatness) In their zones, the magnitude of the electric field is less than about 50% (near the zone) than the pair of parallel electrodes. In a region close to the change in flatness (characterized by an r value of about 2 μm), the deviation of the electric field can be as much as about 50% higher than the magnitude of the electric field of a pair of parallel electrodes (in the closest change to flatness) In their zone), the magnitude of the electric field is less than about 30% (near the zone) than the pair of parallel electrodes. In a region close to the change in flatness (characterized by an r value of about 5 μm), the deviation of the electric field can be as much as about 20% higher than the magnitude of the electric field of a pair of parallel electrodes (in the closest change to flatness) In their zones, the magnitude of the electric field is less than about 15% (near the zone) than the pair of parallel electrodes. In a region close to the change in flatness (characterized by an r value of about 10 μm), the deviation of the electric field can be as much as about 10% higher than the magnitude of the electric field of a pair of parallel electrodes (in the closest change to flatness) In their zones, the magnitude of the electric field is less than about 10% (near the zone) than the pair of parallel electrodes.
上述考慮使得以下顯而易見:若製造平面外光電二極體結構而不考慮光電二極體之拓撲一致性,則所得拓撲(將稱作原生拓撲,諸如顯現於圖21至圖24中所展示之實例中)可妨礙實現高品質光電二極體且使併有具有此等光電二極體之陣列之成像器的效能降級。大體而言,暗電流、電荷捕集、電荷釋放及延滯之量值將隨著光電二極體之電極的具有平坦性的急劇改變的區之範圍(亦即,數目及面積)增加而增加。此等量值亦將隨著電極之平坦性之改變的急劇性增加而增加。然而,根據本發明之一實施例,實現了高品質平面外光電二極體結構,其中光電二極體經設計及製造以使得此等區之範圍以及電極之平坦性之改變的急劇性被足夠減小,以使得光電二極體展現暗電流、電荷捕集、電荷釋放及延滯之有利位準。 The above considerations make it obvious that if an out-of-plane photodiode structure is fabricated without regard to the topological consistency of the photodiode, the resulting topology (which will be referred to as a native topology, such as the one shown in Figures 21-24) Medium) can impede the achievement of high quality photodiodes and degrade the performance of an imager having an array of such photodiodes. In general, the magnitudes of dark current, charge trapping, charge release, and retardation will increase as the range (i.e., number and area) of the sharply changing regions of the electrodes of the photodiode increases. . These magnitudes will also increase as the sharpness of the change in the flatness of the electrode increases. However, in accordance with an embodiment of the present invention, a high quality out-of-plane photodiode structure is realized in which the photodiode is designed and fabricated such that the extent of the regions and the sharpness of the change in the flatness of the electrodes are sufficient The reduction is such that the photodiode exhibits a favorable level of dark current, charge trapping, charge release, and retardation.
圖26至圖34展示應用各種方法以改良平面外光電二極體結構之拓撲一致性之結果的實例。一種用於改良拓撲一致性之方法為使在光電二極體結構下方之一材料層完全平坦化。此方法之應用之說明顯現於針對單級像素內放大器設計之狀況的圖26(a)及圖31(b)中,及針對兩級像素內放大器設計之狀況的圖27及圖32(b)中。在每一狀況下,已使鈍化#2之頂面為平坦的。 26 through 34 show examples of the results of applying various methods to improve the topological consistency of an out-of-plane photodiode structure. One method for improving topological uniformity is to completely planarize one of the material layers below the photodiode structure. The description of the application of this method is shown in Figure 26(a) and Figure 31(b) for the state of the single-stage in-pixel amplifier design, and Figure 27 and Figure 32(b) for the state of the two-stage in-pixel amplifier design. in. In each case, the top surface of passivation #2 has been made flat.
此可(例如,在本發明之一實施例中)經由應用化學-機械拋光(CMP,亦稱為化學-機械平坦化)及/或旋塗來達成。在應用此方法的過程中,最初可使鈍化層之厚度比原生拓撲狀況下之厚度厚,以便確保在應用CMP之後的最小厚度。此將有助於確保光電二極體電極與在光電二極體結構下方之電路元件之間的寄生電容保持低於一所要極限。圖26(a)及圖27分別提供與圖21及圖22中所說明之原生拓撲之狀 況下的拓撲一致性相比較的光電二極體之拓撲一致性之所得改良的橫截面圖。圖31(b)及圖32(b)分別提供與圖31(a)及圖32(a)中所說明之原生拓撲相比較的光電二極體之拓撲一致性之所得改良的俯視圖。此方法在顯著改良拓撲一致性方面之有效性係顯而易見的。用於改良平面外光電二極體結構之拓撲一致性之另一方法為使在光電二極體結構下方之一材料層部分地平坦化,如圖26(b)中所說明。此可經由使用各種已知技術(諸如,上文所描述之彼等技術)來達成。 This can be achieved (for example, in one embodiment of the invention) via the application of chemical-mechanical polishing (CMP, also known as chemical-mechanical planarization) and/or spin coating. In applying this method, the thickness of the passivation layer can be initially made thicker than in the native topological condition to ensure a minimum thickness after application of CMP. This will help to ensure that the parasitic capacitance between the photodiode electrode and the circuit components underneath the photodiode structure remains below a desired limit. 26(a) and FIG. 27 provide the same as the native topology illustrated in FIGS. 21 and 22, respectively. An improved cross-sectional view of the topological consistency of the photodiode compared to the topological consistency. 31(b) and 32(b) are plan views showing an improvement in the topological consistency of the photodiode as compared with the native topology illustrated in FIGS. 31(a) and 32(a). The effectiveness of this approach in significantly improving topological consistency is evident. Another method for improving the topological consistency of the out-of-plane photodiode structure is to partially planarize a layer of material beneath the photodiode structure, as illustrated in Figure 26(b). This can be achieved via the use of various known techniques, such as those described above.
在連續平面外光電二極體結構中,底部電極(由金屬#2層形成)之邊緣產生頂部電極之平坦性之急劇改變,如在圖26(a)及圖27(a)中顯而易見的。在本發明之一實施例中,需要使此等邊緣平滑化。一根據本發明之用以達成此平滑化之方法為經由調整用以界定底部電極之邊緣之蝕刻技術,以便達成具有比原生拓撲中之曲率半徑大之曲率半徑的傾斜或圓形形狀。圖28及圖29分別提供與圖26(a)及圖27(a)中所展示之彼拓撲一致性相比較的光電二極體之拓撲一致性之所得改良的橫截面圖。圖31(c)及圖32(c)分別提供與圖31(b)及圖32(b)中所展示之彼拓撲一致性相比較的光電二極體之拓撲一致性之所得改良的俯視圖。此方法在進一步改良拓撲一致性方面之有效性係顯而易見的。 In a continuous out-of-plane photodiode structure, the edge of the bottom electrode (formed by the metal #2 layer) produces a sharp change in the flatness of the top electrode, as is evident in Figures 26(a) and 27(a). In an embodiment of the invention, these edges need to be smoothed. A method for achieving this smoothing in accordance with the present invention is to adjust the etching technique used to define the edges of the bottom electrode to achieve a slanted or circular shape having a radius of curvature greater than the radius of curvature in the native topology. Figures 28 and 29 provide improved cross-sectional views of the topological uniformity of the photodiode as compared to the topological consistency shown in Figures 26(a) and 27(a), respectively. Figures 31(c) and 32(c) respectively provide an improved top view of the topological consistency of the photodiodes compared to the topological consistency shown in Figures 31(b) and 32(b). The effectiveness of this approach in further improving topological consistency is evident.
在連續平面外光電二極體結構中,將光電二極體之底部電極連接至後部接點之一或多個介層孔亦產生頂部電極及底部電極之平坦性之急劇改變。一根據本發明之用於減小平坦性之此等改變的急劇性的方法為藉由使每一介層孔之橫向尺寸(亦即,沿著光電二極體之表面之尺寸)窄化(例如)至設計規則所允許之極限而減小每一介層孔之面積。亦可沈積用於底部電極之金屬以便填充介層孔。圖30為與圖28中所展示之拓撲一致性相比較的光電二極體之拓撲一致性之所得改良的橫截面圖。(由於在圖29之視野內不存在介層孔,未展示兩級像素內放大器設計之對應橫截面說明。)圖31(d)及圖32(d)分別為與圖31(c)及 圖32(c)中所展示之拓撲一致性相比較的光電二極體之拓撲一致性之所得改良的俯視圖。本發明之此方法在進一步改良拓撲一致性方面之有效性係顯而易見的。 In a continuous out-of-plane photodiode structure, connecting the bottom electrode of the photodiode to one or more of the via contacts also produces a sharp change in the flatness of the top and bottom electrodes. A method for reducing the sharpness of such changes in flatness according to the present invention is by narrowing the lateral dimension of each via (i.e., along the surface of the photodiode) (e.g., ) to reduce the area of each via hole to the limits allowed by the design rules. Metal for the bottom electrode can also be deposited to fill the via holes. Figure 30 is a cross-sectional view showing the resulting improved topological consistency of the photodiode as compared to the topological consistency shown in Figure 28. (Because there is no via hole in the field of view of Figure 29, the corresponding cross-section description of the two-stage in-pixel amplifier design is not shown.) Figures 31(d) and 32(d) are shown in Figure 31(c) and An improved top view of the topological consistency of the photodiode compared to the topological consistency shown in Figure 32(c). The effectiveness of this method of the invention in further improving topological consistency is evident.
用於改良平面外光電二極體結構之拓撲一致性之另一方法為使光電二極體中之純質a-Si層之頂面平坦化。此方法針對單級像素內放大器設計之狀況的應用的說明顯現於圖33、圖34(b)及圖34(c)中。 Another method for improving the topological uniformity of the out-of-plane photodiode structure is to planarize the top surface of the pure a-Si layer in the photodiode. A description of the application of this method to the state of the single-stage in-pixel amplifier design is shown in Figures 33, 34(b), and 34(c).
光電二極體中之純質a-Si層之完全平坦化可(例如)在本發明之一實施例中經由應用CMP來達成。在應用此方法的過程中,最初可使純質a-Si層之厚度比較佳厚度厚,以便確保在應用CMP之後所達成的最終厚度對應於彼較佳厚度。此將有助於確保光電二極體展現極佳性質。圖33(a)提供與圖21中所說明之原生拓撲之狀況相比較的所得改良之橫截面圖。圖34(c)提供與圖34(a)中所說明之原生拓撲相比較的光電二極體之拓撲一致性之所得改良的俯視圖。此方法在顯著改良光電二極體之頂部電極之一致性方面的有效性係顯而易見的。與原生拓撲相比較,底部電極之一致性保持不變。用於改良平面外光電二極體結構之拓撲一致性的此方法之另一實施例為使光電二極體中之純質a-Si層部分地平坦化,如圖33(b)及圖34(b)中所說明。此可經由使用各種已知技術(諸如,上文所描述之彼等技術)來達成。 Full planarization of the pure a-Si layer in the photodiode can be achieved, for example, by applying CMP in one embodiment of the invention. In applying this method, the thickness of the pure a-Si layer can be initially made thicker to ensure that the final thickness achieved after application of CMP corresponds to its preferred thickness. This will help ensure that the photodiode exhibits excellent properties. Figure 33 (a) provides a cross-sectional view of the resulting improvement compared to the condition of the native topology illustrated in Figure 21. Figure 34 (c) provides a top view of the resulting improved topological consistency of the photodiode as compared to the native topology illustrated in Figure 34 (a). The effectiveness of this method in significantly improving the uniformity of the top electrode of the photodiode is evident. The consistency of the bottom electrode remains the same compared to the native topology. Another embodiment of the method for improving the topological uniformity of the out-of-plane photodiode structure is to partially planarize the pure a-Si layer in the photodiode, as shown in Figures 33(b) and 34. As explained in (b). This can be achieved via the use of various known techniques, such as those described above.
可組合地使用如本文中所描述的用於改良平面外光電二極體結構之拓撲一致性之方法以達成本發明之所要結果,該等方法包括:使在光電二極體結構下方之一或多個材料層(諸如,鈍化層)平坦化,使光電二極體結構之底部電極之邊緣平滑化,使將光電二極體之底部電極連接至後部接點之介層孔的橫向尺寸窄化及/或沈積用於底部電極之金屬以便填充介層孔,及使光電二極體中之純質a-Si平坦化。 A method for improving the topological uniformity of an out-of-plane photodiode structure as described herein can be used in combination to achieve the desired results of the present invention, including: one of being under the photodiode structure or The planarization of a plurality of material layers (such as a passivation layer) smoothes the edge of the bottom electrode of the photodiode structure, narrowing the lateral dimension of the via hole connecting the bottom electrode of the photodiode to the rear contact And/or depositing a metal for the bottom electrode to fill the via hole and planarizing the pure a-Si in the photodiode.
如自圖31、圖32及圖34中所展示之生動結果顯而易見,本發明提供一種移除與像素電路元件之邊緣相關聯之拓撲不一致性的能力。 該等平坦化技術(如上文所描述)使覆蓋像素電路元件或陣列特徵之層平坦化,該等像素電路元件或陣列特徵諸如以下各項:TFT(包括TFT之源極、汲極及閘極)、二極體、電容器及電阻器,以及介層孔、跡線、控制線、位址線、接地平面、電極表面、阻光表面、偏壓線、後部接點及光電二極體之底部電極(其皆由多個金屬層、鈍化層或介電層製成),如上文所論述且諸如在圖26至圖30及圖33之截面圖中所展示。以此方式,本發明不限於在薄膜電晶體元件之上之平坦化。舉例而言,甚至與所有TFT像素電路元件或陣列特徵(包括但不限於控制線及位址線)相關聯之不一致性之效應亦可藉由平坦化沈積於此等結構之上的後續層而減輕,此等結構包括(例如)穿過下部鈍化層#1之電介層孔互連件(如在(例如)圖26中所展示)。甚至由於單級像素內放大器設計(如在圖17、圖21及圖23中)或兩級像素內放大器設計(如在圖20、圖22及圖24中)而引入的不一致性效應亦可藉由平坦化沈積於此等結構之上之後續層而減輕。 As is apparent from the vivid results shown in Figures 31, 32, and 34, the present invention provides an ability to remove topological inconsistencies associated with edges of pixel circuit components. The planarization techniques (as described above) planarize layers that cover pixel circuit elements or array features, such as the following: TFTs (including the source, drain, and gate of the TFT) ), diodes, capacitors and resistors, as well as vias, traces, control lines, address lines, ground planes, electrode surfaces, light-blocking surfaces, bias lines, rear contacts, and the bottom of the photodiode The electrodes, which are all made of a plurality of metal layers, passivation layers or dielectric layers, are as discussed above and are shown, for example, in the cross-sectional views of Figures 26-30 and 33. In this manner, the invention is not limited to planarization over thin film transistor elements. For example, even the effects of inconsistencies associated with all TFT pixel circuit elements or array features, including but not limited to control lines and address lines, can also be achieved by planarizing subsequent layers deposited over such structures. To mitigate, such structures include, for example, dielectric via interconnects through lower passivation layer #1 (as shown, for example, in Figure 26). Even inconsistencies introduced by single-stage in-pixel amplifier designs (as in Figures 17, 21, and 23) or two-stage in-pixel amplifier designs (as in Figures 20, 22, and 24) can be borrowed Reduced by planarization of subsequent layers deposited on top of such structures.
鑒於上述詳細描述,下文以更一般之術語來描述本發明之不同實施例之各種元件(但並不以其他方式限制本發明),以便說明本發明之特徵。 In view of the above detailed description, the various elements of the various embodiments of the present invention are described in the <RTIgt;
在第一說明實施例中,一輻射感測器包括:一閃爍層,該閃爍層經組態以在與電離輻射相互作用時發射光子;及一光偵測器,其按次序包括一第一電極、一感光層,及接近於該閃爍層而安置之一可透射光子之第二電極。該感光層經組態以在與該等光子之一部分相互作用時產生電子電洞對。該輻射感測器包括像素電路,其電連接至該第一電極且經組態以量測指示在該感光層中所產生之該等電子電洞對之一成像信號;及一平坦化層,其安置於該像素電路上在該第一電極與該像素電路之間,以使得該第一電極高於包括該像素電路之一平面。該第一電極及該第二電極中之至少一者之一表面至少部分地重疊於該 像素電路且具有高於該像素電路之特徵之一表面反曲。該表面反曲具有大於1/2微米之一曲率半徑。 In a first illustrative embodiment, a radiation sensor includes: a scintillation layer configured to emit photons when interacting with ionizing radiation; and a photodetector including a first in order An electrode, a photosensitive layer, and a second electrode capable of transmitting photons disposed adjacent to the scintillation layer. The photosensitive layer is configured to create an electron hole pair when interacting with a portion of the photons. The radiation sensor includes a pixel circuit electrically coupled to the first electrode and configured to measure an imaging signal indicative of one of the pairs of electron holes generated in the photosensitive layer; and a planarization layer, It is disposed on the pixel circuit between the first electrode and the pixel circuit such that the first electrode is higher than a plane including the pixel circuit. a surface of at least one of the first electrode and the second electrode at least partially overlapping the surface The pixel circuit has a surface recursion that is higher than one of the features of the pixel circuit. The surface recursion has a radius of curvature greater than one of 1/2 microns.
該表面反曲可(例如)取決於所要或所達成之平坦化之程度而具有一大於1微米、大於5微米、大於10微米或大於100微米之曲率半徑。平坦化層可接著完全地或部分地在像素電路之特徵之上、在陣列特徵之上、在連接至TFT之源極或汲極的電介層孔互連件之上、在單級像素內放大器元件之上及/或在兩級像素內放大器元件之上平坦化。平坦化層可為鈍化層、介電層或絕緣層中之至少一者。 The surface recursion can have a radius of curvature greater than 1 micrometer, greater than 5 micrometers, greater than 10 micrometers, or greater than 100 micrometers, for example, depending on the degree of planarization desired or achieved. The planarization layer can then be wholly or partially over the features of the pixel circuit, over the array features, over the dielectric via interconnects connected to the source or drain of the TFT, within a single level of pixels The amplifier element is planarized over the amplifier element and/or over the amplifier elements within the two-stage pixel. The planarization layer can be at least one of a passivation layer, a dielectric layer, or an insulating layer.
在此實施例之一態樣中,輻射感測器可包括安置於光偵測器之下之位址線及資料線,且平坦化層安置於位址線及資料線上以及位址線及資料線之介層孔上。另外,電介層孔互連件可延伸穿過平坦化層且將第一電極連接至像素電路。與感光層接觸之電介層孔互連件之表面反曲可具有一大於1/2微米、大於1微米、大於5微米、大於10微米及大於100微米之曲率半徑。 In one aspect of this embodiment, the radiation sensor can include address lines and data lines disposed under the photodetector, and the planarization layer is disposed on the address lines and data lines as well as the address lines and data. On the layer of the hole. Additionally, the dielectric via interconnects can extend through the planarization layer and connect the first electrode to the pixel circuitry. The surface reflex of the dielectric via interconnect in contact with the photosensitive layer can have a radius of curvature greater than 1/2 micron, greater than 1 micron, greater than 5 microns, greater than 10 microns, and greater than 100 microns.
在此實施例之一態樣中,感光層可為p-i-n半導體堆疊、n-i-p半導體堆疊或金屬絕緣體半導體堆疊中之一者。像素電路可包括薄膜電晶體、二極體、電容器、電阻器、跡線、介層孔、控制線、位址線及接地平面中之一者。像素電路可為非晶系半導體電晶體或多晶半導體電晶體或微晶半導體電晶體中之一者。像素電路可包括定址電晶體、放大器電晶體及重設電晶體中之至少一者。像素電路可為非晶矽、低溫非晶矽及微晶矽中之至少一者。像素電路可為以下各項中之至少一者:矽半導體、氧化物半導體、硫族化物半導體、硒化鎘半導體、有機半導體、有機小分子或聚合物半導體、碳奈米管,或石墨薄膜,或其他半導電材料。 In one aspect of this embodiment, the photosensitive layer can be one of a p-i-n semiconductor stack, an n-i-p semiconductor stack, or a metal insulator semiconductor stack. The pixel circuit can include one of a thin film transistor, a diode, a capacitor, a resistor, a trace, a via, a control line, an address line, and a ground plane. The pixel circuit may be one of an amorphous semiconductor transistor or a polycrystalline semiconductor transistor or a microcrystalline semiconductor transistor. The pixel circuit can include at least one of an address transistor, an amplifier transistor, and a reset transistor. The pixel circuit may be at least one of amorphous germanium, low temperature amorphous germanium, and microcrystalline germanium. The pixel circuit may be at least one of: a germanium semiconductor, an oxide semiconductor, a chalcogenide semiconductor, a cadmium selenide semiconductor, an organic semiconductor, an organic small molecule or a polymer semiconductor, a carbon nanotube, or a graphite film, Or other semi-conductive materials.
在此實施例之一態樣中,感光層可為以下各項中之至少一者:1)跨越複數個光偵測器像素延伸之連續感光層,或2)與該複數個光偵測 器像素中之各別者相關聯的離散感光層。閃爍層可為以下各項中之至少一者:CsI:Tl、Gd2O2S:Tb、CsI:Na、NaI:Tl、CaWO4、ZnWO4、CdWO4、Bi4Ge3O12、Lu1.8Yb0.2SiO5:Ce、Gd2SiO5:Ce、BaFCl:Eu2+、BaSO4:Eu2+、BaFBr:Eu2+、LaOBr:Tb3+、LaOBr:Tm3+、La2O2S:Tb3+、Y2O2S:Tb3+、YTaO4、YTaO4:Nb、ZnS:Ag、(Zn,Cd)S:Ag、ZnSiO4:Mn2+、CSI、LiI:Eu2+、PbWO4、Bi4Si3O12、Lu2SiO5:Ce3+、YAlO3:Ce3+、CSF、CaF2:Eu2+、BaF2、CeF3、Y1.34Gd0.6O3:Eu3+、Pr、Gd2O2S:Pr3+、Ce、SCGl、HFG:Ce3+(5%)及C14H10,或其他閃爍器材料。 In one aspect of this embodiment, the photosensitive layer can be at least one of: 1) a continuous photosensitive layer extending across a plurality of photodetector pixels, or 2) and the plurality of photodetectors A discrete photosensitive layer associated with each of the pixels. The scintillation layer may be at least one of the following: CsI: Tl, Gd 2 O 2 S: Tb, CsI: Na, NaI: Tl, CaWO 4 , ZnWO 4 , CdWO 4 , Bi 4 Ge 3 O 12 , Lu 1.8 Yb 0.2 SiO 5 :Ce, Gd 2 SiO 5 :Ce, BaFCl:Eu 2+ , BaSO 4 :Eu 2+ , BaFBr:Eu 2+ ,LaOBr:Tb 3+ ,LaOBr:Tm 3+ ,La 2 O 2 S: Tb 3+ , Y 2 O 2 S: Tb 3+ , YTaO 4 , YTaO 4 : Nb, ZnS: Ag, (Zn, Cd) S: Ag, ZnSiO 4 : Mn 2+ , CSI, LiI: Eu 2 + , PbWO 4 , Bi 4 Si 3 O 12 , Lu 2 SiO 5 :Ce 3+ , YAlO 3 :Ce 3+ , CSF, CaF 2 :Eu 2+ , BaF 2 , CeF 3 , Y 1.34 Gd 0.6 O 3 : Eu 3+ , Pr, Gd 2 O 2 S: Pr 3+ , Ce, SCG1, HFG: Ce 3+ (5%) and C 14 H 10 , or other scintillator materials.
在此實施例之一態樣中,輻射感測器可包括一支撐像素電路、光偵測器及閃爍層之基底基板,且可包括以規則圖案排列於該基底基板上之複數個光偵測器像素。在此實施例之一態樣中,可透射光子之第二電極可形成一用於該複數個光偵測器像素之偏壓平面。像素電路之一部分可安置於基底基板上在鄰近光偵測器像素之間的間隙區中。此部分可包括薄膜電晶體、二極體、電容器、電阻器、介層孔、跡線、控制線、位址線及接地平面中之一者。在此實施例之一態樣中,第一電極可具有終止於該間隙區近旁之傾斜末端。 In one aspect of this embodiment, the radiation sensor can include a base substrate supporting the pixel circuit, the photodetector, and the scintillation layer, and can include a plurality of light detections arranged on the base substrate in a regular pattern. Pixel. In one aspect of this embodiment, the second electrode that transmits photons can form a bias plane for the plurality of photodetector pixels. A portion of the pixel circuit can be disposed on the base substrate in a gap region between adjacent photodetector pixels. This portion may include one of a thin film transistor, a diode, a capacitor, a resistor, a via, a trace, a control line, an address line, and a ground plane. In one aspect of this embodiment, the first electrode can have a sloped end that terminates near the gap region.
在此實施例之一態樣中,第一電極與可透射光子之第二電極之間的暗電流(正規化至單位光偵測器面積)可小於10pA/mm2,或小於5pA/mm2,或小於1pA/mm2,或小於0.5pA/mm2。暗電流之位準在某種程度上與上文所論述的平坦化之程度及表面反曲之曲率半徑耦合。在此實施例之一態樣中,在感光層中最接近表面反曲之區中的電場可為在一對平行的第一電極與第二電極之間的感光層中之電場的60%以上及300%以下。電場之變化在某種程度上與上文所論述的平坦化之程度及表面反曲之曲率半徑耦合。 In one aspect of this embodiment, the dark current (normalized to unit photodetector area) between the first electrode and the second electrode that can transmit photons can be less than 10 pA/mm 2 , or less than 5 pA/mm 2 , or less than 1pA / mm 2, or less than 0.5pA / mm 2. The level of dark current is somewhat coupled to the degree of planarization discussed above and the radius of curvature of the surface recursion. In one aspect of this embodiment, the electric field in the region of the photosensitive layer closest to the surface recursion may be more than 60% of the electric field in the photosensitive layer between a pair of parallel first and second electrodes. And below 300%. The change in the electric field is coupled to some extent to the degree of planarization discussed above and the radius of curvature of the surface recursion.
在此實施例之一態樣中,感測器可包括一金屬板,其安置於閃 爍層上或安置於閃爍層上之囊封上。 In one aspect of this embodiment, the sensor can include a metal plate that is placed in the flash The encapsulation on the layer or on the scintillation layer.
在第二說明實施例中,一輻射感測器包括:一閃爍層,該閃爍層經組態以在與電離輻射相互作用時發射光子;一光偵測器,其按次序包括一第一電極、一感光層,及接近於該閃爍層而安置之一可透射光子之第二電極。該感光層經組態以在與該等光子之一部分相互作用時產生電子電洞對。該輻射感測器包括像素電路,其電連接至該第一電極且經組態以量測指示在該感光層中所產生之該等電子電洞對之一成像信號;且包括一平坦化層,其安置於該像素電路上在該第一電極與該像素電路之間,以使得該第一電極高於包括該像素電路之一平面。該平坦化層具有沿著像素電路元件之特徵之周邊邊緣的第一表面反曲,該第一電極具有第二表面反曲,該第二表面反曲高於該第一表面反曲且在平坦化層之與基底基板相反之表面上,且該第二表面反曲具有大於1/2微米之一曲率半徑。 In a second illustrative embodiment, a radiation sensor includes: a scintillation layer configured to emit photons when interacting with ionizing radiation; a photodetector including a first electrode in sequence And a photosensitive layer, and a second electrode capable of transmitting photons disposed adjacent to the scintillation layer. The photosensitive layer is configured to create an electron hole pair when interacting with a portion of the photons. The radiation sensor includes a pixel circuit electrically coupled to the first electrode and configured to measure an imaging signal indicative of one of the pairs of electron holes generated in the photosensitive layer; and including a planarization layer And disposed between the first electrode and the pixel circuit on the pixel circuit such that the first electrode is higher than a plane including the pixel circuit. The planarization layer has a first surface recurve along a peripheral edge of a feature of the pixel circuit component, the first electrode having a second surface recursion, the second surface being recurved higher than the first surface and being flat The surface of the layer opposite the base substrate, and the second surface has a curvature radius greater than one of 1/2 micrometers.
在此實施例之一態樣中,第二表面反曲可(例如)取決於所要或所達成之平坦化之程度而具有一大於1微米、大於5微米、大於10微米或大於100微米之曲率半徑。平坦化層可接著完全地或部分地在像素電路之特徵之上、在陣列特徵之上、在連接至TFT之源極或汲極的電介層孔互連件之上、在單級像素內放大器元件之上及/或在兩級像素內放大器元件之上平坦化。平坦化層可為鈍化層、介電層或絕緣層中之至少一者。 In one aspect of this embodiment, the second surface recursion can have a curvature greater than 1 micrometer, greater than 5 micrometers, greater than 10 micrometers, or greater than 100 micrometers, for example, depending on the degree of planarization desired or achieved. radius. The planarization layer can then be wholly or partially over the features of the pixel circuit, over the array features, over the dielectric via interconnects connected to the source or drain of the TFT, within a single level of pixels The amplifier element is planarized over the amplifier element and/or over the amplifier elements within the two-stage pixel. The planarization layer can be at least one of a passivation layer, a dielectric layer, or an insulating layer.
在此實施例之一態樣中,輻射感測器可包括安置於光偵測器之下之位址線及資料線,且平坦化層安置於位址線及資料線上以及位址線及資料線之介層孔上。另外,電介層孔互連件可延伸穿過平坦化層且將第一電極連接至像素電路。與感光層接觸之電介層孔互連件之表面反曲可具有一大於1/2微米、大於1微米、大於5微米、大於10微米或大於100微米之曲率半徑。 In one aspect of this embodiment, the radiation sensor can include address lines and data lines disposed under the photodetector, and the planarization layer is disposed on the address lines and data lines as well as the address lines and data. On the layer of the hole. Additionally, the dielectric via interconnects can extend through the planarization layer and connect the first electrode to the pixel circuitry. The surface reflex of the dielectric via interconnect in contact with the photosensitive layer can have a radius of curvature greater than 1/2 micron, greater than 1 micron, greater than 5 microns, greater than 10 microns, or greater than 100 microns.
在此實施例之一態樣中,感光層可為p-i-n半導體堆疊、n-i-p半導體堆疊或金屬絕緣體半導體堆疊中之一者。像素電路可包括薄膜電晶體、二極體、電容器、電阻器、跡線、介層孔、控制線、位址線及接地平面中之一者。像素電路可為非晶系半導體電晶體或多晶半導體電晶體或微晶半導體電晶體中之一者。像素電路可包括定址電晶體、放大器電晶體及重設電晶體中之至少一者。像素電路可為非晶矽、低溫非晶矽及微晶矽中之至少一者。像素電路可為以下各項中之至少一者:矽半導體、氧化物半導體、硫族化物半導體、硒化鎘半導體、有機半導體、有機小分子或聚合物半導體、碳奈米管,或石墨薄膜,或其他半導電材料。 In one aspect of this embodiment, the photosensitive layer can be one of a p-i-n semiconductor stack, an n-i-p semiconductor stack, or a metal insulator semiconductor stack. The pixel circuit can include one of a thin film transistor, a diode, a capacitor, a resistor, a trace, a via, a control line, an address line, and a ground plane. The pixel circuit may be one of an amorphous semiconductor transistor or a polycrystalline semiconductor transistor or a microcrystalline semiconductor transistor. The pixel circuit can include at least one of an address transistor, an amplifier transistor, and a reset transistor. The pixel circuit may be at least one of amorphous germanium, low temperature amorphous germanium, and microcrystalline germanium. The pixel circuit may be at least one of: a germanium semiconductor, an oxide semiconductor, a chalcogenide semiconductor, a cadmium selenide semiconductor, an organic semiconductor, an organic small molecule or a polymer semiconductor, a carbon nanotube, or a graphite film, Or other semi-conductive materials.
在此實施例之一態樣中,感光層可為以下各項中之至少一者:1)跨越複數個光偵測器像素延伸之連續感光層,或2)與該複數個光偵測器像素中之各別者相關聯的離散感光層。閃爍層可為以下各項中之至少一者:CsI:Tl、Gd2O2S:Tb、CsI:Na、NaI:Tl、CaWO4、ZnWO4、CdWO4、Bi4Ge3O12、Lu1.8Yb0.2SiO5:Ce、Gd2SiO5:Ce、BaFCl:Eu2+、BaSO4:Eu2+、BaFBr:Eu2+、LaOBr:Tb3+、LaOBr:Tm3+、La2O2S:Tb3+、Y2O2S:Tb3+、YTaO4、YTaO4:Nb、ZnS:Ag、(Zn,Cd)S:Ag、ZnSiO4:Mn2+、CsI、LiI:Eu2+、PbWO4、Bi4Si3O12、Lu2SiO5:Ce3+、YAlO3:Ce3+、CsF、CaF2:Eu2+、BaF2、CeF3、Y1.34Gd0.6O3:Eu3+、Pr、Gd2O2S:Pr3+、Ce、SCGl、HFG:Ce3+(5%)及C14H10,或其他閃爍器材料。 In one aspect of this embodiment, the photosensitive layer can be at least one of: 1) a continuous photosensitive layer extending across a plurality of photodetector pixels, or 2) and the plurality of photodetectors A discrete photosensitive layer associated with each of the pixels. The scintillation layer may be at least one of the following: CsI: Tl, Gd 2 O 2 S: Tb, CsI: Na, NaI: Tl, CaWO 4 , ZnWO 4 , CdWO 4 , Bi 4 Ge 3 O 12 , Lu 1.8 Yb 0.2 SiO 5 :Ce, Gd 2 SiO 5 :Ce, BaFCl:Eu 2+ , BaSO 4 :Eu 2+ , BaFBr:Eu 2+ ,LaOBr:Tb 3+ ,LaOBr:Tm 3+ ,La 2 O 2 S: Tb 3+ , Y 2 O 2 S: Tb 3+ , YTaO 4 , YTaO 4 : Nb, ZnS: Ag, (Zn, Cd) S: Ag, ZnSiO 4 : Mn 2+ , CsI, LiI: Eu 2 + , PbWO 4 , Bi 4 Si 3 O 12 , Lu 2 SiO 5 :Ce 3+ , YAlO 3 :Ce 3+ , CsF, CaF 2 :Eu 2+ , BaF 2 , CeF 3 , Y 1.34 Gd 0.6 O 3 : Eu 3+ , Pr, Gd 2 O 2 S: Pr 3+ , Ce, SCG1, HFG: Ce 3+ (5%) and C 14 H 10 , or other scintillator materials.
在此實施例之一態樣中,輻射感測器可包括一支撐像素電路、光偵測器及閃爍層之基底基板。輻射感測器可包括以規則圖案排列於該基底基板上之複數個光偵測器像素。在此實施例之一態樣中,該可透射光子之第二電極可形成一用於該複數個光偵測器像素之偏壓平面。像素電路之一部分可安置於基底基板上在鄰近光偵測器像素之間 的間隙區中。此部分可包括薄膜電晶體、二極體、電容器、電阻器、介層孔、跡線、控制線、位址線及接地平面中之一者。在此實施例之一態樣中,第一電極可具有終止於該間隙區近旁之傾斜末端。該傾斜邊緣可具有一大於1/2微米、或大於1微米、或大於5微米、或大於10微米或大於100微米之曲率半徑。 In one aspect of this embodiment, the radiation sensor can include a base substrate supporting the pixel circuit, the photodetector, and the scintillation layer. The radiation sensor can include a plurality of photodetector pixels arranged in a regular pattern on the base substrate. In one aspect of this embodiment, the photo-transmissive second electrode can form a bias plane for the plurality of photodetector pixels. One portion of the pixel circuit can be disposed on the base substrate between adjacent photodetector pixels In the gap area. This portion may include one of a thin film transistor, a diode, a capacitor, a resistor, a via, a trace, a control line, an address line, and a ground plane. In one aspect of this embodiment, the first electrode can have a sloped end that terminates near the gap region. The sloped edge can have a radius of curvature greater than 1/2 micrometer, or greater than 1 micrometer, or greater than 5 micrometers, or greater than 10 micrometers or greater than 100 micrometers.
在此實施例之一態樣中,第一電極與可透射光子之第二電極之間的暗電流(正規化至單位光偵測器面積)可小於10pA/mm2,或小於5pA/mm2,或小於1pA/mm2,或小於0.5pA/mm2。暗電流之位準在某種程度上與上文所論述的平坦化之程度及表面反曲之曲率半徑耦合。在此實施例之一態樣中,在感光層中最接近表面反曲之區中的電場可為在一對平行的第一電極與第二電極之間的感光層中之電場的60%以上及300%以下。電場之變化在某種程度上與上文所論述的平坦化之程度及表面反曲之曲率半徑耦合。 In one aspect of this embodiment, the dark current (normalized to unit photodetector area) between the first electrode and the second electrode that can transmit photons can be less than 10 pA/mm 2 , or less than 5 pA/mm 2 , or less than 1pA / mm 2, or less than 0.5pA / mm 2. The level of dark current is somewhat coupled to the degree of planarization discussed above and the radius of curvature of the surface recursion. In one aspect of this embodiment, the electric field in the region of the photosensitive layer closest to the surface recursion may be more than 60% of the electric field in the photosensitive layer between a pair of parallel first and second electrodes. And below 300%. The change in the electric field is coupled to some extent to the degree of planarization discussed above and the radius of curvature of the surface recursion.
在此實施例之一態樣中,感測器可包括一安置於閃爍層上之金屬板。 In one aspect of this embodiment, the sensor can include a metal plate disposed on the scintillation layer.
在第三說明實施例中,一輻射感測器包括一閃爍層,該閃爍層經組態以在與電離輻射相互作用時發射光子;一光偵測器,其按次序包括一第一電極、一感光層,及接近於該閃爍層而安置之一可透射光子之第二電極。該感光層經組態以在與該等光子之一部分相互作用時產生電子電洞對。該輻射感測器包括像素電路,其電連接至該第一電極且經組態以量測指示在該感光層中所產生之該等電子電洞對之一成像信號;且包括一平坦化層,其安置於該像素電路上在該第一電極與該像素電路之間,以使得該第一電極高於包括該像素電路之一平面。該光偵測器在第一電極與可透射光子之第二電極之間具有一暗電流(正規化至單位光偵測器面積),該暗電流小於10pA/mm2。 In a third illustrative embodiment, a radiation sensor includes a scintillation layer configured to emit photons when interacting with ionizing radiation; a photodetector including a first electrode in sequence, a photosensitive layer, and a second electrode capable of transmitting photons disposed adjacent to the scintillation layer. The photosensitive layer is configured to create an electron hole pair when interacting with a portion of the photons. The radiation sensor includes a pixel circuit electrically coupled to the first electrode and configured to measure an imaging signal indicative of one of the pairs of electron holes generated in the photosensitive layer; and including a planarization layer And disposed between the first electrode and the pixel circuit on the pixel circuit such that the first electrode is higher than a plane including the pixel circuit. The photodetector has a dark current (normalized to a unit photodetector area) between the first electrode and the second electrode that can transmit photons, the dark current being less than 10 pA/mm 2 .
在此實施例之一態樣中,平坦化層可為鈍化層、介電層或絕緣 層中之至少一者。在此實施例之一態樣中,高於像素電路之第一電極之表面反曲具有一大於1/2微米、大於1微米、大於5微米、大於10微米或大於100微米之曲率半徑。 In one aspect of this embodiment, the planarization layer can be a passivation layer, a dielectric layer, or an insulating layer. At least one of the layers. In one aspect of this embodiment, the surface recursion of the first electrode above the pixel circuit has a radius of curvature greater than 1/2 micron, greater than 1 micron, greater than 5 microns, greater than 10 microns, or greater than 100 microns.
在此實施例之一態樣中,暗電流(正規化至單位光偵測器面積)可小於5pA/mm2,或小於1pA/mm2,或小於0.5pA/mm2。暗電流之位準在某種程度上與上文所論述的平坦化之程度及表面反曲之曲率半徑耦合。 In one embodiment of this aspect of the embodiment, the dark current (normalized to unit area of the light detector) may be less than 5pA / mm 2, or less than 1pA / mm 2, or less than 0.5pA / mm 2. The level of dark current is somewhat coupled to the degree of planarization discussed above and the radius of curvature of the surface recursion.
在第四說明實施例中,一輻射感測器包括:一閃爍層,該閃爍層經組態以在與電離輻射相互作用時發射光子;一光偵測器,其按次序包括一第一電極、一感光層,及接近於該閃爍層而安置之一可透射光子之第二電極。該感光層經組態以在與該等光子之一部分相互作用時產生電子電洞對。該輻射感測器包括像素電路,其電連接至該第一電極且經組態以量測指示在該感光層中所產生之該等電子電洞對之一成像信號;且包括一平坦化層,其安置於該像素電路上在該第一電極與該像素電路之間,以使得該第一電極高於包括該像素電路之一平面。該光偵測器具有每一光偵測器像素之電荷捕集之位準,該位準係由在單一放射攝影圖框期間由於捕集而損失的成像信號(指示在感光層中所產生之電子電洞對)之量來定量,且表達為在電荷捕集與電荷釋放處於平衡之條件下獲得的成像信號之百分比,該百分比小於約20%。 In a fourth illustrative embodiment, a radiation sensor includes: a scintillation layer configured to emit photons when interacting with ionizing radiation; a photodetector including a first electrode in sequence And a photosensitive layer, and a second electrode capable of transmitting photons disposed adjacent to the scintillation layer. The photosensitive layer is configured to create an electron hole pair when interacting with a portion of the photons. The radiation sensor includes a pixel circuit electrically coupled to the first electrode and configured to measure an imaging signal indicative of one of the pairs of electron holes generated in the photosensitive layer; and including a planarization layer And disposed between the first electrode and the pixel circuit on the pixel circuit such that the first electrode is higher than a plane including the pixel circuit. The photodetector has a level of charge trapping for each photodetector pixel, the level is caused by an imaging signal lost during capture during a single radiographic frame (indicating that it is generated in the photosensitive layer) The amount of electron holes is quantified and expressed as a percentage of the imaging signal obtained under conditions in which charge trapping and charge release are in equilibrium, the percentage being less than about 20%.
在此實施例之一態樣中,平坦化層可為鈍化層、介電層或絕緣層中之至少一者。在此實施例之一態樣中,高於像素電路之第一電極之表面反曲具有一大於1/2微米、大於1微米、大於5微米、大於10微米或大於100微米之曲率半徑。 In one aspect of this embodiment, the planarization layer can be at least one of a passivation layer, a dielectric layer, or an insulating layer. In one aspect of this embodiment, the surface recursion of the first electrode above the pixel circuit has a radius of curvature greater than 1/2 micron, greater than 1 micron, greater than 5 microns, greater than 10 microns, or greater than 100 microns.
在此實施例之一態樣中,每一光偵測器像素之電荷捕集之位準可(例如)取決於所要或所達成之平坦化之程度而小於15%、小於10% 或小於5%。 In one aspect of this embodiment, the level of charge trapping of each photodetector pixel can be less than 15%, less than 10%, for example, depending on the degree of planarization desired or achieved. Or less than 5%.
在第五說明實施例中,一輻射感測器包括:一閃爍層,該閃爍層經組態以在與電離輻射相互作用時發射光子;一光偵測器,其按次序包括一第一電極、一感光層,及接近於該閃爍層而安置之一可透射光子之第二電極。該感光層經組態以在與該等光子之一部分相互作用時產生電子電洞對。該輻射感測器包括像素電路,其電連接至該第一電極且經組態以量測指示在該感光層中所產生之該等電子電洞對之一成像信號;且包括一平坦化層,其安置於該像素電路上在該第一電極與該像素電路之間,以使得該第一電極高於包括該像素電路之一平面。該光偵測器具有每一光偵測器像素之電荷釋放,每一光偵測器像素之電荷釋放係由在具有輻射之情況下且在電荷捕集與電荷釋放處於平衡之條件下獲取的一系列圖框之後的在不存在輻射之情況下獲取的第一圖框期間、自捕集狀態釋放的成像信號(指示在感光層中所產生的電子電洞對)之量來定量,且表達為在電荷捕集與釋放處於平衡之條件下獲得的成像信號之百分比,每一光偵測器像素之電荷釋放小於約15%。 In a fifth illustrative embodiment, a radiation sensor includes: a scintillation layer configured to emit photons when interacting with ionizing radiation; a photodetector including a first electrode in sequence And a photosensitive layer, and a second electrode capable of transmitting photons disposed adjacent to the scintillation layer. The photosensitive layer is configured to create an electron hole pair when interacting with a portion of the photons. The radiation sensor includes a pixel circuit electrically coupled to the first electrode and configured to measure an imaging signal indicative of one of the pairs of electron holes generated in the photosensitive layer; and including a planarization layer And disposed between the first electrode and the pixel circuit on the pixel circuit such that the first electrode is higher than a plane including the pixel circuit. The photodetector has a charge release of each photodetector pixel, and the charge release of each photodetector pixel is obtained by having radiation and under the condition that charge trapping and charge release are balanced. The amount of imaging signal (indicating the pair of electron holes generated in the photosensitive layer) released during the first frame acquired in the absence of radiation after a series of frames, indicating the number of electron hole pairs generated in the photosensitive layer, is quantified and expressed The charge release per pixel of the photodetector pixel is less than about 15% for the percentage of imaging signal obtained under conditions of charge trapping and release being balanced.
在此實施例之一態樣中,平坦化層可為鈍化層、介電層或絕緣層中之至少一者。在此實施例之一態樣中,高於像素電路之第一電極之表面反曲具有一大於1/2微米、大於1微米、大於5微米、大於10微米或大於100微米之曲率半徑。 In one aspect of this embodiment, the planarization layer can be at least one of a passivation layer, a dielectric layer, or an insulating layer. In one aspect of this embodiment, the surface recursion of the first electrode above the pixel circuit has a radius of curvature greater than 1/2 micron, greater than 1 micron, greater than 5 microns, greater than 10 microns, or greater than 100 microns.
在此實施例之一態樣中,每一光偵測器像素之電荷釋放可(例如)取決於所要或所達成之平坦化之程度而小於10%、小於5%或小於3%。 In one aspect of this embodiment, the charge release of each photodetector pixel can be, for example, less than 10%, less than 5%, or less than 3%, depending on the degree of planarization desired or achieved.
在第六說明實施例中,一輻射感測器包括:一閃爍層,該閃爍層經組態以在與電離輻射相互作用時發射光子;一光偵測器,其按次序包括一第一電極、一感光層,及接近於該閃爍層而安置之一可透射 光子之第二電極。該感光層經組態以在與該等光子之一部分相互作用時產生電子電洞對。該輻射感測器包括像素電路,其電連接至該第一電極且經組態以量測指示在該感光層中所產生之該等電子電洞對之一成像信號;且包括一平坦化層,其安置於該像素電路上在該第一電極與該像素電路之間,以使得該第一電極高於包括該像素電路之一平面。該光偵測器具有每一光偵測器像素之延滯,每一光偵測器像素之延滯係藉由在具有輻射之情況下獲取的一個圖框或一系列圖框之後的在不存在輻射之情況下獲取的第一圖框期間、自捕集狀態釋放之成像信號(該成像信號指示在感光層中所產生之電子電洞對,且該成像信號起源於在一或多個先前圖框中所捕集的電荷)之量來定量,且表達為來自先前圖框之成像信號之百分比,每一光偵測器像素之延滯小於約15%。 In a sixth illustrative embodiment, a radiation sensor includes: a scintillation layer configured to emit photons when interacting with ionizing radiation; a photodetector including a first electrode in sequence , a photosensitive layer, and one of the light-emitting layers disposed close to the scintillation layer The second electrode of the photon. The photosensitive layer is configured to create an electron hole pair when interacting with a portion of the photons. The radiation sensor includes a pixel circuit electrically coupled to the first electrode and configured to measure an imaging signal indicative of one of the pairs of electron holes generated in the photosensitive layer; and including a planarization layer And disposed between the first electrode and the pixel circuit on the pixel circuit such that the first electrode is higher than a plane including the pixel circuit. The photodetector has a delay of each photodetector pixel, and the delay of each photodetector pixel is followed by a frame or a series of frames acquired under the condition of radiation An imaging signal released from the trapped state during the first frame acquired in the presence of radiation (the imaging signal indicates an electron hole pair generated in the photosensitive layer, and the imaging signal originates from one or more previous The amount of charge trapped in the frame is quantified and expressed as a percentage of the imaging signal from the previous frame, with a retardation of less than about 15% for each photodetector pixel.
在此實施例之一態樣中,平坦化層可為鈍化層、介電層或絕緣層中之至少一者。在此實施例之一態樣中,高於像素電路之第一電極之表面反曲具有一大於1/2微米、大於1微米、大於5微米、大於10微米或大於100微米之曲率半徑。 In one aspect of this embodiment, the planarization layer can be at least one of a passivation layer, a dielectric layer, or an insulating layer. In one aspect of this embodiment, the surface recursion of the first electrode above the pixel circuit has a radius of curvature greater than 1/2 micron, greater than 1 micron, greater than 5 microns, greater than 10 microns, or greater than 100 microns.
在此實施例之一態樣中,每一光偵測器像素之延滯可(例如)取決於所要或所達成之平坦化之程度而小於10%、小於5%或小於3%。 In one aspect of this embodiment, the delay of each photodetector pixel can be, for example, less than 10%, less than 5%, or less than 3%, depending on the degree of planarization desired or achieved.
在第七說明實施例中,一輻射感測器包括:一閃爍層,該閃爍層經組態以在與電離輻射相互作用時發射光子;一光偵測器,其按次序包括一第一電極、一感光層,及接近於該閃爍層而安置之一可透射光子之第二電極。該感光層經組態以在與該等光子之一部分相互作用時產生電子電洞對。該輻射感測器包括像素電路,其電連接至該第一電極且經組態以量測指示在該感光層中所產生之該等電子電洞對之一成像信號;且包括一平坦化層,其安置於該像素電路上在該第一電極與該像素電路之間,以使得該第一電極高於包括該像素電路之一平 面。該第一電極可在該像素電路之一部分之上延伸且可具有一橫向邊緣、一縱向邊緣,及在該橫向邊緣與該縱向邊緣之相交處之一轉角。該橫向邊緣與該縱向邊緣中之至少一者可為一傾斜邊緣。 In a seventh illustrative embodiment, a radiation sensor includes: a scintillation layer configured to emit photons when interacting with ionizing radiation; a photodetector including a first electrode in sequence And a photosensitive layer, and a second electrode capable of transmitting photons disposed adjacent to the scintillation layer. The photosensitive layer is configured to create an electron hole pair when interacting with a portion of the photons. The radiation sensor includes a pixel circuit electrically coupled to the first electrode and configured to measure an imaging signal indicative of one of the pairs of electron holes generated in the photosensitive layer; and including a planarization layer Disposed on the pixel circuit between the first electrode and the pixel circuit such that the first electrode is higher than one of the pixel circuits surface. The first electrode can extend over a portion of the pixel circuit and can have a lateral edge, a longitudinal edge, and a corner at the intersection of the lateral edge and the longitudinal edge. At least one of the lateral edge and the longitudinal edge can be a sloped edge.
在此實施例之一態樣中,該轉角可為將橫向邊緣連接至縱向邊緣之圓形轉角。該傾斜邊緣可具有一大於1/2微米、或大於1微米、或大於5微米、或大於10微米或大於100微米之曲率半徑。在此實施例之一態樣中,平坦化層可為鈍化層、介電層或絕緣層中之至少一者。 In one aspect of this embodiment, the corner may be a rounded corner connecting the lateral edge to the longitudinal edge. The sloped edge can have a radius of curvature greater than 1/2 micrometer, or greater than 1 micrometer, or greater than 5 micrometers, or greater than 10 micrometers or greater than 100 micrometers. In one aspect of this embodiment, the planarization layer can be at least one of a passivation layer, a dielectric layer, or an insulating layer.
在第八說明實施例中,一輻射感測器包括:一閃爍層,該閃爍層經組態以在與電離輻射相互作用時發射光子;一光偵測器像素,其按次序包括一第一電極、一感光層,及接近於該閃爍層而安置之一可透射光子之第二電極。該感光層經組態以在與該等光子之一部分相互作用時產生電子電洞對。該輻射感測器包括像素電路,其電連接至該第一電極且經組態以量測指示在該感光層中所產生之該等電子電洞對之一成像信號;且包括一鈍化層,其安置於該像素電路上在該第一電極與該像素電路之間,以使得該第一電極高於包括該像素電路之一平面。該鈍化層具有高於像素電路元件之一第一表面反曲。該第二電極具有高於該第一表面反曲之一第二表面反曲。該第二表面反曲具有大於1/2微米之一曲率半徑。 In an eighth illustrative embodiment, a radiation sensor includes: a scintillation layer configured to emit photons when interacting with ionizing radiation; a photodetector pixel comprising a first in order An electrode, a photosensitive layer, and a second electrode capable of transmitting photons disposed adjacent to the scintillation layer. The photosensitive layer is configured to create an electron hole pair when interacting with a portion of the photons. The radiation sensor includes a pixel circuit electrically coupled to the first electrode and configured to measure an imaging signal indicative of one of the pairs of electron holes generated in the photosensitive layer; and including a passivation layer, It is disposed on the pixel circuit between the first electrode and the pixel circuit such that the first electrode is higher than a plane including the pixel circuit. The passivation layer has a first surface recursion that is higher than one of the pixel circuit elements. The second electrode has a second surface recursion that is higher than one of the first surface recursions. The second surface recursion has a radius of curvature greater than one of 1/2 microns.
該第二表面反曲可具有一大於1微米、或大於5微米、或大於10微米或大於100微米之曲率半徑。該鈍化層可為一平坦化之鈍化層。該感光層可為一平坦化之感光層。 The second surface recursion can have a radius of curvature greater than 1 micron, or greater than 5 microns, or greater than 10 microns or greater than 100 microns. The passivation layer can be a planarized passivation layer. The photosensitive layer can be a planarized photosensitive layer.
在第九說明實施例中,一輻射感測器包括:一閃爍層,該閃爍層經組態以在與電離輻射相互作用時發射光子;一光偵測器,其按次序包括一第一電極、一感光層,及接近於該閃爍層而安置之一可透射光子之第二電極。該感光層經組態以在與該等光子之一部分相互作用時產生電子電洞對。該輻射感測器包括像素電路,其電連接至該第一 電極且經組態以量測指示在該感光層中所產生之該等電子電洞對之一成像信號;且包括一平坦化層,其安置於該像素電路上在該第一電極與該像素電路之間,以使得該第一電極高於包括該像素電路之一平面。該第一電極及該第二電極中之至少一者之一表面可至少部分地重疊於該像素電路且可無展現指示下伏像素電路之表面特徵。 In a ninth illustrative embodiment, a radiation sensor includes: a scintillation layer configured to emit photons when interacting with ionizing radiation; a photodetector including a first electrode in sequence And a photosensitive layer, and a second electrode capable of transmitting photons disposed adjacent to the scintillation layer. The photosensitive layer is configured to create an electron hole pair when interacting with a portion of the photons. The radiation sensor includes a pixel circuit electrically connected to the first Electrodes and configured to measure an imaging signal indicative of one of the pairs of electron holes generated in the photosensitive layer; and including a planarization layer disposed on the pixel circuit at the first electrode and the pixel Between the circuits such that the first electrode is higher than a plane including the pixel circuit. A surface of at least one of the first electrode and the second electrode may at least partially overlap the pixel circuit and may exhibit no surface features indicative of the underlying pixel circuit.
在上述第一至第九說明實施例中及在下文所論述之彼等實施例中,平坦化層可接著完全地或部分地在像素電路之一些特徵之上平坦化。平坦化層可為鈍化層、介電層或絕緣層中之至少一者。高於像素電路之第一電極之表面反曲可(例如)取決於所要或所達成之平坦化之程度而具有一大於1/2微米、大於1微米、大於5微米、大於10微米或大於100微米之曲率半徑。一金屬板可安置於閃爍層上。另外,在上述第一至第九說明實施例中及在下文所論述之彼等實施例中,一電介層孔互連件可延伸穿過平坦化層且將第一電極連接至像素電路。與感光層接觸之電介層孔互連件之表面反曲可具有一大於1/2微米、大於1微米、大於5微米、大於10微米及大於100微米之曲率半徑。 In the first to ninth illustrative embodiments described above and in the embodiments discussed below, the planarization layer can then be planarized completely or partially over some features of the pixel circuit. The planarization layer can be at least one of a passivation layer, a dielectric layer, or an insulating layer. The surface recursion of the first electrode above the pixel circuit can have, for example, greater than 1/2 micron, greater than 1 micron, greater than 5 micron, greater than 10 micron, or greater than 100 depending on the degree of planarization desired or achieved. The radius of curvature of the micrometer. A metal plate can be placed on the scintillation layer. Additionally, in the first to ninth illustrative embodiments described above and in the embodiments discussed below, a dielectric via interconnect may extend through the planarization layer and connect the first electrode to the pixel circuitry. The surface reflex of the dielectric via interconnect in contact with the photosensitive layer can have a radius of curvature greater than 1/2 micron, greater than 1 micron, greater than 5 microns, greater than 10 microns, and greater than 100 microns.
在上述第一至第九說明實施例中及在下文所論述之彼等實施例中,感光層可為p-i-n半導體堆疊、n-i-p半導體堆疊或金屬絕緣體半導體堆疊中之一者。像素電路可包括薄膜電晶體、二極體、電容器、電阻器、跡線、介層孔、控制線、位址線及接地平面中之一者。像素電路可為非晶系半導體電晶體或多晶半導體電晶體或微晶半導體電晶體中之一者。像素電路可包括定址電晶體、放大器電晶體及重設電晶體中之至少一者。像素電路可為非晶矽、低溫非晶矽及微晶矽中之至少一者。像素電路可為以下各項中之至少一者:矽半導體、氧化物半導體、硫族化物半導體、硒化鎘半導體、有機半導體、有機小分子或聚合物半導體、碳奈米管,或石墨薄膜,或其他半導電材料。 In the first to ninth illustrative embodiments described above and in the embodiments discussed below, the photosensitive layer may be one of a p-i-n semiconductor stack, an n-i-p semiconductor stack, or a metal insulator semiconductor stack. The pixel circuit can include one of a thin film transistor, a diode, a capacitor, a resistor, a trace, a via, a control line, an address line, and a ground plane. The pixel circuit may be one of an amorphous semiconductor transistor or a polycrystalline semiconductor transistor or a microcrystalline semiconductor transistor. The pixel circuit can include at least one of an address transistor, an amplifier transistor, and a reset transistor. The pixel circuit may be at least one of amorphous germanium, low temperature amorphous germanium, and microcrystalline germanium. The pixel circuit may be at least one of: a germanium semiconductor, an oxide semiconductor, a chalcogenide semiconductor, a cadmium selenide semiconductor, an organic semiconductor, an organic small molecule or a polymer semiconductor, a carbon nanotube, or a graphite film, Or other semi-conductive materials.
在上述第一至第九說明實施例中及在下文所論述之彼等實施例 中,感光層可為以下各項中之至少一者:1)跨越複數個光偵測器像素延伸之連續感光層,或2)與該複數個光偵測器像素中之各別者相關聯的離散感光層。閃爍層可為以下各項中之至少一者:CsI:Tl、Gd2O2S:Tb、CsI:Na、NaI:Tl、CaWO4、ZnWO4、CdWO4、Bi4Ge3O12、Lu1.8Yb0.2SiO5:Ce、Gd2SiO5:Ce、BaFCl:Eu2+、BaSO4:Eu2+、BaFBr:Eu2+、LaOBr:Tb3+、LaOBr:Tm3+、La2O2S:Tb3+、Y2O2S:Tb3+、YTaO4、YTaO4:Nb、ZnS:Ag、(Zn,Cd)S:Ag、ZnSiO4:Mn2+、CsI、LiI:Eu2+、PbWO4、Bi4Si3O12、Lu2SiO5:Ce3+、YAlO3:Ce3+、CsF、CaF2:Eu2+、BaF2、CeF3、Y1.34Gd0.6O3:Eu3+、Pr、Gd2O2S:Pr3+、Ce、SCGl、HFG:Ce3+(5%)及C14H10,或其他閃爍器材料。 In the first to ninth illustrative embodiments described above and in the embodiments discussed below, the photosensitive layer can be at least one of the following: 1) continuous sensitization across a plurality of photodetector pixels a layer, or 2) a discrete photosensitive layer associated with each of the plurality of photodetector pixels. The scintillation layer may be at least one of the following: CsI: Tl, Gd 2 O 2 S: Tb, CsI: Na, NaI: Tl, CaWO 4 , ZnWO 4 , CdWO 4 , Bi 4 Ge 3 O 12 , Lu 1.8 Yb 0.2 SiO 5 :Ce, Gd 2 SiO 5 :Ce, BaFCl:Eu 2+ , BaSO 4 :Eu 2+ , BaFBr:Eu 2+ ,LaOBr:Tb 3+ ,LaOBr:Tm 3+ ,La 2 O 2 S: Tb 3+ , Y 2 O 2 S: Tb 3+ , YTaO 4 , YTaO 4 : Nb, ZnS: Ag, (Zn, Cd) S: Ag, ZnSiO 4 : Mn 2+ , CsI, LiI: Eu 2 + , PbWO 4 , Bi 4 Si 3 O 12 , Lu 2 SiO 5 :Ce 3+ , YAlO 3 :Ce 3+ , CsF, CaF 2 :Eu 2+ , BaF 2 , CeF 3 , Y 1.34 Gd 0.6 O 3 : Eu 3+ , Pr, Gd 2 O 2 S: Pr 3+ , Ce, SCG1, HFG: Ce 3+ (5%) and C 14 H 10 , or other scintillator materials.
在上述第一至第九說明實施例中及在下文所論述之彼等實施例中,輻射感測器可包括一支撐像素電路、光偵測器及閃爍層之基底基板。輻射感測器可包括以規則圖案排列於該基底基板上之複數個光偵測器像素。在此實施例之一態樣中,該可透射光子之第二電極可形成一用於該複數個光偵測器像素之偏壓平面。像素電路之一部分可安置於基底基板上在鄰近光偵測器像素之間的間隙區中。此部分可包括薄膜電晶體、二極體、電容器、電阻器、介層孔、跡線、控制線、位址線及接地平面中之一者。第一電極可具有終止於該間隙區近旁之傾斜末端。下文提供此等特徵之較佳組合的實例。 In the first to ninth illustrative embodiments described above and in the embodiments discussed below, the radiation sensor can include a base substrate supporting the pixel circuit, the photodetector, and the scintillation layer. The radiation sensor can include a plurality of photodetector pixels arranged in a regular pattern on the base substrate. In one aspect of this embodiment, the photo-transmissive second electrode can form a bias plane for the plurality of photodetector pixels. A portion of the pixel circuit can be disposed on the base substrate in a gap region between adjacent photodetector pixels. This portion may include one of a thin film transistor, a diode, a capacitor, a resistor, a via, a trace, a control line, an address line, and a ground plane. The first electrode can have a slanted end that terminates near the gap region. Examples of preferred combinations of such features are provided below.
在上述第一至第九說明實施例中及在下文所論述之彼等實施例中,一金屬板可安置於可透射電離輻射之第二電極上或可安置於可透射電離輻射之第二電極上之囊封層上。另外,平坦化層可至少部分地在陣列特徵之上、在連接至TFT之源極或汲極的電介層孔互連件之上、在單級像素內放大器元件之上或在兩級像素內放大器元件之上平坦化。 In the first to ninth illustrative embodiments described above and in the embodiments discussed below, a metal plate may be disposed on the second electrode that is transmissive to ionizing radiation or may be disposed on the second electrode that is transmissive to ionizing radiation. On the encapsulation layer. Additionally, the planarization layer can be at least partially over the array features, over the dielectric via interconnects connected to the source or drain of the TFT, over a single-stage in-pixel amplifier component, or at two-level pixels The inner amplifier element is planarized.
在第十說明實施例中,一輻射感測器包括一光導體偵測器,其按次序包括一第一電極、一光導層,及一可透射電離輻射之第二電極。該光導層經組態以在與電離輻射相互作用時產生電子電洞對。該輻射感測器包括像素電路,其電連接至該第一電極且經組態以量測指示在該光導層中所產生之該等電子電洞對之一成像信號;及一平坦化層,其安置於該像素電路上在該第一電極與該像素電路之間,以使得該第一電極高於包括該像素電路之一平面。該第一電極及該第二電極中之至少一者之一表面至少部分地重疊於該像素電路且具有高於該像素電路之特徵之一表面反曲。該表面反曲具有大於1/2微米之一曲率半徑。 In a tenth illustrative embodiment, a radiation sensor includes a photoconductor detector that includes a first electrode, a photoconductive layer, and a second electrode that transmits ionizing radiation in sequence. The photoconductive layer is configured to create an electron hole pair upon interaction with ionizing radiation. The radiation sensor includes a pixel circuit electrically coupled to the first electrode and configured to measure an imaging signal indicative of one of the pairs of electron holes generated in the light guiding layer; and a planarization layer, It is disposed on the pixel circuit between the first electrode and the pixel circuit such that the first electrode is higher than a plane including the pixel circuit. A surface of at least one of the first electrode and the second electrode at least partially overlaps the pixel circuit and has a surface recursion higher than one of the features of the pixel circuit. The surface recursion has a radius of curvature greater than one of 1/2 microns.
在此實施例之一態樣中,平坦化層可為鈍化層、介電層或絕緣層中之至少一者。在此實施例之一態樣中,高於像素電路之第一電極之表面反曲具有一大於1/2微米、大於1微米、大於5微米、大於10微米或大於100微米之曲率半徑。另外,電介層孔互連件可延伸穿過平坦化層且將第一電極連接至像素電路。與感光層接觸之電介層孔互連件之表面反曲可具有一大於1/2微米、大於1微米、大於5微米、大於10微米及大於100微米之曲率半徑。 In one aspect of this embodiment, the planarization layer can be at least one of a passivation layer, a dielectric layer, or an insulating layer. In one aspect of this embodiment, the surface recursion of the first electrode above the pixel circuit has a radius of curvature greater than 1/2 micron, greater than 1 micron, greater than 5 microns, greater than 10 microns, or greater than 100 microns. Additionally, the dielectric via interconnects can extend through the planarization layer and connect the first electrode to the pixel circuitry. The surface reflex of the dielectric via interconnect in contact with the photosensitive layer can have a radius of curvature greater than 1/2 micron, greater than 1 micron, greater than 5 microns, greater than 10 microns, and greater than 100 microns.
在此實施例之一態樣中,像素電路可包括薄膜電晶體、二極體、電容器、電阻器、跡線、介層孔、控制線、位址線及接地平面中之一者。像素電路可為非晶系半導體電晶體或多晶半導體電晶體或微晶半導體電晶體中之一者。像素電路可包括定址電晶體、放大器電晶體及重設電晶體中之至少一者。像素電路可為非晶矽、低溫非晶矽及微晶矽中之至少一者。像素電路可為以下各項中之至少一者:矽半導體、氧化物半導體、硫族化物半導體、硒化鎘半導體、有機半導體、有機小分子或聚合物半導體、碳奈米管,或石墨薄膜,或其他半導電材料。 In one aspect of this embodiment, the pixel circuit can include one of a thin film transistor, a diode, a capacitor, a resistor, a trace, a via, a control line, an address line, and a ground plane. The pixel circuit may be one of an amorphous semiconductor transistor or a polycrystalline semiconductor transistor or a microcrystalline semiconductor transistor. The pixel circuit can include at least one of an address transistor, an amplifier transistor, and a reset transistor. The pixel circuit may be at least one of amorphous germanium, low temperature amorphous germanium, and microcrystalline germanium. The pixel circuit may be at least one of: a germanium semiconductor, an oxide semiconductor, a chalcogenide semiconductor, a cadmium selenide semiconductor, an organic semiconductor, an organic small molecule or a polymer semiconductor, a carbon nanotube, or a graphite film, Or other semi-conductive materials.
在此實施例之一態樣中,一金屬板可安置於該可透射電離輻射之第二電極上或可安置於該可透射電離輻射之第二電極上之囊封層上。另外,平坦化層可至少部分地在陣列特徵之上、在連接至TFT之源極或汲極的電介層孔互連件之上、在單級像素內放大器元件之上或在兩級像素內放大器元件之上平坦化。 In one aspect of this embodiment, a metal plate can be disposed on the second electrode of the transmissive ionizing radiation or can be disposed on the encapsulating layer of the second electrode that transmits the ionizing radiation. Additionally, the planarization layer can be at least partially over the array features, over the dielectric via interconnects connected to the source or drain of the TFT, over a single-stage in-pixel amplifier component, or at two-level pixels The inner amplifier element is planarized.
在此實施例之一態樣中,光導層可為以下各項中之至少一者:1)跨越複數個光導體偵測器像素延伸之連續光導層,或2)與該複數個光導體偵測器像素中之各別者相關聯的離散光導層。輻射感測器可包括一支撐像素電路及光導層之基底基板。輻射感測器可包括以規則圖案排列於該基底基板上之複數個光導體偵測器像素。在此實施例之一態樣中,該可透射電離輻射之第二電極可形成一用於該複數個光導體偵測器像素之偏壓平面。像素電路之一部分可安置於基底基板上在鄰近光導體偵測器像素之間的間隙區中。此部分可包括薄膜電晶體、二極體、電容器、電阻器、介層孔、跡線、控制線、位址線及接地平面中之一者。第一電極可具有終止於該間隙區近旁之傾斜末端。 In one aspect of this embodiment, the light guiding layer can be at least one of: 1) a continuous light guiding layer extending across a plurality of photoconductor detector pixels, or 2) detecting the plurality of light conductors A discrete photoconductive layer associated with each of the detector pixels. The radiation sensor can include a base substrate supporting the pixel circuit and the light guiding layer. The radiation sensor can include a plurality of photoconductor detector pixels arranged in a regular pattern on the base substrate. In one aspect of this embodiment, the second electrode that transmits the ionizing radiation forms a bias plane for the plurality of photoconductor detector pixels. A portion of the pixel circuit can be disposed on the base substrate in a gap region between adjacent photodetector pixels. This portion may include one of a thin film transistor, a diode, a capacitor, a resistor, a via, a trace, a control line, an address line, and a ground plane. The first electrode can have a slanted end that terminates near the gap region.
因此,第十說明實施例包括與上述第一說明實施例類似之特徵,但不需要第一說明實施例中之閃爍器層及感光層。在此,在第十說明實施例中,光導層在與x光或其他電離輻射相互作用時產生電子電洞對。光導層可包括以下半導體中之至少一者:VB-VIB、VB-VIIB、IIB-VIB、IIB-VB、IIIB-VB、IIIB-VIB、IB-VIB及IVB-VIIB,且更具體言之,可包括以下各項中之至少一者:a-Se、PbI2、HgI2、PbO、CdZnTe、CdTe、Bi2S3、Bi2Se3、BiI3、BiBr3、CdS、CdSe、Hgs、Cd2P3、InAs、InP、In2S3、In2Se3、Ag2S、PbI4 -2及Pb2I7 -3。 Accordingly, the tenth illustrative embodiment includes features similar to those of the first illustrative embodiment described above, but does not require the scintillator layer and the photosensitive layer in the first illustrative embodiment. Here, in the tenth illustrative embodiment, the photoconductive layer generates an electron hole pair when interacting with x-rays or other ionizing radiation. The photoconductive layer may include at least one of the following semiconductors: VB-VIB, VB-VIIB, IIB-VIB, IIB-VB, IIIB-VB, IIIB-VIB, IB-VIB, and IVB-VIIB, and more specifically, may comprise at least one of: a-Se, PbI 2, HgI 2, PbO, CdZnTe, CdTe, Bi 2 S 3, Bi 2 Se 3, BiI 3, BiBr 3, CdS, CdSe, Hgs, Cd 2 P 3 , InAs, InP, In 2 S 3 , In 2 Se 3 , Ag 2 S, PbI 4 -2 and Pb 2 I 7 -3 .
另外,上文關於第一實施例所描述之特徵可包括於第十說明實施例中。此相同概括適用於下文之剩餘實施例,且出於清晰起見,下文將選擇性地重複此相同概括。另外,上文所描述的曲率半徑、暗電 流、電荷捕集之位準、電荷釋放及延滯之值及範圍適當地適用於此處。下文提供此等參數之較佳組合的實例。 Additionally, the features described above with regard to the first embodiment may be included in the tenth illustrative embodiment. This same generalization applies to the remaining embodiments below, and for the sake of clarity, this same generalization will be selectively repeated below. In addition, the radius of curvature, dark electricity described above The values and ranges of flow, charge trapping levels, charge release and retardation are suitably applied here. Examples of preferred combinations of such parameters are provided below.
在第十一說明實施例中,一輻射感測器包括一光導體偵測器,其按次序包括一第一電極、一光導層,及一可透射電離輻射之第二電極。該光導層經組態以在與電離輻射相互作用時產生電子電洞對。該輻射感測器包括:像素電路,其電連接至該第一電極且經組態以量測指示在該光導層中所產生之該等電子電洞對之一成像信號;及一平坦化層,其安置於該像素電路上在該第一電極與該像素電路之間,以使得該第一電極高於包括該像素電路之一平面。該平坦化層具有沿著像素電路元件之特徵之周邊邊緣的第一表面反曲。該第一電極具有一第二表面反曲,該第二表面反曲高於該第一表面反曲且在該平坦化層之與基底基板相反之表面上。該第二表面反曲具有大於1/2微米之一曲率半徑。 In an eleventh illustrative embodiment, a radiation sensor includes a photoconductor detector that includes a first electrode, a photoconductive layer, and a second electrode that transmits ionizing radiation in sequence. The photoconductive layer is configured to create an electron hole pair upon interaction with ionizing radiation. The radiation sensor includes: a pixel circuit electrically coupled to the first electrode and configured to measure an imaging signal indicative of one of the pairs of electron holes generated in the light guiding layer; and a planarization layer And disposed between the first electrode and the pixel circuit on the pixel circuit such that the first electrode is higher than a plane including the pixel circuit. The planarization layer has a first surface recurve along a peripheral edge of a feature of the pixel circuit component. The first electrode has a second surface recursion, and the second surface is recurved higher than the first surface and is on a surface of the planarization layer opposite to the base substrate. The second surface recursion has a radius of curvature greater than one of 1/2 microns.
在第十二說明實施例中,一輻射感測器包括一光導體偵測器,其按次序包括一第一電極、一光導層,及一可透射電離輻射之第二電極。該光導層經組態以在與電離輻射相互作用時產生電子電洞對。該輻射感測器包括:像素電路,其電連接至該第一電極且經組態以量測指示在該光導層中所產生之該等電子電洞對之一成像信號;及一平坦化層,其安置於該像素電路上在該第一電極與該像素電路之間,以使得該第一電極高於包括該像素電路之一平面。該光導體偵測器在第一電極與第二電極之間具有一暗電流(正規化至單位光導體偵測器面積),該暗電流小於10pA/mm2。 In a twelfth illustrative embodiment, a radiation sensor includes a photoconductor detector that includes a first electrode, a photoconductive layer, and a second electrode that transmits ionizing radiation in sequence. The photoconductive layer is configured to create an electron hole pair upon interaction with ionizing radiation. The radiation sensor includes: a pixel circuit electrically coupled to the first electrode and configured to measure an imaging signal indicative of one of the pairs of electron holes generated in the light guiding layer; and a planarization layer And disposed between the first electrode and the pixel circuit on the pixel circuit such that the first electrode is higher than a plane including the pixel circuit. The photoconductor detector has a dark current (normalized to a unit photodetector area) between the first electrode and the second electrode, the dark current being less than 10 pA/mm 2 .
在此實施例之一態樣中,暗電流(正規化至單位光導體偵測器面積)可小於5pA/mm2,或小於1pA/mm2,或小於0.5pA/mm2。暗電流之位準在某種程度上與上文所論述的平坦化之程度及表面反曲之曲率半徑耦合。 In one embodiment of this aspect of the embodiment, the dark current (normalized to unit photoconductor detector area) may be less than 5pA / mm 2, or less than 1pA / mm 2, or less than 0.5pA / mm 2. The level of dark current is somewhat coupled to the degree of planarization discussed above and the radius of curvature of the surface recursion.
在第十三說明實施例中,一輻射感測器包括一光導體偵測器,其按次序包括一第一電極、一光導層,及一可透射電離輻射之第二電極。該光導層經組態以在與電離輻射相互作用時產生電子電洞對。該輻射感測器包括:像素電路,其電連接至該第一電極且經組態以量測指示在該光導層中所產生之該等電子電洞對之一成像信號;及一平坦化層,其安置於該像素電路上在該第一電極與該像素電路之間,以使得該第一電極高於包括該像素電路之一平面。該光導體偵測器具有每一光導體偵測器像素之電荷捕集之位準,該位準係藉由在單一放射攝影圖框期間由於捕集而損失的成像信號(指示在光導層中所產生之電子電洞對)之量來定量,且表達為在電荷捕集與電荷釋放處於平衡之條件下獲得的成像信號之百分比,每一光導體偵測器像素之電荷捕集之該位準小於約20%。 In a thirteenth illustrative embodiment, a radiation sensor includes a photoconductor detector that includes a first electrode, a photoconductive layer, and a second electrode that transmits ionizing radiation in sequence. The photoconductive layer is configured to create an electron hole pair upon interaction with ionizing radiation. The radiation sensor includes: a pixel circuit electrically coupled to the first electrode and configured to measure an imaging signal indicative of one of the pairs of electron holes generated in the light guiding layer; and a planarization layer And disposed between the first electrode and the pixel circuit on the pixel circuit such that the first electrode is higher than a plane including the pixel circuit. The photoconductor detector has a level of charge trapping for each photoconductor detector pixel, the level being lost due to capture during capture of a single radiographic frame (indicated in the photoconductive layer) The amount of electron holes generated is quantified and expressed as a percentage of the imaged signal obtained under conditions in which charge trapping and charge release are in equilibrium, and the bit of charge trapping of each photoconductor detector pixel Less than about 20%.
在此實施例之一態樣中,每一光導體偵測器像素之電荷捕集之位準可(例如)取決於所要或所達成之平坦化之程度而小於15%、小於10%或小於5%。 In one aspect of this embodiment, the level of charge trapping of each photoconductor detector pixel can be, for example, less than 15%, less than 10%, or less, depending on the degree of planarization desired or achieved. 5%.
在第十四說明實施例中,一輻射感測器包括一光導體偵測器,其按次序包括一第一電極、一光導層,及一可透射電離輻射之第二電極。該光導層經組態以在與電離輻射相互作用時產生電子電洞對。該輻射感測器包括:像素電路,其電連接至該第一電極且經組態以量測指示在該光導層中所產生之該等電子電洞對之一成像信號;及一平坦化層,其安置於該像素電路上在該第一電極與該像素電路之間,以使得該第一電極高於包括該像素電路之一平面。該光導體偵測器具有每一光導體偵測器像素之電荷釋放,每一光導體偵測器像素之電荷釋放係藉由在具有輻射之情況下且在電荷捕集與電荷釋放處於平衡之條件下獲取的一系列圖框之後的在不存在輻射之情況下獲取的第一圖框期間、自捕集狀態釋放的成像信號(指示在光導層中所產生的電子電洞 對)之量來定量,且表達為在電荷捕集與釋放處於平衡之條件下獲得的成像信號之百分比,每一光導體偵測器像素之電荷釋放小於約15%。 In a fourteenth illustrative embodiment, a radiation sensor includes a photoconductor detector that includes a first electrode, a photoconductive layer, and a second electrode that transmits ionizing radiation in sequence. The photoconductive layer is configured to create an electron hole pair upon interaction with ionizing radiation. The radiation sensor includes: a pixel circuit electrically coupled to the first electrode and configured to measure an imaging signal indicative of one of the pairs of electron holes generated in the light guiding layer; and a planarization layer And disposed between the first electrode and the pixel circuit on the pixel circuit such that the first electrode is higher than a plane including the pixel circuit. The photoconductor detector has a charge release for each photoconductor detector pixel, and the charge release of each photoconductor detector pixel is balanced by the presence of radiation and between charge trapping and charge release. An imaging signal released from the trapped state during the first frame acquired in the absence of radiation after a series of frames acquired under conditions (indicating an electronic hole generated in the photoconductive layer) The amount is quantified and expressed as a percentage of the imaging signal obtained under conditions in which charge trapping and release are in equilibrium, and the charge release of each photoconductor detector pixel is less than about 15%.
在此實施例之一態樣中,每一光導體偵測器像素之電荷釋放可(例如)取決於所要或所達成之平坦化之程度而小於10%、小於5%或小於3%。 In one aspect of this embodiment, the charge release of each photoconductor detector pixel can be, for example, less than 10%, less than 5%, or less than 3%, depending on the degree of planarization desired or achieved.
在第十五說明實施例中,一輻射感測器包括一光導體偵測器,其按次序包括一第一電極、一光導層,及一可透射電離輻射之第二電極。該光導層經組態以在與電離輻射相互作用時產生電子電洞對。該輻射感測器包括:像素電路,其電連接至該第一電極且經組態以量測指示在該光導層中所產生之該等電子電洞對之一成像信號;及一平坦化層,其安置於該像素電路上在該第一電極與該像素電路之間,以使得該第一電極高於包括該像素電路之一平面。該光導體偵測器具有每一光導體偵測器像素之延滯,每一光導體偵測器像素之延滯係藉由在具有輻射之情況下獲取的一個圖框或一系列圖框之後的在不存在輻射之情況下獲取的第一圖框期間、自捕集狀態釋放之成像信號(該成像信號指示在光導層中所產生之電子電洞對,且該成像信號起源於在一或多個先前圖框中所捕集的電荷)之量來定量,且表達為來自先前圖框之成像信號之百分比,每一光導體偵測器像素之延滯小於約15%。 In a fifteenth illustrative embodiment, a radiation sensor includes a photoconductor detector that includes a first electrode, a photoconductive layer, and a second electrode that transmits ionizing radiation in sequence. The photoconductive layer is configured to create an electron hole pair upon interaction with ionizing radiation. The radiation sensor includes: a pixel circuit electrically coupled to the first electrode and configured to measure an imaging signal indicative of one of the pairs of electron holes generated in the light guiding layer; and a planarization layer And disposed between the first electrode and the pixel circuit on the pixel circuit such that the first electrode is higher than a plane including the pixel circuit. The photoconductor detector has a delay of each photoconductor detector pixel, and the delay of each photoconductor detector pixel is followed by a frame or a series of frames acquired with radiation An imaging signal released from the trapped state during the first frame acquired in the absence of radiation (the imaging signal indicates an electron hole pair generated in the photoconductive layer, and the imaging signal originates in one or The amount of charge trapped in the plurality of previous frames is quantified and expressed as a percentage of the imaging signal from the previous frame, with each photodetector pixel having a retardation of less than about 15%.
在此實施例之一態樣中,每一光導體偵測器像素之延滯可(例如)取決於所要或所達成之平坦化之程度而小於10%、小於5%或小於3%。 In one aspect of this embodiment, the retardation of each photoconductor detector pixel can be, for example, less than 10%, less than 5%, or less than 3%, depending on the degree of planarization desired or achieved.
在第十六說明實施例中,一輻射感測器包括一光導體偵測器,其按次序包括一第一電極、一光導層,及一可透射電離輻射之第二電極。該光導層經組態以在與電離輻射相互作用時產生電子電洞對。該輻射感測器包括:像素電路,其電連接至該第一電極且經組態以量測 指示在該光導層中所產生之該等電子電洞對之一成像信號;及一平坦化層,其安置於該像素電路上在該第一電極與該像素電路之間,以使得該第一電極高於包括該像素電路之一平面。該第一電極在該像素電路之上延伸且具有一橫向邊緣、一縱向邊緣,及在該橫向邊緣與該縱向邊緣之相交處之一轉角。該橫向邊緣及該縱向邊緣中之至少一者包括一傾斜邊緣。 In a sixteenth illustrative embodiment, a radiation sensor includes a photoconductor detector that includes a first electrode, a photoconductive layer, and a second electrode that transmits ionizing radiation in sequence. The photoconductive layer is configured to create an electron hole pair upon interaction with ionizing radiation. The radiation sensor includes a pixel circuit electrically coupled to the first electrode and configured to measure An imaging signal indicating one of the pair of electron holes generated in the light guiding layer; and a planarization layer disposed on the pixel circuit between the first electrode and the pixel circuit such that the first The electrode is higher than a plane including the pixel circuit. The first electrode extends over the pixel circuit and has a lateral edge, a longitudinal edge, and a corner at the intersection of the lateral edge and the longitudinal edge. At least one of the lateral edge and the longitudinal edge includes a sloped edge.
在第十七說明實施例中,一輻射感測器包括一光導體偵測器,其按次序包括一第一電極、一光導層,及一可透射電離輻射之第二電極。該光導層經組態以在與電離輻射相互作用時產生電子電洞對。該輻射感測器包括:像素電路,其電連接至該第一電極且經組態以量測指示在該光導層中所產生之該等電子電洞對之一成像信號;及一鈍化層,其安置於該像素電路上在該第一電極與該像素電路之間,以使得該第一電極高於包括該像素電路之一平面。該鈍化層具有高於像素電路元件之一第一表面反曲。該第二電極具有高於該第一表面反曲之一第二表面反曲。該第二表面反曲具有大於1/2微米之一曲率半徑。 In a seventeenth illustrative embodiment, a radiation sensor includes a photoconductor detector that includes a first electrode, a photoconductive layer, and a second electrode that transmits ionizing radiation in sequence. The photoconductive layer is configured to create an electron hole pair upon interaction with ionizing radiation. The radiation sensor includes a pixel circuit electrically coupled to the first electrode and configured to measure an imaging signal indicative of one of the pairs of electron holes generated in the light guiding layer; and a passivation layer, It is disposed on the pixel circuit between the first electrode and the pixel circuit such that the first electrode is higher than a plane including the pixel circuit. The passivation layer has a first surface recursion that is higher than one of the pixel circuit elements. The second electrode has a second surface recursion that is higher than one of the first surface recursions. The second surface recursion has a radius of curvature greater than one of 1/2 microns.
該第二表面反曲可具有一大於1微米、或大於5微米、或大於10微米或大於100微米之曲率半徑。該鈍化層可為一平坦化之鈍化層。感光層可為一平坦化之光導層。 The second surface recursion can have a radius of curvature greater than 1 micron, or greater than 5 microns, or greater than 10 microns or greater than 100 microns. The passivation layer can be a planarized passivation layer. The photosensitive layer can be a planarized photoconductive layer.
在第十八說明實施例中,一輻射感測器包括一光導體偵測器,其按次序包括一第一電極、一光導層,及一可透射電離輻射之第二電極。該光導層經組態以在與電離輻射相互作用時產生電子電洞對。該輻射感測器包括:像素電路,其電連接至該第一電極且經組態以量測指示在該光導層中所產生之該等電子電洞對之一成像信號;及一平坦化層,其安置於該像素電路上在該第一電極與該像素電路之間,以使得該第一電極高於包括該像素電路之一平面。該第一電極及該第二電極中之至少一者之一表面可至少部分地重疊於該像素電路且可無展現 指示下伏像素電路之表面特徵。 In an eighteenth embodiment, a radiation sensor includes a photoconductor detector that includes a first electrode, a photoconductive layer, and a second electrode that transmits ionizing radiation in sequence. The photoconductive layer is configured to create an electron hole pair upon interaction with ionizing radiation. The radiation sensor includes: a pixel circuit electrically coupled to the first electrode and configured to measure an imaging signal indicative of one of the pairs of electron holes generated in the light guiding layer; and a planarization layer And disposed between the first electrode and the pixel circuit on the pixel circuit such that the first electrode is higher than a plane including the pixel circuit. One surface of at least one of the first electrode and the second electrode may at least partially overlap the pixel circuit and may exhibit no Indicates the surface characteristics of the underlying pixel circuit.
在第十九說明實施例中,一種用於製造一輻射感測器之方法包括:在一基底基板上形成像素電路元件,在該等像素電路元件之上形成一平坦化層,在該平坦化層中形成一孔洞以曝露至該等像素電路元件之一連接件,使該圖案化之孔洞金屬化,形成與該金屬化孔洞電接觸之一第一電極,及在該第一電極上形成對光或電離輻射敏感之一層。形成該平坦化層在至少部分地重疊於該像素電路之該第一電極之一表面上提供一表面反曲,該表面反曲高於該像素電路之特徵、具有大於1/2微米之一曲率半徑。 In a nineteenth illustrative embodiment, a method for fabricating a radiation sensor includes: forming a pixel circuit component on a base substrate, and forming a planarization layer over the pixel circuit component, in the planarization Forming a hole in the layer to expose to one of the pixel circuit components, causing the patterned hole to be metallized, forming a first electrode in electrical contact with the metallized hole, and forming a pair on the first electrode One layer of light or ionizing radiation is sensitive. Forming the planarization layer to provide a surface recursion on a surface of the first electrode at least partially overlapping the pixel circuit, the surface recursion being higher than a characteristic of the pixel circuit, having a curvature greater than 1/2 micron radius.
在此實施例之一態樣中,將一感光層及一可透射光子之第二電極形成於第一電極上,且將一鈍化層形成於該可透射光子之第二電極上,且將一閃爍層形成於此鈍化層上,該閃爍層經組態以在與電離輻射相互作用時發射光子。在此例子中,感光層可為平坦化的或可在形成可透射光子之第二電極之前使感光層平坦化。 In one aspect of this embodiment, a photosensitive layer and a second electrode capable of transmitting photons are formed on the first electrode, and a passivation layer is formed on the second electrode of the phototransmissive photo, and a A scintillation layer is formed on the passivation layer that is configured to emit photons when interacting with ionizing radiation. In this example, the photosensitive layer can be planarized or the photosensitive layer can be planarized prior to forming the second electrode that can transmit photons.
在此實施例之一不同態樣中,將一光導層形成於第一電極上(該光導層經組態以在與x光或其他電離輻射相互作用時產生電子電洞對),且將一可透射電離輻射之第二電極形成於該光導層上。 In a different aspect of this embodiment, a photoconductive layer is formed on the first electrode (the photoconductive layer is configured to generate an electron hole pair when interacting with x-rays or other ionizing radiation), and A second electrode transmissive ionizing radiation is formed on the photoconductive layer.
在此等兩個態樣中,一第二電極可安置於閃爍層上之鈍化層上或安置於光導層上之囊封層上。在此等兩個態樣中,一金屬板可安置於閃爍層上或安置於閃爍層上之囊封上,或安置於可透射電離輻射之第二電極上之囊封層上。 In these two aspects, a second electrode can be disposed on the passivation layer on the scintillation layer or on the encapsulation layer on the photoconductive layer. In these two aspects, a metal plate can be placed on the scintillation layer or on the encapsulation on the scintillation layer or on the encapsulation layer on the second electrode that can transmit ionizing radiation.
在此實施例之一態樣中,可(例如)取決於所要或所達成之平坦化之程度而形成平坦化層以具有一大於1微米、大於5微米、大於10微米或大於100微米之曲率半徑。可藉由對所沈積之鈍化層之化學機械拋光來形成平坦化層。或者,可藉由旋塗一鈍化層且接著對彼鈍化層進行化學機械拋光來形成平坦化層。或者,可藉由使用旋塗在一(或第 一)鈍化層之頂部上沈積另一鈍化層且接著對該另一(或第二)鈍化層進行化學機械拋光來形成平坦化層。平坦化層可至少部分地在陣列特徵之上、在連接至TFT之源極或汲極的電介層孔互連件之上、在單級像素內放大器元件之上或在兩級像素內放大器元件之上平坦化。 In one aspect of this embodiment, the planarization layer can be formed, for example, to have a curvature greater than 1 micrometer, greater than 5 micrometers, greater than 10 micrometers, or greater than 100 micrometers, depending on the degree of planarization desired or achieved. radius. The planarization layer can be formed by chemical mechanical polishing of the deposited passivation layer. Alternatively, the planarization layer can be formed by spin coating a passivation layer followed by chemical mechanical polishing of the passivation layer. Alternatively, by using spin coating in one (or A) depositing another passivation layer on top of the passivation layer and then chemical mechanical polishing the other (or second) passivation layer to form a planarization layer. The planarization layer can be at least partially over the array features, over the dielectric via interconnects connected to the source or drain of the TFT, over a single-stage in-pixel amplifier component, or in a two-stage pixel amplifier The component is flattened.
在此實施例之一態樣中,第一電極之接近輻射感測器之鄰近像素之間的間隙區的末端可為傾斜的。在此實施例之一態樣中,可(例如)取決於所要或所達成之平坦化之程度而使金屬化孔洞逐漸變細而具有一大於1/2微米、或大於1微米、大於5微米、大於10微米或大於100微米之曲率半徑。 In one aspect of this embodiment, the end of the gap region between adjacent pixels of the first electrode proximate to the radiation sensor can be tilted. In one aspect of this embodiment, the metallized holes can be tapered, for example, depending on the degree of planarization desired or achieved to have a thickness greater than 1/2 micrometer, or greater than 1 micrometer, greater than 5 micrometers. a radius of curvature greater than 10 microns or greater than 100 microns.
在此第十九實施例之一態樣中,可在基底基板上形成在第一說明實施例之態樣中針對像素電路元件及感光層所列出之特徵。舉例而言,當形成一閃爍層時,可在可透射光子之第二電極上形成以下各項中之至少一者:CsI:Tl、Gd2O2S:Tb、CsI:Na、NaI:Tl、CaWO4、ZnWO4、CdWO4、Bi4Ge3O12、Lu1.8Yb0.2SiO5:Ce、Gd2SiO5:Ce、BaFCl:Eu2+、BaSO4:Eu2+、BaFBr:Eu2+、LaOBr:Tb3+、LaOBr:Tm3+、La2O2S:Tb3+、Y2O2S:Tb3+、YTaO4、YTaO4:Nb、ZnS:Ag、(Zn,Cd)S:Ag、ZnSiO4:Mn2+、CsI、LiI:Eu2+、PbWO4、Bi4Si3O12、Lu2SiO5:Ce3+、YAlO3:Ce3+、CsF、CaF2:Eu2+、BaF2、CeF3、Y1.34Gd0.6O3:Eu3+、Pr、Gd2O2S:Pr3+、Ce、SCGl、HFG:Ce3+(5%)及C14H10。可在提供閃爍層之前在第二電極上形成一鈍化層。舉例而言,當形成一感光層時,形成以下各項中之至少一者:1)跨越複數個光偵測器像素延伸之連續感光層,或2)與該複數個光偵測器像素中之一者相關聯的離散感光層。 In one aspect of the nineteenth embodiment, the features listed for the pixel circuit element and the photosensitive layer in the aspect of the first illustrative embodiment can be formed on the base substrate. For example, when a scintillation layer is formed, at least one of the following may be formed on the second electrode that can transmit photons: CsI: Tl, Gd 2 O 2 S: Tb, CsI: Na, NaI: Tl , CaWO 4 , ZnWO 4 , CdWO 4 , Bi 4 Ge 3 O 12 , Lu 1.8 Yb 0.2 SiO 5 :Ce, Gd 2 SiO 5 :Ce, BaFCl:Eu 2+ , BaSO 4 :Eu 2+ ,BaFBr:Eu 2 + , LaOBr: Tb 3+ , LaOBr: Tm 3+ , La 2 O 2 S: Tb 3+ , Y 2 O 2 S: Tb 3+ , YTaO 4 , YTaO 4 : Nb, ZnS: Ag, (Zn, Cd S: Ag, ZnSiO 4 : Mn 2+ , CsI, LiI: Eu 2+ , PbWO 4 , Bi 4 Si 3 O 12 , Lu 2 SiO 5 : Ce 3+ , YAlO 3 : Ce 3+ , CsF, CaF 2 :Eu 2+ , BaF 2 , CeF 3 , Y 1.34 Gd 0.6 O 3 :Eu 3+ , Pr, Gd 2 O 2 S:Pr 3+ , Ce, SCGl, HFG: Ce 3+ (5%) and C 14 H 10 . A passivation layer can be formed on the second electrode prior to providing the scintillation layer. For example, when forming a photosensitive layer, at least one of the following is formed: 1) a continuous photosensitive layer extending across a plurality of photodetector pixels, or 2) and a plurality of photodetector pixels One of the associated discrete photosensitive layers.
舉例而言,當形成一光導層時,可在第一電極上形成以下半導體中之至少一者:VB-VIB、VB-VIIB、IIB-VIB、IIB-VB、IIIB-VB、IIIB-VIB、IB-VIB及IVB-VIIB,或更具體言之,可在第一電極上形成 以下各項中之至少一者:a-Se、PbI2、HgI2、PbO、CdZnTe、CdTe、Bi2S3、Bi2Se3、BiI3、BiBr3、CdS、CdSe、HgS、Cd2P3、InAs、InP、In2S3、In2Se3、Ag2S、PbI4 -2及Pb2I7 -3。舉例而言,當形成一光導層時,形成以下各項中之至少一者:1)跨越複數個光導體偵測器像素延伸之連續光導層,或2)與該複數個光導體偵測器像素中之一者相關聯的離散光導層。 For example, when forming a photoconductive layer, at least one of the following semiconductors may be formed on the first electrode: VB-VIB, VB-VIIB, IIB-VIB, IIB-VB, IIIB-VB, IIIB-VIB, IB-VIB and IVB-VIIB, or more specifically, at least one of: a-Se, PbI 2 , HgI 2 , PbO, CdZnTe, CdTe, Bi 2 S 3 may be formed on the first electrode. , Bi 2 Se 3 , BiI 3 , BiBr 3 , CdS, CdSe, HgS, Cd 2 P 3 , InAs, InP, In 2 S 3 , In 2 Se 3 , Ag 2 S, PbI 4 -2 and Pb 2 I 7 -3 . For example, when forming a light guiding layer, at least one of the following is formed: 1) a continuous light guiding layer extending across a plurality of photoconductor detector pixels, or 2) and the plurality of photoconductor detectors A discrete photoconductive layer associated with one of the pixels.
舉例而言,當形成像素電路元件時,可在基底基板上形成非晶系半導體電晶體或微晶半導體電晶體或多晶半導體電晶體中之至少一者。當形成像素電路元件時,可在基底基板上形成以下各項中之至少一者:定址電晶體、放大器電晶體,及重設電晶體。當形成像素電路元件時,可在基底基板上形成以下各項中之至少一者:矽半導體、氧化物半導體、硫族化物半導體、硒化鎘半導體、有機半導體、有機小分子或聚合物半導體、碳奈米管,或石墨薄膜。當形成像素電路元件時,可在基底基板上形成以下各項中之至少一者:薄膜電晶體、二極體、電容器、電阻器、跡線、介層孔、控制線、位址線及接地平面。 For example, when the pixel circuit element is formed, at least one of an amorphous semiconductor transistor or a microcrystalline semiconductor transistor or a polycrystalline semiconductor transistor may be formed on the base substrate. When the pixel circuit component is formed, at least one of the following may be formed on the base substrate: an address transistor, an amplifier transistor, and a reset transistor. When the pixel circuit component is formed, at least one of the following may be formed on the base substrate: a germanium semiconductor, an oxide semiconductor, a chalcogenide semiconductor, a cadmium selenide semiconductor, an organic semiconductor, an organic small molecule or a polymer semiconductor, Carbon nanotubes, or graphite films. When the pixel circuit component is formed, at least one of the following may be formed on the base substrate: a thin film transistor, a diode, a capacitor, a resistor, a trace, a via, a control line, an address line, and a ground. flat.
另外,在第十九說明實施例中,可將一第二電極形成於對光或電離輻射敏感之層上。可將一金屬板形成於可透射光子之第二電極上或形成於閃爍層上之囊封上。在第十九說明實施例中,可將一金屬板形成於可透射電離輻射之第二電極上或形成於可透射電離輻射之第二電極上之囊封層上。 Further, in the nineteenth illustrative embodiment, a second electrode may be formed on a layer sensitive to light or ionizing radiation. A metal plate may be formed on the second electrode that transmits photons or on the encapsulation formed on the scintillation layer. In a nineteenth illustrative embodiment, a metal plate may be formed on the second electrode that is transmissive to ionizing radiation or on the encapsulating layer that is transmissive to the second electrode of ionizing radiation.
在第二十說明實施例中,一種用於製造一輻射感測器之方法包括:在一基底基板上形成像素電路元件,在該像素電路上方形成一第一電極及一感光層,使該感光層平坦化,在該平坦化之感光層上形成一可透射光子之第二電極,及在該可透射光子之第二電極上形成一閃爍器層。該第一電極及該第二電極中之至少一者具有高於該像素電路之特徵之一表面反曲,該表面反曲(例如)取決於所要或所達成之平坦 化之程度而具有一大於1/2微米、或大於1微米、大於5微米、大於10微米或大於100微米之曲率半徑。 In a twentieth illustrative embodiment, a method for fabricating a radiation sensor includes: forming a pixel circuit component on a base substrate, forming a first electrode and a photosensitive layer over the pixel circuit to make the photosensitive The layer is planarized, a second electrode capable of transmitting photons is formed on the planarized photosensitive layer, and a scintillator layer is formed on the second electrode of the phototransmissible photon. At least one of the first electrode and the second electrode has a surface recursion that is higher than a characteristic of the pixel circuit, the surface being recurved, for example, depending on desired or achieved flatness To the extent that it has a radius of curvature greater than 1/2 micrometer, or greater than 1 micrometer, greater than 5 micrometers, greater than 10 micrometers, or greater than 100 micrometers.
在第二十一說明實施例中,一種用於製造一輻射感測器之方法包括:在一基底基板上形成像素電路元件,在該像素電路上方形成一第一電極及一光導層,使該光導層平坦化,及在該平坦化之光導層上形成一可透射電離輻射之第二電極。該可透射電離輻射之第二電極具有高於該像素電路之特徵之一表面反曲,該表面反曲(例如)取決於所要或所達成之平坦化之程度而具有一大於1/2微米、或大於1微米、大於5微米、大於10微米或大於100微米之曲率半徑。 In a twenty-first embodiment, a method for fabricating a radiation sensor includes: forming a pixel circuit component on a base substrate, forming a first electrode and a light guiding layer over the pixel circuit, The photoconductive layer is planarized, and a second electrode that transmits ionizing radiation is formed on the planarized photoconductive layer. The second electrode of the transmissive ionizing radiation has a surface recursion that is higher than one of the features of the pixel circuit, the surface recursion having a greater than 1/2 micron, for example, depending on the degree of planarization desired or achieved, Or a radius of curvature greater than 1 micron, greater than 5 microns, greater than 10 microns, or greater than 100 microns.
在第二十二說明實施例中,一種用於製造一輻射感測器之方法包括:在一基底基板上形成像素電路元件,在該等像素電路元件之上形成一平坦化層,在該平坦化層中形成一孔洞以曝露至該等像素電路元件之一連接件,使該圖案化之孔洞金屬化,形成與該金屬化孔洞電接觸之一第一電極,及在該第一電極上形成對光或電離輻射敏感之一層。形成該平坦化層提供第一電極之一表面,該表面至少部分地重疊於該像素電路,該表面無展現指示下伏像素電路之表面特徵。 In a twenty-second illustrative embodiment, a method for fabricating a radiation sensor includes: forming a pixel circuit component on a base substrate, and forming a planarization layer over the pixel circuit component, Forming a hole in the layer to expose to one of the pixel circuit components, causing the patterned hole to be metallized, forming a first electrode in electrical contact with the metallized hole, and forming on the first electrode One layer that is sensitive to light or ionizing radiation. Forming the planarization layer provides a surface of a first electrode that at least partially overlaps the pixel circuit, the surface exhibiting no surface features indicative of the underlying pixel circuitry.
在第二十三說明實施例中,一種用於製造一輻射感測器之方法包括:在一基底基板上形成像素電路元件,在該像素電路上方形成一第一電極及一感光層,使該感光層平坦化,在該平坦化之感光層上形成一可透射光子之第二電極,及在該可透射光子之第二電極上形成一閃爍器層。使該感光層平坦化提供第二電極之一表面,該表面至少部分地重疊於該像素電路,該表面無展現指示下伏像素電路之表面特徵。 In a twenty-third illustrative embodiment, a method for fabricating a radiation sensor includes: forming a pixel circuit component on a base substrate, forming a first electrode and a photosensitive layer over the pixel circuit, The photosensitive layer is planarized, a second electrode capable of transmitting photons is formed on the planarized photosensitive layer, and a scintillator layer is formed on the second electrode of the phototransmissible photon. Flattening the photosensitive layer provides a surface of a second electrode that at least partially overlaps the pixel circuitry that does not exhibit surface features indicative of the underlying pixel circuitry.
在第二十四說明實施例中,一輻射感測器包括:一閃爍層,該閃爍層經組態以在與電離輻射相互作用時發射光子;一光偵測器,其按次序包括一第一電極、一感光層,及接近於該閃爍層而安置之一可 透射光子之第二電極。該感光層經組態以在與該等光子之一部分相互作用時產生電子電洞對。該輻射感測器包括像素電路,其電連接至該第一電極且經組態以量測指示在該感光層中所產生之該等電子電洞對之一成像信號,且該像素電路包括氧化物半導體。該輻射感測器包括一平坦化層,其安置於該像素電路上在該第一電極與該像素電路之間,以使得該第一電極高於包括該像素電路之一平面。該第一電極及該第二電極中之至少一者之一表面至少部分地重疊於該像素電路且具有高於該像素電路之特徵之一表面反曲。該表面反曲具有大於1/2微米之一曲率半徑。 In a twenty-fourth illustrative embodiment, a radiation sensor includes: a scintillation layer configured to emit photons when interacting with ionizing radiation; a photodetector comprising a first An electrode, a photosensitive layer, and one of the layers adjacent to the scintillation layer A second electrode that transmits photons. The photosensitive layer is configured to create an electron hole pair when interacting with a portion of the photons. The radiation sensor includes a pixel circuit electrically coupled to the first electrode and configured to measure an imaging signal indicative of one of the pairs of electron holes generated in the photosensitive layer, and the pixel circuit includes oxidation Semiconductor. The radiation sensor includes a planarization layer disposed between the first electrode and the pixel circuit on the pixel circuit such that the first electrode is higher than a plane including the pixel circuit. A surface of at least one of the first electrode and the second electrode at least partially overlaps the pixel circuit and has a surface recursion higher than one of the features of the pixel circuit. The surface recursion has a radius of curvature greater than one of 1/2 microns.
在此實施例之一態樣中,氧化物半導體包括以下各項中之至少一者:含鋅氧化物、SnO2、TiO2、Ga2O3、InGaO、In2O3及InSnO。含鋅氧化物可包括ZnO、InGaZnO、InZnO、ZnSnO中之至少一者。氧化物半導體可包括非晶系半導體或多晶半導體中之至少一者。 In one aspect of this embodiment, the oxide semiconductor includes at least one of zinc oxide, SnO 2 , TiO 2 , Ga 2 O 3 , InGaO, In 2 O 3 , and InSnO. The zinc-containing oxide may include at least one of ZnO, InGaZnO, InZnO, and ZnSnO. The oxide semiconductor may include at least one of an amorphous semiconductor or a polycrystalline semiconductor.
第二十四實施例因此在範疇上類似於第一實施例且包括上文所論述之第一實施例之態樣,接著描述較佳組合之實例。 The twenty-fourth embodiment is thus similar in scope to the first embodiment and includes the first embodiment discussed above, and then examples of preferred combinations are described.
該表面反曲可(例如)取決於所要或所達成之平坦化之程度而具有一大於1微米、大於5微米、大於10微米或大於100微米之曲率半徑。在另一態樣中,該第一電極及該第二電極中之至少一者之表面可至少部分地重疊於該像素電路且可無展現指示下伏像素電路之表面特徵。 The surface recursion can have a radius of curvature greater than 1 micrometer, greater than 5 micrometers, greater than 10 micrometers, or greater than 100 micrometers, for example, depending on the degree of planarization desired or achieved. In another aspect, a surface of at least one of the first electrode and the second electrode can at least partially overlap the pixel circuit and can exhibit no surface features indicative of an underlying pixel circuit.
在此實施例之一態樣中,位址線及資料線安置於光偵測器之下,且平坦化層安置於位址線及資料線上以及位址線及資料線之介層孔上。平坦化層可接著完全地或部分地在像素電路之特徵之上、在陣列特徵之上、在連接至TFT之源極或汲極的電介層孔互連件之上、在單級像素內放大器元件之上及/或在兩級像素內放大器元件之上平坦化。平坦化層可為鈍化層、介電層或絕緣層中之至少一者。 In one aspect of this embodiment, the address lines and data lines are disposed under the photodetector, and the planarization layer is disposed on the address lines and the data lines and the via holes of the address lines and the data lines. The planarization layer can then be wholly or partially over the features of the pixel circuit, over the array features, over the dielectric via interconnects connected to the source or drain of the TFT, within a single level of pixels The amplifier element is planarized over the amplifier element and/or over the amplifier elements within the two-stage pixel. The planarization layer can be at least one of a passivation layer, a dielectric layer, or an insulating layer.
在此實施例之一態樣中,輻射感測器可包括安置於光偵測器之 下之位址線及資料線,且平坦化層安置於位址線及資料線上以及位址線及資料線之介層孔上。另外,電介層孔互連件可延伸穿過平坦化層且將第一電極連接至像素電路。與感光層接觸之電介層孔互連件之表面反曲可具有一大於1/2微米、大於1微米、大於5微米、大於10微米及大於100微米之曲率半徑。 In one aspect of this embodiment, the radiation sensor can include a photodetector The address line and the data line are located below, and the planarization layer is disposed on the address line and the data line and the via hole of the address line and the data line. Additionally, the dielectric via interconnects can extend through the planarization layer and connect the first electrode to the pixel circuitry. The surface reflex of the dielectric via interconnect in contact with the photosensitive layer can have a radius of curvature greater than 1/2 micron, greater than 1 micron, greater than 5 microns, greater than 10 microns, and greater than 100 microns.
在此實施例之一態樣中,感光層可為p-i-n半導體堆疊、n-i-p半導體堆疊或金屬絕緣體半導體堆疊中之一者。像素電路可包括薄膜電晶體、二極體、電容器、電阻器、跡線、介層孔、控制線、位址線及接地平面中之一者。像素電路可進一步包括非晶系半導體電晶體或多晶半導體電晶體或微晶半導體電晶體中之一者。像素電路可包括定址電晶體、放大器電晶體及重設電晶體中之至少一者。像素電路可進一步包括由非晶矽、低溫非晶矽及微晶矽中之至少一者製成的元件。像素電路可進一步包括由以下各項中之至少一者製成的元件:矽半導體、硫族化物半導體、硒化鎘半導體、有機半導體、有機小分子或聚合物半導體、碳奈米管,或石墨薄膜,或其他半導電材料。 In one aspect of this embodiment, the photosensitive layer can be one of a p-i-n semiconductor stack, an n-i-p semiconductor stack, or a metal insulator semiconductor stack. The pixel circuit can include one of a thin film transistor, a diode, a capacitor, a resistor, a trace, a via, a control line, an address line, and a ground plane. The pixel circuit may further include one of an amorphous semiconductor transistor or a polycrystalline semiconductor transistor or a microcrystalline semiconductor transistor. The pixel circuit can include at least one of an address transistor, an amplifier transistor, and a reset transistor. The pixel circuit may further include an element made of at least one of an amorphous germanium, a low temperature amorphous germanium, and a microcrystalline germanium. The pixel circuit may further include an element made of at least one of: germanium semiconductor, chalcogenide semiconductor, cadmium selenide semiconductor, organic semiconductor, organic small molecule or polymer semiconductor, carbon nanotube, or graphite Film, or other semi-conductive material.
在此實施例之一態樣中,感光層可為以下各項中之至少一者:1)跨越複數個光偵測器像素延伸之連續感光層,或2)與該複數個光偵測器像素中之各別者相關聯的離散感光層。閃爍層可為以下各項中之至少一者:CsI:Tl、Gd2O2S:Tb、CsI:Na、NaI:Tl、CaWO4、ZnWO4、CdWO4、Bi4Ge3O12、Lu1.8Yb0.2SiO5:Ce、Gd2SiO5:Ce、BaFCl:Eu2+、BaSO4:Eu2+、BaFBr:Eu2+、LaOBr:Tb3+、LaOBr:Tm3+、La2O2S:Tb3+、Y2O2S:Tb3+、YTaO4、YTaO4:Nb、ZnS:Ag、(Zn,Cd)S:Ag、ZnSiO4:Mn2+、CsI、LiI:Eu2+、PbWO4、Bi4Si3O12、Lu2SiO5:Ce3+、YAlO3:Ce3+、CsF、CaF2:Eu2+、BaF2、CeF3、Y1.34Gd0.6O3:Eu3+、Pr、Gd2O2S:Pr3+、Ce、SCGl、HFG:Ce3+(5%)及C14H10,或其他閃爍器材料。 In one aspect of this embodiment, the photosensitive layer can be at least one of: 1) a continuous photosensitive layer extending across a plurality of photodetector pixels, or 2) and the plurality of photodetectors A discrete photosensitive layer associated with each of the pixels. The scintillation layer may be at least one of the following: CsI: Tl, Gd 2 O 2 S: Tb, CsI: Na, NaI: Tl, CaWO 4 , ZnWO 4 , CdWO 4 , Bi 4 Ge 3 O 12 , Lu 1.8 Yb 0.2 SiO 5 :Ce, Gd 2 SiO 5 :Ce, BaFCl:Eu 2+ , BaSO 4 :Eu 2+ , BaFBr:Eu 2+ ,LaOBr:Tb 3+ ,LaOBr:Tm 3+ ,La 2 O 2 S: Tb 3+ , Y 2 O 2 S: Tb 3+ , YTaO 4 , YTaO 4 : Nb, ZnS: Ag, (Zn, Cd) S: Ag, ZnSiO 4 : Mn 2+ , CsI, LiI: Eu 2 + , PbWO 4 , Bi 4 Si 3 O 12 , Lu 2 SiO 5 :Ce 3+ , YAlO 3 :Ce 3+ , CsF, CaF 2 :Eu 2+ , BaF 2 , CeF 3 , Y 1.34 Gd 0.6 O 3 : Eu 3+ , Pr, Gd 2 O 2 S: Pr 3+ , Ce, SCG1, HFG: Ce 3+ (5%) and C 14 H 10 , or other scintillator materials.
在此實施例之一態樣中,輻射感測器可包括一支撐像素電路、光偵測器及閃爍層之基底基板,且可包括以規則圖案排列於該基底基板上之複數個光偵測器像素。在此實施例之一態樣中,該可透射光子之第二電極可形成一用於該複數個光偵測器像素之偏壓平面。像素電路之一部分可安置於基底基板上在鄰近光偵測器像素之間的間隙區中。此部分可包括薄膜電晶體、二極體、電容器、電阻器、介層孔、跡線、控制線、位址線及接地平面中之一者。在此實施例之一態樣中,第一電極可具有終止於該間隙區近旁之傾斜末端。 In one aspect of this embodiment, the radiation sensor can include a base substrate supporting the pixel circuit, the photodetector, and the scintillation layer, and can include a plurality of light detections arranged on the base substrate in a regular pattern. Pixel. In one aspect of this embodiment, the photo-transmissive second electrode can form a bias plane for the plurality of photodetector pixels. A portion of the pixel circuit can be disposed on the base substrate in a gap region between adjacent photodetector pixels. This portion may include one of a thin film transistor, a diode, a capacitor, a resistor, a via, a trace, a control line, an address line, and a ground plane. In one aspect of this embodiment, the first electrode can have a sloped end that terminates near the gap region.
在此實施例之一態樣中,在第一電極與可透射光子之第二電極之間的暗電流(正規化至單位光偵測器面積)可小於10pA/mm2,或小於5pA/mm2,或小於1pA/mm2,或小於0.5pA/mm2。暗電流之位準在某種程度上與上文所論述的平坦化之程度及表面反曲之曲率半徑耦合。在此實施例之一態樣中,在感光層中最接近表面反曲之區中的電場可為在一對平行的第一電極與第二電極之間的感光層中之電場的60%以上及300%以下。電場之變化在某種程度上與上文所論述的平坦化之程度及表面反曲之曲率半徑耦合。 In one aspect of this embodiment, the dark current (normalized to unit photodetector area) between the first electrode and the second electrode that can transmit photons can be less than 10 pA/mm 2 , or less than 5 pA/mm. 2, or less than 1pA / mm 2, or less than 0.5pA / mm 2. The level of dark current is somewhat coupled to the degree of planarization discussed above and the radius of curvature of the surface recursion. In one aspect of this embodiment, the electric field in the region of the photosensitive layer closest to the surface recursion may be more than 60% of the electric field in the photosensitive layer between a pair of parallel first and second electrodes. And below 300%. The change in the electric field is coupled to some extent to the degree of planarization discussed above and the radius of curvature of the surface recursion.
在此實施例之一態樣中,感測器可包括一安置於閃爍層上之金屬板。 In one aspect of this embodiment, the sensor can include a metal plate disposed on the scintillation layer.
在此實施例之一態樣中,每一光偵測器像素之電荷捕集之位準(其係藉由在單一放射攝影圖框期間由於捕集而損失之該成像信號之量來定量,且表達為在電荷捕集與電荷釋放處於平衡之條件下獲得的成像信號之百分比)(例如)取決於所要或所達成之平坦化之程度而可小於20%、可小於15%、小於10%或小於5%。 In one aspect of this embodiment, the level of charge trapping of each photodetector pixel (which is quantified by the amount of the imaging signal lost due to trapping during a single radiographic frame, And expressed as a percentage of the imaging signal obtained under conditions in which charge trapping and charge release are in equilibrium), for example, may be less than 20%, may be less than 15%, less than 10% depending on the degree of planarization desired or achieved. Or less than 5%.
在此實施例之一態樣中,每一光偵測器像素之電荷釋放(其係藉由在具有輻射之情況下且在電荷捕集與電荷釋放處於平衡之條件下獲取的一系列圖框之後的在不存在輻射之情況下獲取的第一圖框期間、 自捕集狀態釋放的該成像信號之量來定量,且表達為在電荷捕集與釋放處於平衡之條件下獲得的成像信號之百分比)可(例如)取決於所要或所達成之平坦化之程度而小於15%、小於10%、小於5%或小於3%。 In one aspect of this embodiment, the charge release of each photodetector pixel is obtained by a series of frames obtained with radiation and under equilibrium with charge trapping and charge release. Subsequent period of the first frame acquired in the absence of radiation, The amount of the imaging signal released from the trapping state is quantified and expressed as a percentage of the imaging signal obtained under conditions in which charge trapping and release are in equilibrium) may, for example, depend on the degree of planarization desired or achieved Less than 15%, less than 10%, less than 5% or less than 3%.
該光偵測器具有每一光偵測器像素之延滯,每一光偵測器像素之延滯係藉由在具有輻射之情況下獲取的一個圖框或一系列圖框之後的在不存在輻射之情況下獲取的第一圖框期間、自捕集狀態釋放之成像信號(該成像信號指示在感光層中所產生之電子電洞對,且該成像信號起源於在一或多個先前圖框中所捕集的電荷)之量來定量,且表達為來自先前圖框之成像信號之百分比,每一光偵測器像素之延滯小於約15%。在此實施例之一態樣中,每一光偵測器像素之延滯可(例如)取決於所要或所達成之平坦化之程度而小於10%、小於5%或小於3%。 The photodetector has a delay of each photodetector pixel, and the delay of each photodetector pixel is followed by a frame or a series of frames acquired under the condition of radiation An imaging signal released from the trapped state during the first frame acquired in the presence of radiation (the imaging signal indicates an electron hole pair generated in the photosensitive layer, and the imaging signal originates from one or more previous The amount of charge trapped in the frame is quantified and expressed as a percentage of the imaging signal from the previous frame, with a retardation of less than about 15% for each photodetector pixel. In one aspect of this embodiment, the delay of each photodetector pixel can be, for example, less than 10%, less than 5%, or less than 3%, depending on the degree of planarization desired or achieved.
在第二十五說明實施例中,一輻射感測器包括一光導體偵測器,其按次序具有一第一電極、一光導層,及一可透射電離輻射之第二電極。該光導層經組態以在與電離輻射相互作用時產生電子電洞對。該輻射感測器包括像素電路,其電連接至該第一電極且經組態以量測指示在該光導層中所產生之該等電子電洞對之一成像信號,且該像素電路包括氧化物半導體。該輻射感測器包括一平坦化層,其安置於該像素電路上在該第一電極與該像素電路之間,以使得該第一電極高於包括該像素電路之一平面。該第一電極及該第二電極中之至少一者之一表面至少部分地重疊於該像素電路且具有高於該像素電路之特徵之一表面反曲。 In a twenty-fifth illustrative embodiment, a radiation sensor includes a photoconductor detector having a first electrode, a photoconductive layer, and a second electrode that transmits ionizing radiation in sequence. The photoconductive layer is configured to create an electron hole pair upon interaction with ionizing radiation. The radiation sensor includes a pixel circuit electrically coupled to the first electrode and configured to measure an imaging signal indicative of one of the pairs of electron holes generated in the light guiding layer, and the pixel circuit includes oxidation Semiconductor. The radiation sensor includes a planarization layer disposed between the first electrode and the pixel circuit on the pixel circuit such that the first electrode is higher than a plane including the pixel circuit. A surface of at least one of the first electrode and the second electrode at least partially overlaps the pixel circuit and has a surface recursion higher than one of the features of the pixel circuit.
在此實施例之一態樣中,氧化物半導體包括以下各項中之至少一者:含鋅氧化物、SnO2、TiO2、Ga2O3、InGaO、In2O3及InSnO。含鋅氧化物可包括ZnO、InGaZnO、InZnO、ZnSnO中之至少一者。氧化物半導體可包括非晶系半導體或多晶半導體中之至少一者。 In one aspect of this embodiment, the oxide semiconductor includes at least one of zinc oxide, SnO 2 , TiO 2 , Ga 2 O 3 , InGaO, In 2 O 3 , and InSnO. The zinc-containing oxide may include at least one of ZnO, InGaZnO, InZnO, and ZnSnO. The oxide semiconductor may include at least one of an amorphous semiconductor or a polycrystalline semiconductor.
第二十五實施例因此在範疇上類似於第十實施例且包括上文所論述之第十實施例之態樣,接著描述較佳組合之實例。 The twenty-fifth embodiment is thus similar in scope to the tenth embodiment and includes the tenth embodiment discussed above, and then examples of preferred combinations are described.
在此實施例之一態樣中,平坦化層可為鈍化層、介電層或絕緣層中之至少一者。在此實施例之一態樣中,第一電極或第二電極之高於像素電路之表面反曲具有一大於1/2微米、大於1微米、大於5微米、大於10微米或大於100微米之曲率半徑。在另一態樣中,該第一電極及該第二電極中之至少一者之表面可至少部分地重疊於該像素電路且可無展現指示下伏像素電路之表面特徵。 In one aspect of this embodiment, the planarization layer can be at least one of a passivation layer, a dielectric layer, or an insulating layer. In one aspect of this embodiment, the surface of the first electrode or the second electrode that is higher than the surface of the pixel circuit has a recursion greater than 1/2 micrometer, greater than 1 micrometer, greater than 5 micrometers, greater than 10 micrometers, or greater than 100 micrometers. Radius of curvature. In another aspect, a surface of at least one of the first electrode and the second electrode can at least partially overlap the pixel circuit and can exhibit no surface features indicative of an underlying pixel circuit.
在此實施例之一態樣中,位址線及資料線安置於光導體偵測器之下,且平坦化層安置於位址線及資料線上以及位址線及資料線之介層孔上。另外,電介層孔互連件可延伸穿過平坦化層且將第一電極連接至像素電路。與感光層接觸之電介層孔互連件之表面反曲可具有一大於1/2微米、大於1微米、大於5微米、大於10微米及大於100微米之曲率半徑。 In one aspect of this embodiment, the address line and the data line are disposed under the photoconductor detector, and the planarization layer is disposed on the address line and the data line and the via hole of the address line and the data line. . Additionally, the dielectric via interconnects can extend through the planarization layer and connect the first electrode to the pixel circuitry. The surface reflex of the dielectric via interconnect in contact with the photosensitive layer can have a radius of curvature greater than 1/2 micron, greater than 1 micron, greater than 5 microns, greater than 10 microns, and greater than 100 microns.
在此實施例之一態樣中,像素電路可包括薄膜電晶體、二極體、電容器、電阻器、跡線、介層孔、控制線、位址線及接地平面中之一者。像素電路可進一步包括非晶系半導體電晶體或多晶半導體電晶體或微晶半導體電晶體中之一者。像素電路可包括定址電晶體、放大器電晶體及重設電晶體中之至少一者。像素電路可進一步包括由非晶矽、低溫非晶矽及微晶矽中之至少一者製成的元件。像素電路可進一步包括由以下各項中之至少一者製成的元件:矽半導體、硫族化物半導體、硒化鎘半導體、有機半導體、有機小分子或聚合物半導體、碳奈米管,或石墨薄膜,或其他半導電材料。 In one aspect of this embodiment, the pixel circuit can include one of a thin film transistor, a diode, a capacitor, a resistor, a trace, a via, a control line, an address line, and a ground plane. The pixel circuit may further include one of an amorphous semiconductor transistor or a polycrystalline semiconductor transistor or a microcrystalline semiconductor transistor. The pixel circuit can include at least one of an address transistor, an amplifier transistor, and a reset transistor. The pixel circuit may further include an element made of at least one of an amorphous germanium, a low temperature amorphous germanium, and a microcrystalline germanium. The pixel circuit may further include an element made of at least one of: germanium semiconductor, chalcogenide semiconductor, cadmium selenide semiconductor, organic semiconductor, organic small molecule or polymer semiconductor, carbon nanotube, or graphite Film, or other semi-conductive material.
在此實施例之一態樣中,一金屬板可安置於該可透射電離輻射之第二電極上或可安置於該可透射電離輻射之第二電極上之囊封層上。另外,平坦化層可至少部分地在陣列特徵之上、在連接至TFT之 源極或汲極的電介層孔互連件之上、在單級像素內放大器元件之上或在兩級像素內放大器元件之上平坦化。 In one aspect of this embodiment, a metal plate can be disposed on the second electrode of the transmissive ionizing radiation or can be disposed on the encapsulating layer of the second electrode that transmits the ionizing radiation. Additionally, the planarization layer can be at least partially over the array features, connected to the TFT Above the source or drain dielectric via interconnects, planarize over the single-stage in-pixel amplifier components or over the two-level pixel amplifier components.
在此實施例之一態樣中,光導層可為以下各項中之至少一者:1)跨越複數個光導體偵測器像素延伸之連續光導層,或2)與該複數個光導體偵測器像素中之各別者相關聯的離散光導層。輻射感測器可包括一支撐像素電路及光導層之基底基板。輻射感測器可包括以規則圖案排列於該基底基板上之複數個光導體偵測器像素。在此實施例之一態樣中,該可透射電離輻射之第二電極可形成一用於該複數個光導體偵測器像素之偏壓平面。像素電路之一部分可安置於基底基板上在鄰近光導體偵測器像素之間的間隙區中。此部分可包括薄膜電晶體、二極體、電容器、電阻器、介層孔、跡線、控制線、位址線及接地平面中之一者。第一電極可具有終止於該間隙區近旁之傾斜末端。 In one aspect of this embodiment, the light guiding layer can be at least one of: 1) a continuous light guiding layer extending across a plurality of photoconductor detector pixels, or 2) detecting the plurality of light conductors A discrete photoconductive layer associated with each of the detector pixels. The radiation sensor can include a base substrate supporting the pixel circuit and the light guiding layer. The radiation sensor can include a plurality of photoconductor detector pixels arranged in a regular pattern on the base substrate. In one aspect of this embodiment, the second electrode that transmits the ionizing radiation forms a bias plane for the plurality of photoconductor detector pixels. A portion of the pixel circuit can be disposed on the base substrate in a gap region between adjacent photodetector pixels. This portion may include one of a thin film transistor, a diode, a capacitor, a resistor, a via, a trace, a control line, an address line, and a ground plane. The first electrode can have a slanted end that terminates near the gap region.
因此,在第二十五說明實施例中,光導層在與x光或其他電離輻射相互作用時產生電子電洞對。光導層可包括以下半導體中之至少一者:VB-VIB、VB-VIIB、IIB-VIB、IIB-VB、IIIB-VB、IIIB-VIB、IB-VIB及IVB-VIIB,且更具體言之,可包括以下各項中之至少一者:a-Se、PbI2、HgI2、PbO、CdZnTe、CdTe、Bi2S3、Bi2Se3、BiI3、BiBr3、CdS、CdSe、HgS、Cd2P3、InAs、InP、In2S3、In2Se3、Ag2S、PbI4 -2及Pb2I7 -3。 Thus, in the twenty-fifth illustrative embodiment, the photoconductive layer produces an electron hole pair when interacting with x-rays or other ionizing radiation. The photoconductive layer may include at least one of the following semiconductors: VB-VIB, VB-VIIB, IIB-VIB, IIB-VB, IIIB-VB, IIIB-VIB, IB-VIB, and IVB-VIIB, and more specifically, may comprise at least one of: a-Se, PbI 2, HgI 2, PbO, CdZnTe, CdTe, Bi 2 S 3, Bi 2 Se 3, BiI 3, BiBr 3, CdS, CdSe, HgS, Cd 2 P 3 , InAs, InP, In 2 S 3 , In 2 Se 3 , Ag 2 S, PbI 4 -2 and Pb 2 I 7 -3 .
在此實施例之一態樣中,在第一電極與第二電極之間的暗電流(正規化至單位光導體偵測器面積)可小於10pA/mm2,或小於5pA/mm2,或小於1pA/mm2,或小於0.5pA/mm2。暗電流之位準在某種程度上與上文所論述的平坦化之程度及表面反曲之曲率半徑耦合。 In one aspect of this embodiment, the dark current (normalized to unit photoconductor detector area) between the first electrode and the second electrode may be less than 10 pA/mm 2 , or less than 5 pA/mm 2 , or Less than 1 pA/mm 2 , or less than 0.5 pA/mm 2 . The level of dark current is somewhat coupled to the degree of planarization discussed above and the radius of curvature of the surface recursion.
在此實施例之一態樣中,每一光導體偵測器像素之電荷捕集之位準(其係藉由在單一放射攝影圖框期間由於捕集而損失之該成像信號之量來定量,且表達為在電荷捕集與電荷釋放處於平衡之條件下獲 得的成像信號之百分比)(例如)取決於所要或所達成之平坦化之程度而可小於20%、可小於15%、小於10%或小於5%。 In one aspect of this embodiment, the level of charge trapping of each photodetector pixel is quantified by the amount of the imaging signal lost during capture during a single radiographic frame. And expressed as a condition in which charge trapping and charge release are in equilibrium The percentage of imaging signal obtained can be, for example, less than 20%, less than 15%, less than 10%, or less than 5%, depending on the degree of planarization desired or achieved.
在此實施例之一態樣中,每一光導體偵測器像素之電荷釋放(其係藉由在具有輻射之情況下且在電荷捕集與電荷釋放處於平衡之條件下獲取的一系列圖框之後的在不存在輻射之情況下獲取的第一圖框期間,自捕集狀態釋放的該成像信號之量來定量,且表達為在電荷捕集與釋放處於平衡之條件下獲得的成像信號之百分比)(例如)取決於所要或所達成之平坦化之程度而可小於15%、可小於10%、小於5%或小於3%。 In one aspect of this embodiment, the charge release of each photoconductor detector pixel is obtained by a series of pictures obtained with radiation and under equilibrium with charge trapping and charge release. During the first frame acquired after the frame in the absence of radiation, the amount of the imaging signal released from the trapped state is quantified and expressed as an imaging signal obtained under conditions in which charge trapping and release are in equilibrium. The percentage) may, for example, be less than 15%, may be less than 10%, less than 5%, or less than 3%, depending on the degree of planarization desired or achieved.
該光導體偵測器具有每一光導體偵測器像素之延滯,每一光導體偵測器像素之延滯係藉由在具有輻射之情況下獲取的一個圖框或一系列圖框之後的在不存在輻射之情況下獲取的第一圖框期間、自捕集狀態釋放之成像信號(該成像信號指示在光導層中所產生之電子電洞對,且該成像信號起源於在一或多個先前圖框中所捕集的電荷)之量來定量,且表達為來自先前圖框之成像信號之百分比,每一光導體偵測器像素之延滯小於約15%。在此實施例之一態樣中,每一光導體偵測器像素之延滯可(例如)取決於所要或所達成之平坦化之程度而小於10%、小於5%或小於3%。 The photoconductor detector has a delay of each photoconductor detector pixel, and the delay of each photoconductor detector pixel is followed by a frame or a series of frames acquired with radiation An imaging signal released from the trapped state during the first frame acquired in the absence of radiation (the imaging signal indicates an electron hole pair generated in the photoconductive layer, and the imaging signal originates in one or The amount of charge trapped in the plurality of previous frames is quantified and expressed as a percentage of the imaging signal from the previous frame, with each photodetector pixel having a retardation of less than about 15%. In one aspect of this embodiment, the retardation of each photoconductor detector pixel can be, for example, less than 10%, less than 5%, or less than 3%, depending on the degree of planarization desired or achieved.
在第二十六說明實施例中,一種用於製造一輻射感測器之方法包括:在一基底基板上形成像素電路元件,其中該像素電路包括氧化物半導體;在該等像素電路元件之上形成一平坦化層;在該平坦化層中形成一孔洞以曝露至該等像素電路元件之一連接件;使該圖案化之孔洞金屬化;形成與該金屬化孔洞電接觸之一第一電極;及在該第一電極上形成對光或電離輻射敏感之一層。該平坦化層在至少部分地重疊於該像素電路之第一電極之一表面上提供高於該像素電路之特徵的一表面反曲。該表面反曲可(例如)取決於所要或所達成之平坦化之程 度而具有一大於1/2微米、大於1微米、大於5微米、大於10微米或大於100微米之曲率半徑。 In a twenty-sixth illustrative embodiment, a method for fabricating a radiation sensor includes: forming a pixel circuit component on a base substrate, wherein the pixel circuit comprises an oxide semiconductor; above the pixel circuit component Forming a planarization layer; forming a hole in the planarization layer to expose to one of the pixel circuit components; metallizing the patterned hole; forming a first electrode in electrical contact with the metallization hole And forming a layer sensitive to light or ionizing radiation on the first electrode. The planarization layer provides a surface recursion that is higher than a characteristic of the pixel circuit on a surface of the first electrode that at least partially overlaps the pixel circuit. The surface recursion may, for example, depend on the desired or achieved flattening process The degree of curvature has a radius of curvature greater than 1/2 micron, greater than 1 micron, greater than 5 microns, greater than 10 microns, or greater than 100 microns.
在此實施例之一態樣中,氧化物半導體包括以下各項中之至少一者:含鋅氧化物、SnO2、TiO2、Ga2O3、InGaO、In2O3及InSnO。含鋅氧化物可包括ZnO、InGaZnO、InZnO、ZnSnO中之至少一者。氧化物半導體可包括非晶系半導體或多晶半導體中之至少一者。 In one aspect of this embodiment, the oxide semiconductor includes at least one of zinc oxide, SnO 2 , TiO 2 , Ga 2 O 3 , InGaO, In 2 O 3 , and InSnO. The zinc-containing oxide may include at least one of ZnO, InGaZnO, InZnO, and ZnSnO. The oxide semiconductor may include at least one of an amorphous semiconductor or a polycrystalline semiconductor.
在此實施例之一態樣中,將一感光層及一可透射光子之第二電極形成於第一電極上,且將一鈍化層形成於該可透射光子之第二電極上,且將一閃爍層形成於此鈍化層上,該閃爍層經組態以在與電離輻射相互作用時發射光子。在此例子中,感光層可為平坦化的或可在形成可透射光子之第二電極之前使感光層平坦化。 In one aspect of this embodiment, a photosensitive layer and a second electrode capable of transmitting photons are formed on the first electrode, and a passivation layer is formed on the second electrode of the phototransmissive photo, and a A scintillation layer is formed on the passivation layer that is configured to emit photons when interacting with ionizing radiation. In this example, the photosensitive layer can be planarized or the photosensitive layer can be planarized prior to forming the second electrode that can transmit photons.
在此實施例之一不同態樣中,將一光導層形成於第一電極上(該光導層經組態以在與x光或其他電離輻射相互作用時產生電子電洞對),且將一可透射電離輻射之第二電極形成於該光導層上。 In a different aspect of this embodiment, a photoconductive layer is formed on the first electrode (the photoconductive layer is configured to generate an electron hole pair when interacting with x-rays or other ionizing radiation), and A second electrode transmissive ionizing radiation is formed on the photoconductive layer.
在此等兩個態樣中,一第二電極可安置於閃爍層上之鈍化層上或安置於光導層上之囊封層上。在此等兩個態樣中,一金屬板可安置於閃爍層上或安置於閃爍層上之囊封上,或安置於可透射電離輻射之第二電極上之囊封層上。 In these two aspects, a second electrode can be disposed on the passivation layer on the scintillation layer or on the encapsulation layer on the photoconductive layer. In these two aspects, a metal plate can be placed on the scintillation layer or on the encapsulation on the scintillation layer or on the encapsulation layer on the second electrode that can transmit ionizing radiation.
在此實施例之一態樣中,可(例如)取決於所要或所達成之平坦化之程度而形成平坦化層以具有一大於1/2微米、大於1微米、大於5微米、大於10微米或大於100微米之曲率半徑。可藉由對所沈積之鈍化層之化學機械拋光來形成平坦化層。或者,可藉由旋塗一鈍化層且接著對彼鈍化層進行化學機械拋光來形成平坦化層。或者,可藉由使用旋塗在一(或第一)鈍化層之頂部上沈積另一鈍化層且接著對該另一(或第二)鈍化層進行化學機械拋光來形成平坦化層。平坦化層可至少部分地在陣列特徵之上、在連接至TFT之源極或汲極的電介層孔互連件 之上、在單級像素內放大器元件之上或在兩級像素內放大器元件之上平坦化。 In one aspect of this embodiment, the planarization layer can be formed, for example, to have a greater than 1/2 micron, greater than 1 micron, greater than 5 micron, greater than 10 micron, depending on the degree of planarization desired or achieved. Or a radius of curvature greater than 100 microns. The planarization layer can be formed by chemical mechanical polishing of the deposited passivation layer. Alternatively, the planarization layer can be formed by spin coating a passivation layer followed by chemical mechanical polishing of the passivation layer. Alternatively, the planarization layer can be formed by depositing another passivation layer on top of a (or first) passivation layer using spin coating and then chemical mechanical polishing the other (or second) passivation layer. The planarization layer can be at least partially over the array features, at the dielectric via interconnects connected to the source or drain of the TFT Above, planarize on top of the single-stage in-pixel amplifier components or on the two-stage in-pixel amplifier components.
在此實施例之一態樣中,第一電極之接近輻射感測器之鄰近像素之間的間隙區的末端可為傾斜的。在此實施例之一態樣中,可(例如)取決於所要或所達成之平坦化之程度而使金屬化孔洞逐漸變細而具有一大於1/2微米、或大於1微米、大於5微米、大於10微米或大於100微米之曲率半徑。 In one aspect of this embodiment, the end of the gap region between adjacent pixels of the first electrode proximate to the radiation sensor can be tilted. In one aspect of this embodiment, the metallized holes can be tapered, for example, depending on the degree of planarization desired or achieved to have a thickness greater than 1/2 micrometer, or greater than 1 micrometer, greater than 5 micrometers. a radius of curvature greater than 10 microns or greater than 100 microns.
在此實施例之一態樣中,可在基底基板上形成在第一說明實施例之態樣中針對像素電路元件及感光層所列出之特徵。舉例而言,當形成一閃爍層時,可在可透射光子之第二電極上形成以下各項中之至少一者:CsI:Tl、Gd2O2S:Tb、CsI:Na、NaI:Tl、CaWO4、ZnWO4、CdWO4、Bi4Ge3O12、Lu1.8Yb0.2SiO5:Ce、Gd2SiO5:Ce、BaFCl:Eu2+、BaSO4:Eu2+、BaFBr:Eu2+、LaOBr:Tb3+、LaOBr:Tm3+、La2O2S:Tb3+、Y2O2S:Tb3+、YTaO4、YTaO4:Nb、ZnS:Ag、(Zn,Cd)S:Ag、ZnSiO4:Mn2+、CsI、LiI:Eu2+、PbWO4、Bi4Si3O12、Lu2SiO5:Ce3+、YAlO3:Ce3+、CsF、CaF2:Eu2+、BaF2、CeF3、Y1.34Gd0.6O3:Eu3+、Pr、Gd2O2S:Pr3+、Ce、SCGl、HFG:Ce3+(5%)及C14H10。舉例而言,當形成一感光層時,形成以下各項中之至少一者:1)跨越複數個光偵測器像素延伸之連續感光層,或2)與該複數個光偵測器像素中之一者相關聯的離散感光層。 In one aspect of this embodiment, the features listed for the pixel circuit component and the photosensitive layer in the aspect of the first illustrative embodiment may be formed on the base substrate. For example, when a scintillation layer is formed, at least one of the following may be formed on the second electrode that can transmit photons: CsI: Tl, Gd 2 O 2 S: Tb, CsI: Na, NaI: Tl , CaWO 4 , ZnWO 4 , CdWO 4 , Bi 4 Ge 3 O 12 , Lu 1.8 Yb 0.2 SiO 5 :Ce, Gd 2 SiO 5 :Ce, BaFCl:Eu 2+ , BaSO 4 :Eu 2+ ,BaFBr:Eu 2 + , LaOBr: Tb 3+ , LaOBr: Tm 3+ , La 2 O 2 S: Tb 3+ , Y 2 O 2 S: Tb 3+ , YTaO 4 , YTaO 4 : Nb, ZnS: Ag, (Zn, Cd S: Ag, ZnSiO 4 : Mn 2+ , CsI, LiI: Eu 2+ , PbWO 4 , Bi 4 Si 3 O 12 , Lu 2 SiO 5 : Ce 3+ , YAlO 3 : Ce 3+ , CsF, CaF 2 :Eu 2+ , BaF 2 , CeF 3 , Y 1.34 Gd 0.6 O 3 :Eu 3+ , Pr, Gd 2 O 2 S:Pr 3+ , Ce, SCGl, HFG: Ce 3+ (5%) and C 14 H 10 . For example, when forming a photosensitive layer, at least one of the following is formed: 1) a continuous photosensitive layer extending across a plurality of photodetector pixels, or 2) and a plurality of photodetector pixels One of the associated discrete photosensitive layers.
舉例而言,當形成一光導層時,可在第一電極上形成以下半導體中之至少一者:VB-VIB、VB-VIIB、IIB-VIB、IIB-VB、IIIB-VB、IIIB-VIB、IB-VIB及IVB-VIIB,或更具體言之,可在第一電極上形成以下各項中之至少一者:a-Se、PbI2、HgI2、PbO、CdZnTe、CdTe、Bi2S3、Bi2Se3、BiI3、BiBr3、CdS、CdSe、HgS、Cd2P3、InAs、InP、In2S3、In2Se3、Ag2S、PbI4 -2及Pb2I7 -3。舉例而言,當形成一光導層 時,形成以下各項中之至少一者:1)跨越複數個光導體偵測器像素延伸之連續光導層,或2)與該複數個光導體偵測器像素中之一者相關聯的離散光導層。 For example, when forming a photoconductive layer, at least one of the following semiconductors may be formed on the first electrode: VB-VIB, VB-VIIB, IIB-VIB, IIB-VB, IIIB-VB, IIIB-VIB, IB-VIB and IVB-VIIB, or more specifically, at least one of: a-Se, PbI 2 , HgI 2 , PbO, CdZnTe, CdTe, Bi 2 S 3 may be formed on the first electrode. , Bi 2 Se 3 , BiI 3 , BiBr 3 , CdS, CdSe, HgS, Cd 2 P 3 , InAs, InP, In 2 S 3 , In 2 Se 3 , Ag 2 S, PbI 4 -2 and Pb 2 I 7 -3 . For example, when forming a light guiding layer, at least one of the following is formed: 1) a continuous light guiding layer extending across a plurality of photoconductor detector pixels, or 2) and the plurality of photoconductor detectors A discrete photoconductive layer associated with one of the pixels.
此外,當在基底基板上形成像素電路元件時,像素電路可進一步包括非晶系半導體電晶體或多晶半導體電晶體或微晶半導體電晶體中之一者。像素電路可包括定址電晶體、放大器電晶體及重設電晶體中之至少一者。像素電路可進一步包括由非晶矽、低溫非晶矽及微晶矽中之至少一者製成的元件。像素電路可進一步包括由以下各項中之至少一者製成的元件:矽半導體、硫族化物半導體、硒化鎘半導體、有機半導體、有機小分子或聚合物半導體、碳奈米管,或石墨薄膜,或其他半導電材料。 Further, when the pixel circuit element is formed on the base substrate, the pixel circuit may further include one of an amorphous semiconductor transistor or a polycrystalline semiconductor transistor or a microcrystalline semiconductor transistor. The pixel circuit can include at least one of an address transistor, an amplifier transistor, and a reset transistor. The pixel circuit may further include an element made of at least one of an amorphous germanium, a low temperature amorphous germanium, and a microcrystalline germanium. The pixel circuit may further include an element made of at least one of: germanium semiconductor, chalcogenide semiconductor, cadmium selenide semiconductor, organic semiconductor, organic small molecule or polymer semiconductor, carbon nanotube, or graphite Film, or other semi-conductive material.
鑒於上述教示,本發明之眾多修改及變化係可能的。因此,應理解,在附加申請專利範圍之範疇內,可以不同於如本文中特別描述之方式的方式來實踐本發明。 Numerous modifications and variations of the present invention are possible in light of the above teachings. Therefore, it is to be understood that the invention may be practiced otherwise than as specifically described herein.
圖1. 圖1為a-Si TFT之一形式之示意性三維圖式。自斜角檢視TFT之頂部。雖然TFT之說明為一般性的,但該圖式亦描繪在TFT為AMFPI像素中之定址開關之情況下所需的位址線。因此,該圖說明閘極位址線之一區段(在其連接至TFT之閘極的點處),及資料位址線之一區段(在其連接至TFT之汲極的點處)。TFT之通道具有15μm之寬度及10μm之長度,如藉由虛線箭頭指示。連續底部介電層及a-Si層被說明為在很大程度上透明,以便允許下伏特征可見。另外,為了呈現之清晰起見,相對於平行於基板之方向,在垂直於基板之方向上將圖式放大4倍,且僅描繪基板厚度之部分。由疊印於圖式上之黑色實線框界定的平面指示在圖2中顯現之橫截面圖之位置。此圖式中之其他有標記要素在圖2說明中加以描述。 Figure 1. Figure 1 is a schematic three-dimensional representation of one of the a-Si TFTs. View the top of the TFT from the bevel. Although the description of the TFT is general, the figure also depicts the address lines required in the case where the TFT is an address switch in the AMFPI pixel. Thus, the figure illustrates a section of the gate address line (at the point where it is connected to the gate of the TFT) and a section of the data address line (at the point where it is connected to the drain of the TFT) . The channel of the TFT has a width of 15 μm and a length of 10 μm as indicated by the dashed arrows. The continuous bottom dielectric layer and the a-Si layer are illustrated as being largely transparent to allow the underlying features to be visible. In addition, for clarity of presentation, the pattern is magnified 4 times in a direction perpendicular to the substrate with respect to the direction parallel to the substrate, and only a portion of the thickness of the substrate is depicted. The plane defined by the black solid line frame superimposed on the drawing indicates the position of the cross-sectional view appearing in FIG. Other marked elements in this figure are described in the description of Figure 2.
圖2. 圖2為圖1中所展示之a-Si TFT之示意性橫截面圖。此橫截 面之位置對應於由圖1中之線框界定的平面,且TFT之元件之灰階陰影的約定大致對應於圖1中所使用之約定。為了呈現之清晰起見,相對於平行於基板之方向,在垂直於基板之方向上已將圖式放大8倍,且僅描繪基板厚度之部分。使用標記來指示基板、TFT之閘極、源極及汲極、TFT中之底部介電層及頂部介電層、形成TFT之通道之a-Si層,及用以完成此n-型電晶體之結構的n+型摻雜a-Si材料。 Figure 2. Figure 2 is a schematic cross-sectional view of the a-Si TFT shown in Figure 1. The position of this cross section corresponds to the plane defined by the wireframe in Fig. 1, and the convention of the grayscale shading of the elements of the TFT substantially corresponds to the convention used in Fig. 1. For clarity of presentation, the pattern has been magnified 8 times in a direction perpendicular to the substrate relative to the direction parallel to the substrate, and only portions of the substrate thickness are depicted. Marking is used to indicate the substrate, the gate, the source and the drain of the TFT, the bottom dielectric layer and the top dielectric layer in the TFT, the a-Si layer forming the channel of the TFT, and to complete the n-type transistor The structure of the n + type doped a-Si material.
圖3. 圖3為多晶-Si TFT之一形式之示意性三維圖式。自斜角檢視TFT之頂部。雖然TFT之說明為一般性的,但該圖式亦描繪在TFT為AMFPI像素中之定址開關之情況下所需的位址線。因此,該圖說明閘極位址線之一區段(在其連接至TFT之多晶-Si閘極的點處),及資料位址線之一區段(在於介層孔處建立至TFT之汲極之接點的點處)。TFT之通道具有15μm之寬度及10μm之長度,如由虛線箭頭指示。連續鈍化層(鈍化#1)經說明為在很大程度上透明,以便允許下伏特征可見。另外,為了呈現之清晰起見,相對於平行於基板之方向,在垂直於基板之方向上將圖式放大4倍,且僅描繪基板厚度之部分。藉由疊印於圖式上之黑色實線框界定的平面指示在圖4中顯現之橫截面圖之位置。此圖式中之其他有標記要素在圖4說明中加以描述。 Figure 3. Figure 3 is a schematic three-dimensional representation of one of the forms of poly-Si TFT. View the top of the TFT from the bevel. Although the description of the TFT is general, the figure also depicts the address lines required in the case where the TFT is an address switch in the AMFPI pixel. Therefore, the figure illustrates a section of the gate address line (at the point where it is connected to the poly-Si gate of the TFT), and a section of the data address line (established to the TFT at the via hole) At the point of the bungee joint.) The channel of the TFT has a width of 15 μm and a length of 10 μm as indicated by the dashed arrow. The continuous passivation layer (passivation #1) is illustrated as being largely transparent to allow the underlying features to be visible. In addition, for clarity of presentation, the pattern is magnified 4 times in a direction perpendicular to the substrate with respect to the direction parallel to the substrate, and only a portion of the thickness of the substrate is depicted. The plane defined by the black solid line frame superimposed on the drawing indicates the position of the cross-sectional view appearing in FIG. Other marked elements in this figure are described in the description of FIG.
圖4. 圖4為圖3中所展示之多晶-Si TFT之示意性橫截面圖。此橫截面之位置對應於由圖3中之線框界定的平面且TFT之元件之灰階陰影的約定大致對應於圖3中所使用之約定。為了呈現之清晰起見,相對於平行於基板之方向,在垂直於基板之方向上已將圖式放大8倍,且僅描繪基板厚度之部分。使用標記來指示基板、緩衝鈍化、閘極介電質、TFT之閘極(其在此狀況下由多晶-Si形成)、用以形成TFT通道(在閘極介電質之下)之活性多晶-Si層以及TFT之源極及汲極(由疊印於多晶-Si層之部分之上的成角度線指示),及在TFT之上之鈍化層(「鈍化#1」)。此橫截面圖之位置並不展示閘極位址線與多晶-Si閘極之間 的連接。 Figure 4. Figure 4 is a schematic cross-sectional view of the poly-Si TFT shown in Figure 3. The position of this cross section corresponds to the plane defined by the wireframe in Fig. 3 and the convention of the grayscale shadow of the elements of the TFT substantially corresponds to the convention used in Fig. 3. For clarity of presentation, the pattern has been magnified 8 times in a direction perpendicular to the substrate relative to the direction parallel to the substrate, and only portions of the substrate thickness are depicted. Marking is used to indicate substrate, buffer passivation, gate dielectric, gate of the TFT (which is formed by poly-Si in this case), and activity to form the TFT channel (under the gate dielectric) The poly-Si layer and the source and drain of the TFT (indicated by the angled lines superimposed over the portion of the poly-Si layer) and the passivation layer over the TFT ("passivation #1"). The position of this cross-sectional view does not show the gate address line and the poly-Si gate Connection.
圖5. 圖5為來自主動式矩陣成像陣列之像素的示意性電路圖,該主動式矩陣成像陣列使用入射輻射之間接偵測。由筆直虛線界定之區指示像素之邊界。 Figure 5. Figure 5 is a schematic circuit diagram of a pixel from an active matrix imaging array that uses incident radiation inter-connect detection. The area defined by the straight dashed line indicates the boundary of the pixel.
圖6. 圖6為具有一離散光電二極體之間接偵測像素之一形式的示意性橫截面圖。此表示圖5中之像素電路之一特定結構實施且稱作基線架構。該視圖平行於閘極位址線之方向,閘極位址線在此橫截面中不可見。垂直虛線之間的距離表示一個像素之寬度。為了清晰之目的,此說明中之層及特徵未按比例繪製。 Figure 6. Figure 6 is a schematic cross-sectional view of one of the patterns of inter-connected detection pixels with a discrete photodiode. This represents a specific structure implementation of the pixel circuit of Figure 5 and is referred to as a baseline architecture. The view is parallel to the direction of the gate address line, and the gate address line is not visible in this cross section. The distance between the vertical dashed lines represents the width of one pixel. The layers and features in this description are not drawn to scale for clarity.
圖7. 圖7為來自主動式矩陣成像陣列之像素的示意性電路圖,該主動式矩陣成像陣列使用入射輻射之直接偵測。標記、線及符號之約定類似於圖5中所使用之彼等約定。由筆直虛線界定之區指示像素之邊界。 Figure 7. Figure 7 is a schematic circuit diagram of a pixel from an active matrix imaging array that uses direct detection of incident radiation. The conventions for marks, lines and symbols are similar to those used in Figure 5. The area defined by the straight dashed line indicates the boundary of the pixel.
圖8. 圖8為直接偵測像素之一形式之示意性橫截面圖。該視圖平行於閘極位址線之方向,閘極位址線在此橫截面中不可見。標記、線、符號及箭頭之約定類似於圖6中所使用之彼等約定。垂直虛線之間的距離表示一個像素之寬度。為了清晰之目的,此說明中之層及特徵未按比例繪製。又,未說明TFT及介層孔對光導體之拓撲之一致性的影響。 Figure 8. Figure 8 is a schematic cross-sectional view of one of the direct detection pixels. The view is parallel to the direction of the gate address line, and the gate address line is not visible in this cross section. The conventions for marks, lines, symbols and arrows are similar to those used in Figure 6. The distance between the vertical dashed lines represents the width of one pixel. The layers and features in this description are not drawn to scale for clarity. Moreover, the influence of the TFT and via holes on the uniformity of the topography of the photoconductor is not explained.
圖9. 圖9為間接偵測主動式矩陣陣列之四個鄰近像素的示意性呈現。此等像素之設計表示分別在圖5及圖6中所說明的像素電路之實施及基線架構之實施。圖式中之每一像素顯露了該設計之不同程度的架構細節。在圖底部之像素中,僅展示閘極位址線及定址TFT之閘極。在左手側之像素中,已添加定址TFT之源極及汲極,以及被光電二極體之n+型摻雜a-Si層覆蓋之底部電極。在右手側像素中,說明了統稱為光電二極體堆疊之n+型摻雜a-Si、純質a-Si、p+型摻雜a-Si及頂部光 學透明電極的組合層。在此設計中,底部電極輕微地延伸超出堆疊之邊緣。在圖頂部之像素中,已添加憑藉介層孔而連接至定址TFT之汲極的資料位址線,及憑藉介層孔而連接至光電二極體之頂部電極的偏壓線。 Figure 9. Figure 9 is a schematic representation of indirect detection of four adjacent pixels of an active matrix array. The design of such pixels represents the implementation of the pixel circuits and the implementation of the baseline architecture illustrated in Figures 5 and 6, respectively. Each pixel in the diagram reveals varying degrees of architectural detail of the design. In the pixel at the bottom of the figure, only the gate address line and the gate of the addressed TFT are shown. In the pixel on the left hand side, the source and drain of the addressed TFT and the bottom electrode covered by the n + -type doped a-Si layer of the photodiode are added. In the right-hand side pixel, a combined layer of n + -type doped a-Si, pure a-Si, p + -type doped a-Si, and top optically transparent electrode collectively referred to as a photodiode stack is illustrated. In this design, the bottom electrode extends slightly beyond the edge of the stack. In the pixel at the top of the figure, a data address line connected to the drain of the addressed TFT by the via hole and a bias line connected to the top electrode of the photodiode by the via hole have been added.
圖10. 圖10為一對間接偵測主動式矩陣陣列之在單一像素之區中的頂面的顯微照片。在每一狀況下,設計表示圖6中所說明之基線架構之實施。(a)為來自早先陣列之像素的顯微照片,該早先陣列具有對應於圖9中之說明之設計。(b)為來自稍後陣列設計之像素的顯微照片,在該稍後陣列設計中,已經由像素設計之最佳化而增加光學填充因子。在每一顯微照片中,定址TFT定位於由疊印於影像上之圓標明界限的區中,且亦指示閘極位址線、資料位址線、偏壓線及光電二極體之位置。注意,在每一顯微照片中,未被偏壓線遮住的光電二極體之部分之頂面看起來非常一致。 Figure 10. Figure 10 is a photomicrograph of a top surface of a pair of indirect-detected active matrix arrays in a single pixel region. In each case, the design represents the implementation of the baseline architecture illustrated in Figure 6. (a) is a photomicrograph of a pixel from an earlier array having a design corresponding to that illustrated in FIG. (b) is a photomicrograph of a pixel from a later array design in which the optical fill factor has been increased by optimization of the pixel design. In each photomicrograph, the addressed TFT is positioned in a region bounded by a circle superimposed on the image, and also indicates the location of the gate address line, the data address line, the bias line, and the photodiode. Note that in each photomicrograph, the top surface of the portion of the photodiode that is not covered by the bias line appears to be very uniform.
圖11. 圖11為具有離散的平面外光電二極體結構之間接偵測像素設計的橫截面圖的示意性圖式。該視圖平行於閘極位址線之方向,閘極位址線在此橫截面中不可見。圖式中之標記、線、箭頭、符號及約定類似於圖6中所使用之彼等標記、線、箭頭、符號及約定。垂直虛線之間的距離表示一個像素之寬度。為了清晰之目的,此說明中之層及特徵未按比例繪製。又,未說明TFT及介層孔對光電二極體之拓撲之一致性的影響。 Figure 11. Figure 11 is a schematic illustration of a cross-sectional view of an inter-detected pixel design with discrete out-of-plane photodiode structures. The view is parallel to the direction of the gate address line, and the gate address line is not visible in this cross section. The symbols, lines, arrows, symbols, and conventions in the drawings are similar to the ones, lines, arrows, symbols, and conventions used in FIG. The distance between the vertical dashed lines represents the width of one pixel. The layers and features in this description are not drawn to scale for clarity. Moreover, the influence of the TFT and the via hole on the uniformity of the topology of the photodiode is not explained.
圖12. 圖12為具有連續的平面外光電二極體結構之間接偵測像素設計的橫截面圖的示意性圖式。該視圖平行於閘極位址線之方向,閘極位址線在此橫截面中不可見。圖式中之標記、線、箭頭、符號及約定類似於圖11中所使用之彼等標記、線、箭頭、符號及約定。垂直虛線之間的距離表示一個像素之寬度。為了清晰之目的,此說明中之層及特徵未按比例繪製。又,未說明TFT及介層孔對光電二極體之拓撲 之一致性的影響。 Figure 12. Figure 12 is a schematic illustration of a cross-sectional view of an inter-connected detection pixel design with a continuous out-of-plane photodiode structure. The view is parallel to the direction of the gate address line, and the gate address line is not visible in this cross section. The symbols, lines, arrows, symbols, and conventions in the drawings are similar to the ones, lines, arrows, symbols, and conventions used in FIG. The distance between the vertical dashed lines represents the width of one pixel. The layers and features in this description are not drawn to scale for clarity. Moreover, the topology of the TFT and the via hole to the photodiode is not described. The impact of consistency.
圖13. 圖13為間接偵測主動式矩陣陣列之四個鄰近像素的示意性呈現。此等像素之設計表示分別在圖5及圖12中所說明的像素電路之實施及架構之實施。圖式中之每一像素顯露了該設計之不同程度的架構細節。在圖底部之像素中,僅展示閘極位址線及定址TFT之閘極。在左手側像素中,已添加定址TFT之源極及汲極、資料位址線,及後部接點。在右手側像素中,說明了底部電極,包括將此電極連接至後部接點(其駐留於由虛線標明界限之區中)之介層孔。在圖頂部之像素圖中,展示連續光電二極體結構之簡單表示,其中n+型摻雜層不可見且光電二極體之剩餘層未加以區別。 Figure 13. Figure 13 is a schematic representation of indirect detection of four adjacent pixels of an active matrix array. The design of such pixels represents the implementation and architecture of the pixel circuits illustrated in Figures 5 and 12, respectively. Each pixel in the diagram reveals varying degrees of architectural detail of the design. In the pixel at the bottom of the figure, only the gate address line and the gate of the addressed TFT are shown. In the left-hand side pixel, the source and drain of the addressed TFT, the data address line, and the rear contact have been added. In the right hand side pixel, the bottom electrode is illustrated, including a via hole that connects this electrode to the back contact (which resides in the region marked by the dashed line). In the pixmap at the top of the figure, a simple representation of the structure of a continuous photodiode is shown, where the n + type doped layer is not visible and the remaining layers of the photodiode are not distinguished.
圖14. 圖14為間接偵測主動式矩陣陣列之在單一像素之區中的頂面的顯微照片。設計表示圖12中所說明之架構之實施且對應於圖13中之呈現。指示了閘極位址線、資料位址線、底部電極及將此電極連接至後部接點之介層孔的位置。注意,影像中可見之各種細節對應於連續光電二極體結構之頂部的拓撲。 Figure 14. Figure 14 is a photomicrograph of the top surface of the active matrix array in the region of a single pixel. The design represents the implementation of the architecture illustrated in Figure 12 and corresponds to the presentation in Figure 13. Indicates the position of the gate address line, the data address line, the bottom electrode, and the via hole that connects the electrode to the back contact. Note that the various details visible in the image correspond to the topology of the top of the continuous photodiode structure.
圖15. 圖15為來自基於主動式像素設計之間接偵測陣列之像素的示意性電路圖,該主動式像素設計具有單級像素內放大器。指示了資料位址線、閘極位址線、重設TFT(TFTRST)、源極隨耦器TFT(TFTSF)、定址TFT(TFTADDR),及光電二極體(PD,具有電容CPD)。VBIAS為施加至光電二極體之頂部電極之反向偏壓電壓的量值,且VG-RST、VD-RST及VCC為用以操作陣列之其他電壓。TFT中之兩者,TFTRST及TFTADDR經說明為具有雙閘極結構。所有TFT皆為n-型電晶體。 Figure 15. Figure 15 is a schematic circuit diagram of a pixel from an interferometric detection array based on an active pixel design with a single-stage in-pixel amplifier. Indicates data address line, gate address line, reset TFT (TFT RST ), source follower TFT (TFT SF ), addressed TFT (TFT ADDR ), and photodiode (PD with capacitor C) PD ). V BIAS is the magnitude of the reverse bias voltage applied to the top electrode of the photodiode, and V G-RST , V D-RST and V CC are other voltages used to operate the array. Both of the TFTs, TFT RST and TFT ADDR are illustrated as having a dual gate structure. All TFTs are n-type transistors.
圖16. 圖16為基於主動式像素設計之間接偵測陣列的四個鄰近像素之示意性呈現,該主動式像素設計使用多晶-Si TFT。此等像素之設計表示圖15中所說明之像素電路之實施。此圖中之TFT具有類似於 圖3及圖4中所說明之多晶-Si TFT之結構的結構。光電二極體具有類似於圖12中所展示之結構之連續結構。圖式中之每一像素顯露了該設計之不同程度的架構細節。在圖底部之像素中,展示了每一TFT之閘極(由多晶-Si形成)、用以形成每一TFT之通道之活性多晶-Si、閘極位址線,及用於重設TFT之操作中的重設電壓線。在左手側像素中,已添加資料位址線、後部接點、供電電壓線,以及各種跡線及介層孔。在右手側像素中,說明了底部電極,包括將此電極連接至後部接點之介層孔。在圖頂部之像素中,展示了連續光電二極體結構之簡單表示,其中圖案化之n+型摻雜層不可見且光電二極體之剩餘層未加以區別。 Figure 16. Figure 16 is a schematic representation of four adjacent pixels based on an active pixel design inter-connected detection array using a poly-Si TFT. The design of such pixels represents the implementation of the pixel circuit illustrated in FIG. The TFT in this figure has a structure similar to that of the poly-Si TFT illustrated in FIGS. 3 and 4. The photodiode has a continuous structure similar to the structure shown in FIG. Each pixel in the diagram reveals varying degrees of architectural detail of the design. In the pixel at the bottom of the figure, the gate of each TFT (formed by poly-Si), the active poly-Si for forming the channel of each TFT, the gate address line, and the reset are shown. The reset voltage line in the operation of the TFT. In the left-hand side pixels, data address lines, rear contacts, supply voltage lines, and various traces and via holes have been added. In the right hand side pixel, the bottom electrode is illustrated, including the via hole that connects this electrode to the back contact. In the pixels at the top of the figure, a simple representation of the structure of a continuous photodiode is shown in which the patterned n + type doped layer is not visible and the remaining layers of the photodiode are not distinguished.
圖17. 圖17為間接偵測陣列之在單一像素之區中的頂面的顯微照片。該設計表示圖15中所說明之像素電路之實施且對應於圖16中之呈現。顯微照片經定向以使得陣列之閘極位址線及資料位址線(其在該設計之連續光電二極體之下方)之方向分別沿著此影像之平面垂直地及水平地對準。一由粗虛線(指示一個完整像素之邊界)及細的水平虛線(指示在稍後圖中顯現之橫截面圖之位置)形成的方框疊印於影像上。注意,影像中可見之各種細節對應於連續光電二極體結構之頂部的拓撲。 Figure 17. Figure 17 is a photomicrograph of the top surface of the indirect detection array in the region of a single pixel. This design represents the implementation of the pixel circuit illustrated in Figure 15 and corresponds to the presentation in Figure 16. The photomicrographs are oriented such that the direction of the gate address lines and data address lines of the array (which are below the continuous photodiode of the design) are vertically and horizontally aligned along the plane of the image, respectively. A box formed by a thick dashed line (indicating the boundary of one complete pixel) and a thin horizontal dashed line (indicating the position of the cross-sectional view appearing in later figures) is overlaid on the image. Note that the various details visible in the image correspond to the topology of the top of the continuous photodiode structure.
圖18. 圖18為來自基於主動式像素設計之間接偵測陣列之像素的示意性電路圖,該主動式像素設計具有兩級像素內放大器。指示了資料位址線、閘極位址線、重設TFT(TFTRST)、共源極放大器TFT(TFTCSA)、有效負載TFT(TFTAL)、源極隨耦器TFT(TFTSF)、定址TFT(TFTADDR)、回饋電容器(具有電容CFB)及光電二極體(PD,具有電容CPD)。VBIAS為施加至光電二極體之頂部電極之反向偏壓電壓的量值,且VG-RST、VG-AL、VCC及VGND為用以操作陣列之其他電壓。TFT中之兩者,TFTRST及TFTADDR經說明為具有雙閘極結構。在該等TFT 中,TFTAL為p-型電晶體而剩餘電晶體為n-型。 Figure 18. Figure 18 is a schematic circuit diagram of a pixel from an interferometric detection array based on an active pixel design with a two-stage in-pixel amplifier. Indicates data address line, gate address line, reset TFT (TFT RST ), common source amplifier TFT (TFT CSA ), payload TFT (TFT AL ), source follower TFT (TFT SF ), Addressing TFT (TFT ADDR ), feedback capacitor (having capacitor C FB ), and photodiode (PD, having capacitance C PD ). V BIAS is the magnitude of the reverse bias voltage applied to the top electrode of the photodiode, and V G-RST , V G-AL , V CC , and V GND are other voltages used to operate the array. Both of the TFTs, TFT RST and TFT ADDR are illustrated as having a dual gate structure. In these TFTs, the TFT AL is a p-type transistor and the remaining transistor is an n-type.
圖19. 圖19為基於主動式像素設計之間接偵測陣列的四個鄰近像素之示意性呈現,該主動式像素設計使用多晶-Si TFT。此等像素之設計表示圖18中所說明之像素電路之實施。此圖中之TFT具有類似於圖3及圖4中所說明之多晶-Si TFT之結構的結構。光電二極體具有類似於圖12中所展示之結構之連續結構。圖式中之每一像素顯露了該設計之不同程度的架構細節。在圖底部之像素中,展示了各種TFT之閘極(由多晶-Si形成)、用以形成每一TFT之通道之活性多晶-Si,及閘極位址線。在左手側像素中,已添加資料位址線、後部接點,以及各種跡線及介層孔。在右手側像素中,說明了底部電極,包括將此電極連接至後部接點之介層孔。在圖頂部之像素中,展示了連續光電二極體結構之簡單表示,其中圖案化之n+型摻雜層不可見且光電二極體之剩餘層未加以區別。 Figure 19. Figure 19 is a schematic representation of four adjacent pixels based on an active pixel design inter-connected detection array using a poly-Si TFT. The design of such pixels represents the implementation of the pixel circuit illustrated in FIG. The TFT in this figure has a structure similar to that of the poly-Si TFT illustrated in FIGS. 3 and 4. The photodiode has a continuous structure similar to the structure shown in FIG. Each pixel in the diagram reveals varying degrees of architectural detail of the design. In the pixels at the bottom of the figure, the gates of various TFTs (formed by poly-Si), the active poly-Si for forming the vias of each TFT, and the gate address lines are shown. In the left-hand side pixels, data bit lines, rear contacts, and various traces and via holes have been added. In the right hand side pixel, the bottom electrode is illustrated, including the via hole that connects this electrode to the back contact. In the pixels at the top of the figure, a simple representation of the structure of a continuous photodiode is shown in which the patterned n + type doped layer is not visible and the remaining layers of the photodiode are not distinguished.
圖20. 圖20為間接偵測陣列之在單一像素之區中的頂面的顯微照片。該設計表示圖18中所說明之像素電路之實施且對應於圖19中之呈現。顯微照片經定向以使得陣列之閘極位址線及資料位址線(其在該設計之連續光電二極體之下方)之方向分別沿著此影像之平面垂直地及水平地對準。一由粗虛線(指示一個完整像素之邊界)及細的水平虛線(指示在稍後圖中顯現之橫截面圖之位置)形成的方框疊印於影像上。注意,在影像中可見之各種細節對應於連續光電二極體結構之頂部的拓撲。 Figure 20. Figure 20 is a photomicrograph of the top surface of the indirect detection array in the region of a single pixel. This design represents the implementation of the pixel circuit illustrated in Figure 18 and corresponds to the presentation in Figure 19. The photomicrographs are oriented such that the direction of the gate address lines and data address lines of the array (which are below the continuous photodiode of the design) are vertically and horizontally aligned along the plane of the image, respectively. A box formed by a thick dashed line (indicating the boundary of one complete pixel) and a thin horizontal dashed line (indicating the position of the cross-sectional view appearing in later figures) is overlaid on the image. Note that the various details visible in the image correspond to the topology of the top of the continuous photodiode structure.
圖21. 圖21為基於單級像素內放大器設計之間接偵測陣列的計算之橫截面圖,該單級像素內放大器設計使用多晶-Si TFT。設計表示圖15中所說明之像素電路之實施且對應於圖16及圖17中之說明。此橫截面之位置對應於垂直於陣列之頂面、穿過在圖17中顯現之細的水平虛線的平面。水平視野對應於略大於單一像素之距離,且垂直虛線之 間的距離表示一個像素之寬度。此說明(由沈積、光微影、蝕刻及用於陣列之製造中的其他製程之計算模擬產生)展示陣列中之各種特徵及材料之次序、結構及原生拓撲。為了呈現之清晰起見,相對於平行於基板之方向,在垂直於基板之方向上已將圖式放大8倍,且僅描繪基板厚度之部分。 Figure 21. Figure 21 is a cross-sectional view of the calculation of an inter-connected detection array based on a single-stage in-pixel amplifier design using a poly-Si TFT. The design represents the implementation of the pixel circuit illustrated in Figure 15 and corresponds to the description in Figures 16 and 17. The position of this cross section corresponds to a plane perpendicular to the top surface of the array, passing through the thin horizontal dashed line appearing in Figure 17. The horizontal field of view corresponds to a distance slightly larger than a single pixel, and the vertical dashed line The distance between them represents the width of one pixel. This description (produced by deposition, photolithography, etching, and computational simulation of other processes used in the fabrication of arrays) demonstrates the order, structure, and native topology of the various features and materials in the array. For clarity of presentation, the pattern has been magnified 8 times in a direction perpendicular to the substrate relative to the direction parallel to the substrate, and only portions of the substrate thickness are depicted.
圖22. 圖22為基於兩級像素內放大器設計之間接偵測陣列的計算之橫截面圖,該兩級像素內放大器設計使用多晶-Si TFT。該設計表示圖18中所說明之像素電路之實施且對應於圖19及圖20中之說明。兩個橫截面之位置對應於垂直於陣列之頂面、穿過在圖20中顯現之細的水平虛線的平面。(a)此說明中之水平視野對應於略大於單一像素之距離,且垂直虛線之間的距離表示一個像素之寬度。(b)此說明中之水平視野對應於與圖21中之視野相同的距離,且僅展示一個像素之部分。此等說明(由沈積、光微影、蝕刻及用於陣列之製造中的其他製程之計算模擬產生)展示陣列中之各種特徵及材料之次序、結構及原生拓撲。為了呈現之清晰起見,相對於平行於基板之方向,在垂直於基板之方向上已將圖式放大8倍,且僅描繪基板厚度之部分。 Figure 22. Figure 22 is a cross-sectional view of a calculated inter-detection array based on a two-stage in-pixel amplifier design using a poly-Si TFT. This design represents the implementation of the pixel circuit illustrated in FIG. 18 and corresponds to the description in FIGS. 19 and 20. The position of the two cross-sections corresponds to a plane perpendicular to the top surface of the array, passing through the thin horizontal dashed lines appearing in Figure 20. (a) The horizontal field of view in this description corresponds to a distance slightly larger than a single pixel, and the distance between vertical dashed lines represents the width of one pixel. (b) The horizontal field of view in this description corresponds to the same distance as the field of view in Fig. 21, and only a portion of one pixel is shown. These descriptions (produced by deposition, photolithography, etching, and computational simulations of other processes used in the fabrication of arrays) demonstrate the order, structure, and native topology of the various features and materials in the array. For clarity of presentation, the pattern has been magnified 8 times in a direction perpendicular to the substrate relative to the direction parallel to the substrate, and only portions of the substrate thickness are depicted.
圖23. 圖23為單級像素內放大器陣列之在單一像素之區中的俯視圖,其對應於圖16中所說明之設計。(a)為自用以產生圖21之相同計算模擬產生的說明。(b)為陣列之實際實現之表面的顯微照片,其對應於圖17中之顯微照片。注意,在每一視圖中可見之各種細節對應於連續光電二極體結構之頂部的原生拓撲。 Figure 23. Figure 23 is a top plan view of a single-stage in-pixel amplifier array in a single pixel region, corresponding to the design illustrated in Figure 16. (a) is an illustration generated from the same computational simulation used to generate Figure 21. (b) is a photomicrograph of the actual realized surface of the array, which corresponds to the photomicrograph in FIG. Note that the various details visible in each view correspond to the native topology at the top of the continuous photodiode structure.
圖24. 圖24為兩級像素內放大器陣列之在單一像素之區中的俯視圖,其對應於圖19中所說明之設計。(a)為自用以產生圖22之相同計算模擬產生的說明。(b)為陣列之實際實現之表面的顯微照片,其對應於圖20中之顯微照片。注意,在每一視圖中可見之各種細節對應於連續光電二極體結構之頂部的原生拓撲。 Figure 24. Figure 24 is a top plan view of a two-stage intra-pixel amplifier array in a single pixel region, corresponding to the design illustrated in Figure 19. (a) is an illustration generated from the same computational simulation used to generate Figure 22. (b) is a photomicrograph of the actual realized surface of the array, which corresponds to the photomicrograph in Figure 20. Note that the various details visible in each view correspond to the native topology at the top of the continuous photodiode structure.
圖25. 圖25為說明曲率半徑之一般概念的圖式,曲率半徑可應用於表面之平坦度之改變的特性化。表面平坦度之改變的急劇性(亦即,突然性)之程度由半徑弧r來定量。(a)中所描述之較急劇(亦即,較突然)改變具有比(b)中所描繪之較不急劇改變短的曲率半徑。圖式之比例使得r 2 =10×r 1 。 Figure 25. Figure 25 is a diagram illustrating the general concept of radius of curvature, which can be applied to the characterization of changes in the flatness of the surface. The degree of sharpness (i.e., suddenness) of the change in surface flatness is quantified by the radius arc r . The sharper (i.e., more abrupt) change described in (a) has a radius of curvature that is shorter than the less sharp change depicted in (b). The ratio of the formula is such that r 2 = 10 × r 1 .
圖26. 圖26為基於單級像素內放大器設計之間接偵測陣列的計算之橫截面圖。(a)此視圖對應於在圖21中顯現之橫截面圖,但經由對該等鈍化層中之一者(鈍化#2)之完全平坦化而達成光電二極體結構的更一致之拓撲。(b)此視圖亦對應於在圖21中顯現之橫截面圖,但經由對鈍化#2之部分平坦化而達成光電二極體結構的更一致之拓撲。 Figure 26. Figure 26 is a cross-sectional view of the calculation of the inter-connected detection array based on a single-stage in-pixel amplifier design. (a) This view corresponds to the cross-sectional view appearing in Figure 21, but achieves a more consistent topology of the photodiode structure via complete planarization of one of the passivation layers (passivation #2). (b) This view also corresponds to the cross-sectional view appearing in FIG. 21, but achieves a more consistent topology of the photodiode structure via partial planarization of passivation #2.
圖27. 圖27為基於兩級像素內放大器設計之間接偵測陣列的計算之橫截面圖。(a)及(b)中之視圖分別對應於在圖22(a)及圖22(b)中顯現之橫截面圖,但經由對該等鈍化層中之一者(鈍化#2)之完全平坦化而達成光電二極體結構的更一致之拓撲。 Figure 27. Figure 27 is a cross-sectional view of the calculation of the inter-connected detection array based on a two-stage in-pixel amplifier design. The views in (a) and (b) correspond to the cross-sectional views appearing in Figures 22(a) and 22(b), respectively, but via one of the passivation layers (passivation #2) Flattening to achieve a more consistent topology of the photodiode structure.
圖28. 圖28為基於單級像素內放大器設計之間接偵測陣列的計算之橫截面圖。此視圖對應於在圖26(a)中顯現之橫截面圖,但經由對光電二極體之底部電極(由金屬#2層形成)之周邊邊緣的平滑化而達成光電二極體結構的更一致之拓撲。 Figure 28. Figure 28 is a cross-sectional view of the calculation of the inter-connect detection array based on a single-stage in-pixel amplifier design. This view corresponds to the cross-sectional view appearing in FIG. 26(a), but achieves a photodiode structure by smoothing the peripheral edge of the bottom electrode (formed by the metal #2 layer) of the photodiode. Consistent topology.
圖29. 圖29為基於兩級像素內放大器設計之間接偵測陣列的計算之橫截面圖。此視圖對應於在圖27(a)中顯現之橫截面圖,但經由對光電二極體之底部電極(由金屬#2層形成)之周邊邊緣的平滑化而達成光電二極體結構的更一致之拓撲。 Figure 29. Figure 29 is a cross-sectional view of the calculation of the inter-connect detection array based on a two-stage in-pixel amplifier design. This view corresponds to the cross-sectional view appearing in FIG. 27(a), but achieves a photodiode structure by smoothing the peripheral edge of the bottom electrode (formed by the metal #2 layer) of the photodiode. Consistent topology.
圖30. 圖30為基於單級像素內放大器設計之間接偵測陣列的計算之橫截面圖。此視圖對應於在圖28中顯現之橫截面圖,但經由對連接光電二極體之底部電極與後部接點之介層孔的窄化及用金屬填充彼等介層孔而達成光電二極體結構的甚至更一致之拓撲。 Figure 30. Figure 30 is a cross-sectional view of the calculation of the inter-connected detection array based on a single-stage in-pixel amplifier design. This view corresponds to the cross-sectional view appearing in FIG. 28, but the photodiode is achieved by narrowing the via holes connecting the bottom electrode and the rear contact of the photodiode and filling the via holes with metal. An even more consistent topology of the volume structure.
圖31. 圖31為單級像素內放大器陣列之在單一像素之區中的俯視圖,其係自計算模擬產生。(a)為對應於圖23(a)中所展示之相同視圖的說明。(b)為對應於(a)中之說明的說明,但經由對該等鈍化層中之一者(鈍化#2)之完全平坦化而達成光電二極體結構的更一致之拓撲。(c)為對應於(b)中之說明的說明,但經由對光電二極體之底部電極之周邊邊緣的平滑化而達成光電二極體結構的更一致之拓撲。(d)為對應於(c)中之說明的說明,但經由對連接光電二極體之底部電極與後部接點之介層孔的窄化及用金屬填充彼等介層孔而達成光電二極體結構的甚至更一致之拓撲。 Figure 31. Figure 31 is a top plan view of a single-pixel in-pixel amplifier array in a single pixel region, generated from a computational simulation. (a) is an explanation corresponding to the same view shown in Fig. 23 (a). (b) is a description corresponding to the description in (a), but achieves a more consistent topology of the photodiode structure via complete planarization of one of the passivation layers (passivation #2). (c) is a description corresponding to the description in (b), but a more uniform topology of the photodiode structure is achieved by smoothing the peripheral edge of the bottom electrode of the photodiode. (d) is the description corresponding to the description in (c), but the photoperiod is achieved by narrowing the via holes connecting the bottom electrode and the rear contact of the photodiode and filling the via holes with metal. An even more consistent topology of the polar body structure.
圖32. 圖32為兩級像素內放大器陣列之在單一像素之區中的俯視圖,其係自計算模擬產生。(a)為對應於圖24(a)中所展示之相同視圖的說明。(b)為對應於(a)中之說明的說明,但經由對該等鈍化層中之一者(鈍化#2)之完全平坦化而達成光電二極體結構的更一致之拓撲。(c)為對應於(b)中之說明的說明,但經由對光電二極體之底部電極之周邊邊緣的平滑化而達成光電二極體結構的更一致之拓撲。(d)為對應於(c)中之說明的說明,但經由對連接光電二極體之底部電極與後部接點之介層孔的窄化及用金屬填充彼等介層孔而達成光電二極體結構的甚至更一致之拓撲。 Figure 32. Figure 32 is a top plan view of a two-stage intra-pixel amplifier array in a single pixel region, generated from a computational simulation. (a) is an explanation corresponding to the same view shown in Fig. 24 (a). (b) is a description corresponding to the description in (a), but achieves a more consistent topology of the photodiode structure via complete planarization of one of the passivation layers (passivation #2). (c) is a description corresponding to the description in (b), but a more uniform topology of the photodiode structure is achieved by smoothing the peripheral edge of the bottom electrode of the photodiode. (d) is the description corresponding to the description in (c), but the photoperiod is achieved by narrowing the via holes connecting the bottom electrode and the rear contact of the photodiode and filling the via holes with metal. An even more consistent topology of the polar body structure.
圖33. 圖33為基於單級像素內放大器設計之間接偵測陣列的計算之橫截面圖。(a)此視圖對應於在圖21中顯現之橫截面圖,但經由對光電二極體中之純質a-Si層之完全平坦化而達成光電二極體結構之頂部電極的更一致之拓撲。(b)此視圖對應於在圖21中顯現之橫截面圖,但經由對光電二極體中之純質a-Si層之部分平坦化而達成光電二極體結構之頂部電極的更一致之拓撲。 Figure 33. Figure 33 is a cross-sectional view of the calculation of the inter-connected detection array based on a single-stage in-pixel amplifier design. (a) This view corresponds to the cross-sectional view appearing in FIG. 21, but achieves a more uniform top electrode of the photodiode structure via complete planarization of the pure a-Si layer in the photodiode. Topology. (b) This view corresponds to the cross-sectional view appearing in FIG. 21, but achieves a more uniform top electrode of the photodiode structure by planarizing a portion of the pure a-Si layer in the photodiode. Topology.
圖34. 圖34為單級像素內放大器陣列之在單一像素之區中的俯視圖,其係自計算模擬產生。(a)為對應於圖23(a)中所展示之相同視圖 的說明。(b)為對應於(a)中之說明的說明,但經由對光電二極體中之純質a-Si層之部分平坦化而達成光電二極體結構的更一致之拓撲。(c)為對應於(b)中之說明的說明,但經由對光電二極體中之純質a-Si層之完全平坦化而達成光電二極體結構的更一致之拓撲。 Figure 34. Figure 34 is a top view of a single-pixel in-pixel amplifier array in a single pixel region, generated from a computational simulation. (a) corresponds to the same view as shown in Figure 23(a) instruction of. (b) is a description corresponding to the description in (a), but achieves a more uniform topology of the photodiode structure by planarizing a portion of the pure a-Si layer in the photodiode. (c) is a description corresponding to the description in (b), but achieves a more consistent topology of the photodiode structure via complete planarization of the pure a-Si layer in the photodiode.
PD‧‧‧光電二極體 PD‧‧‧Photoelectric diode
TFT‧‧‧像素定址電晶體 TFT‧‧‧pixel addressed transistor
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Families Citing this family (96)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9741901B2 (en) * | 2006-11-07 | 2017-08-22 | Cbrite Inc. | Two-terminal electronic devices and their methods of fabrication |
US9991311B2 (en) | 2008-12-02 | 2018-06-05 | Arizona Board Of Regents On Behalf Of Arizona State University | Dual active layer semiconductor device and method of manufacturing the same |
KR101819757B1 (en) * | 2009-06-17 | 2018-01-17 | 더 리젠츠 오브 더 유니버시티 오브 미시간 | Photodiode and other sensor structures in flat-panel x-ray imagers and method for improving topological uniformity of the photodiode and other sensor structures in flat-panel x-ray imagers based on thin-film electronics |
TWI424574B (en) * | 2009-07-28 | 2014-01-21 | Prime View Int Co Ltd | Digital x ray detecting panel and method for manufacturing the same |
RU2426694C1 (en) * | 2010-02-15 | 2011-08-20 | Общество С Ограниченной Ответственностью "Сцинтилляционные Технологии Радиационного Контроля" | Inorganic scintillation material, crystalline scintillator and radiation detector |
KR20120076439A (en) * | 2010-12-29 | 2012-07-09 | 삼성모바일디스플레이주식회사 | X ray detection device |
KR101257699B1 (en) * | 2011-02-07 | 2013-04-24 | 삼성전자주식회사 | Radiation detector and manufacturing method thereof |
US8969779B2 (en) * | 2011-02-11 | 2015-03-03 | Nokia Corporation | Photodetecting structure with photon sensing graphene layer(s) and vertically integrated graphene field effect transistor |
US20120242621A1 (en) * | 2011-03-24 | 2012-09-27 | Christopher James Brown | Image sensor and display device incorporating the same |
JP5875420B2 (en) * | 2011-04-07 | 2016-03-02 | キヤノン株式会社 | Radiation detection element and manufacturing method thereof |
US9347893B2 (en) * | 2011-07-26 | 2016-05-24 | Robert Sigurd Nelson | Enhanced resolution imaging systems for digital radiography |
RU2605518C2 (en) * | 2011-07-28 | 2016-12-20 | Конинклейке Филипс Н.В. | Scintillator for detector based on terbium |
CN103296035B (en) * | 2012-02-29 | 2016-06-08 | 中国科学院微电子研究所 | X-ray flat panel detector and manufacturing method thereof |
CN102790068B (en) * | 2012-07-26 | 2014-10-22 | 北京京东方光电科技有限公司 | Manufacturing method for sensor |
CN102790069B (en) * | 2012-07-26 | 2014-09-10 | 北京京东方光电科技有限公司 | Sensor and manufacturing method thereof |
KR101965259B1 (en) * | 2012-07-27 | 2019-08-08 | 삼성디스플레이 주식회사 | X-ray detector |
US8872120B2 (en) * | 2012-08-23 | 2014-10-28 | Semiconductor Energy Laboratory Co., Ltd. | Imaging device and method for driving the same |
US20150243826A1 (en) * | 2012-08-28 | 2015-08-27 | Northeastern University | Tunable heterojunction for multifunctional electronics and photovoltaics |
US9214782B2 (en) * | 2012-09-11 | 2015-12-15 | The Board Of Trustees Of The Leland Stanford Junior University | Dielectric laser electron accelerators |
DE102013217278B4 (en) | 2012-09-12 | 2017-03-30 | Semiconductor Energy Laboratory Co., Ltd. | A photodetector circuit, an imaging device, and a method of driving a photodetector circuit |
TWI496277B (en) * | 2012-12-03 | 2015-08-11 | Innocom Tech Shenzhen Co Ltd | X-ray detector |
BR112015013392A2 (en) * | 2012-12-12 | 2017-07-11 | Koninklijke Philips Nv | imaging system, and method |
US9773824B2 (en) * | 2012-12-13 | 2017-09-26 | Cbrite Inc. | Active matrix light emitting diode array and projector display comprising it |
US9935152B2 (en) | 2012-12-27 | 2018-04-03 | General Electric Company | X-ray detector having improved noise performance |
KR101919426B1 (en) * | 2013-01-08 | 2018-11-19 | 삼성전자주식회사 | Graphene electronic device and Manufacturing method of the same |
RU2532645C1 (en) | 2013-04-29 | 2014-11-10 | Общество с ограниченной ответственностью "Научно-технический центр "МТ" (ООО "НТЦ-МТ") | Method of forming patterned scintillator on surface of pixelated photodetector (versions) and scintillation detector made using said method (versions) |
KR101520433B1 (en) * | 2013-07-08 | 2015-05-14 | 주식회사 레이언스 | Image sensor and manufacturing method thereof |
TWI587186B (en) * | 2013-07-15 | 2017-06-11 | Ying-Jia Xue | Multi-function display |
US9360564B2 (en) | 2013-08-30 | 2016-06-07 | Semiconductor Energy Laboratory Co., Ltd. | Imaging device |
WO2015038986A1 (en) * | 2013-09-13 | 2015-03-19 | Baek Seung H | Dental x-ray imaging system having higher spatial resolution |
TWI535289B (en) * | 2013-11-22 | 2016-05-21 | 財團法人工業技術研究院 | Method and apparatus for eliminating residual charge in a flat-panel x-ray detector |
US9917133B2 (en) | 2013-12-12 | 2018-03-13 | General Electric Company | Optoelectronic device with flexible substrate |
US9817137B2 (en) * | 2014-01-15 | 2017-11-14 | Sharp Kabushiki Kaisha | Energy ray detector |
US10381224B2 (en) | 2014-01-23 | 2019-08-13 | Arizona Board Of Regents On Behalf Of Arizona State University | Method of providing an electronic device and electronic device thereof |
WO2017034644A2 (en) | 2015-06-09 | 2017-03-02 | ARIZONA BOARD OF REGENTS a body corporate for THE STATE OF ARIZONA for and on behalf of ARIZONA STATE UNIVERSITY | Method of providing an electronic device and electronic device thereof |
US20160013243A1 (en) * | 2014-03-10 | 2016-01-14 | Dpix, Llc | Photosensor arrays for detection of radiation and process for the preparation thereof |
EP3117204B1 (en) | 2014-03-13 | 2021-06-16 | General Electric Company | Curved digital x-ray detector for weld inspection |
WO2015141777A1 (en) * | 2014-03-20 | 2015-09-24 | シャープ株式会社 | Light detection device |
CN106663640B (en) | 2014-05-13 | 2020-01-07 | 代表亚利桑那大学的亚利桑那校董会 | Method of providing an electronic device and electronic device thereof |
KR102349955B1 (en) | 2014-08-06 | 2022-01-11 | 삼성전자주식회사 | Photo sensor comprising multiple detection mode and operation method of the same |
US9520437B2 (en) * | 2014-08-14 | 2016-12-13 | Cbrite Inc. | Flexible APS X-ray imager with MOTFT pixel readout and a pin diode sensing element |
US9515106B2 (en) * | 2014-08-15 | 2016-12-06 | Perkinelmer Holdings, Inc. | Radiation imaging device with metal-insulator-semiconductor photodetector and thin film transistor |
JP2016062997A (en) * | 2014-09-16 | 2016-04-25 | ソニー株式会社 | Image pickup device, solid state image pickup device and electronic device |
KR20160048535A (en) * | 2014-10-24 | 2016-05-04 | 삼성전자주식회사 | X-ray detector and method of manufacturing the same and system comprising X-ray detector and method of operating the same |
EP3038157A1 (en) * | 2014-12-22 | 2016-06-29 | Nokia Technologies OY | Detector structure for electromagnetic radiation sensing |
US9741742B2 (en) | 2014-12-22 | 2017-08-22 | Arizona Board Of Regents, A Body Corporate Of The State Of Arizona, Acting For And On Behalf Of Arizona State University | Deformable electronic device and methods of providing and using deformable electronic device |
US10446582B2 (en) | 2014-12-22 | 2019-10-15 | Arizona Board Of Regents On Behalf Of Arizona State University | Method of providing an imaging system and imaging system thereof |
US9847369B2 (en) | 2015-02-17 | 2017-12-19 | Redlen Technologies, Inc. | High-performance radiation detectors and methods of fabricating thereof |
US10269839B2 (en) * | 2015-03-26 | 2019-04-23 | Carestream Health, Inc. | Apparatus and method using a dual gate TFT structure |
CN104716152B (en) * | 2015-04-01 | 2018-09-14 | 京东方科技集团股份有限公司 | X-ray flat panel detector and preparation method thereof and white insulating materials |
CN104810375B (en) * | 2015-04-28 | 2018-09-04 | 合肥鑫晟光电科技有限公司 | A kind of array substrate and preparation method thereof and a kind of display device |
KR101723438B1 (en) * | 2015-06-16 | 2017-04-06 | 한국원자력연구원 | The radiation detector and method of manufacturing the same |
CN105093259B (en) * | 2015-08-14 | 2018-12-18 | 京东方科技集团股份有限公司 | Ray detector |
US9786856B2 (en) | 2015-08-20 | 2017-10-10 | Dpix, Llc | Method of manufacturing an image sensor device |
ES2778676T3 (en) | 2015-10-28 | 2020-08-11 | Nokia Technologies Oy | An apparatus and associated methods for computed tomography |
JP6700737B2 (en) * | 2015-11-20 | 2020-05-27 | キヤノン株式会社 | Radiation imaging system, signal processing device, and signal processing method for radiation image |
KR102547798B1 (en) | 2015-12-08 | 2023-06-26 | 삼성전자주식회사 | Radiation detector and radiographic apparatus employing the same |
US11137504B2 (en) * | 2016-02-05 | 2021-10-05 | General Electric Company | Tiled radiation detector |
EP3206235B1 (en) * | 2016-02-12 | 2021-04-28 | Nokia Technologies Oy | Method of forming an apparatus comprising a two dimensional material |
CN107134496B (en) * | 2016-02-29 | 2019-05-31 | 昆山工研院新型平板显示技术中心有限公司 | Thin film transistor (TFT) and its manufacturing method, display panel and display device |
KR102567713B1 (en) * | 2016-03-24 | 2023-08-17 | 삼성디스플레이 주식회사 | Thin film transistor array panel and manufacturing method thereof |
CN105789324B (en) * | 2016-04-15 | 2019-05-03 | 京东方科技集团股份有限公司 | Sensor and its manufacturing method, electronic equipment |
WO2017218898A2 (en) | 2016-06-16 | 2017-12-21 | Arizona Board Of Regents On Behalf Of Arizona State University | Electronic devices and related methods |
US9929215B2 (en) | 2016-07-12 | 2018-03-27 | Dpix, Llc | Method of optimizing an interface for processing of an organic semiconductor |
US10125312B2 (en) | 2016-09-06 | 2018-11-13 | Ut-Battelle, Llc | Divalent-ion-doped single crystal alkali halide scintillators |
US9947704B1 (en) * | 2016-10-18 | 2018-04-17 | Cbrite Inc. | Method of recovery of MOTFT backplane after a-Si photodiode fabrication |
AU2017367615B9 (en) * | 2016-11-30 | 2022-06-16 | The Research Foundation For The State University Of New York | Hybrid active matrix flat panel detector system and method |
US10366674B1 (en) | 2016-12-27 | 2019-07-30 | Facebook Technologies, Llc | Display calibration in electronic displays |
CN106684199B (en) * | 2017-02-13 | 2018-04-03 | 中北大学 | The ultrafast detecting structure of metal micro-nano superstructure surface phasmon |
CN114252902A (en) * | 2017-04-24 | 2022-03-29 | 睿生光电股份有限公司 | Sensing device |
JP7150415B2 (en) * | 2017-04-27 | 2022-10-11 | コーニンクレッカ フィリップス エヌ ヴェ | Medical device for magnetic resonance imaging guided radiation therapy |
CN107219698B (en) * | 2017-06-13 | 2020-04-03 | 京东方科技集团股份有限公司 | Display panel and display device |
KR20200083433A (en) | 2017-08-03 | 2020-07-08 | 더 리서치 파운데이션 포 더 스테이트 유니버시티 오브 뉴욕 | Dual-screen digital radiography with asymmetric reflective screen |
WO2019084701A1 (en) * | 2017-10-30 | 2019-05-09 | Shenzhen Xpectvision Technology Co., Ltd. | Image sensor based on charge carrier avalanche |
KR102552845B1 (en) * | 2017-12-19 | 2023-07-06 | 엘지디스플레이 주식회사 | X-ray detector |
US10797193B2 (en) * | 2018-01-23 | 2020-10-06 | Lumentum Operations Llc | Bias control structure for avalanche photodiodes |
US10684555B2 (en) * | 2018-03-22 | 2020-06-16 | Applied Materials, Inc. | Spatial light modulator with variable intensity diodes |
CN110398767B (en) * | 2018-04-25 | 2020-11-10 | 中国科学院高能物理研究所 | Ray detection circuit |
CN112020328A (en) * | 2018-04-26 | 2020-12-01 | 瓦里安医疗系统公司 | Image forming apparatus |
US11016202B2 (en) | 2018-04-26 | 2021-05-25 | Varian Medical Systems, Inc. | Imaging devices |
US10444378B1 (en) * | 2018-04-27 | 2019-10-15 | Varian Medical Systems, Inc. | Imaging devices |
US10627530B2 (en) * | 2018-05-07 | 2020-04-21 | Ka Imaging Inc. | Method and apparatus for a high resolution, high speed radiation imaging |
JP2019220685A (en) | 2018-06-19 | 2019-12-26 | シャープ株式会社 | Radiation detector |
US10418408B1 (en) * | 2018-06-22 | 2019-09-17 | Omnivision Technologies, Inc. | Curved image sensor using thermal plastic substrate material |
CN110660816B (en) | 2018-06-29 | 2022-06-10 | 京东方科技集团股份有限公司 | Flat panel detector |
CN109742178B (en) * | 2019-01-29 | 2020-07-17 | 西安工业大学 | Infrared-transmitting high-sensitivity visible light detector and preparation method thereof |
CN110031883B (en) * | 2019-03-05 | 2022-06-07 | 中国辐射防护研究院 | High ionizing radiation dose sensor based on wireless capacitance |
CN113614575B (en) * | 2019-03-29 | 2023-11-28 | 深圳帧观德芯科技有限公司 | Radiation detector with scintillator |
US10910432B1 (en) * | 2019-07-23 | 2021-02-02 | Cyber Medical Imaging, Inc. | Use of surface patterning for fabricating a single die direct capture dental X-ray imaging sensor |
US11551777B2 (en) | 2019-08-09 | 2023-01-10 | Micron Technology, Inc. | Apparatus with circuit-locating mechanism |
US11378701B2 (en) | 2019-10-08 | 2022-07-05 | Redlen Technologies, Inc. | Low dark current radiation detector and method of making the same |
US11086032B1 (en) * | 2020-03-04 | 2021-08-10 | Prismatic Sensors Ab | Edge-on X-ray detector |
US11733408B2 (en) | 2020-04-28 | 2023-08-22 | Redlen Technologies, Inc. | High-performance radiation detectors and methods of fabricating thereof |
CN112133717B (en) * | 2020-09-24 | 2024-03-29 | 京东方科技集团股份有限公司 | Detection substrate and ray detector |
FR3119708B1 (en) * | 2021-02-11 | 2023-08-25 | Trixell | Digital detector with superimposed conversion stages |
JP2022167161A (en) * | 2021-04-22 | 2022-11-04 | シャープディスプレイテクノロジー株式会社 | X-ray imaging panel and method for fabricating the same |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5262649A (en) * | 1989-09-06 | 1993-11-16 | The Regents Of The University Of Michigan | Thin-film, flat panel, pixelated detector array for real-time digital imaging and dosimetry of ionizing radiation |
US6288388B1 (en) * | 1997-09-26 | 2001-09-11 | Semiconductor Energy Laboratory Co., Ltd. | Photoelectric converter wherein the lower electrode has bends |
Family Cites Families (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6045057A (en) * | 1983-08-23 | 1985-03-11 | Toshiba Corp | Manufacture of solid-state image pickup device |
CA2065246C (en) | 1989-09-06 | 2001-11-13 | Larry E. Antonuk | Multi-element-amorphous-silicon-detector-array for real-time imaging and dosimetry of megavoltage photons and diagnostic x-rays |
CA2034118A1 (en) | 1990-02-09 | 1991-08-10 | Nang Tri Tran | Solid state radiation detector |
US5057892A (en) * | 1990-09-14 | 1991-10-15 | Xsirius Photonics, Inc. | Light responsive avalanche diode |
EP0546779A1 (en) * | 1991-12-13 | 1993-06-16 | Shimadzu Corporation | Oxynitride glass fiber for composite products, and glass fiber-reinforced products |
JPH06314779A (en) * | 1993-04-28 | 1994-11-08 | Nec Corp | Image sensor |
JPH08250698A (en) * | 1995-03-14 | 1996-09-27 | Toshiba Corp | Solid-stat image sensor |
JP3957803B2 (en) | 1996-02-22 | 2007-08-15 | キヤノン株式会社 | Photoelectric conversion device |
JPH1093062A (en) * | 1996-09-11 | 1998-04-10 | Toshiba Corp | Photodetector |
JP3838806B2 (en) * | 1999-03-26 | 2006-10-25 | 株式会社東芝 | Signal multiplication X-ray imaging device |
JP3984808B2 (en) | 2000-09-07 | 2007-10-03 | キヤノン株式会社 | Signal processing apparatus, imaging apparatus using the same, and radiation imaging system |
US6891194B2 (en) * | 2001-02-07 | 2005-05-10 | Sharp Kabushiki Kaisha | Active matrix substrate, electromagnetic detector, and liquid crystal display apparatus |
US6730914B2 (en) * | 2002-02-05 | 2004-05-04 | E-Phocus, Inc. | Photoconductor-on-active-pixel (POAP) sensor utilizing equal-potential pixel electrodes |
JP4147094B2 (en) | 2002-11-22 | 2008-09-10 | キヤノン株式会社 | Radiation imaging apparatus and radiation imaging system |
JP3621400B2 (en) | 2003-03-03 | 2005-02-16 | 松下電器産業株式会社 | Solid-state imaging device and manufacturing method thereof |
US7279353B2 (en) | 2003-04-02 | 2007-10-09 | Micron Technology, Inc. | Passivation planarization |
JP4683836B2 (en) * | 2003-12-12 | 2011-05-18 | 株式会社神戸製鋼所 | Diamond semiconductor device and manufacturing method thereof |
JP2006156555A (en) * | 2004-11-26 | 2006-06-15 | Toshiba Corp | X-ray plane detector |
JP2006017742A (en) * | 2005-08-24 | 2006-01-19 | Canon Inc | Device for detecting radiation |
JP4498283B2 (en) * | 2006-01-30 | 2010-07-07 | キヤノン株式会社 | Imaging apparatus, radiation imaging apparatus, and manufacturing method thereof |
JP5109686B2 (en) * | 2007-06-22 | 2012-12-26 | セイコーエプソン株式会社 | Detection device and electronic device |
JP2009010075A (en) * | 2007-06-27 | 2009-01-15 | Fujifilm Corp | Radiation image detector |
JP2009038123A (en) * | 2007-07-31 | 2009-02-19 | Fujifilm Corp | Image detecting apparatus |
JP2009047577A (en) * | 2007-08-21 | 2009-03-05 | Konica Minolta Medical & Graphic Inc | Scintillator panel and its manufacturing method |
JP5489423B2 (en) * | 2007-09-21 | 2014-05-14 | 富士フイルム株式会社 | Radiation imaging device |
JP2010186723A (en) | 2009-02-13 | 2010-08-26 | Fujifilm Corp | Organic el device and method of manufacturing the same |
KR101819757B1 (en) * | 2009-06-17 | 2018-01-17 | 더 리젠츠 오브 더 유니버시티 오브 미시간 | Photodiode and other sensor structures in flat-panel x-ray imagers and method for improving topological uniformity of the photodiode and other sensor structures in flat-panel x-ray imagers based on thin-film electronics |
-
2010
- 2010-06-16 KR KR1020127001362A patent/KR101819757B1/en active IP Right Grant
- 2010-06-16 WO PCT/US2010/038777 patent/WO2010148060A1/en active Application Filing
- 2010-06-16 JP JP2012516229A patent/JP5744861B2/en active Active
- 2010-06-16 CA CA2765702A patent/CA2765702A1/en not_active Abandoned
- 2010-06-16 CN CN201610942592.8A patent/CN107425020B/en active Active
- 2010-06-16 ES ES18197740T patent/ES2880357T3/en active Active
- 2010-06-16 EP EP10790100.1A patent/EP2443656B1/en active Active
- 2010-06-16 ES ES10790100T patent/ES2710101T3/en active Active
- 2010-06-16 EP EP18197740.6A patent/EP3447802B1/en active Active
- 2010-06-17 US US12/817,634 patent/US8492728B2/en active Active
- 2010-06-17 TW TW104135939A patent/TWI615956B/en active
- 2010-06-17 TW TW099119799A patent/TWI520315B/en active
-
2013
- 2013-07-01 US US13/932,519 patent/US8754379B2/en active Active
-
2014
- 2014-05-12 US US14/275,476 patent/US20140246596A1/en not_active Abandoned
-
2015
- 2015-04-16 US US14/477,960 patent/US9395453B2/en active Active
-
2016
- 2016-07-18 US US15/213,390 patent/US9880296B2/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5262649A (en) * | 1989-09-06 | 1993-11-16 | The Regents Of The University Of Michigan | Thin-film, flat panel, pixelated detector array for real-time digital imaging and dosimetry of ionizing radiation |
US6288388B1 (en) * | 1997-09-26 | 2001-09-11 | Semiconductor Energy Laboratory Co., Ltd. | Photoelectric converter wherein the lower electrode has bends |
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EP3447802B1 (en) | 2021-04-21 |
ES2710101T3 (en) | 2019-04-23 |
KR101819757B1 (en) | 2018-01-17 |
US20140246596A1 (en) | 2014-09-04 |
US20130292573A1 (en) | 2013-11-07 |
JP5744861B2 (en) | 2015-07-08 |
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ES2880357T3 (en) | 2021-11-24 |
TW201119021A (en) | 2011-06-01 |
US8754379B2 (en) | 2014-06-17 |
JP2012531046A (en) | 2012-12-06 |
TWI520315B (en) | 2016-02-01 |
US20170045629A1 (en) | 2017-02-16 |
TW201605034A (en) | 2016-02-01 |
US8492728B2 (en) | 2013-07-23 |
EP2443656A4 (en) | 2013-11-20 |
CA2765702A1 (en) | 2010-12-23 |
CN107425020B (en) | 2019-10-18 |
US20100320391A1 (en) | 2010-12-23 |
US9395453B2 (en) | 2016-07-19 |
EP2443656B1 (en) | 2018-11-07 |
CN102576715A (en) | 2012-07-11 |
EP3447802A1 (en) | 2019-02-27 |
EP2443656A1 (en) | 2012-04-25 |
WO2010148060A1 (en) | 2010-12-23 |
KR20120027541A (en) | 2012-03-21 |
CN107425020A (en) | 2017-12-01 |
US9880296B2 (en) | 2018-01-30 |
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