TWI615956B - Radiation sensor and method for fabricating the same - Google Patents

Abstract

A radiation sensor includes: a scintillation layer configured to emit photons when interacting with ionizing radiation; and a photodetector including a first electrode, a photosensitive layer, and close in order A second electrode capable of transmitting photons is disposed in the scintillation layer. The photosensitive layer is configured to create an electron hole pair when interacting with a portion of the photons. The radiation sensor includes: a pixel circuit electrically coupled to the first electrode and configured to measure an imaging signal indicative of one of the pairs of electron holes generated in the photosensitive layer; and a planarization layer And disposed between the first electrode and the pixel circuit on the pixel circuit such that the first electrode is higher than a plane including the pixel circuit. A surface of at least one of the first electrode and the second electrode at least partially overlaps the pixel circuit and has a surface recursion higher than one of the features of the pixel circuit. The surface recursion has a radius of curvature greater than 1/2 micron.

Description

Radiation sensor and its preparation method

The present invention generally relates to devices designed to detect incident ionizing radiation to form an image.

This application is related to the following application and claims the priority of the following application in accordance with the provisions of 35 USC119: "PHOTODIODE AND OTHER SENSOR STRUCTURES IN FLAT-PANEL X-RAY IMAGERS AND METHOD FOR" IMPROVING TOPOLOGICAL UNIFORMITY OF THE PHOTODIODE AND OTHER SENSOR STRUCTURES IN FLAT-PANEL X-RAY IMAGERS BASED ON THIN-FILM ELECTRONICS, US Provisional Patent Application No. 61/213, 530, the entire disclosure of which is hereby incorporated by reference. in.

Narrative about federally funded research or development

This invention was made with government support under EB000558 awarded by the National Institutes of Health . The U.S. Government has certain rights in the invention.

In the field of x-ray imaging, imagers based on active matrix imaging arrays are commonly used in many medical and non-medical applications. Unless otherwise indicated herein, the term " active matrix " will be used to refer to the principle of addressing a two-dimensional grid of imaging pixels by means of switches, with a positional switch in each pixel. An imager based on an active matrix imaging array will be referred to as an " active matrix planar panel imager " (AMFPI) or, more simply, as an " active matrix imager. " In addition, the terms " active matrix array " and " active matrix imaging array " will be used interchangeably.

AMFPI usually has a single array, including materials that are highly resistant to the effects of ionizing radiation. However, AMFPI sometimes includes two adjacent arrays arranged side by side, or four adjacent arrays arranged in a square or rectangular shape. One reason for the versatility and usefulness of active matrix imagers is that they can be manufactured with acceptable yields and at reasonable cost, significantly beyond the size that can be achieved with conventional crystalline 矽 (c-Si) technology. . In the case of c-Si technology, pixelated imaging arrays (such as charge-coupled devices (CCDs), CMOS sensors, active pixel sensors, and passive pixel sensors) are ultimately used in manufacturing wafers. The size (currently up to about 300mm) is limited. CCDs, CMOS sensors and active pixel sensors and passive pixel sensors made of crystalline germanium are typically fabricated to have dimensions of less than about 4 cm x 4 cm. While these devices have been fabricated to have dimensions up to about 20 cm x 20 cm, such devices are difficult to produce and costly to produce. Also, while large area devices can be fabricated by tiling small area c-Si arrays, this approach introduces additional significant engineering issues, challenges, and costs. In the case of AMFPI, although the active matrix array can be as small as two pixels x two pixels (which will be less than 1 cm x 1 cm), the active matrix array for AMFPI typically ranges from about 10 cm x 10 cm up to about 43 cm. Manufactured in the range of ×43 cm, which greatly exceeds the range of pixelated c-Si imaging arrays. In addition, there is no ban on the generation of even larger active matrix imaging arrays (eg, equivalent to the largest active matrix liquid crystal display (AMLCD) size, the largest active matrix liquid crystal display has been fabricated to be on the diagonal up to about 108吋) Technical reasons.

In an active matrix imaging array, a two-dimensional grid of imaging pixels is addressed by means of a membrane switch. The array includes a thin substrate on which imaging pixels are fabricated. Each pixel has a circuit in which the address switch is connected to some form of pixel storage capacitor. Each switch is usually in the form of a thin film transistor (TFT), but can also be used as a thin film. A form of a diode or a combination of two or more thin film diodes. While a simple array design has only a single switch per pixel for addressing purposes, a more complex design can include additional circuit components in the pixel to improve performance and/or extend the imager. ability. In addition, other circuit components can be placed on the array substrate outside of the pixels. These components can be configured to perform functions such as controlling the voltage on the gate address line, multiplexing the signal from the data line, or for other purposes related to the operation of the array.

Materials used in array fabrication include various metals used to form features such as address lines, contacts to address lines, traces, via holes, electrode surfaces and light blocking surfaces, and TFTs. Source, drain and gate. Metals such as aluminum, copper, chromium, molybdenum, niobium, titanium, tungsten, indium tin oxide, and gold, and alloys of such materials, such as TiW, MoCr, and AlCu, can be used. The thickness of a given metal layer deposited onto the array during fabrication can range from about 10 nm to several μm. The passivation layer may include materials such as bismuth oxynitride (Si ₂ N ₂ O), cerium nitride (Si ₃ N ₄ ), polyimine, and benzocyclobutene polymer (BCB). The thickness of a given passivation layer deposited onto the surface of the array during fabrication can range from about 100 nm up to 10 μm. Dielectrics in devices such as TFTs and capacitors may include, for example, tantalum nitride (Si ₃ N ₄ ), hafnium oxide (SiO ₂ ), amorphous germanium, and amorphous germanium nitride (a-Si ₃ N _{4 ).} :H) Material. The thickness of a given dielectric layer deposited onto the surface of the array during fabrication can range from about 1 nm to several μm. Typically, multiple metal layers, passivation layers, and dielectric layers are used to fabricate the various circuit elements in an array.

The semiconductor material used for TFT (and diode switching) is most usually hydrogenated amorphous germanium (a-Si), but may also be microcrystalline germanium, polycrystalline germanium (polycrystalline-Si), chalcogenide or cadmium selenide ( CdSe), all of these materials are suitable for large area processing, allowing for the fabrication of large area arrays. In this case, the substrate may be made of a material such as glass (such as Corning 7059, 1737F, 1737G, about 1 mm thick), or quartz (about 1 mm thick), or stainless steel sheet (about 25 to 500 μm thick). The manufacture of array circuits involves the following operations: use Area deposition techniques deposit a continuous layer of material (such as a semiconductor layer, a metal layer, a dielectric layer, and a passivation layer) on a substrate, and regional deposition techniques such as plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD) , chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering and spin coating. In the case of poly-Si, a common method for producing such a semiconductor is to crystallize the previously deposited a-Si material by means of an excimer laser. In addition, the combination of photolithography and etching techniques is used to form features of the circuit (such as TFTs, diodes, photodiodes, capacitors, traces, vias, address lines, and contacts to the address lines). And other features).

Alternatively, the semiconductor materials used for such switches may take the form of other materials suitable for large area deposition, such as low temperature a-Si, organic small molecules or polymer semiconductors. Low temperature a-Si is deposited using PECVD, LPCVD, and PVD, while organic small molecules and polymer semiconductors can be deposited using either regional deposition techniques or printing techniques. For such semiconductor materials, the substrate can be thin and flexible (made of a sheet of material such as polyimine (PI) or polyethylene naphthalate (PEM, about 25 to 200 μm thick)). Alternatively, a glass, quartz or stainless steel substrate can be used. One or a combination of photolithography, etching, subtractive printing, and additive printing techniques can be used to form the features of the array circuitry. Other semiconductor materials that can be used for both TFTs and other devices include carbon nanotubes and graphite films. Other semiconductor materials that can be used for both TFTs and other devices include oxide semiconductors including, but not limited to, ZnO, InGaZnO, InZnO, ZnSnO (and any other Zn-containing oxide), SnO ₂ , TiO ₂ , Ga ₂ O ₃ , InGaO, In ₂ O ₃ and InSnO. These oxide semiconductors are known to exist as amorphous or polycrystalline and are suitable for use in the present invention when available. For all types of semiconductors, materials are used in their pure form and in doped form to provide p-type doped or n-type doped semiconductor materials.

The TFT has a gate, a source, and a drain. The magnitude of the current flowing between the source and the drain through the TFT's semiconductor channel is controlled by a number of factors such as the width and length of the TFT channel, the mobility of the semiconductor used in the channel, and the application to the gate. Electricity between sources The magnitude and polarity of the voltage, and the voltage difference between the source and the drain. Manipulation of the voltage applied to the gate allows the transistor to be highly conductive (described as "on") or highly non-conductive (depicted as "off").

1 to 4 show examples of a-Si and poly-Si TFTs. Fig. 1 is a schematic view showing the structure of one form of an a-Si TFT. Figure 2 is a schematic cross-sectional view corresponding to the position of the plane indicated by the wire frame in Figure 1. The symmetry of the structure of the a-Si TFT is such that the cross-sectional view will remain largely unchanged for any position of the wireframe along the width of the transistor. Fig. 3 is a schematic view showing the structure of one form of a polycrystalline-Si TFT. The version shown has a single gate, but two or more gates are also possible. Figure 4 is a schematic cross-sectional view corresponding to the position of the plane indicated by the wire frame in Figure 3. Compared with the a-Si TFTs illustrated in FIGS. 1 and 2, the poly-Si TFTs illustrated in FIGS. 3 and 4 have a lower degree of symmetry due to the presence of via holes, so that for the wire frame At other locations along the width of the transistor, the cross-sectional view of the transistor will vary significantly.

An active matrix imager typically includes: (a) an active matrix imaging array; (b) a layer of material overlying the array for use as an x-ray converter; (c) an external electronic device that is positioned by a data address The contact pads at the ends of the line and gate address lines are connected to the array. Some of these electronic devices are positioned in close proximity to the perimeter of the array and provide digital logic that assists in controlling the voltage and timing necessary to operate the array, as well as amplification, multiplexing, and digitization along the data. The analog signal extracted from the pixel by the address line. The electronic devices also include voltage supplies required to operate the array and peripheral electronics, and digital electronic interfaces to allow communication between the electronic devices and one or more computers; (d) one or more computers Transmitting control information to the electronic devices, receiving digital pixel information from the electronic devices, synchronizing the operation of the array with the delivery of radiation from the x-ray source, and processing, displaying, and storing the imaging information; e) software, firmware and other coded instructions for use in the digital logic of such computers and of such electronic devices.

The array substrate, the thin film electronic device, and the x-ray converter are all relatively thin, and the combined thickness is less than 1 cm. This allows these components to be configured in a package along with peripheral electronics having a compact thickness of about 1 cm, similar to the thickness of a standard x-ray film cassette or computer radiography (CR) sheet. Electronic x-ray imagers with such contours are often referred to as planar panel imagers (FPIs), regardless of the technology on which the imager is based. In contrast to planar panel imagers produced in accordance with other technologies, such as tiled CMOS sensors, the descriptive term broadly associated with film-based electronic device-based imagers is the " film flat panel imager. " In the specific case of an imager using an active matrix array, the term " active matrix flat panel imager (AMFPI) " is appropriate.

The pixels used in the active matrix imaging array are arranged in columns and rows. For arrays using TFT switches, and for a given column of pixels, the gates of all of the addressed TFTs along the column are connected to a common gate address line, with each pixel column having a gate line. External manipulation of the voltage applied to each gate address line thus allows control of the conductivity of all of the addressed TFTs along the column. For a given row of pixels, the drains of all of the addressed TFTs along the row are connected to a common data address line, with each pixel row having a data address line.

During operation of the AMFPI, all of the addressed TFTs remain non-conducting during x-ray delivery to allow imaging signals to be collected in the pixel storage capacitor. The imaging signals stored in these capacitors are typically read out one pixel column at a time by conducting the addressed TFTs in the columns. This allows the imaging signal to be sampled from the corresponding data address line with full spatial resolution of the array. For a given data address line, each sampled signal is amplified by a preamplifier and digitized by an analog to digital converter, both preamplifiers and analog to digital converters being positioned external to the array. Of course, the imaging signal can be sampled from two or more consecutive columns at a time, which reduces readout time, but at the expense of reduced spatial resolution.

Active matrix imagers are most commonly operated in conjunction with x-ray sources, but they can also operate with other forms of ionizing radiation sources such as gamma rays, electrons, protons, neutrons, Alpha particles, and heavy ions. The pixel pitch of the array (which is equal to the width of one pixel) and the size, the frame rate of the array and imager, and the beam energy, filtering, and time characteristics of the x-ray source are all selected to match the needs of the imaging application. For many forms of breast imaging applications (including mammography, breast tomosynthesis, mammography, and image-guided tissue sectioning), arrays with pixel pitches of from about 25 [mu]m up to about 200 [mu]m and x of about 15 to 40 kVp can be used. Light beams are used to perform diagnostic and interventional medical imaging. For many forms of radiography, fluoroscopy and tomography applications (including chest imaging, chest tomosynthesis, dual energy imaging, angiography, interventional therapy, tissue sectioning, limb imaging, pediatric imaging, cardiac imaging) , abdomen, chest, head, neck, conical beam computed tomography of the teeth, and simulation, positioning, confirmation and quality assurance in radiotherapy), and arrays having a pixel pitch of about 75 μm up to about 1000 μm and Diagnostic and interventional medical imaging is performed with an x-ray beam of approximately 50 to 150 kVp. In addition, medical imaging can be performed with a pixel pitch of about 300 [mu]m up to about 1000 [mu]m and a therapeutic beam for external beam radiation therapy. In this case, the source may be a Co-60 source (average energy of about 1.25 MeV), or an output from a linear accelerator or any other type of accelerator that produces millions of volts of radiation in the range of about 3 up to 50 MV. Medical imaging using an active matrix imager, such as cesium-137 ( ¹³⁷ Cs), iodine-125 ( ^125I ), cesium-192 ( ¹⁹² Ir), palladium-103 (can also be performed with a brachytherapy source) ¹⁰³ Pd), 锶-90 ( ⁹⁰ Sr) and 钇-90 ( ⁹⁰ Y). Additionally, non-medical applications, such as industrial radiography, use active matrix imagers in conjunction with all of the sources described above and sources that provide x-ray energy in the range of a few kVp up to about 15 kVp. The design and capabilities of the x-ray converters and associated electronics of the planar panel imager are matched to the array design, mode of operation, and the needs of various non-medical applications.

Based on the way the converter detects x-rays, imagers based on active matrix arrays can be roughly divided into two categories: indirect detection and direct detection . For an indirect detection imager , some of the incident x-ray energy that interacts with the converter is first converted to visible light, and a portion of the photons are then converted into electrical signals stored in a pixel storage capacitor of the array. For direct detection of the imager , some of the incident x-ray energy that interacts with the converter is directly converted into an electrical signal stored in the pixel storage capacitor.

For indirect detection of an imager, the converter takes the form of a scintillator. For many applications, doped yttrium iodide (written as CsI:Tl or CsI:Tl ⁺ , usually grown to form structures with aligned needle crystals), or doped yttrium oxysulfide (writing) Gd ₂ O ₂ S: Tb or Gd ₂ O ₂ S: Tb ³⁺ , also known as GOS, usually in the form of a powder phosphor screen). However, other scintillators are also possible, such as sodium-doped cesium iodide (written as CsI:Na or CsI:Na ⁺ ), cesium iodide (written as NaI:Tl or NaI:Tl ⁺ ), tungsten Calcium acid (CaWO ₄ ), zinc tungstate (ZnWO ₄ ), cadmium tungstate (CdWO ₄ ), bismuth ruthenate (Bi ₄ Ge ₃ O ₁₂ , also known as BGO), yttrium yttrium orthosilicate (Writing Lu _1.8 Yb _0.2 SiO ₅ :Ce or Lu _1.8 Yb _0.2 SiO ₅ :Ce ³⁺ , also known as LYSO), and ytterbium ytterbium ytterbium (written as Gd ₂ SiO ₅ :Ce or Gd ₂ SiO ₅ : Ce ³⁺ , also known as GSO). Other scintillators are possible, such as BaFCl:Eu ²⁺ , BaSO ₄ :Eu ²⁺ , BaFBr:Eu ²⁺ , LaOBr:Tb ³⁺ , LaOBr:Tm ³⁺ ,La ₂ O ₂ S:Tb ³⁺ ,Y ₂ O ₂ S: Tb ³⁺ , YTaO ₄ , YTaO ₄ : Nb, ZnS: Ag, (Zn, Cd) S: Ag, ZnSiO ₄ : Mn ²⁺ , CsI, LiI: Eu ²⁺ , PbWO ₄ , Bi ₄ Si ₃ O ₁₂ , Lu ₂ SiO ₅ :Ce ³⁺ , YAlO ₃ :Ce ³⁺ , CsF, CaF ₂ :Eu ²⁺ , BaF ₂ , CeF ₃ , Y _1.34 Gd _0.6 O ₃ :Eu ³⁺ , Pr, Gd ₂ O ₂ S: Pr ³⁺ , Ce, SCG1, HFG: Ce ³⁺ (5%) and C ₁₄ H ₁₀ . For many types of scintillator materials (such as CsI:Tl, BGO, and LYSO), the converter can take the form of a segmented detector, in the segmented detector, the individual components of the scintillator material (each The individual components have a cross-sectional area substantially equal to or less than the pixel pitch of the imaging array (or a multiple of the pixel pitch of the array) assembled with the intermediate partition material that separates the components to form a region detector The medial wall material provides optical isolation between the elements, thereby maintaining spatial resolution.

A layer of material (referred to as an encapsulation or encapsulation layer) can be deposited to form the top layer of the scintillator to mechanically and chemically protect the scintillator.

For indirect detection of AMFPI, the pixel storage capacitor takes the form of an optical sensor, such as a photodiode or a metal-insulated semiconductor (MIS) structure. These optical sensors are usually There is also an a-Si semiconductor, which is a material that is well suited for imaging of ionizing radiation due to the fact that the signal, noise and dark current properties of the a-Si sensor are only very weakly affected by extremely high radiation doses. The properties of TFTs based on a-Si and poly-Si are also only weakly affected by extremely high radiation doses, making these TFTs extremely suitable for imaging of ionizing radiation.

One form of the structure of the a-Si photodiode includes a bottom electrode (which is connected to the source of the addressed TFT), a doped layer (n ⁺ type doped a-Si, about 10 to 500 nm thick and preferably about 50 to 100 nm thick), pure a-Si layer (preferably about 0.5 to 2.0 μm thick), second doped layer (p ⁺ type doped a-Si, about 10 to 500 nm thick and preferably about 5 to 20 nm thick) And a top electrode made of a material that is transparent to visible light, such as indium tin oxide, ITO. In an alternative form of the a-Si photodiode structure, the doping of the upper a-Si layer and the lower a-Si layer are interchangeable. Minimizing the thickness of the top doped a-Si layer reduces the fraction of visible light absorbed in this layer, thereby helping to maximize the imaging signal recorded in the pixel.

An example of a pixel circuit for an indirect detection, active matrix imaging array is schematically illustrated in FIG. The circuit components depicted in this figure include a photodiode (PD) and a pixel addressed transistor (TFT). The source, drain and gate of the TFT surrounded by the dashed oval are marked. The second dashed oval emphasizes that the photodiode, which is an optical sensor of a pixel, is also used as a pixel storage capacitor having a capacitance C _PD . Gate address lines and data address lines corresponding to the columns and rows of pixels depicted are also shown. The magnitude of the reverse bias voltage applied to the top electrode of the photodiode is V _BIAS . This voltage is provided by an external voltage supply. V _BIAS is typically set to a value in the range of about 1V to 8V.

6 is a schematic cross-sectional illustration of a structural implementation of a pixel design corresponding to the pixel circuit of FIG. 5, the implementation of which is referred to as a baseline architecture . In this implementation, the addressed TFT shares the surface area of the pixel with a number of other components, including discrete a-Si photodiodes having a stacked structure, address lines, and address lines, photodiodes, and TFTs. The gap between them.

。憑藉金屬介層孔而連接至TFT之汲極的資料位址線及偏壓線之方向與圖式平面正交。藉由陰影示意性地指示鈍化材料之大致位置。此包括沈積於陣列之整個頂面上以便囊封陣列之鈍化材料，從而以機械方式保護陣列且防止與偏壓線及資料位址線的非意欲之電接觸。亦描繪閃爍器之形式的x光轉換器，該閃爍器在整個陣列之上延伸。入射x光(波狀箭頭)在閃爍器中產生可見光子(筆直的、暗淡箭頭)。一些可見光子進入光電二極體之純質層中，產生由於電場而朝向電極漂移之電子及電洞，藉此產生儲存於像素中且最終自像素讀出之成像信號。 In Fig. 6, the general position of the a-Si addressed transistor (TFT) is indicated by a dashed oval (only the drain, source and gate are illustrated). The bottom gate of the photodiode is formed by an extension of the metal used to form the source of the TFT. The remaining layers of the photodiode (which do not overlap the TFT) are patterned such that they align with the edges of the bottom electrode and form a stacked structure in this manner. These layers include an n ⁺ -type doped a-Si layer, a pure a-Si layer, a p ⁺ -type doped a-Si layer, and an ITO layer used as an optically transparent top electrode. Applying a reverse bias voltage of V _BIAS to the top electrode of the photodiode by means of a bias line, thereby generating an electric field across the photodiode

. The direction of the data address line and the bias line connected to the drain of the TFT by the via hole is orthogonal to the plane of the drawing. The approximate location of the passivation material is schematically indicated by the shading. This includes depositing a passivation material over the entire top surface of the array to encapsulate the array, thereby mechanically protecting the array and preventing unintended electrical contact with bias lines and data address lines. An x-ray converter in the form of a scintillator is also depicted that extends over the entire array. Incident x-rays (wavy arrows) produce visible light (straight, dim arrows) in the scintillator. Some of the visible light ions enter the pure layer of the photodiode, producing electrons and holes that drift toward the electrode due to the electric field, thereby producing an imaging signal that is stored in the pixel and ultimately read out from the pixel.

For a direct detection, active matrix planar panel imager, the transducer can take the form of a layer of photoconductive material having a thickness sufficient to stop most of the incident x-rays. A suitable photoconductive material is amorphous selenium a-Se, which can be fabricated up to about 2000 [mu]m thick, and is preferably fabricated to have a thickness in the range of from about 200 to 1000 [mu]m. Other photoconductive materials suitable as direct detection converters include single crystal and polycrystalline lead iodide (PbI ₂ ), mercury iodide (HgI ₂ ), lead oxide (PbO), and cadmium zinc telluride (CdZnTe). , cadmium telluride (CdTe), Bi ₂ S ₃ , Bi ₂ Se ₃ , BiI ₃ , BiBr ₃ , CdS, CdSe, HgS, Cd ₂ P ₃ , InAs, InP, In ₂ S ₃ , In ₂ Se ₃ , Ag ₂ S, PbI ₄ ^-2 and Pb ₂ I ₇ ^-3 . The choice of the thickness of the photoconductor increases as the x-ray energy increases to achieve a reasonably large fraction of x-ray conversion, which may be between about 10% and 90% (at diagnostic energy) and about 1%. Any value within the range of 10% (under radiotherapy energy).

In the case of imaging with millions of volts of radiation (eg, extracorporeal radiotherapy imaging or industrial radiography, including scanning for safety applications), a thin (about 1 mm) metal plate is typically positioned over the transducer (for Indirect detection, directly on the scintillator, or for direct detection, directly on the envelope overlying the top electrode of the photoconductor). The composition of the board can take many forms including copper, steel, tungsten and lead. An example of a pixel circuit for a direct detection, active matrix imaging array is schematically illustrated in FIG. The circuit components depicted in this figure include a photoconductor (PC), a pixel addressed transistor (TFT), and a pixel storage capacitor having a capacitance C _STORAGE (as indicated by the dashed oval). The source, drain and gate of the TFT surrounded by another dashed ellipse are marked. The third dashed ellipse emphasizes that the photoconductor has a capacitance C _PC and also acts like a large resistor in the circuit that is a large resistor of R _PC . Gate address lines and data address lines corresponding to the columns and rows of pixels depicted are also shown. The magnitude of the bias voltage applied to the top electrode of the photoconductor is V _BIAS . This voltage is provided by an external voltage supply. The V _BIAS value used depends on the type of photoconductor material and generally increases in proportion to the layer thickness of the material. For a-Se, V _BIAS is typically about 10V per micron thickness. Thus, for a 1000 μm a-Se layer, V _BIAS will be about 10,000V. For HgI ₂ , V _BIAS is typically in the range of about 0.5 to 2.0 V per micron. Thus, for a 500 μm HgI ₂ layer, V _BIAS will be about 250 to 1,000V. The photoconductive layer can also operate in a collapse mode in which the value of V _BIAS across the other layer is generally higher - for the example of a-Se, in the range of about 50V to 100V per micron. In this case, the sag layer can be made thick enough to stop most of the x-rays themselves, or the sag layer can be made thinner, and a photoconductor or scintillator layer (such as having a sufficient thickness to make it large) Part of the incident x-light stopped a-Se or CsI:Tl) is deposited on the avalanche layer. In this case, the purpose of the sag layer is to amplify the signal from the overlying converter.

Figure 8 is a schematic cross-sectional illustration of a structural implementation of a pixel design corresponding to the pixel circuit of Figure 7. In this implementation, the addressed TFT shares the surface area of the pixel with: a pixel storage capacitor, an address line, and an address line, between the storage capacitor and the TFT. gap. The photoconductor structure (including the bottom electrode, the layer of photoconductive material, and the top electrode) resides above the plane of the addressed TFT (ie, above the horizontal plane).

In Fig. 8, the general position of the a-Si addressed transistor (TFT) is indicated by a dashed oval (only the drain, source and gate are illustrated). For pixel storage capacitors whose position is indicated by a second dashed oval, only the top and bottom electrodes are illustrated. The top electrode of the pixel storage capacitor is formed by a rear contact which is an extension of the metal used to form the source of the TFT. The bottom electrode of the photoconductor is connected to the TFT by means of a via hole to the back contact (indicated by a third ellipse) and does not extend over the TFT. A thick layer of continuous layer of photoconductor material (which acts as an x-ray converter) is deposited across the entire array to bring the material into contact with the bottom electrode. A continuous top electrode is deposited over the entire surface of the photoconductor. A bias voltage of magnitude V _BIAS is applied to the top electrode to establish an electric field across the photoconductor. A layer of material (referred to as an encapsulation or encapsulation layer) is deposited over the entire top electrode to encapsulate the array to mechanically and chemically protect the array and prevent unintended electrical contact with the top electrode. The direction of the data address line connected to the drain of the TFT by the via hole is orthogonal to the plane of the drawing. The position of the passivation material is indicated by a shadow. Note that in an alternative configuration for directly detecting pixels and arrays, a thin layer of material (typically about 1 to 10 microns thick) can be deposited between the bottom electrode and the photoconductor or between the top electrode and the photoconductor, acting as a barrier , dielectric or doped layer). Alternatively, the thin material layer can be deposited in both locations, and the type and thickness of the thin material layer can be different in each location.

For an indirect-detect active matrix imaging array having the baseline architecture illustrated in FIG. 6, the addressed TFT and the photodiode compete directly with each other and compete with other pixel elements for regions in the pixel. This is apparent in Figure 6 and in the corresponding schematic representation of the four pixels appearing in Figure 9. It is further apparent in Figure 10, which shows a photomicrograph of a pixel obtained from a pair of indirect detection active matrix arrays. In general, the design indirectly detects the active matrix array so that the area of the photodiode is as large as possible. In addition, for an array design in which the bias lines extend over the top surface of the photodiode, the lines and associated vias (both are optically opaque and block light from reaching the photodiode) The area is as small as possible. For a given array design, the fraction of the pixel area that is occupied by the surface of the photodiode (which is open to incident light from above) is called the optical fill factor .

The maximization of the optical fill factor is driven by the fact that more efficient use of incident light from the overlying scintillator increases the pixel signal size and thus increases the imager's signal to noise ratio, resulting in improved image quality. For applications requiring small pixel pitch (eg, below about 100 μm) or imager for low exposure (such as low exposure areas for fluoroscopy, where each frame exposure is less than about 1 μR) In terms of array design, it is especially important to maximize the optical fill factor.

The high optical fill factor excites the minimization of the size of the addressed TFT, the width of the address line, the width of the bias line, and the gap between the photodiode, the TFT, and the address line. However, the manufacturing process imposes a minimum feature size on each component of the design. In addition, the address and bias lines must be wide enough to limit the resistance along these lines (because high resistance will negatively impact the time and/or electrical operation of the array, and may reduce signal-to-noise performance). In addition, the gap must not be narrow enough to cause unintended contact (and thus electrical shorting) between pixel elements or to cause high levels of parasitic capacitance (which can degrade signal-to-noise ratio and time performance). Finally, the width-to-length ratio (referred to as the aspect ratio) of the TFT channel must be large enough to provide the amount of TFT turn-on current required for the desired array read speed (because the TFT with a higher aspect ratio is in its conduction mode) Provide a higher level of current). Figure 10 illustrates a practical example of such considerations in which the optical fill factor of the earlier array design (assisted by the reduction of the minimum feature size) via the gap, the address line, and the size of the TFT (Figure 10(a) Showcase) has increased significantly in later designs (shown in Figure 10(b)). As the pixel pitch decreases, the challenge of maintaining a large optical fill factor becomes more difficult because the area occupied by the address lines, gaps, and addressed TFTs consumes a larger fraction of the pixel area.

A highly efficient method of avoiding the above limitation on the optical fill factor is to implement a pixel in which the photodiode structure is located above the plane of the addressed TFT (ie, above the horizontal plane). Architecture. A variety of such out-of-plane architectures are possible, and two such architectures are shown in Figures 11 and 12. In these illustrations, the out-of-plane photodiode structure partially or completely overlaps one of the addressed TFTs to maximize the optical fill factor.

The photodiode of Figure 11 includes a discrete stack of structures aligned with the bottom electrode. As shown in FIG. 6, a single address TFT is connected to a discrete a-Si photodiode having three a-Si layers and a top electrode and a bottom electrode. However, in this pixel architecture, the bottom electrode of the photodiode is positioned above the plane of the addressed TFT. The bottom electrode is connected to the TFT by means of a via hole to the back contact whose position is indicated by a dashed oval, which is an extension of the metal used to form the source of the TFT. The a-Si layers of the photodiode and the top electrode are patterned to form a stack aligned with the bottom electrode. The direction of the data address line (whose position is indicated by the solid ellipse) and the bias line are orthogonal to the plane of the drawing.

The photodiode of Figure 12 has a structure in which some of the layers are continuous. As shown in Figure 11, a single address TFT is connected to an a-Si photodiode positioned above the plane of the TFT. However, in this pixel architecture, the p ⁺ doped layer and the pure layer are unpatterned, but are continuous across the array to aid in maximizing the optical fill factor. The n ⁺ -type doped a-Si layer is patterned to align with the bottom electrode of the photodiode to suppress charge sharing between adjacent pixels. The bottom electrode is connected to the TFT by means of a via hole to the back contact whose position is indicated by a dashed oval, which is an extension of the metal used to form the source of the TFT. The direction of the data address line (the position of which is indicated by the solid ellipse) and the body of the graphic plane.

13 and 14 correspond to an actual implementation having an inter-pixel detection active matrix array design of the pixel architecture depicted in FIG. Figure 13 is a schematic representation of four pixels and Figure 14 is a photomicrograph of pixels from an array.

In an embodiment of the invention, a radiation sensor is provided, comprising: a flash a scintillation layer configured to emit photons when interacting with ionizing radiation; and a photodetector comprising, in order, a first electrode, a photosensitive layer, and one of the photoluminescent layers disposed adjacent to the scintillation layer A second electrode that transmits photons. The photosensitive layer is configured to create an electron hole pair when interacting with a portion of the photons. The radiation sensor includes: a pixel circuit electrically coupled to the first electrode and configured to measure an imaging signal indicative of one of the pairs of electron holes generated in the photosensitive layer; and a planarization layer And disposed between the first electrode and the pixel circuit on the pixel circuit such that the first electrode is higher than a plane including the pixel circuit. A surface of at least one of the first electrode and the second electrode at least partially overlaps the pixel circuit and has a surface recursion higher than one of the features of the pixel circuit. The surface recursion has a radius of curvature greater than one of 1/2 microns.

In another embodiment of the present invention, a radiation sensor is provided, comprising: a photoconductor detector comprising a first electrode, a photoconductive layer, and a transmissive ionizing radiation in order The second electrode. The photoconductive layer is configured to create an electron hole pair upon interaction with ionizing radiation. The radiation sensor includes: a pixel circuit electrically coupled to the first electrode and configured to measure an imaging signal indicative of one of an electron hole pair generated in the light guiding layer; and a planarization layer Disposed on the pixel circuit between the first electrode and the pixel circuit such that the first electrode is higher than a plane including the pixel circuit. A surface of at least one of the first electrode and the second electrode at least partially overlaps the pixel circuit and has a surface recursion higher than one of the features of the pixel circuit. The surface recursion has a radius of curvature greater than one of 1/2 microns.

In yet another embodiment of the invention, a method for fabricating a radiation sensor is provided. The method includes: forming a pixel circuit component on a base substrate, forming a planarization layer on the pixel circuit component, and forming a hole in the planarization layer to expose to a connector of the pixel circuit component, The patterned holes are metallized to form a first electrode in electrical contact with the metallized holes, and a layer sensitive to light or ionizing radiation is formed on the first electrode. Forming the planarization layer at least partially overlapping the pixel circuit A surface reversal is provided on one of the surfaces of the first electrode, the surface being recurved above the features of the pixel circuit, having a radius of curvature greater than one-half micron.

The above general description of the present invention is intended to be illustrative and not restrictive.

PC‧‧‧Light Conductor

PD‧‧‧Photoelectric diode

TFT‧‧‧pixel addressed transistor

TFT _ADDR ‧‧‧ Addressing TFT

TFT _AL ‧‧‧ payload TFT

TFT _CSA ‧‧‧ Common source amplifier TFT

TFT _RST ‧‧‧Reset TFT

TFT _SF ‧‧‧Source follower TFT

1 is a schematic three-dimensional view of one form of an a-Si thin film transistor (TFT) showing the top of a TFT from a bevel view; FIG. 2 is a schematic cross section of the a-Si TFT shown in FIG. Figure 3 is a schematic three-dimensional view of one of the poly-Si TFTs, showing the top of the TFT from the oblique angle view; Figure 4 is a schematic cross-sectional view of the poly-Si TFT shown in Figure 3. Figure 5 is a schematic circuit diagram of a pixel from an active matrix imaging array using incident radiation inter-connect detection; Figure 6 is in the form of an inter-connected detection pixel design with discrete photodiodes A schematic diagram of a cross-sectional view of the indirect detection pixel design corresponding to one of the pixel structures of FIG. 5 and referred to as a baseline architecture; FIG. 7 is a schematic circuit diagram of pixels from an active matrix imaging array, Active matrix imaging arrays use direct detection of incident radiation; Figure 8 is a schematic diagram of a cross-sectional view of one form of direct detection pixel design; Figure 9 is an indirect detection of four adjacent pixels of an active matrix array Schematic representation, which corresponds to The implementation of the pixel circuit and the baseline architecture shown in FIGS. 5 and 6; FIG. 10 is a photomicrograph collection of a pair of indirect detection active matrix arrays in a single pixel region, corresponding to the map Implementation of a baseline architecture in Figure 6; Figure 11 is a schematic diagram of a cross-sectional view of an inter-detected pixel design with discrete out-of-plane photodiode structures; Figure 12 is a continuous out-of-plane photodiode structure Interconnect detection pixel design Schematic diagram of a cross-sectional view; FIG. 13 is a schematic representation of indirect detection of four adjacent pixels of an active matrix array, corresponding to the implementation of the pixel circuits and architecture shown in FIGS. 5 and 12, respectively Figure 14 is a photomicrograph of the top surface of the active matrix array in a single pixel region, which corresponds to the implementation of the pixel architecture in Figure 12 and the presentation in Figure 13; Figure 15 is from active-based A schematic circuit diagram of a pixel design inter-detecting a pixel of the array having a single-stage in-pixel amplifier; FIG. 16 is a schematic representation of four adjacent pixels based on an active pixel design inter-detection array, The active pixel design uses a poly-Si TFT, which schematically represents the implementation of the pixel circuit of FIG. 15 and a photodiode structure similar to the structure of FIG. 12; FIG. 17 shows that the indirect detection array is single. A photomicrograph of the top surface in the pixel region, which corresponds to the implementation of the pixel circuit of FIG. 15 and the representation of FIG. 16; FIG. 18 is a schematic diagram of the pixel from the interferometric detection array based on the active pixel design The active pixel design has a two-stage in-pixel amplifier; FIG. 19 is a schematic representation of four adjacent pixels based on an active pixel design inter-connected detection array using a poly-Si TFT, The schematic representation corresponds to the implementation of the pixel circuit of FIG. 18 and a photodiode structure similar to the structure of FIG. 12; FIG. 20 is a photomicrograph of the top surface of the indirect detection array in a single pixel region, Corresponding to the implementation of the pixel circuit in FIG. 18 and the presentation in FIG. 19; FIG. 21 is a cross-sectional view of the calculation of the inter-connected detection array based on a single-stage in-pixel amplifier design using polycrystalline -Si TFT, the cross-sectional view corresponding to Figures 16 and 17 and showing the native topology of various features and materials; Figure 22 (a) is a cross-sectional view of the calculation based on the inter-detection array of the two-stage in-pixel amplifier design, The two-stage in-pixel amplifier design uses a poly-Si TFT, the cross-sectional view Corresponding to Figures 19 and 20 and showing the native topology of various features and materials; Figure 22 (b) corresponds to a portion of Figure 22 (a); Figure 23 (a) is a single-pixel in-pixel amplifier array in a single pixel region In the top view, the figure is obtained according to the same calculations used in FIG. 21, which corresponds to FIGS. 16 and 17 and shows the native topology of the top of the continuous photodiode structure; FIG. 23(b) is obtained from FIG. A photomicrograph, which is shown for comparison with the top view of the calculation in Figure 23(a); Figure 24(a) is a top view of the two-stage in-pixel amplifier array in a single pixel region, the graph Obtained according to the same calculations used in FIG. 22, which corresponds to FIGS. 19 and 20 and shows the native topology of the top of the continuous photodiode structure; FIG. 24(b) is a photomicrograph obtained from FIG. Shown for comparison with the top view of the calculation in Figure 24(a); Figure 25 is a pair of diagrams illustrating the general concept of radius of curvature, which can be applied to the characterization of the change in the flatness of the surface; Figure 26 (a) is a cross-sectional view of the calculation of the indirect detection array, which corresponds to Figure 21, but with A more consistent topology achieved by complete planarization of passivation #2; Figure 26(b) is a cross-sectional view of the calculation of the indirect detection array, corresponding to Figure 21, but with partial planarization via passivation #2 A more consistent topology is achieved; Figure 27(a) is a cross-sectional view of the calculation of the indirect detection array, which corresponds to Figure 22(a) but with a more consistent topology achieved by complete planarization of passivation #2 Figure 27(b) corresponds to a portion of Figure 27(a); Figure 28 is a cross-sectional view of the indirect detection array, which corresponds to Figure 26(a) but with a bottom electrode via a photodiode A more consistent topology achieved by smoothing the peripheral edges; Figure 29 is a cross-sectional view of the indirect detection array, corresponding to Figure 27(a) but with peripheral edges of the bottom electrode via the photodiode Smoother and more consistent Topology; Figure 30 is a cross-sectional view of the indirect detection array, corresponding to Figure 28, but with a more consistent topology achieved by narrowing the via holes and filling their via holes with metal. The interlayer hole is connected to the bottom electrode and the rear contact of the photodiode; FIG. 31(a) is a top view of the single-stage in-pixel amplifier array in a single pixel region, which is obtained by calculation and corresponds completely to FIG. (a), the figure shows the native topology of the top continuous photodiode structure and is included for comparison with the remaining views in this Figure 31; Figure 31 (b) shows complete flatness via passivation #2 The improvement of the surface topology with respect to Fig. 31(a) is obtained from the same calculation used for Fig. 26(a); Fig. 31(c) shows the peripheral edge of the bottom electrode via the photodiode The improvement of the surface topology with respect to Fig. 31(b) achieved by smoothing, the figure is obtained from the same calculation used in Fig. 28; Fig. 31(d) shows the narrowing through the via holes and filling them with metal Improvement of the surface topology achieved by the layer hole relative to the surface of FIG. 31(c) The bottom electrode and the back contact of the electric diode are obtained from the same calculation used in FIG. 30; FIG. 32(a) is a top view of the two-stage pixel in-amplifier array in a single pixel region, which is self-calculating Obtained and fully corresponds to Figure 24(a), which shows the native topology of the top continuous photodiode structure and is included for purposes of comparison with the remaining views in this Figure 32; Figure 32(b) shows Improvements to the surface topology of Figure 32(a) achieved by complete planarization of passivation #2, which is obtained from the same calculations used in Figure 27; Figure 32(c) shows the bottom electrode via the photodiode The improvement of the surface topology with respect to FIG. 32(b) achieved by the smoothing of the peripheral edge, which is obtained from the same calculation used in FIG. 29; FIG. 32(d) shows the narrowing and metal through the via hole. Filled with their mesopores Compared with the improvement of the surface topology of FIG. 32(c), the via hole is connected to the bottom electrode and the rear contact of the photodiode, and the figure is obtained by calculation; FIG. 33(a) is the calculation of the indirect detection array. A cross-sectional view corresponding to Figure 21, but with a more consistent topology achieved by complete planarization of the pure a-Si layer in the photodiode; Figure 33(b) is an indirect detection array calculation A cross-sectional view corresponding to Figure 21, but with a more consistent topology achieved by partial planarization of the pure a-Si layer in the photodiode; Figure 34 (a) is a single-stage in-pixel amplifier array a top view in a single pixel region, obtained from calculations and fully corresponding to Figure 23(a), which shows the native topology of the top continuous photodiode structure, and is included for use in this Figure 34 The remaining views are compared for the purpose; FIG. 34(b) shows an improvement over the surface topology of FIG. 34(a) achieved by partial planarization of the pure a-Si layer in the photodiode, the figure Obtained from the same calculation used in Figure 33(b); and Figure 34(c) shows the completion of the pure a-Si layer in the photodiode The improvement of the surface topology with respect to Fig. 34(a) achieved by full planarization is obtained from the same calculations used for Fig. 33(a).

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Incorporating an out-of-plane photodiode structure into a pixel design of an indirect detection active matrix array provides a mechanism for significantly improving the optical fill factor. In the case of implementing a continuous photodiode structure, it is possible to achieve an optical fill factor of up to 1 corresponding to the entire pixel area. These optical fill factor improvements result from the elimination of the pixel area between the photodiode and other pixel elements (such as addressed TFTs, address lines and gaps). Fight.

The out-of-plane photodiode structure also makes it possible to introduce additional components into the pixel (such as TFTs, diodes, capacitors and resistors, as well as vias, traces, control lines, address lines, and ground planes). This makes it possible to implement more complex pixel circuits. As in the case of an active matrix array, such additional components will reside in a plane separate from the plane of the photodiode and will therefore not compete with the photodiode for the pixel region. By introducing more complex circuitry in pixel design and elsewhere in the array design, considerable performance can be achieved compared to the performance of an active matrix planar panel imaging array with only a single TFT (acting as a pixel addressing switch) per pixel. Performance improvement. While the types of semiconductor materials used for such additional TFTs and diodes can be any of the types described above, examples of more complex circuits described below relate to poly-Si TFTs. In addition, although the following examples relate to indirect detection array designs in which imaging signals are collected and stored in pixel storage capacitors prior to reading, the out-of-plane photodiode structure also makes it possible to detect and count individual A pixel circuit of x-ray (usually referred to as the ability to count a single photon) without competing such circuits with the photodiode. Such single photon counting pixels will include detectors (such as out-of-plane photodiode structures), as well as amplifiers, discriminators (with pulse shaping circuitry as needed), and event counters (eg, linear feedback shifts) The form of the register) and the circuitry for addressing and pixel resetting. A single photon counting array provides a number of advantages, such as the ability to generate high contrast images based on selected portions of the x-ray spectrum (a technique known as energy discrimination or energy windowing).

For array designs based on incident detection of incident radiation and direct detection, the added complexity improves the imager's signal-to-noise ratio. In the case of indirect detection, greater complexity may also help to limit the trapping of charge in the metastable electron state (also known as the trapping state) of a-Si in the photodiode. Release the associated undesirable effects.

Referring now to the drawings, wherein like reference numerals refer to the same or corresponding parts throughout the several, and more particularly, referring to FIG. 5, for the active matrix array pixel circuit having the general form shown in FIG. During readout of the pixel column, the electric field across the corresponding photodiode is increased back to a maximum value defined by the magnitude of V _BIAS and the thickness of a-Si in the photodiode. Thus, pixel readout results in sampling of the imaging signal and initialization of the pixel. During the collection of imaging signals in each pixel storage capacitor, the electric field is reduced. For a given pixel, if the imaging signal is large enough, the magnitude of the electric field will be reduced to almost zero, the storage capacitor will not be able to store further charge, and the pixel will be saturated. The probability of charge trapping in a photodiode generally increases as the electric field strength decreases, and becomes very high near the condition of pixel saturation. In radiographic imaging, which typically involves large x-ray exposures, the high level of trapped charge results in substantial loss of imaging signal. This reduces the signal to noise ratio of the imager and can degrade image quality. In fluoroscopic imaging, the charge trapped during the capture of the previous image will be released in later images. This can result in image information from earlier images appearing in later images - a generally undesirable effect known as lag or image lag. In addition, if an imager is used to generate a radiographic image with a large x-ray exposure, and if the image is generated by using the imager after a short time, the image information from the radiographic image can be displayed in the fluorescent image - It is an undesirable effect called ghosting. Delay and ghosting are the causes of image artifacts. These image artifacts can make important information in the image unclear, thus degrading the usefulness of the image, and these artifacts are usually based on active matrix arrays. Encountered in the case of an imager. However, array designs with circuits that have greater complexity than the complexity of active matrix arrays can overcome signal-to-noise limitations and reduce image artifacts while maintaining tightness, large area, and resistance to radiation damage. advantage.

An example of a more complex pixel circuit for indirectly detecting an array is schematically illustrated in FIG. This circuit design includes three TFTs that are configured to provide a single-stage in-pixel amplifier, address TFT, and reset TFT. This design is called active pixel design due to the presence of an in-pixel amplifier. During operation of the array with this design, the imaging signal is collected and stored in a photodiode that acts as a pixel storage capacitor. As in the case of an active matrix array, readout can be performed on one pixel column at a time (if the maximum spatial resolution is desired), but the sampling of the pixel signals and pixel initialization are no longer performed simultaneously. When an imaging signal in a given pixel storage capacitor is sampled by using an addressed TFT, the in-pixel amplifier amplifies the signal by an amount equal to the ratio of the capacitance of the data address line to the capacitance C _PD of the photodiode. Because this amplification occurs in the imager circuit before the noise effects from the addressed TFT and from the external preamplifier, which is the two main sources of noise in the active matrix imager, this pixel circuit design provides imaging The signal-to-noise ratio of the device has increased substantially. Additionally, for this pixel circuit, sampling the imaging signal does not initialize the pixels. The reality is that the imaging signal continues to reside in the pixel storage capacitor until the pixel is initialized via the use of the reset TFT. Thus, the imaging signal can be sampled multiple times and then averaged, resulting in a further improvement in the imager's signal to noise ratio. 16 and 17 correspond to an actual implementation of an inter-connected detection array having a single-stage in-pixel amplifier design, which represents the implementation of the pixel circuit of FIG. Figure 16 is a schematic representation of four pixels, and Figure 17 is a photomicrograph of pixels from an actual array.

Another example of an even more complex pixel circuit for indirectly detecting an array is schematically illustrated in FIG. The circuit design includes five TFTs and a feedback capacitor configured to provide a two-stage in-pixel amplifier, an addressable TFT, and a reset TFT. This is another example of an active pixel design. During operation of the array with this design, the imaging signal is collected and stored in a feedback capacitor that acts as a pixel storage capacitor. The operation and advantages of this design are similar to the operation and advantages of the single-stage in-pixel amplifier design described above - due to the in-pixel amplification of the imaging signal and the availability of the imager due to multiple sampling and averaging of the imaging signal. Increased in substance. In addition, in this design, the electric field across the photodiode is only slightly reduced during the collection and storage of the imaging signal - in the case of an active matrix pixel design or the previously described single-stage in-pixel amplifier design. sharp contrast.

As a result, the amount of charge trapping in the photodiode is reduced and the lag and ghosting artifacts are alleviated, even under very high x-ray exposures. Another advantage of this two-stage in-pixel amplifier design is that it allows for a greater degree of control over the gain of the amplifier (defined as the multiplication factor by which the amplifier increases the imaging signal) compared to the single-stage design. . In a two-stage design, the in-pixel amplifier amplifies the imaging signal by an amount equal to the ratio of the capacitance of the data address line to the capacitance C _FB of the pixel feedback capacitor. Thus, for both a single-stage design and a two-stage design, for a given pixel pitch and pixel storage capacitor capacitance, the magnitude of the amplifier gain in the pixel increases as the data line capacitance increases. Thus, if a larger array is fabricated based on a given pixel design (i.e., an array having a larger number of pixels along the direction of the data line), the amount of amplification will increase. This is because the data line capacitance will increase in proportion to the number of pixels along the data address line. In the case of a single-stage design, the amplifier gain in the pixel depends on the array size without changing the thickness or area of the photodiode (the specification needs to be optimized independently for maximum photodetection efficiency). Sex (which is generally undesirable) cannot be offset. However, for a two-stage design, the magnitude of C _FB can be adjusted (eg, by adjusting the thickness of the capacitor dielectric or the area of the capacitor) to offset the change in data line capacitance. This allows a given two-stage design to be implemented for various array sizes without having to change the range of magnitudes of the imaging signals extracted from the array - thus simplifying the design of external preamplifier electronics required for imager operation. 19 and 20 correspond to an actual implementation of an inter-pixel in-detection detection array having two levels of pixels, which represents the implementation of the pixel circuit of FIG. Figure 19 is a schematic representation of four pixels, and Figure 20 is a photomicrograph of pixels from an actual array.

As described above, the out-of-plane photodiode structure enables substantial performance improvement. These improvements are a direct result of the increased optical fill factor and are the result of increased pixel circuit complexity facilitated by such photodiode structures. However, for practical implementation of such benefits, the out-of-plane photodiode structure should not introduce other factors that degrade performance. In this regard, the inventors have discovered significant problems that degrade performance, as explained below.

21 and 22 are cross-sectional views showing the calculation of the single-stage in-pixel amplifier design and the two-stage in-pixel amplifier design corresponding to the photomicrographs in FIGS. 17 and 20, respectively. These cross-sectional views illustrate the various features and materials present in the pixel design. For example, there are four passivation layers: buffer passivation, passivation #1, passivation #2, and top passivation. In addition, there are four metal layers: shunt metal (for components such as reset voltage lines and gate address lines); metal #1 (for components such as back contacts, data address lines, and vias) Metal #2 (for elements such as the bottom electrode of a photodiode); and ITO (for the top electrode of a photodiode). Other layers and features shown in Figures 21 and 22 include poly-Si (labeled as active poly-Si) for TFT channels; TFT gates (formed by poly-Si); and for optoelectronics The n ⁺ type doped, pure and p ⁺ type doped a-Si of the diode. The topological inconsistency of the photodiode structures apparent in such cross-sections represents topological inconsistencies in the corresponding fabricated arrays, and the photomicrographs in Figures 17 and 20 are from the corresponding fabricated arrays. obtain. For example, in Figures 23 and 24, the close view of the top view of the pixel (obtained from the same calculation used to generate the cross-sectional views of Figures 21 and 22) and the actual realized photomicrograph of the corresponding array Obvious.

The photodiode structure illustrated in Figures 21 through 24 demonstrates the extremely high degree of inconsistency in its topology. This topological inconsistency is due to the presence of features in the pixel design that are positioned below the photodiode or part of the photodiode. For the example of pixel design shown, these features include TFTs, capacitors, address lines, traces, and vias (including vias that connect the bottom electrode of the photodiode to the back contact). These features create inconsistencies in the out-of-plane photodiode structure, whether the structure is continuous (as in such examples) or discrete (i.e., has the photodiode structure shown in Figure 11). . Note that in the case of direct detection of the array, the presence of features under the photoconductor structure or portions of the photoconductor structure (such as TFTs, capacitors, address lines, traces, and via holes) is also present in the structure. A similar degree of topological inconsistency is produced. For an in-line detection array with a continuous out-of-plane photodiode structure, and for a direct detection array, along the bottom electrode Topological inconsistencies are created throughout the perimeter and in the region of the via hole connecting the bottom electrode to the back contact, as is evident in Figures 14, 21 and 22(a).

In comparison, for an in-line detection array using a baseline architecture, the discrete photodiode structure demonstrates a very high degree of consistency in its topology. This topological consistency is due to the absence of any features in the pixel design that are positioned below the photodiode or part of the photodiode, as is evident in Figures 6 and 9. In this case, when the processing steps for fabricating the various layers of the photodiode structure are performed over the smooth, planar surface of the array substrate, a smooth and flat surface and thickness uniformity is achieved for each layer. Therefore, the top of the photodiode structure will be smooth and flat, as observed in FIG. This smoothness and flatness is only limited by random local variations (approximately a few hundred angstroms) that originate from the processing steps used for the fabrication of the array. Note that during processing, other process variations can produce up to tens of percent system variation (eg, increase or decrease) across the thickness of a given layer of material across the array.

The photodiode exhibits excellent properties, including the high efficiency of sensing the visible light and collecting the resulting signal, and the benefits of dark current, charge trapping, charge release and delay, in the case of using an inter-connected detection array with a baseline architecture. The low level - there is no random local variation due to the smoothness and flatness of the manufacturing process that interferes with these excellent properties, nor the systematic variation of the material thickness attributed to the manufacturing process that interferes with such excellent properties. Photodiode structures that exhibit these excellent properties (whether including discrete baseline architecture designs or continuous or discrete out-of-plane designs) are said to be of high quality. For a given imaging array, each of these properties can be obtained by measuring the signal properties of the individual pixels, and the results from the individual pixels or the average of the results from many pixels can be expressed in the following manner. The magnitude of this favorable level of dark current per pixel (normalized to unit photodiode area) is less than about 1 pA/mm ² . The magnitude of this favorable level of charge trapping per pixel (quantized by the amount of imaging signal lost due to trapping during a single radiographic frame, and expressed as being in equilibrium between charge trapping and charge release) The percentage of imaging signal obtained under conditions is less than about 20%. The magnitude of this favorable level of charge release per pixel (in the absence of radiation after a series of frames acquired with radiation and under conditions of charge trapping and charge release being balanced) The amount of imaging signal released from the capture state during the first frame acquired is quantified and expressed as a percentage of the imaging signal obtained under conditions in which charge trapping and release are in equilibrium) less than about 15%. The magnitude of this advantageous level of delay for each pixel (by the frame after a frame or series of frames acquired with radiation, during the first frame acquired in the absence of radiation) The amount of imaging signal released by the capture state (which originates from the charge trapped in one or more previous frames) is quantified and expressed as a percentage of the imaging signal from the previous frame) of less than about 15%. The result of these measurements is also commonly referred to as the first domain delay, or, referred to as the first frame delay. For direct detection of active matrix arrays using photoconductive materials for converters, the magnitudes of dark current (normalized to unit photoconductor area), charge trapping, charge release, and lag are similar to those described above. Indirectly detect the level described by the array.

For the use of a high quality photodiode structure in the inter-connected detection array of the baseline architecture, one of the factors contributing to the excellent properties described above is the degree of topological consistency. Each of the individual n ⁺ -type doped, pure and p ⁺ -type doped a-Si layers in the photodiode within the limits of surface smoothness, surface flatness, and thickness uniformity previously described With a uniform thickness, both the top and bottom electrodes are flat and the electrodes are parallel to each other. Therefore, the manner in which the electric field strength varies with the distance across the thickness of the pure layer remains relatively constant over the area of the photodiode, and this causes dark current, charge trapping, and charge in the high quality photodiode. Reasons for the favorable level of release and delay.

Conversely, in a photodiode structure having an inconsistent topology, regions of extremely high and very low electric field strength are produced in the a-Si material of the photodiode. In the region of the photodiode where the top or bottom electrode exhibits a sharp (ie, abrupt) deviation from flatness, the electric field in the pure a-Si will be significantly larger than in the region where the top electrode is parallel to the bottom electrode. Electric field. In the vicinity of this high electric field, the electric field strength will be significantly lower than the top and bottom electrodes The electric field in the parallel zone. The sharper the change in flatness (i.e., the more sudden), the greater the deviation in electric field strength. Since the dark current increases as the electric field strength increases, a region where the electric field strength is significantly increased will result in an unfavorable level of dark current. Similarly, because charge trapping increases with decreasing electric field strength, regions of significantly reduced electric field strength will result in undesirable levels of charge trapping, charge release, and retardation.

The three examples of pixel designs with continuous out-of-plane photodiode structures described above (ie, with active matrix design (Figure 14), with a single-stage in-pixel amplifier design (Figure 21 and Figure 23) ), and with a two-stage in-pixel amplifier design (Figures 22 and 24), the topological inconsistency of the extension of the photodiode in each design results in an extended region with significantly increased electric field strength, and a significant reduction The extension of the electric field strength. A sharp change in electrode flatness can also substantially reduce the minimum distance between the top and bottom electrodes (as is evident in the region of the deep via holes in Figure 21), further contributing to a significant increase in electric field strength. As the inventors have discovered, the presence of such zones results in unfavorably high levels of dark current, charge trapping, charge release and retardation and thus hinders the achievement of high quality photodiodes.

High photodiode dark currents are undesirable for several reasons. Because dark signals (generated by dark current) are stored in the pixel storage capacitor during imaging, the high dark current significantly reduces the range of exposures that the pixel can operate before saturation. In addition, because dark current produces a noise source called shot noise, high dark currents cause high shot noise. Since the effect of the shot noise in the imager occurs before the gain from the in-pixel amplifier (such as in the pixel circuit design of Figures 15 and 18), the imager's signal-to-noise ratio is reduced. Improvement (compared to expected improvement). Similarly, high-volume noise reduces the intended improvement in the signal-to-noise ratio of an imager having an AMFPI array with an out-of-plane photodiode structure (such as the pixel design illustrated in Figures 11 and 12). in). The high level of charge trapping is undesirable for several reasons. In radiographic imaging, the signal loss due to the captured state reduces the imaging signal sampled from the pixel, thereby reducing the messenger of the imager. ratio. In addition, the high level of charge trapping leads to a high level of charge release and lag, which increases the undesirableness of image artifacts.

The sharpness (i.e., suddenness) of the change in the flatness of the surface (such as the topology of the electrodes in the photodiode as shown in Figures 21 to 24) can be quantified by the radius of curvature r , as shown in the figure. As explained in 25. The sharper change in flatness is therefore represented by the smaller value of r . Calculation of the effect of sharp changes in electrode flatness (as parameterized by r ) on the electric field strength in a pure a-Si layer of a photodiode structure (representing their structure in continuous and discrete out-of-plane designs) The decision indicates the importance of reducing such sharp changes in the photodiode structure.

In the region close to the change in flatness (characterized by an r value of 0.1 μm or less), the maximum deviation of the electric field may be very large, which is more than 300% higher than the magnitude of the electric field of a pair of parallel electrodes (in The area closest to the change in flatness) is 60% or more lower than the magnitude of the electric field of a pair of parallel electrodes (near the zones). In a region close to the change in flatness (characterized by an r value of about 0.5 μm), the deviation of the electric field can be as much as about 300% higher than the magnitude of the electric field of a pair of parallel electrodes (the change in the closest flatness) In their respective zones, the magnitude of the electric field is less than about 60% (near the zone) than the magnitude of the electric field of a pair of parallel electrodes.

In a region close to the change in flatness (characterized by an r value of about 1 μm), the deviation of the electric field can be as much as about 200% higher than the magnitude of the electric field of a pair of parallel electrodes (in the closest change to flatness) In their zones, the magnitude of the electric field is less than about 50% (near the zone) than the pair of parallel electrodes. In a region close to the change in flatness (characterized by an r value of about 2 μm), the deviation of the electric field can be as much as about 50% higher than the magnitude of the electric field of a pair of parallel electrodes (in the closest change to flatness) In their zone), the magnitude of the electric field is less than about 30% (near the zone) than the pair of parallel electrodes. In a region close to the change in flatness (characterized by an r value of about 5 μm), the deviation of the electric field can be as much as about 20% higher than the magnitude of the electric field of a pair of parallel electrodes (in the closest change to flatness) In their zones, the magnitude of the electric field is less than about 15% (near the zone) than the pair of parallel electrodes. In a region close to the change in flatness (characterized by an r value of about 10 μm), the deviation of the electric field can be as much as about 10% higher than the magnitude of the electric field of a pair of parallel electrodes (in the closest change to flatness) In their zones, the magnitude of the electric field is less than about 10% (near the zone) than the pair of parallel electrodes.

The above considerations make it obvious that if an out-of-plane photodiode structure is fabricated without regard to the topological consistency of the photodiode, the resulting topology (which will be referred to as a native topology, such as the one shown in Figures 21-24) Medium) can impede the achievement of high quality photodiodes and degrade the performance of an imager having an array of such photodiodes. In general, the magnitudes of dark current, charge trapping, charge release, and retardation will increase as the range (i.e., number and area) of the sharply changing regions of the electrodes of the photodiode increases. . These magnitudes will also increase as the sharpness of the change in the flatness of the electrode increases. However, in accordance with an embodiment of the present invention, a high quality out-of-plane photodiode structure is realized in which the photodiode is designed and fabricated such that the extent of the regions and the sharpness of the change in the flatness of the electrodes are sufficient The reduction is such that the photodiode exhibits a favorable level of dark current, charge trapping, charge release, and retardation.

26 through 34 show examples of the results of applying various methods to improve the topological consistency of an out-of-plane photodiode structure. One method for improving topological uniformity is to completely planarize one of the material layers below the photodiode structure. The description of the application of this method is shown in Figure 26(a) and Figure 31(b) for the state of the single-stage in-pixel amplifier design, and Figure 27 and Figure 32(b) for the state of the two-stage in-pixel amplifier design. in. In each case, the top surface of passivation #2 has been made flat.

This can be achieved (for example, in one embodiment of the invention) via the application of chemical-mechanical polishing (CMP, also known as chemical-mechanical planarization) and/or spin coating. In applying this method, the thickness of the passivation layer can be initially made thicker than in the native topological condition to ensure a minimum thickness after application of CMP. This will help to ensure that the parasitic capacitance between the photodiode electrode and the circuit components underneath the photodiode structure remains below a desired limit. 26(a) and FIG. 27 provide the same as the native topology illustrated in FIGS. 21 and 22, respectively. An improved cross-sectional view of the topological consistency of the photodiode compared to the topological consistency. 31(b) and 32(b) are plan views showing an improvement in the topological consistency of the photodiode as compared with the native topology illustrated in FIGS. 31(a) and 32(a). The effectiveness of this approach in significantly improving topological consistency is evident. Another method for improving the topological consistency of the out-of-plane photodiode structure is to partially planarize a layer of material beneath the photodiode structure, as illustrated in Figure 26(b). This can be achieved via the use of various known techniques, such as those described above.

In a continuous out-of-plane photodiode structure, the edge of the bottom electrode (formed by the metal #2 layer) produces a sharp change in the flatness of the top electrode, as is evident in Figures 26(a) and 27(a). In an embodiment of the invention, these edges need to be smoothed. A method for achieving this smoothing in accordance with the present invention is to adjust the etching technique used to define the edges of the bottom electrode to achieve a slanted or circular shape having a radius of curvature greater than the radius of curvature in the native topology. Figures 28 and 29 provide improved cross-sectional views of the topological uniformity of the photodiode as compared to the topological consistency shown in Figures 26(a) and 27(a), respectively. Figures 31(c) and 32(c) respectively provide an improved top view of the topological consistency of the photodiodes compared to the topological consistency shown in Figures 31(b) and 32(b). The effectiveness of this approach in further improving topological consistency is evident.

In a continuous out-of-plane photodiode structure, connecting the bottom electrode of the photodiode to one or more of the via contacts also produces a sharp change in the flatness of the top and bottom electrodes. A method for reducing the sharpness of such changes in flatness according to the present invention is by narrowing the lateral dimension of each via (i.e., along the surface of the photodiode) (e.g., ) to reduce the area of each via hole to the limits allowed by the design rules. Metal for the bottom electrode can also be deposited to fill the via holes. Figure 30 is a cross-sectional view showing the resulting improved topological consistency of the photodiode as compared to the topological consistency shown in Figure 28. (Because there is no via hole in the field of view of Figure 29, the corresponding cross-section description of the two-stage in-pixel amplifier design is not shown.) Figures 31(d) and 32(d) are shown in Figure 31(c) and An improved top view of the topological consistency of the photodiode compared to the topological consistency shown in Figure 32(c). The effectiveness of this method of the invention in further improving topological consistency is evident.

Another method for improving the topological uniformity of the out-of-plane photodiode structure is to planarize the top surface of the pure a-Si layer in the photodiode. A description of the application of this method to the state of the single-stage in-pixel amplifier design is shown in Figures 33, 34(b), and 34(c).

Full planarization of the pure a-Si layer in the photodiode can be achieved, for example, by applying CMP in one embodiment of the invention. In applying this method, the thickness of the pure a-Si layer can be initially made thicker to ensure that the final thickness achieved after application of CMP corresponds to its preferred thickness. This will help ensure that the photodiode exhibits excellent properties. Figure 33 (a) provides a cross-sectional view of the resulting improvement compared to the condition of the native topology illustrated in Figure 21. Figure 34 (c) provides a top view of the resulting improved topological consistency of the photodiode as compared to the native topology illustrated in Figure 34 (a). The effectiveness of this method in significantly improving the uniformity of the top electrode of the photodiode is evident. The consistency of the bottom electrode remains the same compared to the native topology. Another embodiment of the method for improving the topological uniformity of the out-of-plane photodiode structure is to partially planarize the pure a-Si layer in the photodiode, as shown in Figures 33(b) and 34. As explained in (b). This can be achieved via the use of various known techniques, such as those described above.

A method for improving the topological uniformity of an out-of-plane photodiode structure as described herein can be used in combination to achieve the desired results of the present invention, including: one of being under the photodiode structure or The planarization of a plurality of material layers (such as a passivation layer) smoothes the edge of the bottom electrode of the photodiode structure, narrowing the lateral dimension of the via hole connecting the bottom electrode of the photodiode to the rear contact And/or depositing a metal for the bottom electrode to fill the via hole and planarizing the pure a-Si in the photodiode.

As is apparent from the vivid results shown in Figures 31, 32, and 34, the present invention provides an ability to remove topological inconsistencies associated with edges of pixel circuit components. The planarization techniques (as described above) planarize layers that cover pixel circuit elements or array features, such as the following: TFTs (including the source, drain, and gate of the TFT) ), diodes, capacitors and resistors, as well as vias, traces, control lines, address lines, ground planes, electrode surfaces, light-blocking surfaces, bias lines, rear contacts, and the bottom of the photodiode The electrodes, which are all made of a plurality of metal layers, passivation layers or dielectric layers, are as discussed above and are shown, for example, in the cross-sectional views of Figures 26-30 and 33. In this manner, the invention is not limited to planarization over thin film transistor elements. For example, even the effects of inconsistencies associated with all TFT pixel circuit elements or array features, including but not limited to control lines and address lines, can also be achieved by planarizing subsequent layers deposited over such structures. To mitigate, such structures include, for example, dielectric via interconnects through lower passivation layer #1 (as shown, for example, in Figure 26). Even inconsistencies introduced by single-stage in-pixel amplifier designs (as in Figures 17, 21, and 23) or two-stage in-pixel amplifier designs (as in Figures 20, 22, and 24) can be borrowed Reduced by planarization of subsequent layers deposited on top of such structures.

In view of the above detailed description, the various elements of the various embodiments of the present invention are described in the <RTIgt;

In a first illustrative embodiment, a radiation sensor includes: a scintillation layer configured to emit photons when interacting with ionizing radiation; and a photodetector including a first in order An electrode, a photosensitive layer, and a second electrode capable of transmitting photons disposed adjacent to the scintillation layer. The photosensitive layer is configured to create an electron hole pair when interacting with a portion of the photons. The radiation sensor includes a pixel circuit electrically coupled to the first electrode and configured to measure an imaging signal indicative of one of the pairs of electron holes generated in the photosensitive layer; and a planarization layer, It is disposed on the pixel circuit between the first electrode and the pixel circuit such that the first electrode is higher than a plane including the pixel circuit. a surface of at least one of the first electrode and the second electrode at least partially overlapping the surface The pixel circuit has a surface recursion that is higher than one of the features of the pixel circuit. The surface recursion has a radius of curvature greater than one of 1/2 microns.

The surface recursion can have a radius of curvature greater than 1 micrometer, greater than 5 micrometers, greater than 10 micrometers, or greater than 100 micrometers, for example, depending on the degree of planarization desired or achieved. The planarization layer can then be wholly or partially over the features of the pixel circuit, over the array features, over the dielectric via interconnects connected to the source or drain of the TFT, within a single level of pixels The amplifier element is planarized over the amplifier element and/or over the amplifier elements within the two-stage pixel. The planarization layer can be at least one of a passivation layer, a dielectric layer, or an insulating layer.

In one aspect of this embodiment, the radiation sensor can include address lines and data lines disposed under the photodetector, and the planarization layer is disposed on the address lines and data lines as well as the address lines and data. On the layer of the hole. Additionally, the dielectric via interconnects can extend through the planarization layer and connect the first electrode to the pixel circuitry. The surface reflex of the dielectric via interconnect in contact with the photosensitive layer can have a radius of curvature greater than 1/2 micron, greater than 1 micron, greater than 5 microns, greater than 10 microns, and greater than 100 microns.

In one aspect of this embodiment, the photosensitive layer can be one of a p-i-n semiconductor stack, an n-i-p semiconductor stack, or a metal insulator semiconductor stack. The pixel circuit can include one of a thin film transistor, a diode, a capacitor, a resistor, a trace, a via, a control line, an address line, and a ground plane. The pixel circuit may be one of an amorphous semiconductor transistor or a polycrystalline semiconductor transistor or a microcrystalline semiconductor transistor. The pixel circuit can include at least one of an address transistor, an amplifier transistor, and a reset transistor. The pixel circuit may be at least one of amorphous germanium, low temperature amorphous germanium, and microcrystalline germanium. The pixel circuit may be at least one of: a germanium semiconductor, an oxide semiconductor, a chalcogenide semiconductor, a cadmium selenide semiconductor, an organic semiconductor, an organic small molecule or a polymer semiconductor, a carbon nanotube, or a graphite film, Or other semi-conductive materials.

In one aspect of this embodiment, the photosensitive layer can be at least one of: 1) a continuous photosensitive layer extending across a plurality of photodetector pixels, or 2) and the plurality of photodetectors A discrete photosensitive layer associated with each of the pixels. The scintillation layer may be at least one of the following: CsI: Tl, Gd ₂ O ₂ S: Tb, CsI: Na, NaI: Tl, CaWO ₄ , ZnWO ₄ , CdWO ₄ , Bi ₄ Ge ₃ O ₁₂ , Lu _1.8 Yb _0.2 SiO ₅ :Ce, Gd ₂ SiO ₅ :Ce, BaFCl:Eu ²⁺ , BaSO ₄ :Eu ²⁺ , BaFBr:Eu ²⁺ ,LaOBr:Tb ³⁺ ,LaOBr:Tm ³⁺ ,La ₂ O ₂ S: Tb ³⁺ , Y ₂ O ₂ S: Tb ³⁺ , YTaO ₄ , YTaO ₄ : Nb, ZnS: Ag, (Zn, Cd) S: Ag, ZnSiO ₄ : Mn ²⁺ , CSI, LiI: Eu ^{2 +} , PbWO ₄ , Bi ₄ Si ₃ O ₁₂ , Lu ₂ SiO ₅ :Ce ³⁺ , YAlO ₃ :Ce ³⁺ , CSF, CaF ₂ :Eu ²⁺ , BaF ₂ , CeF ₃ , Y _1.34 Gd _0.6 O ₃ : Eu ³⁺ , Pr, Gd ₂ O ₂ S: Pr ³⁺ , Ce, SCG1, HFG: Ce ³⁺ (5%) and C ₁₄ H ₁₀ , or other scintillator materials.

In one aspect of this embodiment, the radiation sensor can include a base substrate supporting the pixel circuit, the photodetector, and the scintillation layer, and can include a plurality of light detections arranged on the base substrate in a regular pattern. Pixel. In one aspect of this embodiment, the second electrode that transmits photons can form a bias plane for the plurality of photodetector pixels. A portion of the pixel circuit can be disposed on the base substrate in a gap region between adjacent photodetector pixels. This portion may include one of a thin film transistor, a diode, a capacitor, a resistor, a via, a trace, a control line, an address line, and a ground plane. In one aspect of this embodiment, the first electrode can have a sloped end that terminates near the gap region.

In one aspect of this embodiment, the dark current (normalized to unit photodetector area) between the first electrode and the second electrode that can transmit photons can be less than 10 pA/mm ² , or less than 5 pA/mm ² , or less than 1pA / mm ^2, or less than 0.5pA / mm ^2. The level of dark current is somewhat coupled to the degree of planarization discussed above and the radius of curvature of the surface recursion. In one aspect of this embodiment, the electric field in the region of the photosensitive layer closest to the surface recursion may be more than 60% of the electric field in the photosensitive layer between a pair of parallel first and second electrodes. And below 300%. The change in the electric field is coupled to some extent to the degree of planarization discussed above and the radius of curvature of the surface recursion.

In one aspect of this embodiment, the sensor can include a metal plate that is placed in the flash The encapsulation on the layer or on the scintillation layer.

In a second illustrative embodiment, a radiation sensor includes: a scintillation layer configured to emit photons when interacting with ionizing radiation; a photodetector including a first electrode in sequence And a photosensitive layer, and a second electrode capable of transmitting photons disposed adjacent to the scintillation layer. The photosensitive layer is configured to create an electron hole pair when interacting with a portion of the photons. The radiation sensor includes a pixel circuit electrically coupled to the first electrode and configured to measure an imaging signal indicative of one of the pairs of electron holes generated in the photosensitive layer; and including a planarization layer And disposed between the first electrode and the pixel circuit on the pixel circuit such that the first electrode is higher than a plane including the pixel circuit. The planarization layer has a first surface recurve along a peripheral edge of a feature of the pixel circuit component, the first electrode having a second surface recursion, the second surface being recurved higher than the first surface and being flat The surface of the layer opposite the base substrate, and the second surface has a curvature radius greater than one of 1/2 micrometers.

In one aspect of this embodiment, the second surface recursion can have a curvature greater than 1 micrometer, greater than 5 micrometers, greater than 10 micrometers, or greater than 100 micrometers, for example, depending on the degree of planarization desired or achieved. radius. The planarization layer can then be wholly or partially over the features of the pixel circuit, over the array features, over the dielectric via interconnects connected to the source or drain of the TFT, within a single level of pixels The amplifier element is planarized over the amplifier element and/or over the amplifier elements within the two-stage pixel. The planarization layer can be at least one of a passivation layer, a dielectric layer, or an insulating layer.

In one aspect of this embodiment, the radiation sensor can include address lines and data lines disposed under the photodetector, and the planarization layer is disposed on the address lines and data lines as well as the address lines and data. On the layer of the hole. Additionally, the dielectric via interconnects can extend through the planarization layer and connect the first electrode to the pixel circuitry. The surface reflex of the dielectric via interconnect in contact with the photosensitive layer can have a radius of curvature greater than 1/2 micron, greater than 1 micron, greater than 5 microns, greater than 10 microns, or greater than 100 microns.

In one aspect of this embodiment, the photosensitive layer can be one of a p-i-n semiconductor stack, an n-i-p semiconductor stack, or a metal insulator semiconductor stack. The pixel circuit can include one of a thin film transistor, a diode, a capacitor, a resistor, a trace, a via, a control line, an address line, and a ground plane. The pixel circuit may be one of an amorphous semiconductor transistor or a polycrystalline semiconductor transistor or a microcrystalline semiconductor transistor. The pixel circuit can include at least one of an address transistor, an amplifier transistor, and a reset transistor. The pixel circuit may be at least one of amorphous germanium, low temperature amorphous germanium, and microcrystalline germanium. The pixel circuit may be at least one of: a germanium semiconductor, an oxide semiconductor, a chalcogenide semiconductor, a cadmium selenide semiconductor, an organic semiconductor, an organic small molecule or a polymer semiconductor, a carbon nanotube, or a graphite film, Or other semi-conductive materials.

In one aspect of this embodiment, the photosensitive layer can be at least one of: 1) a continuous photosensitive layer extending across a plurality of photodetector pixels, or 2) and the plurality of photodetectors A discrete photosensitive layer associated with each of the pixels. The scintillation layer may be at least one of the following: CsI: Tl, Gd ₂ O ₂ S: Tb, CsI: Na, NaI: Tl, CaWO ₄ , ZnWO ₄ , CdWO ₄ , Bi ₄ Ge ₃ O ₁₂ , Lu _1.8 Yb _0.2 SiO ₅ :Ce, Gd ₂ SiO ₅ :Ce, BaFCl:Eu ²⁺ , BaSO ₄ :Eu ²⁺ , BaFBr:Eu ²⁺ ,LaOBr:Tb ³⁺ ,LaOBr:Tm ³⁺ ,La ₂ O ₂ S: Tb ³⁺ , Y ₂ O ₂ S: Tb ³⁺ , YTaO ₄ , YTaO ₄ : Nb, ZnS: Ag, (Zn, Cd) S: Ag, ZnSiO ₄ : Mn ²⁺ , CsI, LiI: Eu ^{2 +} , PbWO ₄ , Bi ₄ Si ₃ O ₁₂ , Lu ₂ SiO ₅ :Ce ³⁺ , YAlO ₃ :Ce ³⁺ , CsF, CaF ₂ :Eu ²⁺ , BaF ₂ , CeF ₃ , Y _1.34 Gd _0.6 O ₃ : Eu ³⁺ , Pr, Gd ₂ O ₂ S: Pr ³⁺ , Ce, SCG1, HFG: Ce ³⁺ (5%) and C ₁₄ H ₁₀ , or other scintillator materials.

In one aspect of this embodiment, the radiation sensor can include a base substrate supporting the pixel circuit, the photodetector, and the scintillation layer. The radiation sensor can include a plurality of photodetector pixels arranged in a regular pattern on the base substrate. In one aspect of this embodiment, the photo-transmissive second electrode can form a bias plane for the plurality of photodetector pixels. One portion of the pixel circuit can be disposed on the base substrate between adjacent photodetector pixels In the gap area. This portion may include one of a thin film transistor, a diode, a capacitor, a resistor, a via, a trace, a control line, an address line, and a ground plane. In one aspect of this embodiment, the first electrode can have a sloped end that terminates near the gap region. The sloped edge can have a radius of curvature greater than 1/2 micrometer, or greater than 1 micrometer, or greater than 5 micrometers, or greater than 10 micrometers or greater than 100 micrometers.

In one aspect of this embodiment, the dark current (normalized to unit photodetector area) between the first electrode and the second electrode that can transmit photons can be less than 10 pA/mm ² , or less than 5 pA/mm ² , or less than 1pA / mm ^2, or less than 0.5pA / mm ^2. The level of dark current is somewhat coupled to the degree of planarization discussed above and the radius of curvature of the surface recursion. In one aspect of this embodiment, the electric field in the region of the photosensitive layer closest to the surface recursion may be more than 60% of the electric field in the photosensitive layer between a pair of parallel first and second electrodes. And below 300%. The change in the electric field is coupled to some extent to the degree of planarization discussed above and the radius of curvature of the surface recursion.

In one aspect of this embodiment, the sensor can include a metal plate disposed on the scintillation layer.

In a third illustrative embodiment, a radiation sensor includes a scintillation layer configured to emit photons when interacting with ionizing radiation; a photodetector including a first electrode in sequence, a photosensitive layer, and a second electrode capable of transmitting photons disposed adjacent to the scintillation layer. The photosensitive layer is configured to create an electron hole pair when interacting with a portion of the photons. The radiation sensor includes a pixel circuit electrically coupled to the first electrode and configured to measure an imaging signal indicative of one of the pairs of electron holes generated in the photosensitive layer; and including a planarization layer And disposed between the first electrode and the pixel circuit on the pixel circuit such that the first electrode is higher than a plane including the pixel circuit. The photodetector has a dark current (normalized to a unit photodetector area) between the first electrode and the second electrode that can transmit photons, the dark current being less than 10 pA/mm ² .

In one aspect of this embodiment, the planarization layer can be a passivation layer, a dielectric layer, or an insulating layer. At least one of the layers. In one aspect of this embodiment, the surface recursion of the first electrode above the pixel circuit has a radius of curvature greater than 1/2 micron, greater than 1 micron, greater than 5 microns, greater than 10 microns, or greater than 100 microns.

In one embodiment of this aspect of the embodiment, the dark current (normalized to unit area of the light detector) may be less than 5pA / mm ^2, or less than 1pA / mm ^2, or less than 0.5pA / mm ^2. The level of dark current is somewhat coupled to the degree of planarization discussed above and the radius of curvature of the surface recursion.

In a fourth illustrative embodiment, a radiation sensor includes: a scintillation layer configured to emit photons when interacting with ionizing radiation; a photodetector including a first electrode in sequence And a photosensitive layer, and a second electrode capable of transmitting photons disposed adjacent to the scintillation layer. The photosensitive layer is configured to create an electron hole pair when interacting with a portion of the photons. The radiation sensor includes a pixel circuit electrically coupled to the first electrode and configured to measure an imaging signal indicative of one of the pairs of electron holes generated in the photosensitive layer; and including a planarization layer And disposed between the first electrode and the pixel circuit on the pixel circuit such that the first electrode is higher than a plane including the pixel circuit. The photodetector has a level of charge trapping for each photodetector pixel, the level is caused by an imaging signal lost during capture during a single radiographic frame (indicating that it is generated in the photosensitive layer) The amount of electron holes is quantified and expressed as a percentage of the imaging signal obtained under conditions in which charge trapping and charge release are in equilibrium, the percentage being less than about 20%.

In one aspect of this embodiment, the planarization layer can be at least one of a passivation layer, a dielectric layer, or an insulating layer. In one aspect of this embodiment, the surface recursion of the first electrode above the pixel circuit has a radius of curvature greater than 1/2 micron, greater than 1 micron, greater than 5 microns, greater than 10 microns, or greater than 100 microns.

In one aspect of this embodiment, the level of charge trapping of each photodetector pixel can be less than 15%, less than 10%, for example, depending on the degree of planarization desired or achieved. Or less than 5%.

In a fifth illustrative embodiment, a radiation sensor includes: a scintillation layer configured to emit photons when interacting with ionizing radiation; a photodetector including a first electrode in sequence And a photosensitive layer, and a second electrode capable of transmitting photons disposed adjacent to the scintillation layer. The photosensitive layer is configured to create an electron hole pair when interacting with a portion of the photons. The radiation sensor includes a pixel circuit electrically coupled to the first electrode and configured to measure an imaging signal indicative of one of the pairs of electron holes generated in the photosensitive layer; and including a planarization layer And disposed between the first electrode and the pixel circuit on the pixel circuit such that the first electrode is higher than a plane including the pixel circuit. The photodetector has a charge release of each photodetector pixel, and the charge release of each photodetector pixel is obtained by having radiation and under the condition that charge trapping and charge release are balanced. The amount of imaging signal (indicating the pair of electron holes generated in the photosensitive layer) released during the first frame acquired in the absence of radiation after a series of frames, indicating the number of electron hole pairs generated in the photosensitive layer, is quantified and expressed The charge release per pixel of the photodetector pixel is less than about 15% for the percentage of imaging signal obtained under conditions of charge trapping and release being balanced.

In one aspect of this embodiment, the planarization layer can be at least one of a passivation layer, a dielectric layer, or an insulating layer. In one aspect of this embodiment, the surface recursion of the first electrode above the pixel circuit has a radius of curvature greater than 1/2 micron, greater than 1 micron, greater than 5 microns, greater than 10 microns, or greater than 100 microns.

In one aspect of this embodiment, the charge release of each photodetector pixel can be, for example, less than 10%, less than 5%, or less than 3%, depending on the degree of planarization desired or achieved.

In a sixth illustrative embodiment, a radiation sensor includes: a scintillation layer configured to emit photons when interacting with ionizing radiation; a photodetector including a first electrode in sequence , a photosensitive layer, and one of the light-emitting layers disposed close to the scintillation layer The second electrode of the photon. The photosensitive layer is configured to create an electron hole pair when interacting with a portion of the photons. The radiation sensor includes a pixel circuit electrically coupled to the first electrode and configured to measure an imaging signal indicative of one of the pairs of electron holes generated in the photosensitive layer; and including a planarization layer And disposed between the first electrode and the pixel circuit on the pixel circuit such that the first electrode is higher than a plane including the pixel circuit. The photodetector has a delay of each photodetector pixel, and the delay of each photodetector pixel is followed by a frame or a series of frames acquired under the condition of radiation An imaging signal released from the trapped state during the first frame acquired in the presence of radiation (the imaging signal indicates an electron hole pair generated in the photosensitive layer, and the imaging signal originates from one or more previous The amount of charge trapped in the frame is quantified and expressed as a percentage of the imaging signal from the previous frame, with a retardation of less than about 15% for each photodetector pixel.

In one aspect of this embodiment, the planarization layer can be at least one of a passivation layer, a dielectric layer, or an insulating layer. In one aspect of this embodiment, the surface recursion of the first electrode above the pixel circuit has a radius of curvature greater than 1/2 micron, greater than 1 micron, greater than 5 microns, greater than 10 microns, or greater than 100 microns.

In one aspect of this embodiment, the delay of each photodetector pixel can be, for example, less than 10%, less than 5%, or less than 3%, depending on the degree of planarization desired or achieved.

In a seventh illustrative embodiment, a radiation sensor includes: a scintillation layer configured to emit photons when interacting with ionizing radiation; a photodetector including a first electrode in sequence And a photosensitive layer, and a second electrode capable of transmitting photons disposed adjacent to the scintillation layer. The photosensitive layer is configured to create an electron hole pair when interacting with a portion of the photons. The radiation sensor includes a pixel circuit electrically coupled to the first electrode and configured to measure an imaging signal indicative of one of the pairs of electron holes generated in the photosensitive layer; and including a planarization layer Disposed on the pixel circuit between the first electrode and the pixel circuit such that the first electrode is higher than one of the pixel circuits surface. The first electrode can extend over a portion of the pixel circuit and can have a lateral edge, a longitudinal edge, and a corner at the intersection of the lateral edge and the longitudinal edge. At least one of the lateral edge and the longitudinal edge can be a sloped edge.

In one aspect of this embodiment, the corner may be a rounded corner connecting the lateral edge to the longitudinal edge. The sloped edge can have a radius of curvature greater than 1/2 micrometer, or greater than 1 micrometer, or greater than 5 micrometers, or greater than 10 micrometers or greater than 100 micrometers. In one aspect of this embodiment, the planarization layer can be at least one of a passivation layer, a dielectric layer, or an insulating layer.

In an eighth illustrative embodiment, a radiation sensor includes: a scintillation layer configured to emit photons when interacting with ionizing radiation; a photodetector pixel comprising a first in order An electrode, a photosensitive layer, and a second electrode capable of transmitting photons disposed adjacent to the scintillation layer. The photosensitive layer is configured to create an electron hole pair when interacting with a portion of the photons. The radiation sensor includes a pixel circuit electrically coupled to the first electrode and configured to measure an imaging signal indicative of one of the pairs of electron holes generated in the photosensitive layer; and including a passivation layer, It is disposed on the pixel circuit between the first electrode and the pixel circuit such that the first electrode is higher than a plane including the pixel circuit. The passivation layer has a first surface recursion that is higher than one of the pixel circuit elements. The second electrode has a second surface recursion that is higher than one of the first surface recursions. The second surface recursion has a radius of curvature greater than one of 1/2 microns.

The second surface recursion can have a radius of curvature greater than 1 micron, or greater than 5 microns, or greater than 10 microns or greater than 100 microns. The passivation layer can be a planarized passivation layer. The photosensitive layer can be a planarized photosensitive layer.

In a ninth illustrative embodiment, a radiation sensor includes: a scintillation layer configured to emit photons when interacting with ionizing radiation; a photodetector including a first electrode in sequence And a photosensitive layer, and a second electrode capable of transmitting photons disposed adjacent to the scintillation layer. The photosensitive layer is configured to create an electron hole pair when interacting with a portion of the photons. The radiation sensor includes a pixel circuit electrically connected to the first Electrodes and configured to measure an imaging signal indicative of one of the pairs of electron holes generated in the photosensitive layer; and including a planarization layer disposed on the pixel circuit at the first electrode and the pixel Between the circuits such that the first electrode is higher than a plane including the pixel circuit. A surface of at least one of the first electrode and the second electrode may at least partially overlap the pixel circuit and may exhibit no surface features indicative of the underlying pixel circuit.

In the first to ninth illustrative embodiments described above and in the embodiments discussed below, the planarization layer can then be planarized completely or partially over some features of the pixel circuit. The planarization layer can be at least one of a passivation layer, a dielectric layer, or an insulating layer. The surface recursion of the first electrode above the pixel circuit can have, for example, greater than 1/2 micron, greater than 1 micron, greater than 5 micron, greater than 10 micron, or greater than 100 depending on the degree of planarization desired or achieved. The radius of curvature of the micrometer. A metal plate can be placed on the scintillation layer. Additionally, in the first to ninth illustrative embodiments described above and in the embodiments discussed below, a dielectric via interconnect may extend through the planarization layer and connect the first electrode to the pixel circuitry. The surface reflex of the dielectric via interconnect in contact with the photosensitive layer can have a radius of curvature greater than 1/2 micron, greater than 1 micron, greater than 5 microns, greater than 10 microns, and greater than 100 microns.

In the first to ninth illustrative embodiments described above and in the embodiments discussed below, the photosensitive layer may be one of a p-i-n semiconductor stack, an n-i-p semiconductor stack, or a metal insulator semiconductor stack. The pixel circuit can include one of a thin film transistor, a diode, a capacitor, a resistor, a trace, a via, a control line, an address line, and a ground plane. The pixel circuit may be one of an amorphous semiconductor transistor or a polycrystalline semiconductor transistor or a microcrystalline semiconductor transistor. The pixel circuit can include at least one of an address transistor, an amplifier transistor, and a reset transistor. The pixel circuit may be at least one of amorphous germanium, low temperature amorphous germanium, and microcrystalline germanium. The pixel circuit may be at least one of: a germanium semiconductor, an oxide semiconductor, a chalcogenide semiconductor, a cadmium selenide semiconductor, an organic semiconductor, an organic small molecule or a polymer semiconductor, a carbon nanotube, or a graphite film, Or other semi-conductive materials.

In the first to ninth illustrative embodiments described above and in the embodiments discussed below, the photosensitive layer can be at least one of the following: 1) continuous sensitization across a plurality of photodetector pixels a layer, or 2) a discrete photosensitive layer associated with each of the plurality of photodetector pixels. The scintillation layer may be at least one of the following: CsI: Tl, Gd ₂ O ₂ S: Tb, CsI: Na, NaI: Tl, CaWO ₄ , ZnWO ₄ , CdWO ₄ , Bi ₄ Ge ₃ O ₁₂ , Lu _1.8 Yb _0.2 SiO ₅ :Ce, Gd ₂ SiO ₅ :Ce, BaFCl:Eu ²⁺ , BaSO ₄ :Eu ²⁺ , BaFBr:Eu ²⁺ ,LaOBr:Tb ³⁺ ,LaOBr:Tm ³⁺ ,La ₂ O ₂ S: Tb ³⁺ , Y ₂ O ₂ S: Tb ³⁺ , YTaO ₄ , YTaO ₄ : Nb, ZnS: Ag, (Zn, Cd) S: Ag, ZnSiO ₄ : Mn ²⁺ , CsI, LiI: Eu ^{2 +} , PbWO ₄ , Bi ₄ Si ₃ O ₁₂ , Lu ₂ SiO ₅ :Ce ³⁺ , YAlO ₃ :Ce ³⁺ , CsF, CaF ₂ :Eu ²⁺ , BaF ₂ , CeF ₃ , Y _1.34 Gd _0.6 O ₃ : Eu ³⁺ , Pr, Gd ₂ O ₂ S: Pr ³⁺ , Ce, SCG1, HFG: Ce ³⁺ (5%) and C ₁₄ H ₁₀ , or other scintillator materials.

In the first to ninth illustrative embodiments described above and in the embodiments discussed below, the radiation sensor can include a base substrate supporting the pixel circuit, the photodetector, and the scintillation layer. The radiation sensor can include a plurality of photodetector pixels arranged in a regular pattern on the base substrate. In one aspect of this embodiment, the photo-transmissive second electrode can form a bias plane for the plurality of photodetector pixels. A portion of the pixel circuit can be disposed on the base substrate in a gap region between adjacent photodetector pixels. This portion may include one of a thin film transistor, a diode, a capacitor, a resistor, a via, a trace, a control line, an address line, and a ground plane. The first electrode can have a slanted end that terminates near the gap region. Examples of preferred combinations of such features are provided below.

In the first to ninth illustrative embodiments described above and in the embodiments discussed below, a metal plate may be disposed on the second electrode that is transmissive to ionizing radiation or may be disposed on the second electrode that is transmissive to ionizing radiation. On the encapsulation layer. Additionally, the planarization layer can be at least partially over the array features, over the dielectric via interconnects connected to the source or drain of the TFT, over a single-stage in-pixel amplifier component, or at two-level pixels The inner amplifier element is planarized.

In a tenth illustrative embodiment, a radiation sensor includes a photoconductor detector that includes a first electrode, a photoconductive layer, and a second electrode that transmits ionizing radiation in sequence. The photoconductive layer is configured to create an electron hole pair upon interaction with ionizing radiation. The radiation sensor includes a pixel circuit electrically coupled to the first electrode and configured to measure an imaging signal indicative of one of the pairs of electron holes generated in the light guiding layer; and a planarization layer, It is disposed on the pixel circuit between the first electrode and the pixel circuit such that the first electrode is higher than a plane including the pixel circuit. A surface of at least one of the first electrode and the second electrode at least partially overlaps the pixel circuit and has a surface recursion higher than one of the features of the pixel circuit. The surface recursion has a radius of curvature greater than one of 1/2 microns.

In one aspect of this embodiment, the planarization layer can be at least one of a passivation layer, a dielectric layer, or an insulating layer. In one aspect of this embodiment, the surface recursion of the first electrode above the pixel circuit has a radius of curvature greater than 1/2 micron, greater than 1 micron, greater than 5 microns, greater than 10 microns, or greater than 100 microns. Additionally, the dielectric via interconnects can extend through the planarization layer and connect the first electrode to the pixel circuitry. The surface reflex of the dielectric via interconnect in contact with the photosensitive layer can have a radius of curvature greater than 1/2 micron, greater than 1 micron, greater than 5 microns, greater than 10 microns, and greater than 100 microns.

In one aspect of this embodiment, the pixel circuit can include one of a thin film transistor, a diode, a capacitor, a resistor, a trace, a via, a control line, an address line, and a ground plane. The pixel circuit may be one of an amorphous semiconductor transistor or a polycrystalline semiconductor transistor or a microcrystalline semiconductor transistor. The pixel circuit can include at least one of an address transistor, an amplifier transistor, and a reset transistor. The pixel circuit may be at least one of amorphous germanium, low temperature amorphous germanium, and microcrystalline germanium. The pixel circuit may be at least one of: a germanium semiconductor, an oxide semiconductor, a chalcogenide semiconductor, a cadmium selenide semiconductor, an organic semiconductor, an organic small molecule or a polymer semiconductor, a carbon nanotube, or a graphite film, Or other semi-conductive materials.

In one aspect of this embodiment, a metal plate can be disposed on the second electrode of the transmissive ionizing radiation or can be disposed on the encapsulating layer of the second electrode that transmits the ionizing radiation. Additionally, the planarization layer can be at least partially over the array features, over the dielectric via interconnects connected to the source or drain of the TFT, over a single-stage in-pixel amplifier component, or at two-level pixels The inner amplifier element is planarized.

In one aspect of this embodiment, the light guiding layer can be at least one of: 1) a continuous light guiding layer extending across a plurality of photoconductor detector pixels, or 2) detecting the plurality of light conductors A discrete photoconductive layer associated with each of the detector pixels. The radiation sensor can include a base substrate supporting the pixel circuit and the light guiding layer. The radiation sensor can include a plurality of photoconductor detector pixels arranged in a regular pattern on the base substrate. In one aspect of this embodiment, the second electrode that transmits the ionizing radiation forms a bias plane for the plurality of photoconductor detector pixels. A portion of the pixel circuit can be disposed on the base substrate in a gap region between adjacent photodetector pixels. This portion may include one of a thin film transistor, a diode, a capacitor, a resistor, a via, a trace, a control line, an address line, and a ground plane. The first electrode can have a slanted end that terminates near the gap region.

Accordingly, the tenth illustrative embodiment includes features similar to those of the first illustrative embodiment described above, but does not require the scintillator layer and the photosensitive layer in the first illustrative embodiment. Here, in the tenth illustrative embodiment, the photoconductive layer generates an electron hole pair when interacting with x-rays or other ionizing radiation. The photoconductive layer may include at least one of the following semiconductors: VB-VIB, VB-VIIB, IIB-VIB, IIB-VB, IIIB-VB, IIIB-VIB, IB-VIB, and IVB-VIIB, and more specifically, may comprise at least one _{of: a-Se, PbI 2,} HgI 2, PbO, CdZnTe, CdTe, Bi 2 S 3, Bi 2 Se 3, BiI 3, BiBr 3, CdS, CdSe, Hgs, Cd ₂ P ₃ , InAs, InP, In ₂ S ₃ , In ₂ Se ₃ , Ag ₂ S, PbI ₄ ^-2 and Pb ₂ I ₇ ^-3 .

Additionally, the features described above with regard to the first embodiment may be included in the tenth illustrative embodiment. This same generalization applies to the remaining embodiments below, and for the sake of clarity, this same generalization will be selectively repeated below. In addition, the radius of curvature, dark electricity described above The values and ranges of flow, charge trapping levels, charge release and retardation are suitably applied here. Examples of preferred combinations of such parameters are provided below.

In an eleventh illustrative embodiment, a radiation sensor includes a photoconductor detector that includes a first electrode, a photoconductive layer, and a second electrode that transmits ionizing radiation in sequence. The photoconductive layer is configured to create an electron hole pair upon interaction with ionizing radiation. The radiation sensor includes: a pixel circuit electrically coupled to the first electrode and configured to measure an imaging signal indicative of one of the pairs of electron holes generated in the light guiding layer; and a planarization layer And disposed between the first electrode and the pixel circuit on the pixel circuit such that the first electrode is higher than a plane including the pixel circuit. The planarization layer has a first surface recurve along a peripheral edge of a feature of the pixel circuit component. The first electrode has a second surface recursion, and the second surface is recurved higher than the first surface and is on a surface of the planarization layer opposite to the base substrate. The second surface recursion has a radius of curvature greater than one of 1/2 microns.

In a twelfth illustrative embodiment, a radiation sensor includes a photoconductor detector that includes a first electrode, a photoconductive layer, and a second electrode that transmits ionizing radiation in sequence. The photoconductive layer is configured to create an electron hole pair upon interaction with ionizing radiation. The radiation sensor includes: a pixel circuit electrically coupled to the first electrode and configured to measure an imaging signal indicative of one of the pairs of electron holes generated in the light guiding layer; and a planarization layer And disposed between the first electrode and the pixel circuit on the pixel circuit such that the first electrode is higher than a plane including the pixel circuit. The photoconductor detector has a dark current (normalized to a unit photodetector area) between the first electrode and the second electrode, the dark current being less than 10 pA/mm ² .

In one embodiment of this aspect of the embodiment, the dark current (normalized to unit photoconductor detector area) may be less than 5pA / mm ^2, or less than 1pA / mm ^2, or less than 0.5pA / mm ^2. The level of dark current is somewhat coupled to the degree of planarization discussed above and the radius of curvature of the surface recursion.

In a thirteenth illustrative embodiment, a radiation sensor includes a photoconductor detector that includes a first electrode, a photoconductive layer, and a second electrode that transmits ionizing radiation in sequence. The photoconductive layer is configured to create an electron hole pair upon interaction with ionizing radiation. The radiation sensor includes: a pixel circuit electrically coupled to the first electrode and configured to measure an imaging signal indicative of one of the pairs of electron holes generated in the light guiding layer; and a planarization layer And disposed between the first electrode and the pixel circuit on the pixel circuit such that the first electrode is higher than a plane including the pixel circuit. The photoconductor detector has a level of charge trapping for each photoconductor detector pixel, the level being lost due to capture during capture of a single radiographic frame (indicated in the photoconductive layer) The amount of electron holes generated is quantified and expressed as a percentage of the imaged signal obtained under conditions in which charge trapping and charge release are in equilibrium, and the bit of charge trapping of each photoconductor detector pixel Less than about 20%.

In one aspect of this embodiment, the level of charge trapping of each photoconductor detector pixel can be, for example, less than 15%, less than 10%, or less, depending on the degree of planarization desired or achieved. 5%.

In a fourteenth illustrative embodiment, a radiation sensor includes a photoconductor detector that includes a first electrode, a photoconductive layer, and a second electrode that transmits ionizing radiation in sequence. The photoconductive layer is configured to create an electron hole pair upon interaction with ionizing radiation. The radiation sensor includes: a pixel circuit electrically coupled to the first electrode and configured to measure an imaging signal indicative of one of the pairs of electron holes generated in the light guiding layer; and a planarization layer And disposed between the first electrode and the pixel circuit on the pixel circuit such that the first electrode is higher than a plane including the pixel circuit. The photoconductor detector has a charge release for each photoconductor detector pixel, and the charge release of each photoconductor detector pixel is balanced by the presence of radiation and between charge trapping and charge release. An imaging signal released from the trapped state during the first frame acquired in the absence of radiation after a series of frames acquired under conditions (indicating an electronic hole generated in the photoconductive layer) The amount is quantified and expressed as a percentage of the imaging signal obtained under conditions in which charge trapping and release are in equilibrium, and the charge release of each photoconductor detector pixel is less than about 15%.

In one aspect of this embodiment, the charge release of each photoconductor detector pixel can be, for example, less than 10%, less than 5%, or less than 3%, depending on the degree of planarization desired or achieved.

In a fifteenth illustrative embodiment, a radiation sensor includes a photoconductor detector that includes a first electrode, a photoconductive layer, and a second electrode that transmits ionizing radiation in sequence. The photoconductive layer is configured to create an electron hole pair upon interaction with ionizing radiation. The radiation sensor includes: a pixel circuit electrically coupled to the first electrode and configured to measure an imaging signal indicative of one of the pairs of electron holes generated in the light guiding layer; and a planarization layer And disposed between the first electrode and the pixel circuit on the pixel circuit such that the first electrode is higher than a plane including the pixel circuit. The photoconductor detector has a delay of each photoconductor detector pixel, and the delay of each photoconductor detector pixel is followed by a frame or a series of frames acquired with radiation An imaging signal released from the trapped state during the first frame acquired in the absence of radiation (the imaging signal indicates an electron hole pair generated in the photoconductive layer, and the imaging signal originates in one or The amount of charge trapped in the plurality of previous frames is quantified and expressed as a percentage of the imaging signal from the previous frame, with each photodetector pixel having a retardation of less than about 15%.

In one aspect of this embodiment, the retardation of each photoconductor detector pixel can be, for example, less than 10%, less than 5%, or less than 3%, depending on the degree of planarization desired or achieved.

In a sixteenth illustrative embodiment, a radiation sensor includes a photoconductor detector that includes a first electrode, a photoconductive layer, and a second electrode that transmits ionizing radiation in sequence. The photoconductive layer is configured to create an electron hole pair upon interaction with ionizing radiation. The radiation sensor includes a pixel circuit electrically coupled to the first electrode and configured to measure An imaging signal indicating one of the pair of electron holes generated in the light guiding layer; and a planarization layer disposed on the pixel circuit between the first electrode and the pixel circuit such that the first The electrode is higher than a plane including the pixel circuit. The first electrode extends over the pixel circuit and has a lateral edge, a longitudinal edge, and a corner at the intersection of the lateral edge and the longitudinal edge. At least one of the lateral edge and the longitudinal edge includes a sloped edge.

In a seventeenth illustrative embodiment, a radiation sensor includes a photoconductor detector that includes a first electrode, a photoconductive layer, and a second electrode that transmits ionizing radiation in sequence. The photoconductive layer is configured to create an electron hole pair upon interaction with ionizing radiation. The radiation sensor includes a pixel circuit electrically coupled to the first electrode and configured to measure an imaging signal indicative of one of the pairs of electron holes generated in the light guiding layer; and a passivation layer, It is disposed on the pixel circuit between the first electrode and the pixel circuit such that the first electrode is higher than a plane including the pixel circuit. The passivation layer has a first surface recursion that is higher than one of the pixel circuit elements. The second electrode has a second surface recursion that is higher than one of the first surface recursions. The second surface recursion has a radius of curvature greater than one of 1/2 microns.

The second surface recursion can have a radius of curvature greater than 1 micron, or greater than 5 microns, or greater than 10 microns or greater than 100 microns. The passivation layer can be a planarized passivation layer. The photosensitive layer can be a planarized photoconductive layer.

In an eighteenth embodiment, a radiation sensor includes a photoconductor detector that includes a first electrode, a photoconductive layer, and a second electrode that transmits ionizing radiation in sequence. The photoconductive layer is configured to create an electron hole pair upon interaction with ionizing radiation. The radiation sensor includes: a pixel circuit electrically coupled to the first electrode and configured to measure an imaging signal indicative of one of the pairs of electron holes generated in the light guiding layer; and a planarization layer And disposed between the first electrode and the pixel circuit on the pixel circuit such that the first electrode is higher than a plane including the pixel circuit. One surface of at least one of the first electrode and the second electrode may at least partially overlap the pixel circuit and may exhibit no Indicates the surface characteristics of the underlying pixel circuit.

In a nineteenth illustrative embodiment, a method for fabricating a radiation sensor includes: forming a pixel circuit component on a base substrate, and forming a planarization layer over the pixel circuit component, in the planarization Forming a hole in the layer to expose to one of the pixel circuit components, causing the patterned hole to be metallized, forming a first electrode in electrical contact with the metallized hole, and forming a pair on the first electrode One layer of light or ionizing radiation is sensitive. Forming the planarization layer to provide a surface recursion on a surface of the first electrode at least partially overlapping the pixel circuit, the surface recursion being higher than a characteristic of the pixel circuit, having a curvature greater than 1/2 micron radius.

In one aspect of this embodiment, a photosensitive layer and a second electrode capable of transmitting photons are formed on the first electrode, and a passivation layer is formed on the second electrode of the phototransmissive photo, and a A scintillation layer is formed on the passivation layer that is configured to emit photons when interacting with ionizing radiation. In this example, the photosensitive layer can be planarized or the photosensitive layer can be planarized prior to forming the second electrode that can transmit photons.

In a different aspect of this embodiment, a photoconductive layer is formed on the first electrode (the photoconductive layer is configured to generate an electron hole pair when interacting with x-rays or other ionizing radiation), and A second electrode transmissive ionizing radiation is formed on the photoconductive layer.

In these two aspects, a second electrode can be disposed on the passivation layer on the scintillation layer or on the encapsulation layer on the photoconductive layer. In these two aspects, a metal plate can be placed on the scintillation layer or on the encapsulation on the scintillation layer or on the encapsulation layer on the second electrode that can transmit ionizing radiation.

In one aspect of this embodiment, the planarization layer can be formed, for example, to have a curvature greater than 1 micrometer, greater than 5 micrometers, greater than 10 micrometers, or greater than 100 micrometers, depending on the degree of planarization desired or achieved. radius. The planarization layer can be formed by chemical mechanical polishing of the deposited passivation layer. Alternatively, the planarization layer can be formed by spin coating a passivation layer followed by chemical mechanical polishing of the passivation layer. Alternatively, by using spin coating in one (or A) depositing another passivation layer on top of the passivation layer and then chemical mechanical polishing the other (or second) passivation layer to form a planarization layer. The planarization layer can be at least partially over the array features, over the dielectric via interconnects connected to the source or drain of the TFT, over a single-stage in-pixel amplifier component, or in a two-stage pixel amplifier The component is flattened.

In one aspect of this embodiment, the end of the gap region between adjacent pixels of the first electrode proximate to the radiation sensor can be tilted. In one aspect of this embodiment, the metallized holes can be tapered, for example, depending on the degree of planarization desired or achieved to have a thickness greater than 1/2 micrometer, or greater than 1 micrometer, greater than 5 micrometers. a radius of curvature greater than 10 microns or greater than 100 microns.

In one aspect of the nineteenth embodiment, the features listed for the pixel circuit element and the photosensitive layer in the aspect of the first illustrative embodiment can be formed on the base substrate. For example, when a scintillation layer is formed, at least one of the following may be formed on the second electrode that can transmit photons: CsI: Tl, Gd ₂ O ₂ S: Tb, CsI: Na, NaI: Tl , CaWO ₄ , ZnWO ₄ , CdWO ₄ , Bi ₄ Ge ₃ O ₁₂ , Lu _1.8 Yb _0.2 SiO ₅ :Ce, Gd ₂ SiO ₅ :Ce, BaFCl:Eu ²⁺ , BaSO ₄ :Eu ²⁺ ,BaFBr:Eu ^{2 +} , LaOBr: Tb ³⁺ , LaOBr: Tm ³⁺ , La ₂ O ₂ S: Tb ³⁺ , Y ₂ O ₂ S: Tb ³⁺ , YTaO ₄ , YTaO ₄ : Nb, ZnS: Ag, (Zn, Cd S: Ag, ZnSiO ₄ : Mn ²⁺ , CsI, LiI: Eu ²⁺ , PbWO ₄ , Bi ₄ Si ₃ O ₁₂ , Lu ₂ SiO ₅ : Ce ³⁺ , YAlO ₃ : Ce ³⁺ , CsF, CaF ₂ :Eu ²⁺ , BaF ₂ , CeF ₃ , Y _1.34 Gd _0.6 O ₃ :Eu ³⁺ , Pr, Gd ₂ O ₂ S:Pr ³⁺ , Ce, SCGl, HFG: Ce ³⁺ (5%) and C ₁₄ H ₁₀ . A passivation layer can be formed on the second electrode prior to providing the scintillation layer. For example, when forming a photosensitive layer, at least one of the following is formed: 1) a continuous photosensitive layer extending across a plurality of photodetector pixels, or 2) and a plurality of photodetector pixels One of the associated discrete photosensitive layers.

For example, when forming a photoconductive layer, at least one of the following semiconductors may be formed on the first electrode: VB-VIB, VB-VIIB, IIB-VIB, IIB-VB, IIIB-VB, IIIB-VIB, IB-VIB and IVB-VIIB, or more specifically, at least one of: a-Se, PbI ₂ , HgI ₂ , PbO, CdZnTe, CdTe, Bi ₂ S ₃ may be formed on the first electrode. , Bi ₂ Se ₃ , BiI ₃ , BiBr ₃ , CdS, CdSe, HgS, Cd ₂ P ₃ , InAs, InP, In ₂ S ₃ , In ₂ Se ₃ , Ag ₂ S, PbI ₄ ^-2 and Pb ₂ I ₇ ^-3 . For example, when forming a light guiding layer, at least one of the following is formed: 1) a continuous light guiding layer extending across a plurality of photoconductor detector pixels, or 2) and the plurality of photoconductor detectors A discrete photoconductive layer associated with one of the pixels.

For example, when the pixel circuit element is formed, at least one of an amorphous semiconductor transistor or a microcrystalline semiconductor transistor or a polycrystalline semiconductor transistor may be formed on the base substrate. When the pixel circuit component is formed, at least one of the following may be formed on the base substrate: an address transistor, an amplifier transistor, and a reset transistor. When the pixel circuit component is formed, at least one of the following may be formed on the base substrate: a germanium semiconductor, an oxide semiconductor, a chalcogenide semiconductor, a cadmium selenide semiconductor, an organic semiconductor, an organic small molecule or a polymer semiconductor, Carbon nanotubes, or graphite films. When the pixel circuit component is formed, at least one of the following may be formed on the base substrate: a thin film transistor, a diode, a capacitor, a resistor, a trace, a via, a control line, an address line, and a ground. flat.

Further, in the nineteenth illustrative embodiment, a second electrode may be formed on a layer sensitive to light or ionizing radiation. A metal plate may be formed on the second electrode that transmits photons or on the encapsulation formed on the scintillation layer. In a nineteenth illustrative embodiment, a metal plate may be formed on the second electrode that is transmissive to ionizing radiation or on the encapsulating layer that is transmissive to the second electrode of ionizing radiation.

In a twentieth illustrative embodiment, a method for fabricating a radiation sensor includes: forming a pixel circuit component on a base substrate, forming a first electrode and a photosensitive layer over the pixel circuit to make the photosensitive The layer is planarized, a second electrode capable of transmitting photons is formed on the planarized photosensitive layer, and a scintillator layer is formed on the second electrode of the phototransmissible photon. At least one of the first electrode and the second electrode has a surface recursion that is higher than a characteristic of the pixel circuit, the surface being recurved, for example, depending on desired or achieved flatness To the extent that it has a radius of curvature greater than 1/2 micrometer, or greater than 1 micrometer, greater than 5 micrometers, greater than 10 micrometers, or greater than 100 micrometers.

In a twenty-first embodiment, a method for fabricating a radiation sensor includes: forming a pixel circuit component on a base substrate, forming a first electrode and a light guiding layer over the pixel circuit, The photoconductive layer is planarized, and a second electrode that transmits ionizing radiation is formed on the planarized photoconductive layer. The second electrode of the transmissive ionizing radiation has a surface recursion that is higher than one of the features of the pixel circuit, the surface recursion having a greater than 1/2 micron, for example, depending on the degree of planarization desired or achieved, Or a radius of curvature greater than 1 micron, greater than 5 microns, greater than 10 microns, or greater than 100 microns.

In a twenty-second illustrative embodiment, a method for fabricating a radiation sensor includes: forming a pixel circuit component on a base substrate, and forming a planarization layer over the pixel circuit component, Forming a hole in the layer to expose to one of the pixel circuit components, causing the patterned hole to be metallized, forming a first electrode in electrical contact with the metallized hole, and forming on the first electrode One layer that is sensitive to light or ionizing radiation. Forming the planarization layer provides a surface of a first electrode that at least partially overlaps the pixel circuit, the surface exhibiting no surface features indicative of the underlying pixel circuitry.

In a twenty-third illustrative embodiment, a method for fabricating a radiation sensor includes: forming a pixel circuit component on a base substrate, forming a first electrode and a photosensitive layer over the pixel circuit, The photosensitive layer is planarized, a second electrode capable of transmitting photons is formed on the planarized photosensitive layer, and a scintillator layer is formed on the second electrode of the phototransmissible photon. Flattening the photosensitive layer provides a surface of a second electrode that at least partially overlaps the pixel circuitry that does not exhibit surface features indicative of the underlying pixel circuitry.

In a twenty-fourth illustrative embodiment, a radiation sensor includes: a scintillation layer configured to emit photons when interacting with ionizing radiation; a photodetector comprising a first An electrode, a photosensitive layer, and one of the layers adjacent to the scintillation layer A second electrode that transmits photons. The photosensitive layer is configured to create an electron hole pair when interacting with a portion of the photons. The radiation sensor includes a pixel circuit electrically coupled to the first electrode and configured to measure an imaging signal indicative of one of the pairs of electron holes generated in the photosensitive layer, and the pixel circuit includes oxidation Semiconductor. The radiation sensor includes a planarization layer disposed between the first electrode and the pixel circuit on the pixel circuit such that the first electrode is higher than a plane including the pixel circuit. A surface of at least one of the first electrode and the second electrode at least partially overlaps the pixel circuit and has a surface recursion higher than one of the features of the pixel circuit. The surface recursion has a radius of curvature greater than one of 1/2 microns.

In one aspect of this embodiment, the oxide semiconductor includes at least one of zinc oxide, SnO ₂ , TiO ₂ , Ga ₂ O ₃ , InGaO, In ₂ O _{3 ,} and InSnO. The zinc-containing oxide may include at least one of ZnO, InGaZnO, InZnO, and ZnSnO. The oxide semiconductor may include at least one of an amorphous semiconductor or a polycrystalline semiconductor.

The twenty-fourth embodiment is thus similar in scope to the first embodiment and includes the first embodiment discussed above, and then examples of preferred combinations are described.

The surface recursion can have a radius of curvature greater than 1 micrometer, greater than 5 micrometers, greater than 10 micrometers, or greater than 100 micrometers, for example, depending on the degree of planarization desired or achieved. In another aspect, a surface of at least one of the first electrode and the second electrode can at least partially overlap the pixel circuit and can exhibit no surface features indicative of an underlying pixel circuit.

In one aspect of this embodiment, the address lines and data lines are disposed under the photodetector, and the planarization layer is disposed on the address lines and the data lines and the via holes of the address lines and the data lines. The planarization layer can then be wholly or partially over the features of the pixel circuit, over the array features, over the dielectric via interconnects connected to the source or drain of the TFT, within a single level of pixels The amplifier element is planarized over the amplifier element and/or over the amplifier elements within the two-stage pixel. The planarization layer can be at least one of a passivation layer, a dielectric layer, or an insulating layer.

In one aspect of this embodiment, the radiation sensor can include a photodetector The address line and the data line are located below, and the planarization layer is disposed on the address line and the data line and the via hole of the address line and the data line. Additionally, the dielectric via interconnects can extend through the planarization layer and connect the first electrode to the pixel circuitry. The surface reflex of the dielectric via interconnect in contact with the photosensitive layer can have a radius of curvature greater than 1/2 micron, greater than 1 micron, greater than 5 microns, greater than 10 microns, and greater than 100 microns.

In one aspect of this embodiment, the photosensitive layer can be one of a p-i-n semiconductor stack, an n-i-p semiconductor stack, or a metal insulator semiconductor stack. The pixel circuit can include one of a thin film transistor, a diode, a capacitor, a resistor, a trace, a via, a control line, an address line, and a ground plane. The pixel circuit may further include one of an amorphous semiconductor transistor or a polycrystalline semiconductor transistor or a microcrystalline semiconductor transistor. The pixel circuit can include at least one of an address transistor, an amplifier transistor, and a reset transistor. The pixel circuit may further include an element made of at least one of an amorphous germanium, a low temperature amorphous germanium, and a microcrystalline germanium. The pixel circuit may further include an element made of at least one of: germanium semiconductor, chalcogenide semiconductor, cadmium selenide semiconductor, organic semiconductor, organic small molecule or polymer semiconductor, carbon nanotube, or graphite Film, or other semi-conductive material.

In one aspect of this embodiment, the photosensitive layer can be at least one of: 1) a continuous photosensitive layer extending across a plurality of photodetector pixels, or 2) and the plurality of photodetectors A discrete photosensitive layer associated with each of the pixels. The scintillation layer may be at least one of the following: CsI: Tl, Gd ₂ O ₂ S: Tb, CsI: Na, NaI: Tl, CaWO ₄ , ZnWO ₄ , CdWO ₄ , Bi ₄ Ge ₃ O ₁₂ , Lu _1.8 Yb _0.2 SiO ₅ :Ce, Gd ₂ SiO ₅ :Ce, BaFCl:Eu ²⁺ , BaSO ₄ :Eu ²⁺ , BaFBr:Eu ²⁺ ,LaOBr:Tb ³⁺ ,LaOBr:Tm ³⁺ ,La ₂ O ₂ S: Tb ³⁺ , Y ₂ O ₂ S: Tb ³⁺ , YTaO ₄ , YTaO ₄ : Nb, ZnS: Ag, (Zn, Cd) S: Ag, ZnSiO ₄ : Mn ²⁺ , CsI, LiI: Eu ^{2 +} , PbWO ₄ , Bi ₄ Si ₃ O ₁₂ , Lu ₂ SiO ₅ :Ce ³⁺ , YAlO ₃ :Ce ³⁺ , CsF, CaF ₂ :Eu ²⁺ , BaF ₂ , CeF ₃ , Y _1.34 Gd _0.6 O ₃ : Eu ³⁺ , Pr, Gd ₂ O ₂ S: Pr ³⁺ , Ce, SCG1, HFG: Ce ³⁺ (5%) and C ₁₄ H ₁₀ , or other scintillator materials.

In one aspect of this embodiment, the radiation sensor can include a base substrate supporting the pixel circuit, the photodetector, and the scintillation layer, and can include a plurality of light detections arranged on the base substrate in a regular pattern. Pixel. In one aspect of this embodiment, the photo-transmissive second electrode can form a bias plane for the plurality of photodetector pixels. A portion of the pixel circuit can be disposed on the base substrate in a gap region between adjacent photodetector pixels. This portion may include one of a thin film transistor, a diode, a capacitor, a resistor, a via, a trace, a control line, an address line, and a ground plane. In one aspect of this embodiment, the first electrode can have a sloped end that terminates near the gap region.

In one aspect of this embodiment, the dark current (normalized to unit photodetector area) between the first electrode and the second electrode that can transmit photons can be less than 10 pA/mm ² , or less than 5 pA/mm. ^2, or less than 1pA / mm ^2, or less than 0.5pA / mm ^2. The level of dark current is somewhat coupled to the degree of planarization discussed above and the radius of curvature of the surface recursion. In one aspect of this embodiment, the electric field in the region of the photosensitive layer closest to the surface recursion may be more than 60% of the electric field in the photosensitive layer between a pair of parallel first and second electrodes. And below 300%. The change in the electric field is coupled to some extent to the degree of planarization discussed above and the radius of curvature of the surface recursion.

In one aspect of this embodiment, the sensor can include a metal plate disposed on the scintillation layer.

In one aspect of this embodiment, the level of charge trapping of each photodetector pixel (which is quantified by the amount of the imaging signal lost due to trapping during a single radiographic frame, And expressed as a percentage of the imaging signal obtained under conditions in which charge trapping and charge release are in equilibrium), for example, may be less than 20%, may be less than 15%, less than 10% depending on the degree of planarization desired or achieved. Or less than 5%.

In one aspect of this embodiment, the charge release of each photodetector pixel is obtained by a series of frames obtained with radiation and under equilibrium with charge trapping and charge release. Subsequent period of the first frame acquired in the absence of radiation, The amount of the imaging signal released from the trapping state is quantified and expressed as a percentage of the imaging signal obtained under conditions in which charge trapping and release are in equilibrium) may, for example, depend on the degree of planarization desired or achieved Less than 15%, less than 10%, less than 5% or less than 3%.

The photodetector has a delay of each photodetector pixel, and the delay of each photodetector pixel is followed by a frame or a series of frames acquired under the condition of radiation An imaging signal released from the trapped state during the first frame acquired in the presence of radiation (the imaging signal indicates an electron hole pair generated in the photosensitive layer, and the imaging signal originates from one or more previous The amount of charge trapped in the frame is quantified and expressed as a percentage of the imaging signal from the previous frame, with a retardation of less than about 15% for each photodetector pixel. In one aspect of this embodiment, the delay of each photodetector pixel can be, for example, less than 10%, less than 5%, or less than 3%, depending on the degree of planarization desired or achieved.

In a twenty-fifth illustrative embodiment, a radiation sensor includes a photoconductor detector having a first electrode, a photoconductive layer, and a second electrode that transmits ionizing radiation in sequence. The photoconductive layer is configured to create an electron hole pair upon interaction with ionizing radiation. The radiation sensor includes a pixel circuit electrically coupled to the first electrode and configured to measure an imaging signal indicative of one of the pairs of electron holes generated in the light guiding layer, and the pixel circuit includes oxidation Semiconductor. The radiation sensor includes a planarization layer disposed between the first electrode and the pixel circuit on the pixel circuit such that the first electrode is higher than a plane including the pixel circuit. A surface of at least one of the first electrode and the second electrode at least partially overlaps the pixel circuit and has a surface recursion higher than one of the features of the pixel circuit.

In one aspect of this embodiment, the oxide semiconductor includes at least one of zinc oxide, SnO ₂ , TiO ₂ , Ga ₂ O ₃ , InGaO, In ₂ O _{3 ,} and InSnO. The zinc-containing oxide may include at least one of ZnO, InGaZnO, InZnO, and ZnSnO. The oxide semiconductor may include at least one of an amorphous semiconductor or a polycrystalline semiconductor.

The twenty-fifth embodiment is thus similar in scope to the tenth embodiment and includes the tenth embodiment discussed above, and then examples of preferred combinations are described.

In one aspect of this embodiment, the planarization layer can be at least one of a passivation layer, a dielectric layer, or an insulating layer. In one aspect of this embodiment, the surface of the first electrode or the second electrode that is higher than the surface of the pixel circuit has a recursion greater than 1/2 micrometer, greater than 1 micrometer, greater than 5 micrometers, greater than 10 micrometers, or greater than 100 micrometers. Radius of curvature. In another aspect, a surface of at least one of the first electrode and the second electrode can at least partially overlap the pixel circuit and can exhibit no surface features indicative of an underlying pixel circuit.

In one aspect of this embodiment, the address line and the data line are disposed under the photoconductor detector, and the planarization layer is disposed on the address line and the data line and the via hole of the address line and the data line. . Additionally, the dielectric via interconnects can extend through the planarization layer and connect the first electrode to the pixel circuitry. The surface reflex of the dielectric via interconnect in contact with the photosensitive layer can have a radius of curvature greater than 1/2 micron, greater than 1 micron, greater than 5 microns, greater than 10 microns, and greater than 100 microns.

In one aspect of this embodiment, the pixel circuit can include one of a thin film transistor, a diode, a capacitor, a resistor, a trace, a via, a control line, an address line, and a ground plane. The pixel circuit may further include one of an amorphous semiconductor transistor or a polycrystalline semiconductor transistor or a microcrystalline semiconductor transistor. The pixel circuit can include at least one of an address transistor, an amplifier transistor, and a reset transistor. The pixel circuit may further include an element made of at least one of an amorphous germanium, a low temperature amorphous germanium, and a microcrystalline germanium. The pixel circuit may further include an element made of at least one of: germanium semiconductor, chalcogenide semiconductor, cadmium selenide semiconductor, organic semiconductor, organic small molecule or polymer semiconductor, carbon nanotube, or graphite Film, or other semi-conductive material.

In one aspect of this embodiment, a metal plate can be disposed on the second electrode of the transmissive ionizing radiation or can be disposed on the encapsulating layer of the second electrode that transmits the ionizing radiation. Additionally, the planarization layer can be at least partially over the array features, connected to the TFT Above the source or drain dielectric via interconnects, planarize over the single-stage in-pixel amplifier components or over the two-level pixel amplifier components.

In one aspect of this embodiment, the light guiding layer can be at least one of: 1) a continuous light guiding layer extending across a plurality of photoconductor detector pixels, or 2) detecting the plurality of light conductors A discrete photoconductive layer associated with each of the detector pixels. The radiation sensor can include a base substrate supporting the pixel circuit and the light guiding layer. The radiation sensor can include a plurality of photoconductor detector pixels arranged in a regular pattern on the base substrate. In one aspect of this embodiment, the second electrode that transmits the ionizing radiation forms a bias plane for the plurality of photoconductor detector pixels. A portion of the pixel circuit can be disposed on the base substrate in a gap region between adjacent photodetector pixels. This portion may include one of a thin film transistor, a diode, a capacitor, a resistor, a via, a trace, a control line, an address line, and a ground plane. The first electrode can have a slanted end that terminates near the gap region.

Thus, in the twenty-fifth illustrative embodiment, the photoconductive layer produces an electron hole pair when interacting with x-rays or other ionizing radiation. The photoconductive layer may include at least one of the following semiconductors: VB-VIB, VB-VIIB, IIB-VIB, IIB-VB, IIIB-VB, IIIB-VIB, IB-VIB, and IVB-VIIB, and more specifically, may comprise at least one _{of: a-Se, PbI 2,} HgI 2, PbO, CdZnTe, CdTe, Bi 2 S 3, Bi 2 Se 3, BiI 3, BiBr 3, CdS, CdSe, HgS, Cd ₂ P ₃ , InAs, InP, In ₂ S ₃ , In ₂ Se ₃ , Ag ₂ S, PbI ₄ ^-2 and Pb ₂ I ₇ ^-3 .

In one aspect of this embodiment, the dark current (normalized to unit photoconductor detector area) between the first electrode and the second electrode may be less than 10 pA/mm ² , or less than 5 pA/mm ² , or Less than 1 pA/mm ² , or less than 0.5 pA/mm ² . The level of dark current is somewhat coupled to the degree of planarization discussed above and the radius of curvature of the surface recursion.

In one aspect of this embodiment, the level of charge trapping of each photodetector pixel is quantified by the amount of the imaging signal lost during capture during a single radiographic frame. And expressed as a condition in which charge trapping and charge release are in equilibrium The percentage of imaging signal obtained can be, for example, less than 20%, less than 15%, less than 10%, or less than 5%, depending on the degree of planarization desired or achieved.

In one aspect of this embodiment, the charge release of each photoconductor detector pixel is obtained by a series of pictures obtained with radiation and under equilibrium with charge trapping and charge release. During the first frame acquired after the frame in the absence of radiation, the amount of the imaging signal released from the trapped state is quantified and expressed as an imaging signal obtained under conditions in which charge trapping and release are in equilibrium. The percentage) may, for example, be less than 15%, may be less than 10%, less than 5%, or less than 3%, depending on the degree of planarization desired or achieved.

The photoconductor detector has a delay of each photoconductor detector pixel, and the delay of each photoconductor detector pixel is followed by a frame or a series of frames acquired with radiation An imaging signal released from the trapped state during the first frame acquired in the absence of radiation (the imaging signal indicates an electron hole pair generated in the photoconductive layer, and the imaging signal originates in one or The amount of charge trapped in the plurality of previous frames is quantified and expressed as a percentage of the imaging signal from the previous frame, with each photodetector pixel having a retardation of less than about 15%. In one aspect of this embodiment, the retardation of each photoconductor detector pixel can be, for example, less than 10%, less than 5%, or less than 3%, depending on the degree of planarization desired or achieved.

In a twenty-sixth illustrative embodiment, a method for fabricating a radiation sensor includes: forming a pixel circuit component on a base substrate, wherein the pixel circuit comprises an oxide semiconductor; above the pixel circuit component Forming a planarization layer; forming a hole in the planarization layer to expose to one of the pixel circuit components; metallizing the patterned hole; forming a first electrode in electrical contact with the metallization hole And forming a layer sensitive to light or ionizing radiation on the first electrode. The planarization layer provides a surface recursion that is higher than a characteristic of the pixel circuit on a surface of the first electrode that at least partially overlaps the pixel circuit. The surface recursion may, for example, depend on the desired or achieved flattening process The degree of curvature has a radius of curvature greater than 1/2 micron, greater than 1 micron, greater than 5 microns, greater than 10 microns, or greater than 100 microns.

In one aspect of this embodiment, the oxide semiconductor includes at least one of zinc oxide, SnO ₂ , TiO ₂ , Ga ₂ O ₃ , InGaO, In ₂ O _{3 ,} and InSnO. The zinc-containing oxide may include at least one of ZnO, InGaZnO, InZnO, and ZnSnO. The oxide semiconductor may include at least one of an amorphous semiconductor or a polycrystalline semiconductor.

In one aspect of this embodiment, a photosensitive layer and a second electrode capable of transmitting photons are formed on the first electrode, and a passivation layer is formed on the second electrode of the phototransmissive photo, and a A scintillation layer is formed on the passivation layer that is configured to emit photons when interacting with ionizing radiation. In this example, the photosensitive layer can be planarized or the photosensitive layer can be planarized prior to forming the second electrode that can transmit photons.

In a different aspect of this embodiment, a photoconductive layer is formed on the first electrode (the photoconductive layer is configured to generate an electron hole pair when interacting with x-rays or other ionizing radiation), and A second electrode transmissive ionizing radiation is formed on the photoconductive layer.

In these two aspects, a second electrode can be disposed on the passivation layer on the scintillation layer or on the encapsulation layer on the photoconductive layer. In these two aspects, a metal plate can be placed on the scintillation layer or on the encapsulation on the scintillation layer or on the encapsulation layer on the second electrode that can transmit ionizing radiation.

In one aspect of this embodiment, the planarization layer can be formed, for example, to have a greater than 1/2 micron, greater than 1 micron, greater than 5 micron, greater than 10 micron, depending on the degree of planarization desired or achieved. Or a radius of curvature greater than 100 microns. The planarization layer can be formed by chemical mechanical polishing of the deposited passivation layer. Alternatively, the planarization layer can be formed by spin coating a passivation layer followed by chemical mechanical polishing of the passivation layer. Alternatively, the planarization layer can be formed by depositing another passivation layer on top of a (or first) passivation layer using spin coating and then chemical mechanical polishing the other (or second) passivation layer. The planarization layer can be at least partially over the array features, at the dielectric via interconnects connected to the source or drain of the TFT Above, planarize on top of the single-stage in-pixel amplifier components or on the two-stage in-pixel amplifier components.

In one aspect of this embodiment, the end of the gap region between adjacent pixels of the first electrode proximate to the radiation sensor can be tilted. In one aspect of this embodiment, the metallized holes can be tapered, for example, depending on the degree of planarization desired or achieved to have a thickness greater than 1/2 micrometer, or greater than 1 micrometer, greater than 5 micrometers. a radius of curvature greater than 10 microns or greater than 100 microns.

In one aspect of this embodiment, the features listed for the pixel circuit component and the photosensitive layer in the aspect of the first illustrative embodiment may be formed on the base substrate. For example, when a scintillation layer is formed, at least one of the following may be formed on the second electrode that can transmit photons: CsI: Tl, Gd ₂ O ₂ S: Tb, CsI: Na, NaI: Tl , CaWO ₄ , ZnWO ₄ , CdWO ₄ , Bi ₄ Ge ₃ O ₁₂ , Lu _1.8 Yb _0.2 SiO ₅ :Ce, Gd ₂ SiO ₅ :Ce, BaFCl:Eu ²⁺ , BaSO ₄ :Eu ²⁺ ,BaFBr:Eu ^{2 +} , LaOBr: Tb ³⁺ , LaOBr: Tm ³⁺ , La ₂ O ₂ S: Tb ³⁺ , Y ₂ O ₂ S: Tb ³⁺ , YTaO ₄ , YTaO ₄ : Nb, ZnS: Ag, (Zn, Cd S: Ag, ZnSiO ₄ : Mn ²⁺ , CsI, LiI: Eu ²⁺ , PbWO ₄ , Bi ₄ Si ₃ O ₁₂ , Lu ₂ SiO ₅ : Ce ³⁺ , YAlO ₃ : Ce ³⁺ , CsF, CaF ₂ :Eu ²⁺ , BaF ₂ , CeF ₃ , Y _1.34 Gd _0.6 O ₃ :Eu ³⁺ , Pr, Gd ₂ O ₂ S:Pr ³⁺ , Ce, SCGl, HFG: Ce ³⁺ (5%) and C ₁₄ H ₁₀ . For example, when forming a photosensitive layer, at least one of the following is formed: 1) a continuous photosensitive layer extending across a plurality of photodetector pixels, or 2) and a plurality of photodetector pixels One of the associated discrete photosensitive layers.

For example, when forming a photoconductive layer, at least one of the following semiconductors may be formed on the first electrode: VB-VIB, VB-VIIB, IIB-VIB, IIB-VB, IIIB-VB, IIIB-VIB, IB-VIB and IVB-VIIB, or more specifically, at least one of: a-Se, PbI ₂ , HgI ₂ , PbO, CdZnTe, CdTe, Bi ₂ S ₃ may be formed on the first electrode. , Bi ₂ Se ₃ , BiI ₃ , BiBr ₃ , CdS, CdSe, HgS, Cd ₂ P ₃ , InAs, InP, In ₂ S ₃ , In ₂ Se ₃ , Ag ₂ S, PbI ₄ ^-2 and Pb ₂ I ₇ ^-3 . For example, when forming a light guiding layer, at least one of the following is formed: 1) a continuous light guiding layer extending across a plurality of photoconductor detector pixels, or 2) and the plurality of photoconductor detectors A discrete photoconductive layer associated with one of the pixels.

Further, when the pixel circuit element is formed on the base substrate, the pixel circuit may further include one of an amorphous semiconductor transistor or a polycrystalline semiconductor transistor or a microcrystalline semiconductor transistor. The pixel circuit can include at least one of an address transistor, an amplifier transistor, and a reset transistor. The pixel circuit may further include an element made of at least one of an amorphous germanium, a low temperature amorphous germanium, and a microcrystalline germanium. The pixel circuit may further include an element made of at least one of: germanium semiconductor, chalcogenide semiconductor, cadmium selenide semiconductor, organic semiconductor, organic small molecule or polymer semiconductor, carbon nanotube, or graphite Film, or other semi-conductive material.

Numerous modifications and variations of the present invention are possible in light of the above teachings. Therefore, it is to be understood that the invention may be practiced otherwise than as specifically described herein.

Figure 1. Figure 1 is a schematic three-dimensional representation of one of the a-Si TFTs. View the top of the TFT from the bevel. Although the description of the TFT is general, the figure also depicts the address lines required in the case where the TFT is an address switch in the AMFPI pixel. Thus, the figure illustrates a section of the gate address line (at the point where it is connected to the gate of the TFT) and a section of the data address line (at the point where it is connected to the drain of the TFT) . The channel of the TFT has a width of 15 μm and a length of 10 μm as indicated by the dashed arrows. The continuous bottom dielectric layer and the a-Si layer are illustrated as being largely transparent to allow the underlying features to be visible. In addition, for clarity of presentation, the pattern is magnified 4 times in a direction perpendicular to the substrate with respect to the direction parallel to the substrate, and only a portion of the thickness of the substrate is depicted. The plane defined by the black solid line frame superimposed on the drawing indicates the position of the cross-sectional view appearing in FIG. Other marked elements in this figure are described in the description of Figure 2.

Figure 2. Figure 2 is a schematic cross-sectional view of the a-Si TFT shown in Figure 1. The position of this cross section corresponds to the plane defined by the wireframe in Fig. 1, and the convention of the grayscale shading of the elements of the TFT substantially corresponds to the convention used in Fig. 1. For clarity of presentation, the pattern has been magnified 8 times in a direction perpendicular to the substrate relative to the direction parallel to the substrate, and only portions of the substrate thickness are depicted. Marking is used to indicate the substrate, the gate, the source and the drain of the TFT, the bottom dielectric layer and the top dielectric layer in the TFT, the a-Si layer forming the channel of the TFT, and to complete the n-type transistor The structure of the n ⁺ type doped a-Si material.

Figure 3. Figure 3 is a schematic three-dimensional representation of one of the forms of poly-Si TFT. View the top of the TFT from the bevel. Although the description of the TFT is general, the figure also depicts the address lines required in the case where the TFT is an address switch in the AMFPI pixel. Therefore, the figure illustrates a section of the gate address line (at the point where it is connected to the poly-Si gate of the TFT), and a section of the data address line (established to the TFT at the via hole) At the point of the bungee joint.) The channel of the TFT has a width of 15 μm and a length of 10 μm as indicated by the dashed arrow. The continuous passivation layer (passivation #1) is illustrated as being largely transparent to allow the underlying features to be visible. In addition, for clarity of presentation, the pattern is magnified 4 times in a direction perpendicular to the substrate with respect to the direction parallel to the substrate, and only a portion of the thickness of the substrate is depicted. The plane defined by the black solid line frame superimposed on the drawing indicates the position of the cross-sectional view appearing in FIG. Other marked elements in this figure are described in the description of FIG.

Figure 4. Figure 4 is a schematic cross-sectional view of the poly-Si TFT shown in Figure 3. The position of this cross section corresponds to the plane defined by the wireframe in Fig. 3 and the convention of the grayscale shadow of the elements of the TFT substantially corresponds to the convention used in Fig. 3. For clarity of presentation, the pattern has been magnified 8 times in a direction perpendicular to the substrate relative to the direction parallel to the substrate, and only portions of the substrate thickness are depicted. Marking is used to indicate substrate, buffer passivation, gate dielectric, gate of the TFT (which is formed by poly-Si in this case), and activity to form the TFT channel (under the gate dielectric) The poly-Si layer and the source and drain of the TFT (indicated by the angled lines superimposed over the portion of the poly-Si layer) and the passivation layer over the TFT ("passivation #1"). The position of this cross-sectional view does not show the gate address line and the poly-Si gate Connection.

Figure 5. Figure 5 is a schematic circuit diagram of a pixel from an active matrix imaging array that uses incident radiation inter-connect detection. The area defined by the straight dashed line indicates the boundary of the pixel.

Figure 6. Figure 6 is a schematic cross-sectional view of one of the patterns of inter-connected detection pixels with a discrete photodiode. This represents a specific structure implementation of the pixel circuit of Figure 5 and is referred to as a baseline architecture. The view is parallel to the direction of the gate address line, and the gate address line is not visible in this cross section. The distance between the vertical dashed lines represents the width of one pixel. The layers and features in this description are not drawn to scale for clarity.

Figure 7. Figure 7 is a schematic circuit diagram of a pixel from an active matrix imaging array that uses direct detection of incident radiation. The conventions for marks, lines and symbols are similar to those used in Figure 5. The area defined by the straight dashed line indicates the boundary of the pixel.

Figure 8. Figure 8 is a schematic cross-sectional view of one of the direct detection pixels. The view is parallel to the direction of the gate address line, and the gate address line is not visible in this cross section. The conventions for marks, lines, symbols and arrows are similar to those used in Figure 6. The distance between the vertical dashed lines represents the width of one pixel. The layers and features in this description are not drawn to scale for clarity. Moreover, the influence of the TFT and via holes on the uniformity of the topography of the photoconductor is not explained.

Figure 9. Figure 9 is a schematic representation of indirect detection of four adjacent pixels of an active matrix array. The design of such pixels represents the implementation of the pixel circuits and the implementation of the baseline architecture illustrated in Figures 5 and 6, respectively. Each pixel in the diagram reveals varying degrees of architectural detail of the design. In the pixel at the bottom of the figure, only the gate address line and the gate of the addressed TFT are shown. In the pixel on the left hand side, the source and drain of the addressed TFT and the bottom electrode covered by the n ⁺ -type doped a-Si layer of the photodiode are added. In the right-hand side pixel, a combined layer of n ⁺ -type doped a-Si, pure a-Si, p ⁺ -type doped a-Si, and top optically transparent electrode collectively referred to as a photodiode stack is illustrated. In this design, the bottom electrode extends slightly beyond the edge of the stack. In the pixel at the top of the figure, a data address line connected to the drain of the addressed TFT by the via hole and a bias line connected to the top electrode of the photodiode by the via hole have been added.

Figure 10. Figure 10 is a photomicrograph of a top surface of a pair of indirect-detected active matrix arrays in a single pixel region. In each case, the design represents the implementation of the baseline architecture illustrated in Figure 6. (a) is a photomicrograph of a pixel from an earlier array having a design corresponding to that illustrated in FIG. (b) is a photomicrograph of a pixel from a later array design in which the optical fill factor has been increased by optimization of the pixel design. In each photomicrograph, the addressed TFT is positioned in a region bounded by a circle superimposed on the image, and also indicates the location of the gate address line, the data address line, the bias line, and the photodiode. Note that in each photomicrograph, the top surface of the portion of the photodiode that is not covered by the bias line appears to be very uniform.

Figure 11. Figure 11 is a schematic illustration of a cross-sectional view of an inter-detected pixel design with discrete out-of-plane photodiode structures. The view is parallel to the direction of the gate address line, and the gate address line is not visible in this cross section. The symbols, lines, arrows, symbols, and conventions in the drawings are similar to the ones, lines, arrows, symbols, and conventions used in FIG. The distance between the vertical dashed lines represents the width of one pixel. The layers and features in this description are not drawn to scale for clarity. Moreover, the influence of the TFT and the via hole on the uniformity of the topology of the photodiode is not explained.

Figure 12. Figure 12 is a schematic illustration of a cross-sectional view of an inter-connected detection pixel design with a continuous out-of-plane photodiode structure. The view is parallel to the direction of the gate address line, and the gate address line is not visible in this cross section. The symbols, lines, arrows, symbols, and conventions in the drawings are similar to the ones, lines, arrows, symbols, and conventions used in FIG. The distance between the vertical dashed lines represents the width of one pixel. The layers and features in this description are not drawn to scale for clarity. Moreover, the topology of the TFT and the via hole to the photodiode is not described. The impact of consistency.

Figure 13. Figure 13 is a schematic representation of indirect detection of four adjacent pixels of an active matrix array. The design of such pixels represents the implementation and architecture of the pixel circuits illustrated in Figures 5 and 12, respectively. Each pixel in the diagram reveals varying degrees of architectural detail of the design. In the pixel at the bottom of the figure, only the gate address line and the gate of the addressed TFT are shown. In the left-hand side pixel, the source and drain of the addressed TFT, the data address line, and the rear contact have been added. In the right hand side pixel, the bottom electrode is illustrated, including a via hole that connects this electrode to the back contact (which resides in the region marked by the dashed line). In the pixmap at the top of the figure, a simple representation of the structure of a continuous photodiode is shown, where the n ⁺ type doped layer is not visible and the remaining layers of the photodiode are not distinguished.

Figure 14. Figure 14 is a photomicrograph of the top surface of the active matrix array in the region of a single pixel. The design represents the implementation of the architecture illustrated in Figure 12 and corresponds to the presentation in Figure 13. Indicates the position of the gate address line, the data address line, the bottom electrode, and the via hole that connects the electrode to the back contact. Note that the various details visible in the image correspond to the topology of the top of the continuous photodiode structure.

Figure 15. Figure 15 is a schematic circuit diagram of a pixel from an interferometric detection array based on an active pixel design with a single-stage in-pixel amplifier. Indicates data address line, gate address line, reset TFT (TFT _RST ), source follower TFT (TFT _SF ), addressed TFT (TFT _ADDR ), and photodiode (PD with capacitor C) _PD ). V _BIAS is the magnitude of the reverse bias voltage applied to the top electrode of the photodiode, and V _G-RST , V _D-RST and V _CC are other voltages used to operate the array. Both of the TFTs, TFT _RST and TFT _ADDR are illustrated as having a dual gate structure. All TFTs are n-type transistors.

Figure 16. Figure 16 is a schematic representation of four adjacent pixels based on an active pixel design inter-connected detection array using a poly-Si TFT. The design of such pixels represents the implementation of the pixel circuit illustrated in FIG. The TFT in this figure has a structure similar to that of the poly-Si TFT illustrated in FIGS. 3 and 4. The photodiode has a continuous structure similar to the structure shown in FIG. Each pixel in the diagram reveals varying degrees of architectural detail of the design. In the pixel at the bottom of the figure, the gate of each TFT (formed by poly-Si), the active poly-Si for forming the channel of each TFT, the gate address line, and the reset are shown. The reset voltage line in the operation of the TFT. In the left-hand side pixels, data address lines, rear contacts, supply voltage lines, and various traces and via holes have been added. In the right hand side pixel, the bottom electrode is illustrated, including the via hole that connects this electrode to the back contact. In the pixels at the top of the figure, a simple representation of the structure of a continuous photodiode is shown in which the patterned n ⁺ type doped layer is not visible and the remaining layers of the photodiode are not distinguished.

Figure 17. Figure 17 is a photomicrograph of the top surface of the indirect detection array in the region of a single pixel. This design represents the implementation of the pixel circuit illustrated in Figure 15 and corresponds to the presentation in Figure 16. The photomicrographs are oriented such that the direction of the gate address lines and data address lines of the array (which are below the continuous photodiode of the design) are vertically and horizontally aligned along the plane of the image, respectively. A box formed by a thick dashed line (indicating the boundary of one complete pixel) and a thin horizontal dashed line (indicating the position of the cross-sectional view appearing in later figures) is overlaid on the image. Note that the various details visible in the image correspond to the topology of the top of the continuous photodiode structure.

Figure 18. Figure 18 is a schematic circuit diagram of a pixel from an interferometric detection array based on an active pixel design with a two-stage in-pixel amplifier. Indicates data address line, gate address line, reset TFT (TFT _RST ), common source amplifier TFT (TFT _CSA ), payload TFT (TFT _AL ), source follower TFT (TFT _SF ), Addressing TFT (TFT _ADDR ), feedback capacitor (having capacitor C _FB ), and photodiode (PD, having capacitance C _PD ). V _BIAS is the magnitude of the reverse bias voltage applied to the top electrode of the photodiode, and V _G-RST , V _G-AL , V _{CC ,} and V _GND are other voltages used to operate the array. Both of the TFTs, TFT _RST and TFT _ADDR are illustrated as having a dual gate structure. In these TFTs, the TFT _AL is a p-type transistor and the remaining transistor is an n-type.

Figure 19. Figure 19 is a schematic representation of four adjacent pixels based on an active pixel design inter-connected detection array using a poly-Si TFT. The design of such pixels represents the implementation of the pixel circuit illustrated in FIG. The TFT in this figure has a structure similar to that of the poly-Si TFT illustrated in FIGS. 3 and 4. The photodiode has a continuous structure similar to the structure shown in FIG. Each pixel in the diagram reveals varying degrees of architectural detail of the design. In the pixels at the bottom of the figure, the gates of various TFTs (formed by poly-Si), the active poly-Si for forming the vias of each TFT, and the gate address lines are shown. In the left-hand side pixels, data bit lines, rear contacts, and various traces and via holes have been added. In the right hand side pixel, the bottom electrode is illustrated, including the via hole that connects this electrode to the back contact. In the pixels at the top of the figure, a simple representation of the structure of a continuous photodiode is shown in which the patterned n ⁺ type doped layer is not visible and the remaining layers of the photodiode are not distinguished.

Figure 20. Figure 20 is a photomicrograph of the top surface of the indirect detection array in the region of a single pixel. This design represents the implementation of the pixel circuit illustrated in Figure 18 and corresponds to the presentation in Figure 19. The photomicrographs are oriented such that the direction of the gate address lines and data address lines of the array (which are below the continuous photodiode of the design) are vertically and horizontally aligned along the plane of the image, respectively. A box formed by a thick dashed line (indicating the boundary of one complete pixel) and a thin horizontal dashed line (indicating the position of the cross-sectional view appearing in later figures) is overlaid on the image. Note that the various details visible in the image correspond to the topology of the top of the continuous photodiode structure.

Figure 21. Figure 21 is a cross-sectional view of the calculation of an inter-connected detection array based on a single-stage in-pixel amplifier design using a poly-Si TFT. The design represents the implementation of the pixel circuit illustrated in Figure 15 and corresponds to the description in Figures 16 and 17. The position of this cross section corresponds to a plane perpendicular to the top surface of the array, passing through the thin horizontal dashed line appearing in Figure 17. The horizontal field of view corresponds to a distance slightly larger than a single pixel, and the vertical dashed line The distance between them represents the width of one pixel. This description (produced by deposition, photolithography, etching, and computational simulation of other processes used in the fabrication of arrays) demonstrates the order, structure, and native topology of the various features and materials in the array. For clarity of presentation, the pattern has been magnified 8 times in a direction perpendicular to the substrate relative to the direction parallel to the substrate, and only portions of the substrate thickness are depicted.

Figure 22. Figure 22 is a cross-sectional view of a calculated inter-detection array based on a two-stage in-pixel amplifier design using a poly-Si TFT. This design represents the implementation of the pixel circuit illustrated in FIG. 18 and corresponds to the description in FIGS. 19 and 20. The position of the two cross-sections corresponds to a plane perpendicular to the top surface of the array, passing through the thin horizontal dashed lines appearing in Figure 20. (a) The horizontal field of view in this description corresponds to a distance slightly larger than a single pixel, and the distance between vertical dashed lines represents the width of one pixel. (b) The horizontal field of view in this description corresponds to the same distance as the field of view in Fig. 21, and only a portion of one pixel is shown. These descriptions (produced by deposition, photolithography, etching, and computational simulations of other processes used in the fabrication of arrays) demonstrate the order, structure, and native topology of the various features and materials in the array. For clarity of presentation, the pattern has been magnified 8 times in a direction perpendicular to the substrate relative to the direction parallel to the substrate, and only portions of the substrate thickness are depicted.

Figure 23. Figure 23 is a top plan view of a single-stage in-pixel amplifier array in a single pixel region, corresponding to the design illustrated in Figure 16. (a) is an illustration generated from the same computational simulation used to generate Figure 21. (b) is a photomicrograph of the actual realized surface of the array, which corresponds to the photomicrograph in FIG. Note that the various details visible in each view correspond to the native topology at the top of the continuous photodiode structure.

Figure 24. Figure 24 is a top plan view of a two-stage intra-pixel amplifier array in a single pixel region, corresponding to the design illustrated in Figure 19. (a) is an illustration generated from the same computational simulation used to generate Figure 22. (b) is a photomicrograph of the actual realized surface of the array, which corresponds to the photomicrograph in Figure 20. Note that the various details visible in each view correspond to the native topology at the top of the continuous photodiode structure.

Figure 25. Figure 25 is a diagram illustrating the general concept of radius of curvature, which can be applied to the characterization of changes in the flatness of the surface. The degree of sharpness (i.e., suddenness) of the change in surface flatness is quantified by the radius arc r . The sharper (i.e., more abrupt) change described in (a) has a radius of curvature that is shorter than the less sharp change depicted in (b). The ratio of the formula is such that r ₂ = 10 × r ₁ .

Figure 26. Figure 26 is a cross-sectional view of the calculation of the inter-connected detection array based on a single-stage in-pixel amplifier design. (a) This view corresponds to the cross-sectional view appearing in Figure 21, but achieves a more consistent topology of the photodiode structure via complete planarization of one of the passivation layers (passivation #2). (b) This view also corresponds to the cross-sectional view appearing in FIG. 21, but achieves a more consistent topology of the photodiode structure via partial planarization of passivation #2.

Figure 27. Figure 27 is a cross-sectional view of the calculation of the inter-connected detection array based on a two-stage in-pixel amplifier design. The views in (a) and (b) correspond to the cross-sectional views appearing in Figures 22(a) and 22(b), respectively, but via one of the passivation layers (passivation #2) Flattening to achieve a more consistent topology of the photodiode structure.

Figure 28. Figure 28 is a cross-sectional view of the calculation of the inter-connect detection array based on a single-stage in-pixel amplifier design. This view corresponds to the cross-sectional view appearing in FIG. 26(a), but achieves a photodiode structure by smoothing the peripheral edge of the bottom electrode (formed by the metal #2 layer) of the photodiode. Consistent topology.

Figure 29. Figure 29 is a cross-sectional view of the calculation of the inter-connect detection array based on a two-stage in-pixel amplifier design. This view corresponds to the cross-sectional view appearing in FIG. 27(a), but achieves a photodiode structure by smoothing the peripheral edge of the bottom electrode (formed by the metal #2 layer) of the photodiode. Consistent topology.

Figure 30. Figure 30 is a cross-sectional view of the calculation of the inter-connected detection array based on a single-stage in-pixel amplifier design. This view corresponds to the cross-sectional view appearing in FIG. 28, but the photodiode is achieved by narrowing the via holes connecting the bottom electrode and the rear contact of the photodiode and filling the via holes with metal. An even more consistent topology of the volume structure.

Figure 31. Figure 31 is a top plan view of a single-pixel in-pixel amplifier array in a single pixel region, generated from a computational simulation. (a) is an explanation corresponding to the same view shown in Fig. 23 (a). (b) is a description corresponding to the description in (a), but achieves a more consistent topology of the photodiode structure via complete planarization of one of the passivation layers (passivation #2). (c) is a description corresponding to the description in (b), but a more uniform topology of the photodiode structure is achieved by smoothing the peripheral edge of the bottom electrode of the photodiode. (d) is the description corresponding to the description in (c), but the photoperiod is achieved by narrowing the via holes connecting the bottom electrode and the rear contact of the photodiode and filling the via holes with metal. An even more consistent topology of the polar body structure.

Figure 32. Figure 32 is a top plan view of a two-stage intra-pixel amplifier array in a single pixel region, generated from a computational simulation. (a) is an explanation corresponding to the same view shown in Fig. 24 (a). (b) is a description corresponding to the description in (a), but achieves a more consistent topology of the photodiode structure via complete planarization of one of the passivation layers (passivation #2). (c) is a description corresponding to the description in (b), but a more uniform topology of the photodiode structure is achieved by smoothing the peripheral edge of the bottom electrode of the photodiode. (d) is the description corresponding to the description in (c), but the photoperiod is achieved by narrowing the via holes connecting the bottom electrode and the rear contact of the photodiode and filling the via holes with metal. An even more consistent topology of the polar body structure.

Figure 33. Figure 33 is a cross-sectional view of the calculation of the inter-connected detection array based on a single-stage in-pixel amplifier design. (a) This view corresponds to the cross-sectional view appearing in FIG. 21, but achieves a more uniform top electrode of the photodiode structure via complete planarization of the pure a-Si layer in the photodiode. Topology. (b) This view corresponds to the cross-sectional view appearing in FIG. 21, but achieves a more uniform top electrode of the photodiode structure by planarizing a portion of the pure a-Si layer in the photodiode. Topology.

Figure 34. Figure 34 is a top view of a single-pixel in-pixel amplifier array in a single pixel region, generated from a computational simulation. (a) corresponds to the same view as shown in Figure 23(a) instruction of. (b) is a description corresponding to the description in (a), but achieves a more uniform topology of the photodiode structure by planarizing a portion of the pure a-Si layer in the photodiode. (c) is a description corresponding to the description in (b), but achieves a more consistent topology of the photodiode structure via complete planarization of the pure a-Si layer in the photodiode.

PD‧‧‧Photoelectric diode

TFT‧‧‧pixel addressed transistor

Claims (27)

A radiation sensor comprising: a scintillation layer configured to emit photons when interacting with ionizing radiation; a photodetector comprising, in order, a first electrode, a photosensitive layer, and proximate to the scintillation layer a second electrode capable of transmitting photons; the photosensitive layer configured to generate an electron hole pair when interacting with a portion of the photons; a pixel circuit electrically coupled to the first electrode and configured to Detecting an imaging signal indicating the pair of electron holes generated in the photosensitive layer; a planarization layer disposed on the pixel circuit between the first electrode and the pixel circuit such that the first electrode is high And a surface of the at least one of the first electrode and the second electrode at least partially overlapping the pixel circuit and having a surface recursion higher than a characteristic of the pixel circuit. A sensor as claimed in claim 1, wherein the planarization layer is planarized at least partially over the features of the pixel circuit. The sensor of claim 1, wherein the planarization layer is at least partially over the array features, over a dielectric via interconnect connected to a source or drain of the TFT, in a single stage pixel amplifier Above the component, or above the amplifier elements of the two-stage pixel, or the pixel circuit that allows a single photon count is flattened. The sensor of claim 1, wherein the planarization layer comprises at least one of a passivation layer, a dielectric layer, or an insulating layer. The sensor of claim 1, further comprising: an address line and a data line disposed under the photodetector; and the planarization layer is disposed on the address line and the data line and the address On the vias of the lines and data lines. The sensor of claim 1, wherein the dark current normalized to the unit photodetector area between the first electrode and the second electrode of the phototransmissible photon is less than 10 pA/mm ² . A radiation sensor comprising: a photoconductor detector comprising, in order, a first electrode, a photoconductive layer, and a second electrode transmissive ionizing radiation, and the photoconductive layer is configured to interact with ionizing radiation Generating an electron hole pair; a pixel circuit electrically coupled to the first electrode and configured to measure an imaging signal indicative of the pair of electron holes generated in the light guiding layer; a planarization layer disposed Between the first electrode and the pixel circuit on the pixel circuit such that the first electrode is higher than a plane including one of the pixel circuits; and a surface of at least one of the first electrode and the second electrode At least partially overlapping the pixel circuit and having a surface recursion that is higher than features of the pixel circuit. A sensor as claimed in claim 7, wherein the planarization layer is planarized at least partially over the features of the pixel circuit. The sensor of claim 7, wherein the planarization layer is at least partially over the array features, over the dielectric via interconnects connected to the source or drain of the TFT, in a single stage pixel amplifier Above the component, or above the amplifier elements of the two-stage pixel, or the pixel circuit that allows a single photon count is flattened. The sensor of claim 7, wherein the planarization layer comprises at least one of a passivation layer, a dielectric layer, or an insulating layer. The sensor of claim 7, further comprising: an address line and a data line disposed under the photoconductor detector; and the planarization layer is disposed on the address line and the data line and the same On the via of the address line and the data line. The sensor of claim 7, wherein the dark current normalized to the unit photoconductor detector area between the first electrode and the second electrode is less than 10 pA/mm ² . A radiation sensor comprising: a scintillation layer configured to emit photons when interacting with ionizing radiation; a photodetector comprising, in order, a first electrode, a photosensitive layer, and a second electrode of the phototransmissible photon disposed adjacent to the scintillation layer The photosensitive layer is configured to generate an electron hole pair upon interaction with a portion of the photons; a pixel circuit electrically coupled to the first electrode and configured to measure an indication in the photosensitive layer And the planarization layer is disposed on the pixel circuit between the first electrode and the pixel circuit such that the first electrode is higher than a plane including the pixel circuit; Wherein at least one of the first electrode and the second electrode at least partially overlaps the pixel circuit, and wherein the planarization layer is planarized at least partially over features of the pixel circuit. The radiation sensor of claim 13, wherein: the pixel circuit comprises a thin film transistor array; and the planarization layer is planarized at least partially over the thin film transistor array. The radiation sensor of claim 13, wherein: the pixel circuit comprises a dielectric via interconnect; and the planarization layer is planarized at least partially over the dielectric via interconnect. The radiation sensor of claim 13, wherein: the pixel circuit comprises an in-pixel amplifier component; and the planarization layer is at least partially planarized over the in-pixel amplifier component. The radiation sensor of claim 13, wherein: the pixel circuit comprises an address line and a data line disposed under the photodetector; and the planarization layer is disposed on the address line and the data line. A radiation sensor comprising: a photoconductor detector comprising, in order, a first electrode, a photoconductive layer, and a second electrode transmissive ionizing radiation, and the photoconductive layer is configured to generate an electron hole pair when interacting with ionizing radiation; the pixel circuit Electrically coupled to the first electrode and configured to measure an imaging signal indicative of the pair of electron holes generated in the light guiding layer; and a planarization layer disposed on the pixel circuit at the Between an electrode and the pixel circuit such that the first electrode is higher than a plane including the pixel circuit; wherein at least one of the first electrode and the second electrode at least partially overlaps the pixel circuit, and wherein The planarization layer is planarized at least partially over features of the pixel circuit. The radiation sensor of claim 18, wherein: the pixel circuit comprises a thin film transistor array; and the planarization layer is planarized at least partially over the thin film transistor array. The radiation sensor of claim 18, wherein: the pixel circuit comprises a dielectric via interconnect; and the planarization layer is planarized at least partially over the dielectric via interconnect. The radiation sensor of claim 18, wherein: the pixel circuit comprises an in-pixel amplifier component; and the planarization layer is planarized at least partially over the in-pixel amplifier component. The radiation sensor of claim 18, wherein: the pixel circuit comprises an address line and a data line disposed under the photoconductor detector; and the planarization layer is disposed on the address line and the data line. A method of fabricating a radiation sensor, the method comprising: forming a pixel circuit component on a base substrate; Forming a planarization layer over the pixel circuit elements to at least partially planarize over features of the pixel circuit elements; forming holes in the planarization layer to expose connections to the pixel circuit elements; The hole is metallized; a first electrode is formed in electrical contact with the metallized hole; and a layer sensitive to light or ionizing radiation is formed on the first electrode. The method of claim 23, wherein: forming the pixel circuit component comprises forming a thin film transistor array; and forming the planarization layer comprises planarizing at least partially over the thin film transistor array. The method of claim 23, wherein: forming the pixel circuit component comprises forming a dielectric via interconnect; and forming the planarization layer comprises planarizing at least partially over the dielectric via interconnect. The method of claim 23, wherein: forming the pixel circuit component comprises forming an in-pixel amplifier component; and forming the planarization layer comprises planarizing at least partially over the in-pixel amplifier component. The method of claim 23, wherein forming the pixel circuit component comprises forming an address line and a data line; and forming the planarization layer comprises forming the planarization layer on the address line and the data line.