CN102576715B

CN102576715B - Photodiode in X-ray plane imager and other sensor constructions and the method for the topological uniformity being used for photodiode and other sensor constructions improving in X-ray plane imager based on thin film electronic device

Info

Publication number: CN102576715B
Application number: CN201080034885.7A
Authority: CN
Inventors: L·E·安托努克
Original assignee: University of Michigan
Current assignee: University of Michigan
Priority date: 2009-06-17
Filing date: 2010-06-16
Publication date: 2016-11-30
Anticipated expiration: 2030-06-16

Abstract

A kind of radiation sensor includes: a flash layer, and this flash layer is configured to when interacting launch photon with ionizing radiation；And a photoelectric detector, it includes the first electrode, photosensitive layer and the second electrode of the transmissive photon that arrange neighbouring with flash layer successively.This photosensitive layer is configured to when the part with described photon interacts produce electron hole pair.This radiation sensor includes: image element circuit, is electrically connected to the first electrode, and is configured to measure instruction imaging signal of produced described electron hole pair in photosensitive layer；And planarization layer, it is arranged on the image element circuit between the first electrode and image element circuit so that the first electrode is including above the plane of image element circuit.The surface of at least one in described first electrode and described second electrode is the most overlapping with this image element circuit, and has the surface warp portion above the feature of this image element circuit.Described surface warp portion has the radius of curvature more than 1/2 micron.

Description

Photodiode in X-ray plane imager and other sensor constructions and For improve based on thin film electronic device the photodiode in X-ray plane imager and its The method of the topological uniformity of his sensor construction

Research or the statement of development about federal funding

The EB000558 that the present invention is based on being authorized by NIH props up in government Hold down and make.U.S. government has certain rights in the invention.

To Cross-Reference to Related Applications

The application and following application about and require following application according to the regulation of 35 U.S.C.119 Priority: on June 17th, 2009 submit to entitled " PHOTODIODE AND OTHER SENSOR STRUCTURES IN FLAT-PANEL X-RAY IMAGERS AND METHOD FOR IMPROVING TOPOLOGICAL UNIFORMITY OF THE PHOTODIODE AND OTHER SENSOR STRUCTURES IN FLAT-PANEL X-RAY IMAGERS BASED ON THIN-FILM ELECTRONICS " U.S. Provisional Patent Application 61/213,530, this U.S. The complete disclosure of state's temporary patent application case is incorporated herein by reference.

Technical field

Present invention relates in general to be designed to detect incident ionizing radiation to form image Device.

Background technology

In the field of x-ray imaging, imager based on active matrix imaging array is usually used in In numerous medical treatment and non-medical applications.Unless otherwise indicated herein, term " active matrix " To be used to refer to the principle two-dimensional grid of imaging pixel being addressed by switch, wherein, Each pixel there is search switch.Imager based on active matrix imaging array will be called " active matrix flat-panel imager " (AMFPI), or it is referred to as " active matrix imaging more concisely Device ".It addition, term " active matrix array " and " active matrix imaging will be interchangeably used Array ".

AMFPI generally merges single array, and this single array comprises the tool of the effect to ionizing radiation There is the material of high resistance.But, AMFPI includes two adjacent battle arrays of arranged in parallel sometimes Row, or it is arranged in four adjacent array of square or rectangle.Active matrix imager universal One reason of property and serviceability is: can with acceptable productivity ratio, rational cost and Significantly beyond manufacturing by the size of traditional crystalline silicon (c-Si) technology size in the cards Array.In the case of c-Si technology, imaging array (such as, the charge-coupled image sensor of pixelation (CCD), cmos sensor, CMOS active pixel sensor and passive pixel sensor) finally by with Size (being up to about 300mm at present) in the silicon wafer manufactured limits.It is made up of crystalline silicon CCD, cmos sensor and CMOS active pixel sensor and passive pixel sensor are generally made Cause the size with less than about 4cm × 4cm.Have about although this device being manufactured into The size that 20cm × 20cm is the biggest, but this device is difficult to produce and production cost height.This Outward, although large-area devices can be manufactured by laying little area c-Si array, but so Introduce extra significant engineering problem, difficulty and cost.In the case of AMFPI, though Active matrix array so can be manufactured into two pixel × two pixels, and (it will be less than 1cm × 1 Cm) the least, but it is used for the active matrix array of AMFPI generally with straight at about 10cm × 10cm Size to about 43cm × 43cm manufactures, and this is greatly beyond pixelation The scope of c-Si imaging array.Forbid that producing the biggest active matrix becomes additionally, do not exist Picture array (such as, be equivalent to the size of the AMLCD (AMLCD) of maximum, Maximum AMLCD be manufactured into diagonal be about 108 inches the biggest) Technical reason.

In active matrix imaging array, addressed the two-dimensional grid of imaging pixel by thin film switch Lattice.This array includes a thin substrate, manufactures imaging pixel in this thin substrate.Each pixel is closed And have such circuit, in the circuit, search switch is connected to the pixel of a certain form and deposits Storage capacitor.Each switch is usually taken the form of thin film transistor (TFT) (TFT), but also can take The form of the combination of thin film diode or plural thin film diode.Although simple battle array Row design is only associated with the single switch purpose for addressing to each pixel, but more complicated Design can include extra component within the pixel, and described extra component is in order to improve Performance and/or extended parallel port device ability.Additionally, can close on array base palte in described pixel outside And other component.These elements can be configured to perform the function of such as the following: Voltage in control gate address wire；Multiplexing is from the signal of data wire；Or for Relevant other purposes of operation of array.

Material for manufacturing array includes being formed the various of the feature of such as the following Metal: address wire, contact, trace, through hole, electrode surface and light blocking surface to address wire, And the source electrode of TFT, drain electrode and grid.Can use such as aluminum, copper, chromium, molybdenum, tantalum, titanium, The metal of tungsten, tin indium oxide and gold, and the alloy of these materials, such as TiW, MoCr And AlCu.The thickness of the given metal level deposited during manufacture to array can be at about 10nm To several μm.Passivation layer can include such as silicon oxynitride (Si₂N₂O), silicon nitride (Si₃N₄), polyimides and the material of the polymer of BCB (BCB).Sink during manufacture The thickness of the given passivation layer amassed to array surface can be at about 100nm until the scope of 10 μm In.Electrolyte in device (such as, TFT and capacitor) can include such as silicon nitride (Si₃N₄)、 Silicon dioxide (SiO₂), non-crystalline silicon and amorphous silicon nitride (a-Si₃N₄: H) material.In the phase of manufacture Between the thickness of given dielectric layer that deposits to array surface can be at the model of about 1nm to several μm In enclosing.Generally, use that multiple metal level, passivation layer and dielectric layer come in manufacturing array is each Plant component.

Semi-conducting material for TFT (and diode switch) most typically be amorphous silicon hydride (a-Si), but alternatively microcrystal silicon, polysilicon (polycrystalline-Si), chalkogenide or cadmium selenide (CdSe), All these materials are suitable for large-area treatment, thus allow to manufacture large area array.This In the case of, substrate can be made up of the material of such as the following: glass (such as, Corning 7059,1737F, 1737G, about 1mm are thick), or quartz (about 1mm is thick), or Thin Stainless Steel Sheet (about 25 to 500 μ m-thick).The manufacture of array circuit relates to following operation: use area deposition Technology deposit on substrate continuous layer of material (such as, semiconductor layer, metal level, dielectric layer and Passivation layer), area deposition technology be such as plasma enhanced chemical vapor deposition (PECVD), Low-pressure chemical vapor deposition (LPCVD), chemical gaseous phase deposition (CVD), physical vapour deposition (PVD) (PVD), sputtering and spin coating.In the case of polycrystalline-Si, for producing the one of this quasiconductor Common methods by: made the a-Si material crystalline previously deposited by base laser.It addition, make Feature (such as TFT, diode, the photoelectricity two of circuit is formed with the combination of photoetching with etching technique Pole pipe, capacitor, trace, through hole, address wire and these features of contact to address wire).

Or, can take to be suitable for its of extensive deposition for these semi-conducting materials switched The form of his material (such as low temperature a-Si, organic molecule or polymer semiconductor).Low temperature A-Si uses PECVD, LPCVD and PVD to deposit, and organic molecule and polymer Quasiconductor can use area deposition technology or printing technology to deposit.For these semi-conducting materials, Substrate can be thin, flexible (by such as polyimides (PI) or PEN The material sheet of (PEM, about 25 to 200 μ m-thick) is made).Or, glass, quartz can be used Or stainless steel substrate.One in photoetching, etching, reducing color printing and additive color printing technology can be used Kind or a combination thereof form the feature of array circuit.Can be used for its of TFT and other devices His semi-conducting material includes CNT and Graphene.Can be used for TFT and other devices Other semi-conducting materials include that oxide semiconductor, described oxide semiconductor include (but not limiting In) ZnO, InGaZnO, InZnO, ZnSnO (with any other oxide containing Zn), SnO₂、TiO₂、Ga₂O₃、InGaO、In₂O₃And InSnO.These oxides known are partly led Body exists with amorphous state or polycrystalline form, and is suitable for the present invention when available.For all classes The quasiconductor of type, these materials are used with its free from admixture form, and are made with doped forms With, to provide p-doping or n-type doped semiconductor materials.

TFT has grid, source electrode and drain electrode.Flow through partly leading of TFT between the source and drain The value of the electric current of bulk channel is by many factors control, and described factor is such as the width of TFT channel Degree and length, the mobility of quasiconductor in raceway groove, put between grid and source electrode Voltage difference between value and the polarity, and source electrode and drain electrode of voltage.To putting on grid The manipulation of voltage allows to make transistor highly conductive (being described as " on ") or the most non-conductive (quilt It is described as "off").

Fig. 1 to Fig. 4 illustrates a-Si and the example of polycrystalline-Si TFT.Fig. 1 is diagram a-Si TFT A kind of schematic diagram of the structure of form.Fig. 2 is the plane corresponding to being indicated by the wire frame in Fig. 1 The schematic cross-sectional view of position.The symmetry of the structure of this a-Si TFT makes this cross section Figure will keep not to a great extent for any position of the width along transistor of wire frame Become.Fig. 3 is the schematic diagram of the structure of a kind of form of diagram polycrystalline-Si TFT.Shown version Originally there is single grid, but, plural grid is also possible.Fig. 4 be corresponding to by The schematic cross-sectional view of the position of the plane of the wire frame instruction in Fig. 3.With institute in Fig. 1 and Fig. 2 The a-Si TFT of diagram compares, and polycrystalline-Si TFT illustrated in Fig. 3 and Fig. 4 is due to through hole Exist and there is the symmetry of lower degree, so that the cross-sectional view of transistor is for wire frame Other positions along the width of transistor will change significantly.

Active matrix imager generally includes: (a) active matrix imaging array；This battle array of (b) overlying The material layer of row, it is used as x-ray transducer；C () external electrical device, it is by being positioned The engagement pad of the end of data/address line and grid address wire and be connected to this array.These electronics Some electronic devices in device are in close proximity to the periphery of array and position, and provide numeral to patrol Volume, this Digital Logic is in order to the voltage needed for assist control operation array and timing, and amplify, The analogue signal that multiplexing and digitized are extracted along data/address line from pixel.These electricity Sub-device also includes operating the Voltage Supply Device needed for array and periphery electronic device, and in order to Allow the digital and electronic interface of communication between described electronic device and one or more computer； D () one or more computer, it is in order to send control information to described electronic device, from institute State electronic device and receive digital pixel information, make operation and the radiation from x-ray source of array Transmit and synchronize, and process, show and store this image-forming information；(e) software, firmware and other Coded command, it is in described computer and in the Digital Logic of described electronic device.

Array base palte, thin film electronic device and x-ray transducer are the most relatively thin, and a combination thereof is thick Degree is less than 1cm.So allow together with periphery electronic device, these elements are configured to an encapsulation, This encapsulation has the most close thickness of about 1cm, is similar to Standard x-ray can or computer The thickness of radiophotography (CR) box.The electronics x-ray imager with these profiles is usually referred to as Flat-panel imager (FPI), the technology no matter imager is based on how.In order to according to other skills The flat-panel imager difference that art (such as, laying type cmos sensor) produces, broadly belongs to The descriptive term of imager based on thin film electronic device is " thin film flat-panel imager ".Make With under the particular case of the imager of active matrix array, term " active matrix flat-panel imager (AMFPI) it is " suitable.

Pixel for active matrix imaging array is arranged in columns and rows.For using TFT switch Array, and for given pixel column, the grid along all addressing TFT of these row all connects To common grid address wire, each of which pixel shows a gate line.To applying to each grid The external control of the voltage of address wire is because so allowing control along all addressing TFT's of these row Electric conductivity.For given pixel column, the drain electrode along all addressing TFT of this row is connected to Shared data address wire, each of which pixel column has a data/address line.

During the operation of AMFPI, during the transmission of x-ray, all addressing TFT protect Hold non-conductive, in order to allow to be collected in pixel storage capacitor imaging signal.By making row In addressing TFT conduction, generally every time string pixel ground reads and is stored in these capacitors Imaging signal.So allow to adopt with the self-corresponding data/address line of complete space resolution of array Sample imaging signal.For data-oriented address wire, the signal of each sampling is put by preamplifier Big and from analog to digital converter digitized, this preamplifier and this simulation are to numeral conversion Device both of which is positioned array external.Certainly, can be sampled into from plural successive column every time Image signal, so reduces readout time, but with reduce spatial resolution as cost.

Active matrix imager most commonly combines x-ray source operation, but it also can be with other forms Ionized radiation source operate together, described ionizing radiation be such as gamma ray, electronics, proton, Neutron, alpha particle and heavy ion.The pel spacing (it is equal to the width of a pixel) of array With the frame per second ability of size, array and imager and the beam energy of x-ray source, filtering and time Between characteristic all be chosen so as to mate imaging applications needs.Breast imaging for many forms Application (include breast imaging, the box-like photography of breast fault groups, breast computer tomography, and Image guided tissue slice), available have about 25 μm until the battle array of pel spacing of about 200 μm The x-ray beam of row and about 15 to 40kVp performs diagnostic and interventional medical imaging.Right (breast imaging, chest is included in many radiophotographies of form, cryptoscope and tomography application The box-like photography of fault groups, Dual energy imaging, vasography method, Interventional therapy, tissue slice Method, the imaging of extremity, department of pediatrics imaging, cardiac imaging, abdominal part, chest, head, cervical region, The conical beam computer tomography of tooth, and simulation in radiotherapy, position, examine Test and guarantee with quality), it is also possible to there are about 75 μm until the battle array of pel spacing of about 1000 μm The x-ray beam of row and about 50 to 150kVp performs diagnostic and interventional medical imaging.Separately Outward, available about 300 μm are until the pel spacing of about 1000 μm and controlling for external beam radiation The treatment beam treated performs imaging of medical.In this case, radioactive source can be that Co-60 source is (flat All energy are about 1.25MeV), or from linear accelerator or produce about 3 until 50MV In the range of the output of accelerator of any other types of million volts of radiation.Also can control by short distance Treatment source performs to use the imaging of medical of active matrix imager, and described brachytherapy sources is such as Caesium-137 (¹³⁷Cs), iodine-125 (¹²⁵I), Iridium-192 source (¹⁹²Ir), palladium-103 (¹⁰³Pd), Strontium-90 (⁹⁰Sr) With 90Y (⁹⁰Y).It addition, non-medical applications (such as, industry radiophotography) combines and is retouched above All radioactive sources of stating and provide at several kVp until x-ray energy in the range of about 15kVp The source of amount uses active matrix imager.The x-ray transducer of flat-panel imager and being associated The design of electronic device and ability and the design of array, mode of operation and various non-medical applications Need coupling.

Mode based on transducer detection x-ray, imager based on active matrix array is substantially On can be divided into two kinds: be referred to as indirect detection and directly detection.For indirect detection imaging Device, some the incident x-ray energy interacted with transducer are first be converted into optical photons, And a part for these photons is subsequently converted in the pixel storage capacitor being stored in array The signal of telecommunication.For directly detecting imager, some the incident x-ray energy interacted with transducer Amount is converted directly to the signal of telecommunication being stored in pixel storage capacitor.

For indirect detection imager, transducer takes the form of flasher.Many is applied, Use cesium iodide (writing CsI:Tl or CsI:Tl of doping thallium⁺, it is generally grown as formation has The structure of the acicular crystal of alignment), or gadolinium oxysulfide (the writing Gd of doping terbium₂O₂S:Tb or Gd₂O₂S:Tb³⁺, also referred to as GOS, the usually form of powder phosphor screen).But, Other flashers are also possible, the cesium iodide of such as sodium contaminated (writing CsI:Na or CsI:Na⁺), doping thallium sodium iodide (writing NaI:Tl or NaI:Tl⁺), artificial schellite (CaWO₄)、 Zinc Tungstate (ZnWO₄), cadmium tungstate (CdWO₄), bismuth germanium oxide (Bi₄Ge₃O₁₂, also referred to as BGO), Lutecium yttrium orthosilicate (the writing Lu of doped with cerium_1.8Yb_0.2SiO₅: Ce or Lu_1.8Yb_0.2SiO₅:Ce³⁺, Also referred to as LYSO), and gadolinium siliate (the writing Gd of doped with cerium₂SiO₅: Ce or Gd₂SiO₅:Ce³⁺, Also referred to as GSO).Other flashers are possible, such as BaFCl:Eu²⁺、BaSO₄:Eu²⁺、 BaFBr:Eu²⁺、LaOBr:Tb³⁺、LaOBr:Tm³⁺、La₂O₂S:Tb³⁺、Y₂O₂S:Tb³⁺、 YTaO₄、YTaO₄: Nb, ZnS:Ag, (Zn, Cd) S:Ag, ZnSiO₄:Mn²⁺、CsI、 LiI:Eu²⁺、PbWO₄、Bi₄Si₃O₁₂、Lu₂SiO₅:Ce³⁺、YAlO₃:Ce³⁺、CsF、 CaF₂:Eu²⁺、BaF₂、CeF₃、Y_1.34Gd_0.6O₃:Eu³⁺、Pr、Gd₂O₂S:Pr³⁺、Ce、 SCGl、HFG:Ce³⁺And C (5%)₁₄H₁₀.For the most eurypalynous scintillator material (such as, CsI:Tl, BGO and LYSO), transducer can take the form of segmented detector, examines in segmentation Surveying in device, (each element has and is substantially equal to or less than into for each little element of scintillator material The cross-sectional area of the pel spacing (or multiple of the pel spacing of array) of picture array) and next door material Material fits together, and described in this next door material separation, element is to form an area detector, should be every Wall material provides being optically isolated between element, thereby keeps spatial resolution.

A material layer (referred to as encapsulation or encapsulated layer) can be deposited to form the top layer of flasher, in order to Mechanically and chemically protect flasher.

For indirect detection AMFPI, pixel storage capacitor takes the form of optical pickocff, Such as photodiode or Metal-Insulator-Semi-Conductor (MIS) structure.These optical pickocffs generally close And have that a-Si quasiconductor-it is for being particularly well suited for the material of the imaging of ionizing radiation due to the fact that Material: the signal of a-Si sensor, noise and dark current character only pole are faintly by high radiation agent Amount impact.Character based on a-Si and the TFT of polycrystalline-Si is the most only weakly by high radiation dose Impact so that these TFT are particularly well suited for the imaging of ionizing radiation.

A kind of form of the structure of a-Si photodiode includes that (it is connected to addressing to hearth electrode The source electrode of TFT), doped layer (n⁺Doping a-Si, about 10 to 500nm are thick for type, and are preferably about 50 to 100nm is thick), free from admixture a-Si layer (preferably, about 0.5 to 2.0 μ m-thick), the second doping Layer (p⁺Doping a-Si, about 10 to 500nm are thick for type, and are preferably, and about 5 to 20nm is thick), and By the top electrode that the material of visible transparent (such as, tin indium oxide, ITO) is made.At this a-Si In the alternative form of one of photoelectric diode structure, top a-Si layer and the doping of bottom a-Si layer Interchangeable.The minimizing thickness of a-Si layer of being adulterated at top decreases the optics absorbed in this layer The ratio of photon, thus contribute to maximizing the imaging signal being recorded in pixel.

It is schematically illustrated the pixel of the active matrix imaging array for indirect detection in Figure 5 The example of circuit.The component described in this figure includes that photodiode (PD) and pixel are sought Location transistor (TFT).Marked the source electrode of TFT, drain electrode and the grid by dotted ellipse cincture. Second dotted ellipse is emphasized: photodiode (it is the optical pickocff of pixel) also serves as to be had Electric capacity C_PDPixel storage capacitor.Also show that correspond respectively to described pixel row and The grid address wire of row and data/address line.Apply the most inclined of the top electrode to photodiode The value putting voltage is V_BIAS.This voltage is provided by external voltage supply.V_BIASGenerally set It is set to the value in the range of about 1V to 8V.

Fig. 6 is the structural implementation that the pixel corresponding to the image element circuit in Fig. 5 designs Schematic cross section is shown, this structural implementation is referred to as baseline framework.In this embodiment, The surface area of pixel shared by addressing TFT and other elements multiple, and other elements the plurality of include There is the discrete a-Si photodiode of stack architecture, address wire, and address wire, photoelectricity two pole Gap between pipe and TFT.

In figure 6, ellipse indicates the general location of a-Si addressing transistor (TFT) by a dotted line (only illustrating drain electrode, source electrode and grid).The hearth electrode of photodiode is by order to form TFT's The extension of the metal of source electrode is formed.By the remainder layer of photodiode, (it is not heavy with TFT Folded) patterning, so that it is directed at and is formed in this way a storehouse knot with the edge of hearth electrode Structure.These layers include n⁺Type doping a-Si layer, free from admixture a-Si layer, p⁺Type doping a-Si layer, and ITO layer as optical clear top electrode.It is V by offset line (bias line) by value_BIAS Reverse bias voltage apply to the top electrode of photodiode, thus produce across photoelectricity two pole The electric field of pipe Data/address line and the biasing of the drain electrode of TFT it is connected to by metal throuth hole The direction of line is orthogonal with the plane of this figure.Passivating material is schematically indicated substantially by shade Position.This includes being deposited on the whole end face of array so that the passivating material of array of packages, from And mechanically protect array and prevent from connecing with the electricity being not intended to of offset line and data/address line Touch.Also describing the x-ray transducer of the form of flasher, this flasher is above whole array Extend.Incident x-ray (wavy arrows) produces optical photons (straight dim arrow) in flasher. Some optical photons enter in the i layer of photodiode, produce due to electric field towards electricity The electronics of pole drift and hole, thereby produce the one-tenth being stored in pixel and finally reading from pixel Image signal.

For directly detection, active matrix flat-panel imager, transducer can take light guide material layer Form, this light guide material layer has the thickness that be enough to make major part incident x-ray to stop.A kind of Suitably light-guide material is amorphous selenium a-Se, and it can be fabricated to until about 2000 μ m-thick, and preferably Be fabricated to that there is the thickness in the range of about 200 to 1000 μm.It is adapted as directly examining Other light-guide materials surveying transducer include the lead iodide (PbI of monocrystalline and polycrystalline form₂), mercuric iodixde (HgI₂), lead oxide (PbO), cadmium zinc telluride (CdZnTe), cadmium telluride (CdTe), Bi₂S₃、 Bi₂Se₃、BiI₃、BiBr₃、CdS、CdSe、HgS、Cd₂P₃、InAs、InP、In₂S₃、 In₂Se₃、Ag₂S、PbI₄ ^-2And Pb₂I₇ ^-3.Selecting along with x-ray energy of the thickness of optical conductor Increase and increase, in order to realizing the conversion of the x-ray of rational larger proportion, this ratio can be about 10% to 90% (under diagnostic energy) and the scope of about 1% to 10% (under radiotherapy energy) Interior any value.

(such as, External radiotherapy imaging in the case of using million volts of radiation to carry out imaging Or industry radiophotography, the scanning including for safety applications), generally by one thin (about 1mm) Metallic plate be positioned transducer top (for indirect detection, directly on flasher, or for Directly detection, directly in the encapsulation above the top electrode covering optical conductor).The composition of this plate Many forms can be taked, including copper, steel, tungsten and lead.It is schematically illustrated in the figure 7 for directly Connect the example of the image element circuit of the active matrix imaging array of detection.The circuit described in this figure Element includes optical conductor (PC), pixel address transistor (TFT), and has electric capacity C_STORAGE Pixel storage capacitor (as indicated by dotted ellipse).Marked by another dotted ellipse cincture The source electrode of TFT, drain electrode and grid.3rd dotted ellipse is emphasized: optical conductor has electric capacity C_PC And the resistance being also similar to that in circuit is R_PCBig resistor and work.Also show that corresponding to The grid address wire of the columns and rows of the pixel described and data/address line.Apply to optical conductor The value of the bias voltage of top electrode is V_BIAS.This voltage is provided by external voltage supply. The V used_BIASValue depends on the type of photoconductor material, and generally with the thickness of this material Degree proportionally increases.For a-Se, V_BIASUsually each micron thickness about 10V.Therefore, For the a-Se layer of 1000 μm, V_BIASWould be about 10,000V.For HgI₂, V_BIASGenerally In the range of each micron about 0.5 to 2.0V.Therefore, for the HgI of 500 μm₂Layer, V_BIAS Would be about 250 to 1,000V.Photoconductive layer can also avalanche mode operate, wherein across this layer V_BIASValue generally the highest-for the example of a-Se, at the model of each micron about 50V to 100V In enclosing.In this case, avalanche layer can be made sufficiently thick, itself to make major part x-ray stop, Avalanche layer maybe can be made relatively thin, and by an optical conductor or scintillator layer (such as, be respectively provided with sufficiently thick Degree is so that a-Se or CsI:Tl that stop of major part incident x-ray) it is deposited on the top of avalanche layer.? In this case, the purposes of avalanche layer is to amplify the signal from overlying transducer.

Fig. 8 is the structural implementation that the pixel corresponding to the image element circuit in Fig. 7 designs Schematic cross section is shown.In this embodiment, addressing TFT shares pixel with the following Surface area: pixel storage capacitor, address wire, and address wire, storage capacitor and TFT Between gap.Optical conductor structure (including hearth electrode, light guide material layer, and top electrode) is resident Above the plane of addressing TFT (that is, the top of horizontal plane).

In fig. 8, ellipse indicates the general location of a-Si addressing transistor (TFT) by a dotted line (only illustrating drain electrode, source electrode and grid).For pixel storage capacitor, (its position is by the second dotted line Oval instruction), illustrate only top electrode and hearth electrode.The top electrode of pixel storage capacitor is by rear Contact, portion is formed, and this back contact is the extension of the metal of the source electrode forming TFT. The hearth electrode of optical conductor is by being connected to the through hole of back contact (by the 3rd oval instruction) TFT, and not extending above at TFT.Continuous photoconduction across whole array deposition one thickness Body material layer (it serves as x-ray transducer), so that this material contacts with hearth electrode.Whole The continuous top electrode of disposed thereon one of photoconductor surface.It is V by value_BIASBias voltage apply To top electrode, in order to set up one across the electric field of optical conductor.One material layer (is referred to as encapsulated or seals Dress layer) it is deposited on the top of whole top electrode so that array of packages, thus mechanically with to change Mode protects array, and prevents the electrical contact being not intended to top electrode.Pass through metal throuth hole And the direction that is connected to the data/address line of the drain electrode of TFT is orthogonal with the plane of this figure.The most logical Cross shade to indicate the position of passivating material.Note, replacing of directly detection pixel and array In generation configuration, one can be deposited between hearth electrode and optical conductor or between top electrode and optical conductor Thin-material layers (typically about 1 to 10 micron thickness, serve as barrier, electrolyte or doped layer).Or, This thin-material layers, and the class of this thin-material layers in each position can be all deposited in two positions Type and thickness can be different.

For having the indirect detection active matrix imaging battle array of baseline framework illustrated in Fig. 6 Row, addressing TFT competes directly with one another with photodiode and competes pixel with other pixel elements In region.These four pixels in figure 6 and in being revealed in Fig. 9 corresponding schematically in In Xian obviously.It is in Fig. 10 further it is clear that figure 10 illustrates between a pair Connect the microphotograph of the pixel that detection active matrix array is obtained.By and large, design is indirectly Detection active matrix array is to make the area of photodiode the biggest.It addition, for Offset line, in the array design extended above of the end face of photodiode, makes these lines and is correlated with The area of the through hole (both are optically opaque and stop that light arrives photodiode) of connection is to the greatest extent The least.For given array design, pixel region by photodiode surface, (it is to coming Uncovered from the incident illumination of top) ratio that occupies is referred to as optical fill factor.

The maximization of optical fill factor is promoted by following facts: entered from overlying flasher The more efficient use penetrating light adds picture element signal size, therefore increases the signal to noise ratio of imager, Thus cause the picture quality improved.For being used for needing small pixel pitch (such as, about 100 Below μm) application or imager with low exposure (such as, the low exposure region of fluorescence microscopy, The exposure of each of which frame is less than about 1 μ R) for the array design of application that operates, optics is filled out Fill the factor and maximize particular importance.

High optical fill factor encourages minimizing of the following: the size of addressing TFT, The width of location line, between the width of offset line, and photodiode, TFT and address wire between Gap.But, manufacture process imposes minimum feature size to each element of design.Additionally, Address wire and offset line must be sufficiently wide, to limit the resistance along these lines (because high resistance will Negatively affect time of array and/or electrically operated, and signal may be reduced to noiseproof feature). It addition, gap must not be too narrow to cause the contact being not intended between pixel element (short with electricity therefore Road) or cause high-caliber parasitic capacitance (it can make signal to noise ratio and time performance degradation).Finally, The width of TFT channel must be sufficiently large to length ratio (referred to as aspect ratio), in order to provides desired The value of the TFT turn-on current needed for array reading speed is (because having high aspect ratio TFT provides the electric current of higher level in its conduction mode).Figure 10 illustrates these and considers item Practical examples, wherein the reduction via gap, address wire and the size of TFT is (big by minimal characteristic Little reduction auxiliary), the optical fill factor (shown in Figure 10 (a)) of previous array design is slightly Rear design dramatically increases (shown in Figure 10 (b)).Along with pel spacing reduces, remain big The challenge of optical fill factor becomes increasingly difficult, this is because by address wire, gap and addressing The region that TFT occupies consumes the pixel region of greater proportion.

The highly effective method avoiding the above-mentioned restriction about optical fill factor is: implement light Electric diode structure is positioned at the pixel frame of (that is, the top of horizontal plane) above the plane of addressing TFT Structure.Outside these faces multiple, framework is possible, and two such framves shown in Figure 11 and Figure 12 Structure.These illustrate in, in the face outside photoelectric diode structure with address TFT part or all Overlapping, in order to optical fill factor is maximized.

Photodiode in Figure 11 includes the discrete stack architecture being directed at hearth electrode.Such as figure In 6, single addressing TFT is connected to discrete a-Si photodiode, this discrete a-Si photoelectricity two pole Pipe has three a-Si layers and top electrode and hearth electrode.But, in this pixel structure, light The hearth electrode of electric diode is positioned to address the top of the plane of TFT.Hearth electrode is by rear portion The through hole of contact (the oval instruction by a dotted line of its position) and be connected to TFT, this back contact is In order to form the extension of the metal of the source electrode of TFT.The described a-Si layer of photodiode and This top electrode is patterned to form the storehouse being directed at hearth electrode.(its position leads to data/address line Cross solid oval instruction) orthogonal with the plane of this figure with the direction of offset line.

Photodiode in Figure 12 has a structure, and in the structure shown here, some layers are continuous print. In Figure 11, single addressing TFT is connected to a-Si photoelectricity two pole being positioned above the plane of TFT Pipe.But, in this pixel structure, p⁺Type doped layer and i layer are not patterned, and Being across array is that optical fill factor is maximized by continuous print with auxiliary.n⁺Type doping a-Si layer It is patterned to the hearth electrode with photodiode be directed at, to suppress the electric charge between neighbor Share.Hearth electrode is by connecting to the through hole of back contact (the oval instruction by a dotted line of its position) Being connected to TFT, this back contact is the extension of the metal of the source electrode forming TFT.Number Direction according to address wire (its position is indicated by solid oval) is orthogonal with the plane of this figure.

Figure 13 and Figure 14 has corresponding to the indirect detection with pixel structure depicted in figure 12 The actual realization of source matrix array design.Figure 13 is four schematically presenting of pixel and Figure 14 is Microphotograph from the pixel of an array.

Summary of the invention

In one embodiment of the invention, it is provided that a kind of radiation sensor, comprising: flash Layer, this flash layer is configured to when interacting launch photon with ionizing radiation；With light electric-examination Surveying device, it includes the first electrode, photosensitive layer and the light-transmissive that arrange neighbouring with flash layer successively Second electrode of son.This photosensitive layer is configured to when the part with described photon interacts Produce electron hole pair.This radiation sensor includes: image element circuit, is electrically connected to the first electricity Pole, and be configured to measure instruction one-tenth of produced described electron hole pair in photosensitive layer Image signal；And planarization layer, it is arranged on the image element circuit between the first electrode and image element circuit On so that the first electrode is including above the plane of image element circuit.Described first electrode and institute State the surface of at least one in the second electrode the most overlapping with this image element circuit and have Surface warp portion (surface inflection) above the feature of this image element circuit.This table Warpage portion, face has the radius of curvature more than 1/2 micron.

In another embodiment of the present invention, it is provided that a kind of radiation sensor, it includes photoconduction Detector, this optical conductor detector includes the first electrode, photoconductive layer, and transmissive electricity successively The second electrode from radiation.This photoconductive layer is configured to when interacting with ionizing radiation produce Electron hole pair.This radiation sensor includes: image element circuit, and it is electrically connected to this first electrode And be configured to measure instruction imaging signal of produced electron hole pair in this photoconductive layer； And planarization layer, it is arranged on the image element circuit between the first electrode and image element circuit so that First electrode is including above the plane of image element circuit.Described first electrode and described second electricity The surface of at least one in extremely is the most overlapping with this image element circuit and has in this pixel The surface warp portion of the top of the feature of circuit.This surface warp portion has the song more than 1/2 micron Rate radius.

In yet another embodiment of the present invention, it is provided that a kind of side for manufacturing radiation sensor Method.The method includes: form image element circuit element on basal substrate, at described image element circuit The top of element forms planarization layer, forms hole to expose to image element circuit unit in planarization layer The connector of part, makes the hole metallization of patterning, is formed and the first of the electrical contact of metallized hole Electrode, and on this first electrode, form the layer to light or ionizing radiation sensitive.Form this smooth Change layer and one surface is provided on the surface the most overlapping with this image element circuit of the first electrode Warpage portion, this surface warp portion is above the feature of image element circuit, and has micro-more than 1/2 The radius of curvature of rice.

The above-mentioned general description that should be understood that the present invention is exemplary with both of which described in detail below , and and the unrestricted present invention.

Accompanying drawing explanation

By with reference to be considered in conjunction with the accompanying described in detail below, to the present invention more completely Solve and its many attendant advantages will be readily obtained, and it will become better understood.

Fig. 1 is the schematic three-dimensional figure of a kind of form of a-Si thin film transistor (TFT) (TFT), and it illustrates Top from the TFT of inclination angle viewing；

Fig. 2 is the schematic cross section of the a-Si TFT shown in Fig. 1；

Fig. 3 is the schematic three-dimensional figure of a kind of form of polycrystalline-Si TFT, and it illustrates from inclination angle The top of the TFT of viewing；

Fig. 4 is the schematic cross section of the polycrystalline-Si TFT shown in Fig. 3；

Fig. 5 is the schematic circuit of the pixel from active matrix imaging array, this active square Battle array imaging array uses the indirect detection of incident radiation；

Fig. 6 is the horizontal stroke of a kind of form of the indirect detection pixel design with discrete light electric diode The schematic figure of sectional view, the design of this indirect detection pixel is corresponding to a spy of the image element circuit of Fig. 5 Fixed structure embodiment and referred to as baseline framework；

Fig. 7 is the schematic circuit of the pixel from active matrix imaging array, this active square Battle array imaging array uses the directly detection of incident radiation；

Fig. 8 is the schematic figure of the cross-sectional view of directly a kind of form of detection pixel design；

Fig. 9 is schematically presenting of four neighbors of indirect detection active matrix array, its Corresponding to image element circuit the most shown and the embodiment of baseline framework；

Figure 10 is the top in the region of single pixel of a pair indirect detection active matrix array The microphotograph set in face, it is corresponding to the embodiment of the baseline framework in Fig. 6；

Figure 11 is the indirect detection pixel design with photoelectric diode structure outside discrete face The schematic figure of cross-sectional view；

Figure 12 is the indirect detection pixel design with photoelectric diode structure outside continuous print face The schematic figure of cross-sectional view；

Figure 13 is schematically presenting of four neighbors of indirect detection active matrix array, its Correspond to the image element circuit shown in Fig. 5 and Figure 12 and the embodiment of framework respectively；

Figure 14 is the end face in the region of single pixel of indirect detection active matrix array Microphotograph, it is corresponding to presenting in the embodiment of the pixel structure in Figure 12 and Figure 13；

Figure 15 is the schematic of the pixel from the indirect detection array designed based on active pixel Circuit diagram, the design of this active pixel has amplifier in single-stage pixel；

Figure 16 is showing of four neighbors of indirect detection array based on active pixel design Meaning property presents, and the design of this active pixel uses polycrystalline-Si TFT, and this is schematically in now corresponding to figure Image element circuit in 15 and the embodiment party of the photoelectric diode structure of structure being similar in Figure 12 Formula；

Figure 17 is the microphotograph of the end face in the region of single pixel of indirect detection array, It is corresponding to presenting in the embodiment of the image element circuit in Figure 15 and Figure 16；

Figure 18 is the schematic of the pixel from the indirect detection array designed based on active pixel Circuit diagram, the design of this active pixel has amplifier in two-stage pixel；

Figure 19 is showing of four neighbors of indirect detection array based on active pixel design Meaning property presents, and the design of this active pixel uses polycrystalline-Si TFT, and this is schematically in now corresponding to figure Image element circuit in 18 and the embodiment party of the photoelectric diode structure of structure being similar in Figure 12 Formula；

Figure 20 is the microphotograph of the end face in the region of single pixel of indirect detection array, It is corresponding to presenting in the embodiment of the image element circuit in Figure 18 and Figure 19；

Figure 21 is based on the horizontal stroke of the calculating of the indirect detection array of Amplifier Design in single-stage pixel Sectional view, in this single-stage pixel, Amplifier Design uses polycrystalline-Si TFT, and this cross-sectional view is corresponding In Figure 16 and Figure 17 and the primary topology (native topology) that illustrates various feature and material；

Figure 22 (a) is based on the calculating of the indirect detection array of Amplifier Design in two-stage pixel Cross-sectional view, in this two-stage pixel, Amplifier Design uses polycrystalline-Si TFT, this cross-sectional view pair Should be in Figure 19 and Figure 20 and the primary topology illustrating various feature and material；

Figure 22 (b) is corresponding to a part of Figure 22 (a)；

Figure 23 (a) is the vertical view in the region of single pixel of amplifier array in single-stage pixel Figure, this figure is to obtain according to the identical calculations for Figure 21, this figure corresponding to Figure 16 and Figure 17 and The primary topology at the top of continuous photoelectric diode structure is shown；

Figure 23 (b) be from Figure 17 obtain microphotograph, its for the calculating in Figure 23 (a) The purpose that compares of top view illustrate；

Figure 24 (a) is the vertical view in the region of single pixel of amplifier array in two-stage pixel Figure, this figure is to obtain according to the identical calculations for Figure 22, this figure corresponding to Figure 19 and Figure 20 and The primary topology at the top of continuous photoelectric diode structure is shown；

Figure 24 (b) be from Figure 20 obtain microphotograph, its for the calculating in Figure 24 (a) The purpose that compares of top view illustrate；

Figure 25 is a pair figure of the general concept of curvature radius, and radius of curvature can be applicable to table The sign of the change of the flatness in face；

Figure 26 (a) is the cross-sectional view of the calculating of indirect detection array, and it corresponds to Figure 21, but has There is the topology evenly realized via passivation completely flatization of #2；

Figure 26 (b) is the cross-sectional view of the calculating of indirect detection array, and it corresponds to Figure 21, but has There is the topology evenly realized via the part planarization of passivation #2；

Figure 27 (a) is the cross-sectional view of the calculating of indirect detection array, and it corresponds to Figure 22 (a), But the topology evenly that there is completely flatization via passivation #2 and realize；

Figure 27 (b) is corresponding to a part of Figure 27 (a)；

Figure 28 is the cross-sectional view of the calculating of indirect detection array, and it corresponds to Figure 26 (a), but has The opening up evenly having the smoothing of the periphery edge of the hearth electrode via photodiode and realize Flutter；

Figure 29 is the cross-sectional view of the calculating of indirect detection array, and it corresponds to Figure 27 (a), but has The opening up evenly having the smoothing of the periphery edge of the hearth electrode via photodiode and realize Flutter；

Figure 30 is the cross-sectional view of the calculating of indirect detection array, and it corresponds to Figure 28, but has Via the topology evenly narrowing and realizing with these through holes metal filled of through hole, described Through hole connects hearth electrode and the back contact of photodiode；

Figure 31 (a) is the vertical view in the region of single pixel of amplifier array in single-stage pixel Figure, this figure is that this illustrates the continuous photoelectricity in top from calculating acquisition and being completely corresponding to Figure 23 (a) The primary topology of diode structure, and for the purpose compared with remaining view in this figure And be included；

Figure 31 (b) illustrate realize via passivation completely flatization of #2 relative to Figure 31's (a) The improvement of surface topology, this figure is to obtain from the identical calculations for Figure 26 (a)；

Figure 31 (c) illustrates the smoothing of the periphery edge of the hearth electrode via photodiode and reality The improvement of the existing surface topology relative to Figure 31 (b), this figure is from the identical calculations for Figure 28 Obtain；

Figure 31 (d) illustrates the phase narrowing and realizing with these through holes metal filled via through hole For the improvement of the surface topology of Figure 31 (c), this through hole connect the hearth electrode of photodiode with after Contact, portion, this figure is to obtain from the identical calculations for Figure 30；

Figure 32 (a) is the vertical view in the region of single pixel of amplifier array in two-stage pixel Figure, this figure is that this illustrates the continuous photoelectricity in top from calculating acquisition and being completely corresponding to Figure 24 (a) The primary topology of diode structure, and for the purpose compared with remaining view in this figure And be included；

Figure 32 (b) illustrate realize via passivation completely flatization of #2 relative to Figure 32's (a) The improvement of surface topology, this figure is to obtain from the identical calculations for Figure 27；

Figure 32 (c) illustrates the smoothing of the periphery edge of the hearth electrode via photodiode and reality The improvement of the existing surface topology relative to Figure 32 (b), this figure is from the identical calculations for Figure 29 Obtain；

Figure 32 (d) illustrates the phase narrowing and realizing with these through holes metal filled via through hole For the improvement of the surface topology of Figure 32 (c), this through hole connect the hearth electrode of photodiode with after Contact, portion, this figure is from calculating acquisition；

Figure 33 (a) is the cross-sectional view of the calculating of indirect detection array, and it corresponds to Figure 21, but has Have completely flatization via the free from admixture a-Si layer in photodiode and realize evenly Topology；

Figure 33 (b) is the cross-sectional view of the calculating of indirect detection array, and it corresponds to Figure 21, but has Have planarize via the part of free from admixture a-Si layer in photodiode and realize evenly Topology；

Figure 34 (a) is the vertical view in the region of single pixel of amplifier array in single-stage pixel Figure, this figure is that this illustrates the continuous photoelectricity in top from calculating acquisition and being completely corresponding to Figure 23 (a) The primary topology of diode structure, and for the purpose compared with remaining view in this figure And be included；

Figure 34 (b) illustrate via the free from admixture a-Si layer in photodiode part planarize and The improvement of the surface topology relative to Figure 34 (a) realized, this figure is identical from for Figure 33 (b) Calculate and obtain；

Figure 34 (c) completely flatization via the free from admixture a-Si layer in photodiode is shown and The improvement of the surface topology relative to Figure 34 (a) realized, this figure is identical from for Figure 33 (a) Calculate and obtain.

Detailed description of the invention

Photoelectric diode structure outside face is incorporated to the pixel design of indirect detection active matrix array In provide a kind of mechanism for significantly improving optical fill factor.Implementing continuous photoelectricity two In the case of the tubular construction of pole, may realize corresponding to whole pixel region big to 1 optical filling The factor.The raising of these optical fill factor results from and eliminates photodiode and other pixel elements The competition to pixel region between part (such as, addressing TFT, address wire and gap).

Outside face, photoelectric diode structure also makes it possible to (such as, additional element is introduced pixel TFT, diode, capacitor and resistor, and through hole, trace, control line, address wire And ground plane), thereby make it possible to realize more complicated image element circuit.As at active matrix In the case of array, these additional element will reside at the flat of planar separation with photodiode In face, and therefore will not compete pixel region with photodiode.Neutralize via in pixel design The more complicated circuit of introducing elsewhere in array design, only has single with each pixel The performance of the active matrix surface plate imaging array of TFT (serving as address pixels switch) compares, Sizable performance improvement can be realized.Although for these extra TFT and the quasiconductor of diode The type of material can be any one in these types as described above, but described below The example of more complicated circuit relates to polycrystalline-Si TFT.Although it addition, following instance and indirect detection (wherein imaging signal is through collecting and being stored in pixel storage capacitor before reading for array design In) relevant, but outside face, photoelectric diode structure also makes it possible to produce permission detection and counting is each The image element circuit of individual x-ray (ability of so-called single-photon counting), and do not make these circuit With photodiode competition region.(such as, these single-photons counting pixel will include detector Photoelectric diode structure outside face), and (optionally, there is arteries and veins for amplifier, descriminator Rush shaping circuit) and event counter (such as, the form of linear feedback shift register) and use In the circuit that addressing and pixel reset.Single-photon count array provides many advantages, such as base Selected part in x-ray spectrum produces ability (referred to as Energy identifying or the energy of high-contrast image The technology of amount window limit (energy windowing)).

For indirect detection based on incident radiation and the array design of directly detection, increase Complexity all can improve the signal to noise ratio of imager.In the case of indirect detection, significant complexity Can also contribute to the a-Si in restriction and photodiode is in metasable state electronic state (also referred to as Trapped state) in the capture of electric charge and the unwanted effect that is associated of release.

Referring now to accompanying drawing, wherein, similar in some accompanying drawings reference represents identical or right The part answered, more specifically, with reference to Fig. 5, for having the general type shown in Fig. 5 Active matrix array image element circuit, during the reading of given pixel column, across corresponding photoelectricity two The electric field increase of pole pipe is back to maximum, and this maximum passes through V_BIASValue and photodiode In the thickness of a-Si limit.Therefore, pixel read cause imaging signal is sampled with And pixel is initialized.During the collection of the imaging signal in each pixel storage capacitor, Electric field reduces.For given pixel, if imaging signal is sufficiently large, then the value of electric field will almost Being decreased to zero, storage capacitor will not be able to store further electric charge, and pixel is saturated.Photoelectricity The probability of the charge-trapping in diode generally reduces along with electric field intensity and increases, and close Become the highest during the saturated condition of pixel.In radiophotography imaging, (it is usually directed to big x and penetrates Line exposing) in, the high level of captured electric charge causes the physical loss of imaging signal.So reduce The signal to noise ratio of imager and image quality degradation can be made.In fluoroscopic image, at previous image Acquisition during the electric charge that captured will discharge in image after a while.So may result in from relatively early The image information of image is revealed in after a while in image-its for a kind of be referred to as the most delayed or picture lag General unwanted effect.If it addition, using imager to produce have putting of big x-ray exposure Penetrate photographs, and if use after the short time this imager produce fluoroscopic image, then from The image information of radiographic image can be revealed in fluoroscopic image-and it is referred to as afterimage for one (ghosting) unwanted effect.Delayed and afterimage is the reason causing image artifact, described Image artifact can make the important information in image unclear, hence in so that the serviceability degradation of image, And these artifact generally run in the case of using imager based on active matrix array.So And, it is associated with the array of the circuit with the complexity bigger than the complexity of active matrix array Design can overcome signal limit noise and reduce image artifact, keeps compactness, big face simultaneously Long-pending and radiation damage repellence important advantage.

It is schematically illustrated the more complicated image element circuit for indirect detection array in fig .15 Example.This circuit design includes that three TFT, described TFT are configured to supply in single-stage pixel Amplifier, addressing TFT and replacement TFT.Due to the existence of amplifier in pixel, this designs title Make active pixel design.During being associated with the operation of array of this design, collect imaging signal And be stored in serving as in the photodiode of pixel storage capacitor.As in active matrix battle array In the case of row, string pixel can be performed reading (if expectation maximum space resolution) every time, But the sampling of picture element signal initializes with pixel and carries out the most simultaneously.When via using addressing TFT Sample the imaging signal in given pixel storage capacitor time, in pixel, amplifier is by this signal Amplifying an amount, this amount is equal to the electric capacity of data/address line and the electric capacity C of photodiode_PDRatio Rate.Because this is amplified in self-routing TFT and (it is active matrix from outside preamplifier Two Main Noise Sources in imager) influence of noise before betide in imaging circuits, institute Being substantially increased of signal to noise ratio of imager can be provided with this pixel circuit design.It addition, for this Image element circuit, imaging signal is carried out sampling can't initialized pixel.Exactly, imaging Signal continues to reside in pixel storage capacitor, until should via using replacement TFT to initialize Till pixel.Therefore, imaging signal can be carried out multiple repairing weld and be then averaged, Thus cause the further improvement of the signal to noise ratio of imager.Figure 16 and Figure 17 is corresponding to having single-stage The actual realization of the indirect detection array of Amplifier Design in pixel, it represents the pixel electricity of Figure 15 The embodiment on road.Figure 16 is schematically presenting of four pixels, and Figure 17 is from actual battle array The microphotograph of the pixel of row.

It is schematically illustrated the even more complicated pixel for indirect detection array in figure 18 Another example of circuit.This circuit design includes five TFT and feedback condenser, these five TFT It is configured to supply amplifier in two-stage pixel, addressing TFT and replacement with this feedback condenser TFT.This another example designed for active pixel.Operation at the array being associated with this design Period, collect imaging signal and be stored in serving as the feedback condenser of pixel storage capacitor In.Operation and the advantage of this design are similar to Amplifier Design in single-stage pixel as described above Operation and advantage-due in the pixel to imaging signal amplify and due to imaging signal Multiple repairing weld and average and being substantially increased of the signal to noise ratio of imager is provided.It addition, design at this In, at collection and the memory period of imaging signal, the slightest across the electric field of photodiode Ground reduces-with Amplifier Design in active matrix pixel design or previously described single-stage pixel Situation formed sharp contrast.

Therefore, the amount of the charge-trapping in photodiode is reduced and delayed and afterimage artifact Alleviated, even the most such under the highest x-ray exposure.Amplifier in this two-stage pixel Another advantage of design is: compared with the situation of single-stage design, and this design allows amplification The gain of device (be defined as amplifier increase imaging signal by multiplication factor) more Control.In two-stage design, in pixel, imaging signal is amplified an amount, this amount etc. by amplifier Electric capacity and the electric capacity C of pixel feedback condenser in data/address line_FBRatio.Therefore, for For single-stage design and two-stage design, for given pel spacing and pixel storage capacitor Electric capacity, in pixel, the value of amplifier gain increases along with data line capacitance and increases.Therefore, If manufacturing and designing bigger array based on given pixel (that is, along data wire direction, there is plurality The array of mesh pixel), then the amount amplified will increase.This be due to data line capacitance will with along The number of pixels of data/address line proportionally increases.In the case of single-stage design, constant (its specification is required for maximum light detection efficiency independently for the thickness of more photodiode or area It is optimized) in the case of, amplifier gain this dependence (one to array size in pixel As for undesirable) cannot be offseted.But, for two-stage design, adjustable C_FBValue (example As, by adjusting thickness or the area of capacitor of capacitor dielectric), to offset data wire electricity The change held.So allow to implement given two-stage design, without changing for various array size Become the scope-of the value of the imaging signal extracted from array thus to simplify imager operation required The design of outside preposition amplification electron device.Figure 19 and Figure 20 is corresponding to having in two-stage pixel The actual realization of the indirect detection array of amplifier, the embodiment party of the image element circuit of its expression Figure 18 Formula.Figure 19 is schematically presenting of four pixels, and Figure 20 is the pixel from actual array Microphotograph.

As described above, outside face photoelectric diode structure essence performance improvement is become can Energy.These are improved as the direct result of the optical fill factor increased, and are by these photoelectricity The result of the image element circuit complexity of the increase that diode structure promotes.But, for these benefits The actual realization at place, outside face, photoelectric diode structure should not introduce other factors making performance degradation. Thus, inventor has been found that the prominent question making performance degradation, as explained below.

Figure 21 and Figure 22 is respectively the single-stage pixel corresponding to the microphotograph in Figure 17 and Figure 20 The cross-sectional view of the calculating of Amplifier Design in interior Amplifier Design and two-stage pixel.These are transversal Face figure diagram is present in the various features in pixel design and material.Such as, there are four passivation Layer: buffering passivation, passivation #1, passivation #2 and top passivation.Additionally, there are four metal levels: Shunting metal (shunt metal) (for the element of such as reset voltage line with grid address wire)； Metal #1 (for such as back contact, data/address line and the element of through hole)；Metal #2 (is used for The element of the hearth electrode of such as photodiode)；With ITO (for the top electrode of photodiode). Other layers shown in Figure 21 and Figure 22 and feature include: for the polycrystalline-Si (mark of TFT channel It is designated as active polymorphic-Si)；TFT gate (is formed by polycrystalline-Si)；With the n for photodiode⁺ Type doping, free from admixture and p⁺Type doping a-Si.Obvious photoelectricity two in these cross sections The topological inhomogeneities of pole tubular construction represents that the topology in the corresponding array manufactured is uneven Property, the microphotograph in Figure 17 and Figure 20 is to obtain from the array manufactured of described correspondence.Example As, in Figure 23 and Figure 24, the top view of pixel is (from transversal in order to produce in Figure 21 and Figure 22 The identical calculations of face figure obtains) tight with between the microphotograph of the actual realization of corresponding array Correspondence is apparent from.

Photoelectric diode structure illustrated in Figure 21 to Figure 24 demonstrate its topology high not Uniformity degree.This topology inhomogeneities be due to pixel design in be positioned photodiode Lower section or be the existence of feature of part of photodiode.For shown pixel design Example, these features include that TFT, capacitor, address wire, trace and through hole (include photoelectricity The hearth electrode of diode is connected to the through hole of back contact).These features photodiode outside face In structure produce inhomogeneities, regardless of structure be continuous print (as in these examples) or from (that is, there is the photoelectric diode structure shown in Figure 11) dissipated.Note, in directly detection In the case of array, in the lower section of optical conductor structure or be that the feature of part of optical conductor structure is (all As, TFT, capacitor, address wire, trace and through hole) existence produce class the most in the structure shown here Topological inhomogeneities like degree.For having the indirect inspection of the outer photoelectric diode structure of continuous surface Survey array, and for directly detecting array, along the whole periphery of hearth electrode and by end electricity The region of the through hole that pole is connected to back contact produces topology inhomogeneities, as at Figure 14, figure In 21 and Figure 22 (a) obviously.

Comparatively, for the indirect detection array using baseline framework, discrete light electric diode Structure demonstrates the uniformity of the very high degree of its topology.This topology uniformity is due in pixel Design does not exist and is positioned the lower section of photodiode or for part any of photodiode Feature, as obvious in Fig. 6 and Fig. 9.In this case, when at array base palte The top of smooth flat surfaces performs the process of the various layers in order to manufacture photoelectric diode structure During step, each layer is all realized to flat surfaces and the thickness evenness smoothed.Therefore, The top of photoelectric diode structure is by for that smooth, smooth, as observed in Fig. 10.This Flatness and flatness are only by the random local of the process step originating from the manufacture for array Change (the most hundreds of angstrom) limits.Noting, during manufacture, other processing variation can be across battle array Row produce up to tens the percent of the thickness of given material layer system change (such as, increase or Reduce).

In the case of the indirect detection array using baseline framework, photodiode shows pole Good character, it include sense optical photons and collect gained signal high efficiency, and dark current, The release of charge-trapping, electric charge and delayed the lowest level-these splendid property the most noiseless The flatness owing to manufacture process of matter and the random localized variation of flatness, the most noiseless this The system change of the material thickness owing to manufacture process of a little excellent properties.Show these pole No matter the photoelectric diode structure of good character (comprises discrete baseline architecture design, or continuous print Or design outside discrete face) referred to as there is high-quality.For given imaging array, in these character Each can obtain via the signal properties measuring each pixel, and from each pixel Result or the average result from the result of many pixels can be expressed in the following manner.Each The value (being normalized to unit photodiode area) of this advantageous level of the dark current of pixel is little In about 1pA/mm².The value of this advantageous level of the charge-trapping of each pixel is (by list The amount of the imaging signal lost due to capture during one radiography frame quantifies, and is expressed as The percentage ratio of the imaging signal obtained under conditions of charge-trapping is in balance with electric charge release) Less than about 20%.The value of this advantageous level of the electric charge release of each pixel is (by having spoke Obtain in the case of penetrating and under conditions of charge-trapping is in balance with electric charge release is a series of From trapped state release during the first frame obtained in the case of there is not radiation after frame The amount of imaging signal quantifies, and is expressed as under conditions of charge-trapping and release are in balance The percentage ratio of the imaging signal obtained) less than about 15%.This delayed advantageous level of each pixel Value (by the case of there is radiation obtain a frame or series of frames after From the imaging signal of trapped state release during the first frame obtained in the case of there is not radiation The amount of (it originates from the electric charge captured in one or more previous frames) quantifies, and expresses Percentage ratio for the imaging signal from previous frame) less than about 15%.These results measured are usual Also referred to as the first territory is delayed, or, the referred to as first frame is delayed.For being used for light-guide material turning Parallel operation directly detect active matrix array, dark current (being normalized to unit optical conductor area), The value of the release of charge-trapping, electric charge and delayed advantageous level be similar to above for indirectly Detection level described by array.

For the high-quality photoelectric diode structure in the indirect detection array of use baseline framework, Contribute to the degree of the uniformity that a kind of factor is topology of excellent properties as described above.? In the limit of previously described surface smoothness, surface and thickness evenness, photoelectricity Each n in diode⁺Type doping, free from admixture and p⁺Each in type doping a-Si layer has all Even thickness, top electrode and hearth electrode are smooth, and these electrodes are parallel to each other.Therefore, The mode that electric field intensity changes with the distance of the thickness across i layer is at photodiode Remain relatively unchanged on region, and, this be cause dark current in high-quality light electric diode, The release of charge-trapping, electric charge and the reason of delayed advantageous level.

On the contrary, in the photoelectric diode structure with uneven topology, at photodiode A-Si material in produce the region of high and extremely low electric field intensity.At top electrode or hearth electrode table In the region of the photodiode revealing (that is, unexpected) deviation drastically with flatness, nothing Electric field in impurity a-Si is by the electric field in region parallel with hearth electrode for noticeably greater than top electrode. At the areas adjacent of these high electric fields, electric field intensity is by parallel with hearth electrode for substantially less than top electrode Region in electric field.The change of flatness more drastically (i.e., the most suddenly), electric field intensity inclined Difference will be the biggest.Because dark current increases with the increase of electric field intensity, so electric field intensity is notable The region increased will cause the unfavorable level of dark current.Similarly, because charge-trapping is with electric field The reduction of intensity and increase, so the region that electric field intensity is substantially reduced will cause charge-trapping, Electric charge release and delayed unfavorable level.

For the pixel design with the outer photoelectric diode structure of continuous surface as described above These three examples (that is, have active matrix design (Figure 14), there is single-stage pixel in amplifier set Meter (Figure 21 and Figure 23), and there is Amplifier Design (Figure 22 and Figure 24) in two-stage pixel), each The topological inhomogeneities of the extension of the photodiode in design causes having the electric field dramatically increased The extension area of intensity, and there is the extension area of the electric field intensity being substantially reduced.Electrode flatness Drastically change also can substantially reduce between top electrode and hearth electrode minimum range (as figure In the region of the deep via in 21 apparent), thus further help in the notable of electric field intensity Increase.Such as inventor it has been found that the existence in these regions causes dark current, charge-trapping, electricity Lotus release and delayed disadvantageous high level and therefore hinder realize high-quality light electric diode.

Due to some reasons, high photodiode dark current is undesirable.Because dark signal (by Dark current produces) it is stored in pixel storage capacitor during imaging, so high dark current is notable Reduce the scope of the most exercisable exposure of pixel.It addition, claim because dark current produces Make the noise source of shot noise, so high dark current causes high shot noise.Because in imager This impact of shot noise betide in pixel amplifier (such as, at Figure 15 and Figure 18 Pixel circuit design in) gain effect before, so with expection improvement compared with, reduce The improvement of the signal to noise ratio of imager.Similarly, high shot noise reduces to be associated with and has face The signal to noise ratio of the imager of the AMFPI array of outer photoelectric diode structure desired is improved (all As, in pixel design illustrated in Figure 11 and Figure 12).Due to some reasons, charge-trapping High level be undesirable.In radiophotography imaging, due to the loss of signal of trapped state Decrease the imaging signal from pixel sampling, thereby reduce the signal to noise ratio of imager.It addition, The high level of charge-trapping causes electric charge release and delayed high level, thus it is false to add image Undesirable consequence of shadow.

The flatness on surface is (such as, in the photodiode as shown in Figure 21 to Figure 24 The topology of electrode) the sharpness (that is, sudden) of change can be quantified by radius of curvature r, as Illustrated in Figure 25.Therefore the change more drastically of flatness is represented by the smaller value of r.Electricity Photoelectric diode structure (is represented continuously by the drastically change (as carried out parametrization by r) of pole flatness With discrete outside these structures in design) free from admixture a-Si layer in the impact of electric field intensity Calculate and judge to indicate these importances drastically changed reduced in photoelectric diode structure.

In the region close to the change (being characterized by for the r value below 0.1 μm) of flatness, electricity The maximum deviation of field may be very big, and (in these regions of the change closest to flatness) compare The value height of the electric field of pair of parallel electrode more than 300%, (at these areas adjacent) more flat than a pair The value of the electric field of row electrode is low is more than 60%.In the change close to flatness (by about 0.5 μm R value characterize) region in, the deviation of electric field can be (at these of the change closest to flatness In region) higher than the value of the electric field of pair of parallel electrode up to about 300%, (attached in these regions Closely) low than the value of the electric field of pair of parallel electrode up to about 60%.

In the region close to the change (being characterized by the r value of about 1 μm) of flatness, electric field Deviation can (in these regions of the change closest to flatness) than the electric field of pair of parallel electrode Value high up to about 200%, (at these areas adjacent) ratio amount of the electric field of pair of parallel electrode It is worth low up to about 50%.District in the change (being characterized by the r value of about 2 μm) close to flatness In territory, the deviation of electric field can (in these regions of the change closest to flatness) more flat than a pair The value of the electric field of row electrode high up to about 50%, (at these areas adjacent) than pair of parallel electricity The value of the electric field of pole is low up to about 30%.At the change (r by about 5 μm close to flatness Value characterizes) region in, the deviation of electric field can (these districts in the change closest to flatness In territory) higher than the value of the electric field of pair of parallel electrode up to about 20%, (at these areas adjacent) Lower than the value of the electric field of pair of parallel electrode up to about 15%.Close to flatness change (by Be about 10 μm r value characterize) region in, the deviation of electric field can be (closest to flatness In these regions changed) higher than the value of the electric field of pair of parallel electrode up to about 10%, ( These areas adjacent) lower than the value of the electric field of pair of parallel electrode up to about 10%.

Above-mentioned consideration item make following obviously: if manufacturing photoelectric diode structure outside face Do not consider the topological uniformity of photodiode, then gained topology (will be called former mutual topology, such as It is revealed in the example shown in Figure 21 to Figure 24) can interfere with and realize high-quality light electric diode And make to be associated with the performance degradation of the imager of the array with these photodiodes.Substantially and Speech, the release of dark current, charge-trapping, electric charge and delayed value are by along with photodiode The scope (that is, number and area) in the region drastically changed with flatness of electrode increase and Increase.The sharpness of the change of the flatness along with electrode is also increased and increases by these values. But, according to one embodiment of present invention, it is achieved that photoelectric diode structure outside high-quality face, Wherein photodiode is designed and manufactured to the smooth of the scope so that these regions and electrode The sharpness of the change of property is sufficiently reduced, so that photodiode shows dark current, electricity Lotus capture, electric charge release and delayed advantageous level.

Figure 26 to Figure 34 illustrates application various methods opening up with the outer photoelectric diode structure in improvement face Flutter the example of the result of uniformity.A kind of method for improving topology uniformity is for making at photoelectricity Material layer completely flatization below diode structure.The diagram of the application of the method is revealed in pin To in Figure 26 (a) and Figure 31 (b) of the situation of Amplifier Design in single-stage pixel, with for two-stage picture In element in Figure 27 and Figure 32 (b) of the situation of Amplifier Design.In either case, passivation has been made The end face of #2 is smooth.

So can (such as, in one embodiment of the invention) via applied chemistry-mechanical polishing (CMP, also referred to as chemical-mechanical planarization) and/or spin coating realize.Mistake at adopting said method Cheng Zhong, the thickness that initially can make passivation layer is thicker than the thickness under primary topology situation, in order to guarantee Minimum thickness after application CMP.This will help ensure that photodiode electrode and at light The parasitic capacitance between component below electric diode structure keeps below the desired limit. In the case of Figure 26 (a) and Figure 27 provides the primary topology illustrated with Figure 21 and Figure 22 respectively The cross section that improves of the gained of the topological uniformity of photodiode that compares of topological uniformity Figure.Figure 31 (b) and Figure 32 (b) provides respectively with Figure 31 (a) and Figure 32 (a) in illustrated in primary open up The top view that the gained of the topological uniformity flutterring the photodiode compared improves.The method exists Significantly improve the effectiveness in terms of topology uniformity to be apparent from.For improving photoelectricity outside face The other method of the topological uniformity of diode structure is to make below photoelectric diode structure The planarization of layer material sections ground, as illustrated in Figure 26 (b).So can be various known via using Technology (such as, these technology as described above) realizes.

In the outer photoelectric diode structure of continuous surface, the edge of hearth electrode (being formed by metal #2 layer) Produce the drastically change of the flatness of top electrode, as apparent in Figure 26 (a) and Figure 27 (a) 's.In one embodiment of the invention, it is desirable to make these edge-smoothings.According to the present invention In order to realize this smoothing a kind of method be via adjust in order to the edge limiting hearth electrode Etching technique, in order to realize that there is inclining of the radius of curvature bigger than the radius of curvature in primary topology Oblique or round-shaped.Figure 28 and Figure 29 provides and opening up shown in Figure 26 (a) and Figure 27 (a) respectively The cross-sectional view that the gained of the topological uniformity flutterring the photodiode that uniformity compares improves. Figure 31 (c) and Figure 32 (c) provides and the topological uniformity shown in Figure 31 (b) and Figure 32 (b) respectively The top view that the gained of the topological uniformity of the photodiode compared improves.The method is being entered The effectiveness that one step is improved in terms of topology uniformity is apparent from.

In the outer photoelectric diode structure of continuous surface, after the hearth electrode of photodiode is connected to One or more through holes of contact, portion also produce drastically changing of the flatness of top electrode and hearth electrode Become.A kind of method of these sharpness changed for reducing flatness according to the present invention is By making the lateral dimension (that is, along the size on surface of photodiode) of each through hole narrow The limit that (such as) to design rule is allowed and the area that reduces each through hole.Also use can be deposited In hearth electrode metal in case fill through hole.Figure 30 is and the topological uniformity shown in Figure 28 The cross-sectional view that the gained of the topological uniformity of the photodiode compared improves.(due at figure Through hole is there is not, the cross section taken in correspondence of Amplifier Design in not shown two-stage pixel in the visual field of 29 Diagram.) Figure 31 (d) and Figure 32 (d) is respectively with the topology shown in Figure 31 (c) and Figure 32 (c) all The top view that the gained of the topological uniformity of the photodiode that even property compares improves.The present invention The method effectiveness in terms of improving further topology uniformity be apparent from.

For improving outside face the other method of the topological uniformity of photoelectric diode structure for making light The top planar of the free from admixture a-Si layer in electric diode.The method is put in single-stage pixel The diagram of the application of the situation of big device design is revealed in Figure 33, Figure 34 (b) and Figure 34 (c).

Completely flatization of the free from admixture a-Si layer in photodiode can (such as) the present invention's One embodiment realizes via application CMP.During adopting said method, initially may be used The thickness making free from admixture a-Si layer is thicker than preferred thickness, in order to guarantee institute after application CMP The final thickness realized is corresponding to this preferred thickness.This will help ensure that photodiode table Reveal excellent properties.Figure 33 (a) provides compared with the situation of primary topology illustrated in Figure 21 Gained improve cross-sectional view.Figure 34 (c) provides the primary topology phase illustrated with Figure 34 (a) The top view that the gained of the topological uniformity of photodiode relatively improves.The method is significantly Effectiveness in terms of the uniformity of the top electrode improving photodiode is apparent from.With former Raw topology compares, and the uniformity of hearth electrode keeps constant.For improving photodiode outside face Another embodiment of the method for the topological uniformity of structure is to make the free from admixture in photodiode The planarization of a-Si layer segment ground, as illustrated in Figure 33 (b) and Figure 34 (b).So can be via use Various known technologies (such as, these technology as described above) realize.

Use as described in this article for improving photoelectric diode structure outside face combinedly The method of topological uniformity to realize the desired result of the present invention, described method includes: make One or more material layers (such as, passivation layer) planarization below photoelectric diode structure, Make the edge-smoothing of the hearth electrode of photoelectric diode structure, make the hearth electrode of photodiode The lateral dimension of the through hole being connected to back contact narrows and/or deposits the metal for hearth electrode So that filling through hole, and the free from admixture a-Si in photodiode is made to planarize.

From the obvious result shown in Figure 31, Figure 32 and Figure 34 it will be clear that the present invention carries For a kind of ability removing the topological inhomogeneities being associated with the edge of image element circuit element.Institute Stating planarization (as described above) makes the layer of covering image element circuit element or array features put down Smoothization, described image element circuit element or array features such as the following: TFT (includes TFT's Source electrode, drain electrode and grid), diode, capacitor and resistor, and through hole, trace, control Line processed, address wire, ground plane, electrode surface, light blocking surface, offset line, back contact With the hearth electrode of photodiode (it is all made up of multiple metal levels, passivation layer or dielectric layer), As discussed above and such as shown in the sectional view of Figure 26 to Figure 30 and Figure 33.With this side Formula, the invention is not restricted to the planarization above thin-film transistor element.Such as, even with All TFT image element circuit elements or array features (including but not limited to control line and address wire) phase The effect of the inhomogeneities of association also can be deposited on top follow-up of these structures by planarization Layer and alleviate, these structures include (such as) through lower passivation layer #1 electric through-hole cross tie part (as Shown in (such as) Figure 26).Even due to Amplifier Design in single-stage pixel (as Figure 17, In Figure 21 and Figure 23) or two-stage pixel in Amplifier Design (as in Figure 20, Figure 22 and Figure 24) and The inhomogeneities effect introduced also can be deposited on the succeeding layer of the top of these structures by planarization And alleviate.

In view of foregoing detailed description, hereafter with more generally term, the different real of the present invention is described Execute the various elements (but the most otherwise limiting the present invention) of example, in order to the diagram present invention's Feature.

In the first diagram embodiment, radiation sensor includes: flash layer, and this flash layer is joined It is set to when interacting launch photon with ionizing radiation；And photoelectric detector, it includes successively First electrode, photosensitive layer and the second electrode of the transmissive photon that arrange neighbouring with flash layer.Should Photosensitive layer is configured to when the part with described photon interacts produce electron hole pair. This radiation sensor includes: image element circuit, and it is electrically connected to the first electrode, and is configured For measuring instruction imaging signal of produced electron hole pair in photosensitive layer；And planarization layer, It is arranged on the image element circuit between the first electrode and image element circuit so that the first electrode exists Top including the plane of image element circuit.In described first electrode and described second electrode at least The surface of one is the most overlapping with this image element circuit and has the feature at this image element circuit The surface warp portion of top.This surface warp portion has the radius of curvature more than 1/2 micron.

Such as, according to the degree of planarization that is desired or that realized, this surface warp portion can have There is the radius of curvature more than 1 micron, more than 5 microns, more than 10 microns or more than 100 microns.Connect , planarization layer can be above the feature of image element circuit, above array features, even It is connected to the source electrode of TFT or the top of the electric through-hole cross tie part of drain electrode, amplifier in single-stage pixel The top of element and/or completely or partially put down above amplifier element in two-stage pixel Smoothization.Planarization layer can be at least one in passivation layer, dielectric layer or insulating barrier.

In an aspect of this embodiment, radiation sensor can include being arranged on Photoelectric Detection The address wire of the lower section of device and data wire, and, planarization layer is arranged on address wire and data On line and on the through hole of address wire and data wire.Wear it addition, electric through-hole cross tie part is extensible Cross planarization layer and the first electrode is connected to image element circuit.The electric through-hole contacted with photosensitive layer is mutual Even the surface warp portion of part can have more than 1/2 micron, more than 1 micron, more than 5 microns, be more than 10 microns and more than the radius of curvature of 100 microns.

In an aspect of this embodiment, photosensitive layer can be p-i-n semiconductor stack, n-i-p One in semiconductor stack or metal-insulator semiconductor's storehouse.Image element circuit can include thin film Transistor, diode, capacitor, resistor, trace, through hole, control line, address wire and One in ground plane.Image element circuit can be amorphous semiconductor transistor or poly semiconductor One in transistor or crystallite semiconductor transistor.Image element circuit can include address transistor, At least one in amplifier transistor and reset transistor.Image element circuit can be non-crystalline silicon, low At least one in temperature non-crystalline silicon and microcrystal silicon.Image element circuit can be at least in the following Kind: silicon semiconductor, oxide semiconductor, chalcogenide semiconductor, cadmium selenide quasiconductor, have Machine quasiconductor, organic molecule or polymer semiconductor, CNT or Graphene or other half Conductive material.

In an aspect of this embodiment, photosensitive layer can be at least one in the following: 1) the sense of continuity photosphere extended across multiple photo-detector pixel, or 2) and the plurality of smooth electric-examination Survey the discrete photosensitive layer that each photo-detector pixel in device pixel is associated.Flash layer can be At least one in the following: CsI:Tl, Gd₂O₂S:Tb、CsI:Na、NaI:Tl、CaWO₄、 ZnWO₄、CdWO₄、Bi₄Ge₃O₁₂、Lu_1.8Yb_0.2SiO₅:Ce、Gd₂SiO₅:Ce、 BaFCl:Eu²⁺、BaSO₄:Eu²⁺、BaFBr:Eu²⁺、LaOBr:Tb³⁺、LaOBr:Tm³⁺、 La₂O₂S:Tb³⁺、Y₂O₂S:Tb³⁺、YTaO₄、YTaO₄: Nb, ZnS:Ag, (Zn, Cd) S:Ag, ZnSiO₄:Mn²⁺、CsI、LiI:Eu²⁺、PbWO₄、Bi₄Si₃O₁₂、Lu₂SiO₅:Ce³⁺、 YAlO₃:Ce³⁺、CsF、CaF₂:Eu²⁺、BaF₂、CeF₃、Y_1.34Gd_0.6O₃:Eu³⁺、Pr、 Gd₂O₂S:Pr³⁺、Ce、SCGl、HFG:Ce³⁺And C (5%)₁₄H₁₀, or other flicker equipment Material.

In an aspect of this embodiment, radiation sensor can include supporting image element circuit, light Photodetector and the basal substrate of flash layer, and can include being arranged in this substrate base with regular pattern Multiple photo-detector pixel on plate.In an aspect of this embodiment, transmission photons Second electrode can form the biasing plane for the plurality of photo-detector pixel.Image element circuit A part may be disposed at the interstitial area on basal substrate and between adjacent photo detectors pixel In.This part can include thin film transistor (TFT), diode, capacitor, resistor, through hole, mark One in line, control line, address wire and ground plane.In an aspect of this embodiment, First electrode can have the angled end terminated near this interstitial area.

In an aspect of this embodiment, the second electrode of the first electrode and transmissive photon it Between dark current (being normalized to unit photoelectric detector area) be smaller than 10pA/mm², or be less than 5pA/mm², or less than 1pA/mm², or less than 0.5pA/mm².The level of dark current is at certain With the degree of planarization discussed herein above and (one or more) surface warp portion in the degree of kind Radius of curvature coupling.In an aspect of this embodiment, stick up close to surface in photosensitive layer Electric field in the region of pars convoluta can be more than between the first pair of parallel electrode and the second electrode Photosensitive layer in electric field 60%, and less than at the first pair of parallel electrode and the second electrode Between photosensitive layer in electric field 300%.The change of electric field to a certain extent with discussed above The radius of curvature coupling in the degree of the planarization stated and (one or more) surface warp portion.

In an aspect of this embodiment, sensor can include metallic plate, and it is arranged on sudden strain of a muscle Sparkle on layer or be arranged in the encapsulation on flash layer.

In the second diagram embodiment, radiation sensor includes: flash layer, and this flash layer is joined It is set to when interacting launch photon with ionizing radiation；Photoelectric detector, it includes successively One electrode, photosensitive layer and the second electrode of the transmissive photon that arrange neighbouring with flash layer.This sense Photosphere is configured to when the part with described photon interacts produce electron hole pair.Should Radiation sensor includes image element circuit, and it is electrically connected to the first electrode, and is configured to survey Amount instruction is the imaging signal of produced electron hole pair in photosensitive layer；And include planarization layer, It is arranged on the image element circuit between the first electrode and image element circuit so that the first electrode exists Top including the plane of image element circuit.This planarization layer has the spy along image element circuit element The first surface warpage portion of the periphery edge levied, this first electrode has second surface warpage portion, This second surface warpage portion above this first surface warpage portion and planarization layer and substrate On the surface that substrate is relative, and this second surface warpage portion has the curvature more than 1/2 micron half Footpath.

In an aspect of this embodiment, such as, according to planarization that is desired or that realized Degree, second surface warpage portion can have more than 1 micron, more than 5 microns, more than 10 microns Or the radius of curvature more than 100 microns.Then, planarization layer can upper in the feature of image element circuit Side, above array features, at the electric through-hole cross tie part of the source electrode or drain electrode being connected to TFT Top, in single-stage pixel above amplifier element and/or in two-stage pixel amplifier unit The top of part completely or partially planarizes.Planarization layer can be passivation layer, dielectric layer or At least one in insulating barrier.

In an aspect of this embodiment, radiation sensor can include being arranged on Photoelectric Detection The address wire of the lower section of device and data wire, and planarization layer is arranged on address wire and data wire And on the through hole of address wire and data wire.It addition, electric through-hole cross tie part can extend across flat Smoothization layer and the first electrode is connected to image element circuit.The electric through-hole cross tie part contacted with photosensitive layer Surface warp portion can have more than 1/2 micron, micro-more than 1 micron, more than 5 microns, more than 10 Rice or the radius of curvature more than 100 microns.

In an aspect of this embodiment, radiation sensor can include supporting image element circuit, light Photodetector and the basal substrate of flash layer.Radiation sensor can include being arranged in regular pattern Multiple photo-detector pixel on this basal substrate.In an aspect of this embodiment, should The biasing that second electrode of transmissive photon can be formed for the plurality of photo-detector pixel is put down Face.A part for image element circuit may be disposed on basal substrate and at adjacent photo detectors picture In interstitial area between element.This part can include thin film transistor (TFT), diode, capacitor, electricity One in resistance device, through hole, trace, control line, address wire and ground plane.Implement at this In one aspect of example, the first electrode can have the angled end terminated near this interstitial area. This sloping edge can have more than 1/2 micron or is more than 1 micron or is more than 5 microns or is more than 10 microns or more than the radius of curvature of 100 microns.

In an aspect of this embodiment, sensor can include the gold being arranged on flash layer Belong to plate.

In the 3rd diagram embodiment, radiation sensor includes flash layer, and this flash layer is configured For launching photon with ionizing radiation when interacting；Photoelectric detector, it includes first successively Electrode, photosensitive layer and the second electrode of the transmissive photon that arrange neighbouring with flash layer.This is photosensitive Layer is configured to when the part with described photon interacts produce electron hole pair.This spoke Penetrating sensor and include image element circuit, it is electrically connected to the first electrode, and is configured to measure Instruction is the imaging signal of produced electron hole pair in photosensitive layer；And include planarization layer, It is arranged on the image element circuit between the first electrode and image element circuit so that the first electrode exists Top including the plane of image element circuit.This photoelectric detector is at the first electrode and transmissive photon The second electrode between there is dark current (being normalized to unit photoelectric detector area), this is the most electric Stream is less than 10pA/mm²。

In an aspect of this embodiment, planarization layer can be passivation layer, dielectric layer or exhausted At least one in edge layer.In an aspect of this embodiment, above image element circuit The surface warp portion of the first electrode has more than 1/2 micron, more than 1 micron, more than 5 microns, big In 10 microns or more than the radius of curvature of 100 microns.

In an aspect of this embodiment, dark current (is normalized to unit photoelectric detector face Long-pending) it is smaller than 5pA/mm², or less than 1pA/mm², or less than 0.5pA/mm².Dark current Level to a certain extent with the degree of planarization discussed herein above and (one or more) The radius of curvature coupling in surface warp portion.

In the 4th diagram embodiment, radiation sensor includes: flash layer, and this flash layer is joined It is set to when interacting launch photon with ionizing radiation；Photoelectric detector, it includes successively One electrode, photosensitive layer and the second electrode of the transmissive photon that arrange neighbouring with flash layer.This sense Photosphere is configured to when the part with described photon interacts produce electron hole pair.Should Radiation sensor includes image element circuit, and it is electrically connected to the first electrode, and is configured to survey Amount instruction is the imaging signal of produced electron hole pair in photosensitive layer；And include planarization layer, It is arranged on the image element circuit between the first electrode and image element circuit so that the first electrode exists Top including the plane of image element circuit.This photoelectric detector is for each photo-detector pixel There is the level of charge-trapping, this level be by during single radiography frame due to capture The amount of the imaging signal (instruction is produced electron hole pair in photosensitive layer) of loss quantifies, And it is expressed as the imaging signal of acquisition under conditions of charge-trapping is in balance with electric charge release Percentage ratio, this percentage ratio is less than about 20%.

In an aspect of this embodiment, such as, according to planarization that is desired or that realized Degree, the level of the charge-trapping of each photo-detector pixel is smaller than 15%, less than 10% Or less than 5%.

In the 5th diagram embodiment, radiation sensor includes: flash layer, and this flash layer is joined It is set to when interacting launch photon with ionizing radiation；Photoelectric detector, it includes successively One electrode, photosensitive layer and the second electrode of the transmissive photon that arrange neighbouring with flash layer.This sense Photosphere is configured to when the part with described photon interacts produce electron hole pair.Should Radiation sensor includes image element circuit, and it is electrically connected to the first electrode, and is configured to survey Amount instruction is the imaging signal of produced electron hole pair in photosensitive layer；And include planarization layer, It is arranged on the image element circuit between the first electrode and image element circuit so that the first electrode is at bag Include the top of the plane of image element circuit.This photoelectric detector has for each photo-detector pixel Having electric charge to discharge, the release of this electric charge is by the case of having radiation and at charge-trapping and electricity Lotus release be in after the series of frames obtained under conditions of balance in the situation that there is not radiation During first frame of lower acquisition, from imaging signal (instruction institute in photosensitive layer of trapped state release The electron hole pair produced) amount quantify, and be expressed as being in balance in charge-trapping and release Under conditions of the percentage ratio of imaging signal that obtains, described electric charge release less than about 15%.

In an aspect of this embodiment, such as, according to planarization that is desired or that realized Degree, the electric charge release of each photo-detector pixel is smaller than 10%, less than 5% or be less than 3%.

In the 6th diagram embodiment, radiation sensor includes: flash layer, and this flash layer is joined It is set to when interacting launch photon with ionizing radiation；Photoelectric detector, it includes successively One electrode, photosensitive layer and the second electrode of the transmissive photon that arrange neighbouring with flash layer.This sense Photosphere is configured to when the part with described photon interacts produce electron hole pair.Should Radiation sensor includes image element circuit, and it is electrically connected to the first electrode, and is configured to survey Amount instruction is the imaging signal of produced electron hole pair in photosensitive layer；And include planarization layer, It is arranged on the image element circuit between the first electrode and image element circuit so that the first electrode exists Top including the plane of image element circuit.This photoelectric detector is for each photo-detector pixel Having delayed, this is delayed is a frame or a series of by obtaining in the case of having radiation During the first frame obtained in the case of there is not radiation after frame, discharge from trapped state Imaging signal (this imaging signal instruction produced electron hole pair in photosensitive layer, and this one-tenth Image signal originates from the electric charge captured in one or more previous frames) amount quantify, and table Reach the percentage ratio for the imaging signal from previous frame, described delayed less than about 15%.

In an aspect of this embodiment, such as, according to planarization that is desired or that realized Degree, each photo-detector pixel delayed is smaller than 10%, less than 5% or less than 3%.

In the 7th diagram embodiment, radiation sensor includes: flash layer, and this flash layer is joined It is set to when interacting launch photon with ionizing radiation；Photoelectric detector, it includes successively One electrode, photosensitive layer and the second electrode of the transmissive photon that arrange neighbouring with flash layer.This sense Photosphere is configured to when the part with described photon interacts produce electron hole pair.Should Radiation sensor includes image element circuit, and it is electrically connected to the first electrode, and is configured to survey Amount instruction is the imaging signal of produced electron hole pair in photosensitive layer；And include planarization layer, It is arranged on the image element circuit between the first electrode and image element circuit so that the first electrode exists Top including the plane of image element circuit.This first electrode can be in a part for this image element circuit Extend above, and can have transverse edge, longitudinal edge and this transverse edge with should The corner of the intersection of longitudinal edge.This transverse edge can with at least one in this longitudinal edge For sloping edge.

In an aspect of this embodiment, this corner can be that transverse edge is connected to longitudinal edge The rounded corners of edge.This sloping edge can have more than 1/2 micron or be more than 1 micron or big In 5 microns or more than 10 microns or more than the radius of curvature of 100 microns.In this embodiment one In individual aspect, planarization layer can be at least one in passivation layer, dielectric layer or insulating barrier.

In the 8th diagram embodiment, radiation sensor includes: flash layer, and this flash layer is joined It is set to when interacting launch photon with ionizing radiation；Photo-detector pixel, it wraps successively Include the first electrode, photosensitive layer and the second electrode of the transmissive photon that arrange neighbouring with flash layer. This photosensitive layer is configured to when the part with described photon interacts produce electron hole Right.This radiation sensor includes image element circuit, and it is electrically connected to the first electrode, and is joined It is set to measure instruction imaging signal of produced electron hole pair in photosensitive layer；And include blunt Changing layer, it is arranged on the image element circuit between the first electrode and image element circuit so that first Electrode is including above the plane of image element circuit.This passivation layer has at image element circuit element The first surface warpage portion of top.This second electrode has above this first surface warpage portion Second surface warpage portion.This second surface warpage portion has the radius of curvature more than 1/2 micron.

This second surface warpage portion can have more than 1 micron or be more than 5 microns or micro-more than 10 Rice or the radius of curvature more than 100 microns.This passivation layer can be the passivation layer of planarization.This is photosensitive Layer can be the photosensitive layer of planarization.

In the 9th diagram embodiment, radiation sensor includes: flash layer, and this flash layer is joined It is set to when interacting launch photon with ionizing radiation；Photoelectric detector, it includes successively One electrode, photosensitive layer and the second electrode of the transmissive photon that arrange neighbouring with flash layer.This sense Photosphere is configured to when the part with described photon interacts produce electron hole pair.Should Radiation sensor includes image element circuit, and it is electrically connected to the first electrode, and is configured to survey Amount instruction is the imaging signal of produced electron hole pair in photosensitive layer；And include planarization layer, It is arranged on the image element circuit between the first electrode and image element circuit so that the first electrode exists Top including the plane of image element circuit.In described first electrode and described second electrode at least The surface of one can be the most overlapping with this image element circuit and to can be without showing instruction following The surface character of image element circuit.

Illustrate in embodiment and these embodiments discussed below above-mentioned first to the 9th In, then, planarization layer can above some features of image element circuit completely or partially Planarization.Planarization layer can be at least one in passivation layer, dielectric layer or insulating barrier.Example As, according to the degree of planarization that is desired or that realized, first above image element circuit The surface warp portion of electrode can have more than 1/2 micron, more than 1 micron, more than 5 microns, be more than 10 microns or more than the radius of curvature of 100 microns.Metallic plate may be disposed on flash layer.It addition, Illustrate in embodiment and in these embodiments discussed below above-mentioned first to the 9th, electricity Through-hole interconnection part can extend across planarization layer and the first electrode be connected to image element circuit.With sense The surface warp portion of the electric through-hole cross tie part of photosphere contact can have more than 1/2 micron, more than 1 micro- Rice, more than 5 microns, more than 10 microns with more than the radius of curvature of 100 microns.

Illustrate in embodiment and these embodiments discussed below above-mentioned first to the 9th In, photosensitive layer can be that p-i-n semiconductor stack, n-i-p semiconductor stack or metal insulator are partly led One in body storehouse.Image element circuit can include thin film transistor (TFT), diode, capacitor, electricity One in resistance device, trace, through hole, control line, address wire and ground plane.Image element circuit Can be in amorphous semiconductor transistor or poly semiconductor transistor or crystallite semiconductor transistor One.Image element circuit can include addressing in transistor, amplifier transistor and reset transistor At least one.Image element circuit can be at least in non-crystalline silicon, low temperature amorphous silicon and microcrystal silicon Kind.Image element circuit can be at least one in the following: silicon semiconductor, oxide semiconductor, Chalcogenide semiconductor, cadmium selenide quasiconductor, organic semiconductor, organic molecule or polymer Quasiconductor, CNT or Graphene or other semiconductive materials.

Illustrate in embodiment and these embodiments discussed below above-mentioned first to the 9th In, photosensitive layer can be at least one in the following: 1) across multiple photo-detector pixel Extend sense of continuity photosphere, or 2) with the plurality of photo-detector pixel in each Photoelectric Detection The discrete photosensitive layer that device pixel is associated.Flash layer can be at least one in the following: CsI:Tl、Gd₂O₂S:Tb、CsI:Na、NaI:Tl、CaWO₄、ZnWO₄、CdWO₄、 Bi₄Ge₃O₁₂、Lu_1.8Yb_0.2SiO₅:Ce、Gd₂SiO₅:Ce、BaFCl:Eu²⁺、BaSO₄:Eu²⁺、 BaFBr:Eu²⁺、LaOBr:Tb³⁺、LaOBr:Tm³⁺、La₂O₂S:Tb³⁺、Y₂O₂S:Tb³⁺、 YTaO₄、YTaO₄: Nb, ZnS:Ag, (Zn, Cd) S:Ag, ZnSiO₄:Mn²⁺、CsI、 LiI:Eu²⁺、PbWO₄、Bi₄Si₃O₁₂、Lu₂SiO₅:Ce³⁺、YAlO₃:Ce³⁺、CsF、 CaF₂:Eu²⁺、BaF₂、CeF₃、Y_1.34Gd_0.6O₃:Eu³⁺、Pr、Gd₂O₂S:Pr³⁺、Ce、 SCGl、HFG:Ce³⁺And C (5%)₁₄H₁₀, or other scintillator materials.

Illustrate in embodiment and these embodiments discussed below above-mentioned first to the 9th In, radiation sensor can include supporting image element circuit, photoelectric detector and the substrate base of flash layer Plate.Radiation sensor can include the multiple smooth electric-examination being arranged on this basal substrate with regular pattern Survey device pixel.In an aspect of this embodiment, the second electrode of this transmissive photon can shape Become the biasing plane for the plurality of photo-detector pixel.A part for image element circuit can be set Put in the interstitial area on basal substrate and between adjacent photo detectors pixel.This part can Including thin film transistor (TFT), diode, capacitor, resistor, through hole, trace, control line, One in address wire and ground plane.First electrode can have and terminates near this interstitial area Angled end.The example of the preferred compositions of these features is provided below.

Illustrate in embodiment and these embodiments discussed below above-mentioned first to the 9th In, metallic plate may be disposed on the second electrode of transmissive ionizing radiation or may be disposed at can On encapsulated layer on second electrode of transmitted ionizing radiation.It addition, planarization layer can be special at array The top levied, above the electric through-hole cross tie part of the source electrode or drain electrode that are connected to TFT, at list In level pixel amplifier element top or in two-stage pixel at least portion above amplifier element Divide ground planarization.

In the tenth diagram embodiment, radiation sensor includes optical conductor detector, and it wraps successively Include the second electrode of the first electrode, photoconductive layer and transmissive ionizing radiation.This photoconductive layer is configured For producing electron hole pair with ionizing radiation when interacting.This radiation sensor includes pixel Circuit, it is electrically connected to the first electrode, and is configured to measure instruction institute in photoconductive layer The imaging signal of the electron hole pair produced；And planarization layer, its be arranged on the first electrode with On image element circuit between image element circuit so that first electrode is including the plane of image element circuit Top.The surface of at least one in described first electrode and described second electrode and this pixel electricity Road is overlapping at least in part and has the surface warp portion above the feature of this image element circuit. This surface warp portion has the radius of curvature more than 1/2 micron.

In an aspect of this embodiment, planarization layer can be passivation layer, dielectric layer or exhausted At least one in edge layer.In an aspect of this embodiment, above image element circuit The surface warp portion of the first electrode has more than 1/2 micron, more than 1 micron, more than 5 microns, big In 10 microns or more than the radius of curvature of 100 microns.It addition, electric through-hole cross tie part can extend across Planarization layer and the first electrode is connected to image element circuit.The electric through-hole interconnection contacted with photosensitive layer The surface warp portion of part can have more than 1/2 micron, more than 1 micron, more than 5 microns, more than 10 Micron and the radius of curvature more than 100 microns.

In an aspect of this embodiment, image element circuit can include thin film transistor (TFT), diode, One in capacitor, resistor, trace, through hole, control line, address wire and ground plane. Image element circuit can be amorphous semiconductor transistor or poly semiconductor transistor or crystallite semiconductor One in transistor.Image element circuit can include addressing transistor, amplifier transistor and replacement At least one in transistor.Image element circuit can be in non-crystalline silicon, low temperature amorphous silicon and microcrystal silicon At least one.Image element circuit can be at least one in the following: silicon semiconductor, oxidation Thing quasiconductor, chalcogenide semiconductor, cadmium selenide quasiconductor, organic semiconductor, organic little point Son or polymer semiconductor, CNT or Graphene or other semiconductive materials.

In an aspect of this embodiment, metallic plate may be disposed at this transmissive ionizing radiation The second electrode on or may be disposed at the encapsulated layer on the second electrode of this transmissive ionizing radiation On.It addition, planarization layer can above array features, be connected to source electrode or the leakage of TFT The top of the electric through-hole cross tie part of pole, in single-stage pixel above amplifier element or in two-stage The planarization at least partially above of amplifier element in pixel.

In an aspect of this embodiment, photoconductive layer can be at least one in the following: 1) the continuous light conducting shell extended across multiple optical conductor detector pixel, or 2) and the plurality of photoconduction The discrete light conducting shell that each optical conductor detector pixel in detector pixel is associated.Radiation Sensor can include supporting image element circuit and the basal substrate of photoconductive layer.Radiation sensor can include The multiple optical conductor detector pixel being arranged on this basal substrate with regular pattern.Implement at this In one aspect of example, the second electrode of this transmissive ionizing radiation can be formed for the plurality of light The biasing plane of conductor detector pixel.A part for image element circuit may be disposed at basal substrate In interstitial area above and between adjacent light guides detector pixel.This part can include that thin film is brilliant Body pipe, diode, capacitor, resistor, through hole, trace, control line, address wire and connect One in ground level.First electrode can have the angled end terminated near this interstitial area.

Therefore, the tenth diagram embodiment includes the feature similar with above-mentioned first diagram embodiment, But need not the scintillator layer in the first diagram embodiment and photosensitive layer.Here, in the tenth diagram In embodiment, photoconductive layer produces electron hole when interacting with x-ray or other ionizing radiation Right.Photoconductive layer can include with at least one in lower semiconductor: VB-VIB, VB-VIIB, IIB-VIB, IIB-VB, IIIB-VB, IIIB-VIB, IB-VIB and IVB-VIIB, and more Specifically, it may include at least one in the following: a-Se, PbI₂、HgI₂、PbO、 CdZnTe、CdTe、Bi₂S₃、Bi₂Se₃、BiI₃、BiBr₃、CdS、CdSe、HgS、 Cd₂P₃、InAs、InP、In₂S₃、In₂Se₃、Ag₂S、PbI₄ ^-2And Pb₂I₇ ^-3。

Implement it addition, may be included in the tenth diagram above for the feature described by first embodiment In example.This same summary is applicable to remaining embodiment hereafter, and for the sake of clarity, hereafter To optionally repeat this same summary.It addition, radius of curvature as described above, dark current, The release of the level of charge-trapping, electric charge and delayed value and scope are suitably applicable to herein.Under Literary composition provides the example of the preferred compositions of these parameters.

In the 11st diagram embodiment, radiation sensor includes optical conductor detector, and it is successively The second electrode including the first electrode, photoconductive layer and transmissive ionizing radiation.This photoconductive layer is joined It is set to when interacting produce electron hole pair with ionizing radiation.This radiation sensor includes: Image element circuit, it is electrically connected to the first electrode, and is configured to measure instruction at photoconductive layer The imaging signal of electron hole pair produced by；And planarization layer, it is arranged on the first electricity On image element circuit between pole and image element circuit so that the first electrode is including the flat of image element circuit The top in face.This planarization layer has the of the periphery edge of the feature along image element circuit element One surface warp portion.This first electrode has second surface warpage portion, this second surface warpage portion Above this first surface warpage portion and on the surface relative with basal substrate of this planarization layer On.This second surface warpage portion has the radius of curvature more than 1/2 micron.

In the 12nd diagram embodiment, radiation sensor includes optical conductor detector, and it is successively The second electrode including the first electrode, photoconductive layer and transmissive ionizing radiation.This photoconductive layer is joined It is set to when interacting produce electron hole pair with ionizing radiation.This radiation sensor includes: Image element circuit, it is electrically connected to the first electrode, and is configured to measure instruction at photoconductive layer The imaging signal of electron hole pair produced by；And planarization layer, it is arranged on the first electricity On image element circuit between pole and image element circuit so that the first electrode is including the flat of image element circuit The top in face.This optical conductor detector has dark current (rule between the first electrode and the second electrode Format to unit optical conductor detector area), this dark current is less than 10pA/mm²。

In an aspect of this embodiment, dark current (is normalized to unit optical conductor detector Area) it is smaller than 5pA/mm², or less than 1pA/mm², or less than 0.5pA/mm².Dark electricity Stream level to a certain extent with the degree of planarization discussed herein above and (one or more) The radius of curvature coupling in surface warp portion.

In the 13rd diagram embodiment, radiation sensor includes optical conductor detector, and it is successively The second electrode including the first electrode, photoconductive layer and transmissive ionizing radiation.This photoconductive layer is joined It is set to when interacting produce electron hole pair with ionizing radiation.This radiation sensor includes: Image element circuit, it is electrically connected to the first electrode, and is configured to measure instruction at photoconductive layer The imaging signal of electron hole pair produced by；And planarization layer, it is arranged on the first electricity On image element circuit between pole and image element circuit so that the first electrode is including the flat of image element circuit The top in face.This optical conductor detector has charge-trapping for each optical conductor detector pixel Level, this level is the imaging by losing due to capture during single radiography frame The amount of signal (instruction is produced electron hole pair in photoconductive layer) quantifies, and is expressed as The percentage ratio of the imaging signal that charge-trapping obtains under conditions of being in balance with electric charge release, should Level is less than about 20%.

In an aspect of this embodiment, such as, according to planarization that is desired or that realized Degree, the level of the charge-trapping of each optical conductor detector pixel is smaller than 15%, is less than 10% or less than 5%.

In the 14th diagram embodiment, radiation sensor includes optical conductor detector, and it is successively The second electrode including the first electrode, photoconductive layer and transmissive ionizing radiation.This photoconductive layer is joined It is set to when interacting produce electron hole pair with ionizing radiation.This radiation sensor includes: Image element circuit, it is electrically connected to the first electrode, and is configured to measure instruction at photoconductive layer The imaging signal of electron hole pair produced by；And planarization layer, it is arranged on the first electricity On image element circuit between pole and image element circuit so that the first electrode is including the flat of image element circuit The top in face.This optical conductor detector has electric charge release for each optical conductor detector pixel, The release of this electric charge is to be in by discharging in the case of having radiation and at charge-trapping and electric charge After the series of frames obtained under conditions of balance obtain in the case of there is not radiation the During one frame, from the imaging signal of trapped state release, (instruction is produced electronics in photoconductive layer Hole to) amount quantify, and be expressed as under conditions of charge-trapping is in balance with release obtaining The percentage ratio of the imaging signal obtained, described electric charge release less than about 15%.

In an aspect of this embodiment, such as, according to planarization that is desired or that realized Degree, the electric charge release of each optical conductor detector pixel is smaller than 10%, less than 5% or little In 3%.

In the 15th diagram embodiment, radiation sensor includes optical conductor detector, and it is successively The second electrode including the first electrode, photoconductive layer and transmissive ionizing radiation.This photoconductive layer is joined It is set to when interacting produce electron hole pair with ionizing radiation.This radiation sensor includes: Image element circuit, it is electrically connected to the first electrode, and is configured to measure instruction at photoconductive layer The imaging signal of electron hole pair produced by；And planarization layer, it is arranged on the first electricity On image element circuit between pole and image element circuit so that the first electrode is including the flat of image element circuit The top in face.This optical conductor detector has delayed for each optical conductor detector pixel, should Delayed be by the case of there is radiation obtain a frame or series of frames after not During the first frame obtained in the case of there is radiation, (it is somebody's turn to do from the imaging signal of trapped state release Imaging signal instruction is produced electron hole pair in photoconductive layer, and this imaging signal originates from The electric charge captured in one or more previous frames) amount quantify, and be expressed as from previously The percentage ratio of the imaging signal of frame, described delayed less than about 15%.

In an aspect of this embodiment, such as, according to planarization that is desired or that realized Degree, each optical conductor detector pixel delayed be smaller than 10%, less than 5% or be less than 3%.

In the 16th diagram embodiment, radiation sensor includes optical conductor detector, and it is successively The second electrode including the first electrode, photoconductive layer and transmissive ionizing radiation.This photoconductive layer is joined It is set to when interacting produce electron hole pair with ionizing radiation.This radiation sensor includes: Image element circuit, it is electrically connected to the first electrode, and is configured to measure instruction at photoconductive layer The imaging signal of electron hole pair produced by；And planarization layer, it is arranged on the first electricity On image element circuit between pole and image element circuit so that the first electrode is including the flat of image element circuit The top in face.This first electrode extends above and has transverse edge, vertical at this image element circuit To edge and in the corner of this transverse edge Yu the intersection of this longitudinal edge.This widthwise edge At least one in edge and this longitudinal edge includes sloping edge.

In the 17th diagram embodiment, radiation sensor includes optical conductor detector, and it is successively The second electrode including the first electrode, photoconductive layer and transmissive ionizing radiation.This photoconductive layer is joined It is set to when interacting produce electron hole pair with ionizing radiation.This radiation sensor includes: Image element circuit, it is electrically connected to the first electrode, and is configured to measure instruction at photoconductive layer The imaging signal of electron hole pair produced by；And passivation layer, it is arranged on the first electrode And on the image element circuit between image element circuit so that the first electrode is including the plane of image element circuit Top.This passivation layer has the first surface warpage portion above image element circuit element.Should Second electrode has the second surface warpage portion above this first surface warpage portion.This is second years old Surface warp portion has the radius of curvature more than 1/2 micron.

This second surface warpage portion can have more than 1 micron or be more than 5 microns or micro-more than 10 Rice or the radius of curvature more than 100 microns.This passivation layer can be the passivation layer of planarization.Photosensitive layer It can be the photoconductive layer of planarization.

In the 18th diagram embodiment, radiation sensor includes optical conductor detector, and it is successively The second electrode including the first electrode, photoconductive layer and transmissive ionizing radiation.This photoconductive layer is joined It is set to when interacting produce electron hole pair with ionizing radiation.This radiation sensor includes: Image element circuit, it is electrically connected to the first electrode, and is configured to measure instruction at photoconductive layer The imaging signal of electron hole pair produced by；And planarization layer, it is arranged on the first electricity On image element circuit between pole and image element circuit so that the first electrode is including the flat of image element circuit The top in face.The surface of at least one in described first electrode and described second electrode can be with this Image element circuit is overlapping at least in part and can be without showing the surface of the following image element circuit of instruction Feature.

In the 19th diagram embodiment, a kind of method for manufacturing radiation sensor includes: Basal substrate is formed image element circuit element；Formed flat above described image element circuit element Smoothization layer；Hole is formed to expose the connector to image element circuit element in planarization layer；Make figure The hole metallization of case；Formed and the first electrode of metallized hole electrical contact；Electric with first Extremely upper formation is to light or the layer of ionizing radiation sensitive.Form this planarization layer with image element circuit extremely Thering is provided surface warp portion on the surface of the first partially overlapping electrode, this surface warp portion exists The top of the feature of image element circuit, and there is the radius of curvature more than 1/2 micron.

In an aspect of this embodiment, by photosensitive layer and the second electrode shape of transmissive photon Become on the first electrode, and passivation layer is formed on the second electrode of this transmissive photon, and Flash layer is formed on this passivation layer, this flash layer be configured to ionizing radiation phase interaction Used time launches photon.In this example, photosensitive layer planarizes or can form transmissive Photosensitive layer is made to planarize before second electrode of photon.

In the different aspect of this embodiment, photoconductive layer is formed at (this light on the first electrode Conducting shell is configured to when interacting with x-ray or other ionizing radiation produce electron hole Right), and the second electrode of transmissive ionizing radiation is formed on this photoconductive layer.

In in terms of the two, the second electrode may be disposed on the passivation layer on flash layer or quilt It is arranged on the encapsulated layer on photoconductive layer.In in terms of the two, metallic plate may be disposed at sudden strain of a muscle Sparkle on layer or be arranged in the encapsulation on flash layer, or being arranged on transmissive ionizing radiation On encapsulated layer on second electrode.

In an aspect of this embodiment, such as, according to planarization that is desired or that realized Degree, planarization layer can be formed to have more than 1 micron, more than 5 microns, more than 10 microns Or the radius of curvature more than 100 microns.Can be by the chemically mechanical polishing to the passivation layer deposited Form planarization layer.Or, can be by spin coating passivation layer and then to this passivation layer Learn mechanical polishing and form planarization layer.Or, one (or first) can be spin-coated on by use Another passivation layer of the deposited on top of passivation layer and then this another (or second) passivation layer being carried out Chemically mechanical polishing forms planarization layer.Planarization layer can be above array features, even It is connected to the source electrode of TFT or the top of the electric through-hole cross tie part of drain electrode, amplifier in single-stage pixel The top of element or the planarization at least partially above of amplifier element in two-stage pixel.

In an aspect of this embodiment, the adjacent picture close to radiation sensor of the first electrode The end of the interstitial area between element can be tilt.In an aspect of this embodiment, such as, According to the degree of planarization that is desired or that realized, metallized hole can be made to be tapered and have Have more than 1/2 micron or more than 1 micron, more than 5 microns, more than 10 microns or micro-more than 100 The radius of curvature of rice.

In an aspect of this 19th embodiment, the first figure can be formed on basal substrate Show in the aspect of embodiment for the feature listed by image element circuit element and photosensitive layer.Such as, When forming flash layer, can be formed in the following extremely on the second electrode of transmissive photon Few one: CsI:Tl, Gd₂O₂S:Tb、CsI:Na、NaI:Tl、CaWO₄、ZnWO₄、 CdWO₄、Bi₄Ge₃O₁₂、Lu_1.8Yb_0.2SiO₅:Ce、Gd₂SiO₅:Ce、BaFCl:Eu²⁺、 BaSO₄:Eu²⁺、BaFBr:Eu²⁺、LaOBr:Tb³⁺、LaOBr:Tm³⁺、La₂O₂S:Tb³⁺、 Y₂O₂S:Tb³⁺、YTaO₄、YTaO₄: Nb, ZnS:Ag, (Zn, Cd) S:Ag, ZnSiO₄:Mn²⁺、 CsI、LiI:Eu²⁺、PbWO₄、Bi₄Si₃O₁₂、Lu₂SiO₅:Ce³⁺、YAlO₃:Ce³⁺、CsF、 CaF₂:Eu²⁺、BaF₂、CeF₃、Y_1.34Gd_0.6O₃:Eu³⁺、Pr、Gd₂O₂S:Pr³⁺、Ce、 SCGl、HFG:Ce³⁺And C (5%)₁₄H₁₀.Shape on the second electrode can provided before flash layer Become passivation layer.Such as, when forming photosensitive layer, at least one in formation the following: 1) The sense of continuity photosphere extended across multiple photo-detector pixel, or 2) and the plurality of Photoelectric Detection The discrete photosensitive layer that in device pixel one is associated.

Such as, when formed photoconductive layer time, can be formed on the first electrode with in lower semiconductor extremely Few one: VB-VIB, VB-VIIB, IIB-VIB, IIB-VB, IIIB-VB, IIIB-VIB, IB-VIB and IVB-VIIB, or more specifically, can be formed in the following on the first electrode At least one: a-Se, PbI₂、HgI₂、PbO、CdZnTe、CdTe、Bi₂S₃、Bi₂Se₃、 BiI₃、BiBr₃、CdS、CdSe、HgS、Cd₂P₃、InAs、InP、In₂S₃、In₂Se₃、 Ag₂S、PbI₄ ^-2And Pb₂I₇ ^-3.Such as, when forming photoconductive layer, in formation the following extremely Few one: 1) the continuous light conducting shell that extends across multiple optical conductor detector pixel, or 2) with should The discrete light conducting shell that in multiple optical conductor detector pixel one is associated.

Such as, when forming image element circuit element, amorphous state can be formed on basal substrate and partly lead At least one in body transistor or crystallite semiconductor transistor or poly semiconductor transistor.When When forming image element circuit element, at least one in the following can be formed on basal substrate: Addressing transistor, amplifier transistor and reset transistor.When forming image element circuit element, At least one in the following can be formed: silicon semiconductor, oxide are partly led on basal substrate Body, chalcogenide semiconductor, cadmium selenide quasiconductor, organic semiconductor, organic molecule or poly- Compound quasiconductor, CNT or Graphene.When forming image element circuit element, can be in substrate Form at least one in the following on substrate: thin film transistor (TFT), diode, capacitor, Resistor, trace, through hole, control line, address wire and ground plane.

It addition, in the 19th diagram embodiment, the second electrode can be formed at light or ionization On radiosensitive layer.Metallic plate can be formed on the second electrode of transmissive photon, or Metallic plate can be formed in the encapsulation on flash layer.In the 19th diagram embodiment, can be by Metallic plate is formed on the second electrode of transmissive ionizing radiation, or, metallic plate can be formed On encapsulated layer on the second electrode of transmissive ionizing radiation.

In the 20th diagram embodiment, a kind of method for manufacturing radiation sensor includes: Basal substrate is formed image element circuit element；Formed above image element circuit the first electrode and Photosensitive layer；This photosensitive layer is made to planarize；The photosensitive layer of this planarization is formed transmissive photon The second electrode；With formation scintillator layer on the second electrode of transmissive photon.Described first At least one in electrode and described second electrode has above the feature of this image element circuit Surface warp portion, such as, according to the degree of planarization that is desired or that realized, this surface is stuck up Pars convoluta has more than 1/2 micron or more than 1 micron, more than 5 microns, more than 10 microns or be more than The radius of curvature of 100 microns.

In the 21st diagram embodiment, a kind of method bag for manufacturing radiation sensor Include: on basal substrate, form image element circuit element；The first electricity is formed above this image element circuit Pole and photoconductive layer；This photoconductive layer is made to planarize；Can be saturating with being formed on the photoconductive layer of this planarization Penetrate the second electrode of ionizing radiation.Second electrode of this transmissive ionizing radiation has in this pixel The surface warp portion of the top of the feature of circuit, such as, according to desired or realized smooth The degree changed, this surface warp portion have more than 1/2 micron or more than 1 micron, more than 5 microns, Radius of curvature more than 10 microns or more than 100 microns.

In the 22nd diagram embodiment, a kind of method bag for manufacturing radiation sensor Include: on basal substrate, form image element circuit element；Upper square at described image element circuit element Become planarization layer；Hole is formed to expose the connector to image element circuit element in planarization layer； Make the hole metallization of patterning；Formed and the first electrode of metallized hole electrical contact；With The layer to light or ionizing radiation sensitive is formed on one electrode.Form this planarization layer and the first electricity is provided The surface of pole, this surface is the most overlapping with this image element circuit, and this surface does not show Indicate the surface character of following image element circuit.

In the 23rd diagram embodiment, a kind of method bag for manufacturing radiation sensor Include: on basal substrate, form image element circuit element；The first electricity is formed above image element circuit Pole and photosensitive layer；This photosensitive layer is made to planarize；The photosensitive layer of this planarization is formed transmissive Second electrode of photon；With formation scintillator layer on the second electrode of transmissive photon.Make this Photosensitive layer planarization provides a surface of the second electrode, and this surface is at least part of with this image element circuit Ground is overlapping, and this surface does not show the surface character of the following image element circuit of instruction.

In the 24th diagram embodiment, radiation sensor includes: flash layer, this flash layer It is configured to when interacting launch photon with ionizing radiation；Photoelectric detector, it wraps successively Include the first electrode, photosensitive layer and the second electrode of the transmissive photon that arrange neighbouring with flash layer. This photosensitive layer is configured to when the part with described photon interacts produce electron hole Right.This radiation sensor includes image element circuit, and it is electrically connected to the first electrode, and is joined It is set to measure instruction imaging signal of produced electron hole pair in photosensitive layer, and this pixel Circuit includes oxide semiconductor.This radiation sensor includes planarization layer, and it is arranged on On image element circuit between one electrode and image element circuit so that the first electrode is including image element circuit The top of plane.The surface of at least one in described first electrode and described second electrode with This image element circuit is the most overlapping, and has the table above the feature of this image element circuit Warpage portion, face.This surface warp portion has the radius of curvature more than 1/2 micron.

In an aspect of this embodiment, oxide semiconductor includes in the following at least A kind of: containing zinc oxide, SnO₂、TiO₂、Ga₂O₃、InGaO、In₂O₃And InSnO. At least one in ZnO, InGaZnO, InZnO, ZnSnO can be included containing zinc oxide. Oxide semiconductor can include at least one in amorphous semiconductor or poly semiconductor.

Therefore, the 24th embodiment is similar to first embodiment in scope and includes institute above The aspect of the first embodiment discussed, then describes the example of preferred compositions.

Such as, according to the degree of planarization that is desired or that realized, this surface warp portion can have There is the radius of curvature more than 1 micron, more than 5 microns, more than 10 microns or more than 100 microns.? In another aspect, the surface of at least one in described first electrode and described second electrode can The most overlapping with this image element circuit, and can be without showing the image element circuit that instruction is following Surface character.

In an aspect of this embodiment, address wire and data wire are arranged on photoelectric detector Lower section；And planarization layer is arranged on address wire and data wire and in address wire and data On the through hole of line.Then, planarization layer can be above the feature of image element circuit, array spy The top levied, above the electric through-hole cross tie part of the source electrode or drain electrode that are connected to TFT, at list The top of amplifier element and/or complete above amplifier element in two-stage pixel in level pixel Entirely or partly planarize.Planarization layer can be in passivation layer, dielectric layer or insulating barrier At least one.

In an aspect of this embodiment, radiation sensor can include being arranged on Photoelectric Detection The address wire of the lower section of device and data wire, and planarization layer is arranged on address wire and data wire And on the through hole of address wire and data wire.It addition, electric through-hole cross tie part can extend across flat Smoothization layer and the first electrode is connected to image element circuit.The electric through-hole cross tie part contacted with photosensitive layer Surface warp portion can have more than 1/2 micron, micro-more than 1 micron, more than 5 microns, more than 10 Rice and the radius of curvature more than 100 microns.

In an aspect of this embodiment, photosensitive layer can be p-i-n semiconductor stack, n-i-p One in semiconductor stack or metal-insulator semiconductor's storehouse.Image element circuit can include thin film Transistor, diode, capacitor, resistor, trace, through hole, control line, address wire and One in ground plane.Image element circuit can farther include amorphous semiconductor transistor or many One in brilliant semiconductor transistor or crystallite semiconductor transistor.Image element circuit can include addressing At least one in transistor, amplifier transistor and reset transistor.Image element circuit can enter one Step includes by least one element made in non-crystalline silicon, low temperature amorphous silicon and microcrystal silicon.Picture Element circuit can farther include the element be made up of at least one in the following: silicon semiconductor, Chalcogenide semiconductor, cadmium selenide quasiconductor, organic semiconductor, organic molecule or polymer Quasiconductor, CNT or Graphene or other semiconductive materials.

In an aspect of this embodiment, photosensitive layer can be at least one in the following: 1) the sense of continuity photosphere extended across multiple photo-detector pixel, or 2) and the plurality of smooth electric-examination Survey the discrete photosensitive layer that each photo-detector pixel in device pixel is associated.Flash layer can be At least one in the following: CsI:Tl, Gd₂O₂S:Tb、CsI:Na、NaI:Tl、CaWO₄、 ZnWO₄、CdWO₄、Bi₄Ge₃O₁₂、Lu_1.8Yb_0.2SiO₅:Ce、Gd₂SiO₅:Ce、 BaFCl:Eu²⁺、BaSO₄:Eu²⁺、BaFBr:Eu²⁺、LaOBr:Tb³⁺、LaOBr:Tm³⁺、 La₂O₂S:Tb³⁺、Y₂O₂S:Tb³⁺、YTaO₄、YTaO₄: Nb, ZnS:Ag, (Zn, Cd) S:Ag, ZnSiO₄:Mn²⁺、CsI、LiI:Eu²⁺、PbWO₄、Bi₄Si₃O₁₂、Lu₂SiO₅:Ce³⁺、 YAlO₃:Ce³⁺、CsF、CaF₂:Eu²⁺、BaF₂、CeF₃、Y_1.34Gd_0.6O₃:Eu³⁺、Pr、 Gd₂O₂S:Pr³⁺、Ce、SCGl、HFG:Ce³⁺And C (5%)₁₄H₁₀Or other scintillator materials.

In an aspect of this embodiment, radiation sensor can include supporting image element circuit, light Photodetector and the basal substrate of flash layer, and can include being arranged in this substrate base with regular pattern Multiple photo-detector pixel on plate.In an aspect of this embodiment, this light-transmissive Second electrode of son can form the biasing plane for the plurality of photo-detector pixel.Pixel electricity The part on road may be disposed on basal substrate and between adjacent photo detectors pixel between In gap district.This part can include thin film transistor (TFT), diode, capacitor, resistor, through hole, One in trace, control line, address wire and ground plane.An aspect in this embodiment In, the first electrode can have the angled end terminated near this interstitial area.

In an aspect of this embodiment, at the second electrode of the first electrode Yu transmissive photon Between dark current (being normalized to unit photoelectric detector area) be smaller than 10pA/mm², or little In 5pA/mm², or less than 1pA/mm², or less than 0.5pA/mm².The level of dark current exists In a way with the degree of planarization discussed herein above and (one or more) surface warp The radius of curvature coupling in portion.In an aspect of this embodiment, close to surface in photosensitive layer Electric field in the region in warpage portion can more than the first pair of parallel electrode and the second electrode it Between photosensitive layer in electric field 60%, and electric with second less than at the first pair of parallel electrode 300% of the electric field in photosensitive layer between pole.The change of electric field to a certain extent with institute above The degree of the planarization discussed and the radius of curvature coupling in (one or more) surface warp portion.

In an aspect of this embodiment, such as, according to planarization that is desired or that realized Degree, (it is by single ray to the level of the charge-trapping of each photo-detector pixel The amount of the described imaging signal lost due to capture during photograph frame quantifies, and is expressed as The percentage ratio of the imaging signal that charge-trapping obtains under conditions of being in balance with electric charge release) can Less than 20%, it is smaller than 15%, less than 10% or less than 5%.

In an aspect of this embodiment, such as, according to planarization that is desired or that realized Degree, each photo-detector pixel electric charge release (it is by having the situation of radiation After series of frames that is lower and that obtain under conditions of charge-trapping is in balance with electric charge release During the first frame obtained in the case of there is not radiation, from the described one-tenth of trapped state release The amount of image signal quantifies, and is expressed as under conditions of charge-trapping is in balance with release obtaining The percentage ratio of the imaging signal obtained) it is smaller than 15%, less than 10%, less than 5% or less than 3%.

This photoelectric detector has delayed for each photo-detector pixel, and this is delayed is to pass through In the case of there is radiation obtain a frame or series of frames after there is not radiation In the case of obtain the first frame during, from trapped state release imaging signal (this imaging signal refers to Show produced electron hole pair in photosensitive layer, and this imaging signal originates from one or many The electric charge captured in individual previous frame) amount quantify, and be expressed as from previous frame imaging believe Number percentage ratio, described delayed less than about 15%.In an aspect of this embodiment, such as, According to the degree of planarization that is desired or that realized, the delayed of each photo-detector pixel can Less than 10%, less than 5% or less than 3%.

In the 25th diagram embodiment, radiation sensor includes optical conductor detector, and it depends on Secondary second electrode with the first electrode, photoconductive layer and transmissive ionizing radiation.This photoconductive layer quilt It is configured to when interacting produce electron hole pair with ionizing radiation.This radiation sensor includes Image element circuit, it is electrically connected to the first electrode, and is configured to measure instruction at photoconductive layer In the imaging signal of produced electron hole pair, and this image element circuit includes oxide semiconductor. This radiation sensor includes planarization layer, and it is arranged between the first electrode and image element circuit On image element circuit so that the first electrode is including above the plane of image element circuit.Described first The surface of at least one in electrode and described second electrode weighs at least in part with this image element circuit Fold and there is the surface warp portion above the feature of this image element circuit.

Therefore, the 25th embodiment is similar to the tenth embodiment in scope and includes institute above The aspect of the tenth embodiment discussed, then describes the example of preferred compositions.

In an aspect of this embodiment, planarization layer can be passivation layer, dielectric layer or exhausted At least one in edge layer.In an aspect of this embodiment, the first electrode or the second electrode The surface warp portion above image element circuit have more than 1/2 micron, more than 1 micron, big Radius of curvature in 5 microns, more than 10 microns or more than 100 microns.In one aspect of the method, The surface of at least one in described first electrode and described second electrode can with this image element circuit extremely Partially overlapping and can be without showing the surface character of the following image element circuit of instruction.

In an aspect of this embodiment, address wire and data wire are arranged on optical conductor detection The lower section of device, and planarization layer is arranged on address wire and data wire and in address wire sum According on the through hole of line.It addition, electric through-hole cross tie part can extend across planarization layer and by the first electricity Pole is connected to image element circuit.The surface warp portion of the electric through-hole cross tie part contacted with photosensitive layer can have Have more than 1/2 micron, more than 1 micron, more than 5 microns, more than 10 microns with more than 100 microns Radius of curvature.

In an aspect of this embodiment, image element circuit can include thin film transistor (TFT), diode, One in capacitor, resistor, trace, through hole, control line, address wire and ground plane. Image element circuit can farther include amorphous semiconductor transistor or poly semiconductor transistor or micro- One in brilliant semiconductor transistor.Image element circuit can include addressing transistor, amplifier crystal At least one in pipe and reset transistor.Image element circuit can farther include by non-crystalline silicon, low At least one element made in temperature non-crystalline silicon and microcrystal silicon.Image element circuit can farther include The element being made up of at least one in the following: silicon semiconductor, chalcogenide semiconductor, Cadmium selenide quasiconductor, organic semiconductor, organic molecule or polymer semiconductor, CNT Or Graphene or other semiconductive materials.

Therefore, the 25th diagram embodiment in, photoconductive layer with x-ray or other ionization Electron hole pair is produced during radiation interaction.Photoconductive layer can include with in lower semiconductor at least A kind of: VB-VIB, VB-VIIB, IIB-VIB, IIB-VB, IIIB-VB, IIIB-VIB, IB-VIB and IVB-VIIB, and more specifically, it may include at least one in the following: a-Se、PbI₂、HgI₂、PbO、CdZnTe、CdTe、Bi₂S₃、Bi₂Se₃、BiI₃、BiBr₃、 CdS、CdSe、HgS、Cd₂P₃、InAs、InP、In₂S₃、In₂Se₃、Ag₂S、PbI₄ ^-2 And Pb₂I₇ ^-3。

In an aspect of this embodiment, the dark current between the first electrode and the second electrode (being normalized to unit optical conductor detector area) is smaller than 10pA/mm², or less than 5 pA/mm², or less than 1pA/mm², or less than 0.5pA/mm².The level of dark current is at certain With the degree of planarization discussed herein above and (one or more) surface warp portion in the degree of kind Radius of curvature coupling.

In an aspect of this embodiment, such as, according to planarization that is desired or that realized Degree, (it is by penetrating single to the level of the charge-trapping of each optical conductor detector pixel The amount of the described imaging signal lost due to capture during line photograph frame quantifies, and is expressed as The percentage ratio of the imaging signal obtained under conditions of charge-trapping is in balance with electric charge release) It is smaller than 20%, is smaller than 15%, less than 10% or less than 5%.

In an aspect of this embodiment, such as, according to planarization that is desired or that realized Degree, each optical conductor detector pixel electric charge release (it is by having the feelings of radiation After the series of frames obtained under condition and under conditions of charge-trapping is in balance with electric charge release In the case of there is not radiation obtain the first frame during, from trapped state release described in The amount of imaging signal quantifies, and is expressed as under conditions of charge-trapping and release are in balance The percentage ratio of imaging signal obtained) it is smaller than 15%, is smaller than 10%, less than 5% or be less than 3%.

This optical conductor detector has delayed for each optical conductor detector pixel, and this is delayed is By in the case of there is radiation obtain a frame or series of frames after there is not spoke During the first frame obtained in the case of penetrating, from the imaging signal of trapped state release, (this imaging is believed Number instruction produced electron hole pair in photoconductive layer, and this imaging signal originates from one Or the electric charge captured in multiple previous frame) amount quantify, and be expressed as the one-tenth from previous frame The percentage ratio of image signal, described delayed less than about 15%.In an aspect of this embodiment, Such as, according to the degree of planarization that is desired or that realized, each optical conductor detector pixel Delayed be smaller than 10%, less than 5% or less than 3%.

In the 26th diagram embodiment, a kind of method bag for manufacturing radiation sensor Include: forming image element circuit element on basal substrate, wherein this image element circuit includes oxide half Conductor；Planarization layer is formed above described image element circuit element；Planarization layer is formed Hole is to expose the connector to image element circuit element；Make the hole metallization of patterning；Formed and gold First electrode of the hole electrical contact of genusization；Formed light or ionizing radiation quick on the first electrode The layer of sense.This planarization layer is at the table of first electrode the most overlapping with this image element circuit Surface warp portion above the feature of this image element circuit is provided on face.Such as, according to institute's phase The degree of the planarization hoped or realized, this surface warp portion can have more than 1/2 micron, be more than 1 micron, more than 5 microns, more than 10 microns or more than the radius of curvature of 100 microns.

In an aspect of this embodiment, by photosensitive layer and the second electrode shape of transmissive photon Become on the first electrode, and passivation layer is formed on the second electrode of this transmissive photon, and Flash layer is formed on this passivation layer, this flash layer be configured to ionizing radiation phase interaction Used time launches photon.In this example, photosensitive layer planarizes or can form transmission light Photosensitive layer is made to planarize before second electrode of son.

In an aspect of this embodiment, such as, according to planarization that is desired or that realized Degree, can be formed planarization layer to have more than 1/2 micron, more than 1 micron, more than 5 microns, Radius of curvature more than 10 microns or more than 100 microns.Can be by the change to the passivation layer deposited Learn mechanical polishing and form planarization layer.Or, can be by spin coating passivation layer and then blunt to this Change layer and carry out chemically mechanical polishing to form planarization layer.Or, one can be spin-coated on by use Another passivation layer of deposited on top of (or first) passivation layer and then blunt to this another (or second) Change layer and carry out chemically mechanical polishing to form planarization layer.Planarization layer can upper at array features Square, above the electric through-hole cross tie part of the source electrode or drain electrode that are connected to TFT, in single-stage pixel The top of interior amplifier element or in two-stage pixel the putting down at least partially above of amplifier element Smoothization.

In an aspect of this embodiment, the first diagram can be formed on basal substrate and implement For the feature listed by image element circuit element and photosensitive layer in the aspect of example.Such as, formation is worked as During flash layer, at least one in the following can be formed on the second electrode of transmissive photon: CsI:Tl、Gd₂O₂S:Tb、CsI:Na、NaI:Tl、CaWO₄、ZnWO₄、CdWO₄、 Bi₄Ge₃O₁₂、Lu_1.8Yb_0.2SiO₅:Ce、Gd₂SiO₅:Ce、BaFCl:Eu²⁺、BaSO₄:Eu²⁺、 BaFBr:Eu²⁺、LaOBr:Tb³⁺、LaOBr:Tm³⁺、La₂O₂S:Tb³⁺、Y₂O₂S:Tb³⁺、 YTaO₄、YTaO₄: Nb, ZnS:Ag, (Zn, Cd) S:Ag, ZnSiO₄:Mn²⁺、CsI、 LiI:Eu²⁺、PbWO₄、Bi₄Si₃O₁₂、Lu₂SiO₅:Ce³⁺、YAlO₃:Ce³⁺、CsF、 CaF₂:Eu²⁺、BaF₂、CeF₃、Y_1.34Gd_0.6O₃:Eu³⁺、Pr、Gd₂O₂S:Pr³⁺、Ce、 SCGl、HFG:Ce³⁺And C (5%)₁₄H₁₀.Such as, when forming photosensitive layer, formed following At least one in Xiang: 1) the sense of continuity photosphere that extends across multiple photo-detector pixel, or 2) the discrete photosensitive layer being associated with in the plurality of photo-detector pixel.

Additionally, when forming image element circuit element on basal substrate, image element circuit can be further Including in amorphous semiconductor transistor or poly semiconductor transistor or crystallite semiconductor transistor One.Image element circuit can include addressing in transistor, amplifier transistor and reset transistor At least one.Image element circuit can farther include by non-crystalline silicon, low temperature amorphous silicon and microcrystal silicon In at least one element made.Image element circuit can farther include by the following extremely Few a kind of element made: silicon semiconductor, chalcogenide semiconductor, cadmium selenide quasiconductor, have Machine quasiconductor, organic molecule or polymer semiconductor, CNT or Graphene or other half Conductive material.

In view of above-mentioned teaching, numerous modifications and variations of the present invention are possible.Therefore, Ying Li Solve, within the scope of the appended claims, can be differently configured from the side as being specifically described herein The mode of formula implements the present invention.

Fig. 1. Fig. 1 is the schematic three-dimensional figure of a kind of form of a-Si TFT.Watch from inclination angle The top of TFT.Although being illustrated as of TFT is general, but this figure is also depicted in TFT is Address wire required in the case of search switch in AMFPI pixel.Therefore, this figure diagram grid One section (at the point of its grid being connected to TFT) of pole address wire, and data/address line One section (at the point of its drain electrode being connected to TFT).The raceway groove of TFT has the width of 15 μm With the length of 10 μm, as indicated by dotted arrow.End dielectric layer and a-Si layer are illustrated continuously For the most transparent, in order to allow following feature visible.It addition, in order to present For the sake of Qing Chu, relative to being parallel to the direction of substrate, in a direction perpendicular to a substrate figure is put Big 4 times, and only describe the part of substrate thickness.Limited by the solid black lines frame being superimposed on figure The position of the cross-sectional view that plane instruction manifests in fig. 2.Other in this figure have labelling key element to exist The explanation of Fig. 2 is been described by.

Fig. 2. Fig. 2 is the schematic cross section of the a-Si TFT shown in Fig. 1.This cross section Position corresponding to the plane that limited by the wire frame in Fig. 1, and the gray level shade of the element of TFT Agreement (convention) correspond roughly to the agreement used in Fig. 1.Clear in order to present Chu Qijian, relative to being parallel to the direction of substrate, puts figure the most Big 8 times, and only describe the part of substrate thickness.Use labelling indicate substrate, the grid of TFT, End dielectric layer in source electrode and drain electrode, TFT and top dielectric layer, form the raceway groove of TFT A-Si layer and in order to complete the n of the structure of this n-type transistor⁺Type doping a-Si material.

Fig. 3. Fig. 3 is the schematic three-dimensional figure of a kind of form of polycrystalline-Si TFT.See from inclination angle See the top of TFT.Although being illustrated as of TFT is general, but this figure is also depicted in TFT is Address wire required in the case of search switch in AMFPI pixel.Therefore, this figure diagram grid One section (being connected at the point of polycrystalline-Si grid of TFT at it) of pole address wire, and data ground One section (being that through hole is set up to the point of the contact of the drain electrode of TFT) of location line.The ditch of TFT Road has width and the length of 10 μm of 15 μm, as indicated by dotted arrow.Continuously inactivating layer (passivation #1) is illustrated as the most transparent, in order to allow following feature visible.Separately Outward, in order to present clear for the sake of, relative to being parallel to the direction of substrate, be perpendicular to substrate Direction on figure is amplified 4 times, and only describe the part of substrate thickness.By being superimposed on figure The position of the cross-sectional view that the plane instruction that solid black lines frame limits manifests in the diagram.In this figure Other have labelling key element to be been described by the explanation of Fig. 4.

Fig. 4. Fig. 4 is the schematic cross section of the polycrystalline-Si TFT shown in Fig. 3.This is horizontal The position in cross section is corresponding to the plane limited by the wire frame in Fig. 3, and the gray level of the element of TFT The agreement of shade corresponds roughly to the agreement used in Fig. 3.In order to present clear for the sake of, phase For being parallel to the direction of substrate, the most figure is amplified 8 times, and only Describe the part of substrate thickness.Use labelling indicate substrate, buffering passivation, gate-dielectric, The grid (it is formed by polycrystalline-Si in the case) of TFT, in order to form TFT channel (at grid Dielectric lower section) active polymorphic-Si layer and TFT source electrode and drain electrode (by being superimposed on polycrystalline The angled line instruction of the top of the part of-Si layer), and the passivation layer (" passivation above TFT #1”).The position of this cross-sectional view does not illustrate the company between grid address wire and polycrystalline-Si grid Connect.

Fig. 5. Fig. 5 is the schematic circuit of the pixel from active matrix imaging array, and this has Source matrix imaging array uses the indirect detection of incident radiation.Indicated by the region of straight dotted line limit The border of pixel.

Fig. 6. Fig. 6 is a kind of form of the indirect detection pixel with discrete light electric diode Schematic cross section.This represents that an ad hoc structure of the image element circuit in Fig. 5 is implemented and is referred to as Baseline framework.This view is parallel to the direction of grid address wire, and grid address wire is at this cross section In invisible.Distance between vertical dotted line represents the width of a pixel.For clearly mesh , the layer in this diagram and feature not drawn on scale.

Fig. 7. Fig. 7 is the schematic circuit of the pixel from active matrix imaging array, and this has Source matrix imaging array uses the directly detection of incident radiation.The agreement class of labelling, line and symbol It is similar to these agreements used in Fig. 5.The border of pixel is indicated by the region of straight dotted line limit.

Fig. 8. Fig. 8 is the schematic cross section of a kind of form directly detecting pixel.This view Being parallel to the direction of grid address wire, grid address wire is invisible in this cross section.Labelling, The agreement of line, symbol and arrow is similar to these agreements used in Fig. 6.Between vertical dotted line Distance represent the width of a pixel.For purposes of clarity, the layer in this diagram and feature Not drawn on scale.Additionally, not shown TFT and through hole are to the uniformity of the topology of optical conductor Impact.

Fig. 9. Fig. 9 be four neighbors of indirect detection active matrix array schematic in Existing.The design of these pixels represents the enforcement of image element circuit the most illustrated Mode and the embodiment of baseline framework.Each pixel in figure discloses the different journeys of this design The framework details of degree.In the pixel of the bottom of this figure, grid address wire and addressing TFT are only shown Grid.In the pixel of left-hand side, source electrode and the drain electrode of addressing TFT, and quilt are added The n of photodiode⁺The hearth electrode that type doping a-Si layer covers.In right-hand side pixel, it is illustrated that It is referred to as the n of photodiode storehouse⁺Type doping a-Si, free from admixture a-Si, p⁺Type doping a-Si Combination layer with top optical transparency electrode.In this design, hearth electrode extends beyond slightly The edge of storehouse.In the pixel at the top of this figure, add and be connected to addressing by through hole The data/address line of the drain electrode of TFT, and the top electrode of photodiode it is connected to by through hole Offset line.

Figure 10. Figure 10 is the region in single pixel of a pair indirect detection active matrix array In the microphotograph of end face.In either case, this design represents baseline illustrated in Fig. 6 The embodiment of framework.A () is the microphotograph of the pixel from previous array, this previous array There is the design corresponding to the diagram in Fig. 9.B () is the aobvious of the pixel from array design after a while Micro-photo, in this after a while array design, the optimization that designed by pixel and increase optics and fill out Fill the factor.In each microphotograph, addressing TFT is positioned by the circle being superimposed on image In the region of boundary, and also instruction grid address wire, data/address line, offset line and photoelectricity two The position of pole pipe.Note, in each microphotograph, photoelectricity two pole not covered by offset line The end face of the part of pipe seems highly uniform.

Figure 11. Figure 11 is the indirect detection pixel with photoelectric diode structure outside discrete face The schematic figure of the cross-sectional view of design.This view is parallel to the direction of grid address wire, grid Address wire is invisible in this cross section.Labelling in figure, line, arrow, symbols and convention class It is similar to these labellings used in Fig. 6, line, arrow, symbols and convention.Between vertical dotted line Distance represent the width of a pixel.For purposes of clarity, the layer in this diagram and feature Not drawn on scale.Additionally, uniform to the topology of photodiode of not shown TFT and through hole The impact of property.

Figure 12. Figure 12 is the indirect detection pixel with photoelectric diode structure outside continuous print face The schematic figure of the cross-sectional view of design.This view is parallel to the direction of grid address wire, grid Address wire is invisible in this cross section.Labelling in figure, line, arrow, symbols and convention class It is similar to these labellings used in Figure 11, line, arrow, symbols and convention.Vertical dotted line it Between distance represent the width of a pixel.For purposes of clarity, the layer in this diagram and spy Levy not drawn on scale.Additionally, equal to the topology of photodiode of not shown TFT and through hole The impact of even property.

Figure 13. Figure 13 is the schematic of four neighbors of indirect detection active matrix array Present.The design of these pixels represents the reality of image element circuit illustrated in Fig. 5 and Figure 12 respectively Mode executes the embodiment with framework.Each pixel in figure has appeared this design in various degree Framework details.In pixel bottom figure, grid address wire and the grid of addressing TFT are only shown Pole.In left-hand side pixel, add source electrode and drain electrode, the data/address line of addressing TFT, And back contact.In right-hand side pixel, it is illustrated that hearth electrode, it is connected to including by this electrode The through hole of back contact (it resides in the region being indicated boundary by dotted line).Picture at figure top In sketch map, it is shown that the simple expression of photoelectric diode structure, wherein n continuously⁺Type doped layer can not See and the remainder layer of photodiode is not distinguished by.

Figure 14. Figure 14 be indirect detection active matrix array in the region of single pixel The microphotograph of end face.This design represents embodiment and the correspondence of framework illustrated in Figure 12 Presenting in Figure 13.Indicate grid address wire, data/address line, hearth electrode and by this electricity Pole is connected to the position of the through hole of back contact.Noting, in image, visible various details are corresponding Topology in the top of continuous photoelectric diode structure.

Figure 15. Figure 15 is the pixel from the indirect detection array designed based on active pixel Schematic circuit, the design of this active pixel has amplifier in single-stage pixel.Indicate data Address wire, grid address wire, replacement TFT (TFT_RST), source follower TFT (TFT_SF)、 Addressing TFT (TFT_ADDR), and photodiode (PD has electric capacity C_PD)。V_BIASFor applying To the value of reverse bias voltage of the top electrode of photodiode, and V_G-RST、V_D-RSTAnd V_CC For other voltages in order to operate array.Both in TFT, TFT_RSTAnd TFT_ADDRSchemed It is shown as and there is double-grid structure.All TFT are n-type transistor.

Figure 16. Figure 16 is four adjacent pictures of indirect detection array based on active pixel design Schematically presenting of element, the design of this active pixel uses polycrystalline-Si TFT.The design of these pixels Represent the embodiment of image element circuit illustrated in Figure 15.TFT in this figure has and is similar to The structure of the structure of polycrystalline-Si TFT illustrated in Fig. 3 and Fig. 4.Photodiode has similar Continuous structure in the structure shown in Figure 12.Each pixel in figure has appeared this design Framework details in various degree.In pixel bottom figure, it is shown that the grid of each TFT (by Polycrystalline-Si formed), in order to form the active polymorphic-Si of the raceway groove of each TFT, grid address wire, With the reset voltage line in the operation for resetting TFT.In left-hand side pixel, add number According to address wire, back contact, supply voltage line, and various trace and through hole.At right-hand side In pixel, it is illustrated that hearth electrode, including the through hole that this electrode is connected to back contact.At figure In the pixel at top, it is shown that the simple expression of photoelectric diode structure continuously, wherein pattern N⁺Invisible and photodiode the remainder layer of type doped layer is not distinguished by.

Figure 17. Figure 17 is the aobvious of the end face in the region of single pixel of indirect detection array Micro-photo.This design represents the enforcement of image element circuit illustrated in Figure 15 and corresponding in Figure 16 Present.Microphotograph be oriented such that the grid address wire of array and data/address line (its The lower section of the continuous light electric diode of this design) direction vertical respectively along the plane of this image Ground and be flatly directed at.One by thick dashed line (border of one complete pixel of instruction) and thin level The square frame that dotted line (position of the cross-sectional view that instruction manifests in figure after a while) is formed is superimposed on image On.Noting, in image, visible various details are corresponding to the top of continuous photoelectric diode structure Topology.

Figure 18. Figure 18 is the pixel from the indirect detection array designed based on active pixel Schematic circuit, the design of this active pixel has amplifier in two-stage pixel.Indicate data Address wire, grid address wire, replacement TFT (TFT_RST), commonsource amplifier TFT (TFT_CSA)、 Payload TFT (TFT_AL), source follower TFT (TFT_SF), addressing TFT (TFT_ADDR)、 Feedback condenser (has electric capacity C_FB) and photodiode (PD has electric capacity C_PD)。V_BIASFor Apply the value of the reverse bias voltage of the top electrode to photodiode, and V_G-RST、V_G-AL、 V_CCAnd V_GNDFor other voltages in order to operate array.Both in TFT, TFT_RSTWith TFT_ADDRIt is illustrated as that there is double-grid structure.In described TFT, TFT_ALFor p-type crystal Pipe and remaining transistor is n-type.

Figure 19. Figure 19 is four adjacent pictures of indirect detection array based on active pixel design Schematically presenting of element, the design of this active pixel uses polycrystalline-Si TFT.The design of these pixels Represent the embodiment of image element circuit illustrated in Figure 18.TFT in this figure has and is similar to The structure of the structure of polycrystalline-Si TFT illustrated in Fig. 3 and Fig. 4.Photodiode has similar Continuous structure in the structure shown in Figure 12.Each pixel in figure has appeared this design Framework details in various degree.In pixel bottom figure, it is shown that the grid of various TFT (by Polycrystalline-Si formed), in order to form the active polymorphic-Si of the raceway groove of each TFT, with grid address Line.In left-hand side pixel, data/address line, back contact, and various trace are added And through hole.In right-hand side pixel, it is illustrated that hearth electrode, it is connected to rear portion including by this electrode The through hole of contact.In the pixel at figure top, it is shown that photoelectric diode structure is simple continuously Represent, the n wherein patterned⁺Type doped layer is invisible and the remainder layer of photodiode the most in addition Difference.

Figure 20. Figure 20 is the aobvious of the end face in the region of single pixel of indirect detection array Micro-photo.This design represents the embodiment of image element circuit illustrated in Figure 18 and corresponding to figure Presenting in 19.Microphotograph is oriented such that grid address wire and the data/address line of array The direction of (it is in the lower section of the continuous light electric diode of this design) is respectively along the plane of this image Both vertically and horizontally it is directed at.One by the thick dashed line border of one complete pixel (instruction) and thin The square frame that horizontal dotted line (position of the cross-sectional view that instruction manifests in figure after a while) is formed is superimposed on On image.Noting, the most visible various details correspond to continuous photoelectric diode structure The topology at top.

Figure 21. Figure 21 is based on the meter of the indirect detection array of Amplifier Design in single-stage pixel The cross-sectional view calculated, in this single-stage pixel, Amplifier Design uses polycrystalline-Si TFT.Design represents The embodiment of image element circuit illustrated in Figure 15 and corresponding to the diagram in Figure 16 and Figure 17. The position of this cross section corresponding to be perpendicular to array end face, through manifest in fig. 17 thin The plane of horizontal dotted line.Horizontal field of view is corresponding to the distance slightly larger than single pixel and vertically empty Distance between line represents the width of a pixel.This diagram (by deposition, photoetching, etches and uses The computer sim-ulation of other processing procedures in the manufacture of array produces) the various features in array are shown With the order of material, structure and primary topology.In order to present clear for the sake of, relative to parallel In the direction of substrate, the most figure is amplified 8 times, and only describe substrate The part of thickness.

Figure 22. Figure 22 is based on the meter of the indirect detection array of Amplifier Design in two-stage pixel The cross-sectional view calculated, in this two-stage pixel, Amplifier Design uses polycrystalline-Si TFT.This design table The embodiment of image element circuit illustrated in diagram 18 and corresponding to the figure in Figure 19 and Figure 20 Show.The position of two cross sections is corresponding to being perpendicular to the end face of array, through manifesting in fig. 20 The plane of thin horizontal dotted line.A the horizontal field of view in () this diagram is corresponding to slightly larger than single picture The distance of element, and the distance between vertical dotted line represents the width of a pixel.In (b) this diagram Horizontal field of view corresponding to the distance identical with the visual field in Figure 21, and a pixel is only shown Part.These diagrams (by deposition, photoetching, etch and other processing procedures in the manufacture of array Computer sim-ulation produce) the various features in array and the order of material, structure are shown and primary open up Flutter.In order to present clear for the sake of, relative to being parallel to the direction of substrate, be perpendicular to substrate Direction on figure is amplified 8 times, and only describe the part of substrate thickness.

Figure 23. Figure 23 be in single-stage pixel amplifier array in the region of single pixel Top view, it is corresponding to design illustrated in Figure 16.A () is for from order to produce the identical of Figure 21 The diagram that calculating simulation produces.B () is the microphotograph on the surface of the actual realization of array, it is right Should be in the microphotograph in Figure 17.Noting, in each view, visible various details correspond to The primary topology at the top of photoelectric diode structure continuously.

Figure 24. Figure 24 be in two-stage pixel amplifier array in the region of single pixel Top view, it is corresponding to design illustrated in Figure 19.A () is for from order to produce the identical of Figure 22 The diagram that calculating simulation produces.B () is the microphotograph on the surface of the actual realization of array, it is right Should be in the microphotograph in Figure 20.Noting, in each view, visible various details correspond to The primary topology at the top of photoelectric diode structure continuously.

Figure 25. Figure 25 is the figure of the general concept of curvature radius, and radius of curvature can be applicable to The sign of the change of the flatness on surface.The sharpness (that is, sudden) of the change of surface flatness Degree quantified by arc of radius r.Described in (a) more drastically (i.e., more suddenly) change have Short radius of curvature is the most drastically changed than what (b) was described.The ratio of figure makes r₂=10 × r₁。

Figure 26. Figure 26 is based on the meter of the indirect detection array of Amplifier Design in single-stage pixel The cross-sectional view calculated.A () this view corresponds to the cross-sectional view manifested in figure 21, but via right Completely flatization of one (passivation #2) in described passivation layer and realize photoelectric diode structure Topology evenly.B () this view also corresponds to the cross-sectional view manifested in figure 21, but via The part planarization of passivation #2 is realized the topology evenly of photoelectric diode structure.

Figure 27. Figure 27 is based on the meter of the indirect detection array of Amplifier Design in two-stage pixel The cross-sectional view calculated.A the view in () and (b) corresponds respectively in Figure 22 (a) and Figure 22 (b) aobvious Existing cross-sectional view, but via completely flatization to (passivation #2) in described passivation layer And realize the topology evenly of photoelectric diode structure.

Figure 28. Figure 28 is based on the meter of the indirect detection array of Amplifier Design in single-stage pixel The cross-sectional view calculated.This view corresponds to the cross-sectional view manifested in Figure 26 (a), but via right The smoothing of the periphery edge of the hearth electrode (being formed by metal #2 layer) of photodiode and realize light The topology evenly of electric diode structure.

Figure 29. Figure 29 is based on the meter of the indirect detection array of Amplifier Design in two-stage pixel The cross-sectional view calculated.This view corresponds to the cross-sectional view manifested in Figure 27 (a), but via right The smoothing of the periphery edge of the hearth electrode (being formed by metal #2 layer) of photodiode and realize light The topology evenly of electric diode structure.

Figure 30. Figure 30 is based on the meter of the indirect detection array of Amplifier Design in single-stage pixel The cross-sectional view calculated.This view corresponds to the cross-sectional view manifested in Figure 28, but via to even Connect the hearth electrode of photodiode and the through hole of back contact narrow and these are logical with metal filled Hole and realize the even more uniform topology of photoelectric diode structure.

Figure 31. Figure 31 be in single-stage pixel amplifier array in the region of single pixel Top view, it is to produce from calculating simulation.A () is for regarding corresponding to identical shown in Figure 23 (a) The diagram of figure.B () is the diagram corresponding to the diagram in (a), but via in described passivation layer Completely flatization of one (passivation #2) and realize the topology evenly of photoelectric diode structure. C () is the diagram corresponding to the diagram in (b), but via the periphery of the hearth electrode to photodiode The smoothing at edge and realize the topology evenly of photoelectric diode structure.D () is corresponding to (c) In the diagram of diagram, but via to connecting the hearth electrode of photodiode and the logical of back contact The narrowing and realize the most uniform of photoelectric diode structure with these through holes metal filled of hole Topology.

Figure 32. Figure 32 be in two-stage pixel amplifier array in the region of single pixel Top view, it is to produce from calculating simulation.A () is for regarding corresponding to identical shown in Figure 24 (a) The diagram of figure.B () is the diagram corresponding to the diagram in (a), but via in described passivation layer Completely flatization of one (passivation #2) and realize the topology evenly of photoelectric diode structure. C () is the diagram corresponding to the diagram in (b), but via the periphery of the hearth electrode to photodiode The smoothing at edge and realize the topology evenly of photoelectric diode structure.D () is corresponding to (c) In the diagram of diagram, but via to connecting the hearth electrode of photodiode and the logical of back contact The narrowing and realize the most uniform of photoelectric diode structure with these through holes metal filled of hole Topology.

Figure 33. Figure 33 is based on the meter of the indirect detection array of Amplifier Design in single-stage pixel The cross-sectional view calculated.A () this view corresponds to the cross-sectional view manifested in figure 21, but via right Completely flatization of the free from admixture a-Si layer in photodiode and realize photoelectric diode structure The topology evenly of top electrode.B () this view corresponds to the cross-sectional view manifested in figure 21, But realize photoelectricity two pole via the part planarization to the free from admixture a-Si layer in photodiode The topology evenly of the top electrode of tubular construction.

Figure 34. Figure 34 be in single-stage pixel amplifier array in the region of single pixel Top view, it is to produce from calculating simulation.A () is for regarding corresponding to identical shown in Figure 23 (a) The diagram of figure.B () is the diagram corresponding to the diagram in (a), but via in photodiode The part of free from admixture a-Si layer planarizes and realizes the topology evenly of photoelectric diode structure. C () is the diagram corresponding to the diagram in (b), but via to the free from admixture a-Si in photodiode Layer completely flatization and realize the topology evenly of photoelectric diode structure.

Claims

1. a radiation sensor, including:

Flash layer, is configured to when interacting launch photon with ionizing radiation；

Photoelectric detector, includes the first electrode, photosensitive layer successively and neighbouring with flash layer sets Second electrode of the transmissive photon put；

Described photosensitive layer is configured to when the part with described photon interacts produce electricity Sub-hole pair；

Image element circuit, is electrically connected to the first electrode, and is configured to measure instruction photosensitive The imaging signal of produced described electron hole pair in Ceng；

Planarization layer, is arranged on the image element circuit between the first electrode and image element circuit, makes Obtain the first electrode including above the plane of image element circuit；

The surface of at least one in described first electrode and described second electrode and image element circuit Overlapping at least in part, and there is the surface warp portion above the feature of image element circuit； And

Described surface warp portion has the radius of curvature more than 1/2 micron.

2. sensor as claimed in claim 1, wherein said surface warp portion has more than 1 The radius of curvature of micron.

3. sensor as claimed in claim 1, wherein said surface warp portion has more than 5 The radius of curvature of micron.

4. sensor as claimed in claim 1, wherein said surface warp portion has more than 10 The radius of curvature of micron.

5. sensor as claimed in claim 1, wherein said surface warp portion has and is more than The radius of curvature of 100 microns.

6. sensor as claimed in claim 1, wherein said planarization layer is at image element circuit The planarization at least partially above of described feature.

7. sensor as claimed in claim 1, wherein said planarization layer is at array features Top, above the electric through-hole cross tie part of the source electrode or drain electrode that are connected to TFT, at single-stage picture In element amplifier element top or in two-stage pixel, amplifier element is at least partially above Planarization.

8. sensor as claimed in claim 1, wherein said planarization layer include passivation layer, At least one in dielectric layer or insulating barrier.

9. sensor as claimed in claim 1, also includes:

It is arranged on address wire and the data wire of the lower section of photoelectric detector；And

Described planarization layer is arranged on address wire and data wire and address wire and data wire On through hole.

10. sensor as claimed in claim 1, also includes:

Electric through-hole cross tie part, this electric through-hole cross tie part extends through planarization layer, and by first Electrode is connected to described image element circuit, wherein, the table of the electric through-hole cross tie part contacted with photosensitive layer Warpage portion, face has the radius of curvature more than 1/2 micron.

11. sensor as claimed in claim 10, the wherein described surfaces of electric through-hole cross tie part There is the radius of curvature more than 1 micron.

12. sensor as claimed in claim 10, the wherein described surfaces of electric through-hole cross tie part There is the radius of curvature more than 5 microns.

13. sensor as claimed in claim 10, the wherein described surfaces of electric through-hole cross tie part There is the radius of curvature more than 10 microns.

14. sensor as claimed in claim 10, the wherein described surfaces of electric through-hole cross tie part There is the radius of curvature more than 100 microns.

15. sensors as claimed in claim 1, wherein photosensitive layer includes p-i-n semiconductor stack One in stack, n-i-p semiconductor stack or metal-insulator semiconductor's storehouse.

16. sensors as claimed in claim 1, wherein said image element circuit includes film crystal Pipe, diode, capacitor, resistor, trace, through hole, control line, address wire and ground connection One in plane.

17. sensors as claimed in claim 1, wherein said image element circuit includes amorphous state half One in conductor transistor or poly semiconductor transistor or crystallite semiconductor transistor.

18. sensors as claimed in claim 1, wherein said image element circuit includes addressing crystal At least one in pipe, amplifier transistor and reset transistor.

19. sensors as claimed in claim 1, wherein said image element circuit comprise non-crystalline silicon and At least one in microcrystal silicon.

20. sensors as claimed in claim 1, wherein said image element circuit comprises low temperature amorphous Silicon.

21. sensors as claimed in claim 1, wherein said image element circuit comprises silicon partly leads Body, chalcogenide semiconductor, cadmium selenide quasiconductor, organic semiconductor, CNT or graphite At least one in alkene.

22. sensors as claimed in claim 1, wherein said image element circuit comprises organic little point Son or polymer semiconductor.

23. sensors as claimed in claim 1, wherein said photosensitive layer includes in the following At least one: 1) the continuous print photosensitive layer that extends across multiple photo-detector pixel；Or 2) be associated with the corresponding photo-detector pixel in the plurality of photo-detector pixel from The photosensitive layer dissipated.

24. sensors as claimed in claim 1, wherein said flash layer comprises in the following At least one: CsI:Tl, Gd₂O₂S:Tb, CsI:Na, NaI:Tl, CaWO₄、ZnWO₄、 CdWO₄、Bi₄Ge₃O₁₂、Lu_1.8Yb_0.2SiO₅: Ce, Gd₂SiO₅: Ce, BaFCl:Eu²⁺、 BaSO₄: Eu²⁺, BaFBr:Eu²⁺, LaOBr:Tb³⁺, LaOBr:Tm³⁺、La₂O₂S:Tb³⁺、 Y₂O₂S:Tb³⁺、YTaO₄、YTaO₄: Nb, ZnS:Ag, (Zn, Cd) S:Ag, ZnSiO₄: Mn²⁺、 CsI, LiI:Eu²⁺、PbWO₄、Bi₄Si₃O₁₂、Lu₂SiO₅: Ce³⁺、YAlO₃: Ce³⁺、CsF、 CaF₂: Eu²⁺、BaF₂、CeF₃、Y_1.34Gd_0.6O₃: Eu³⁺、Pr、Gd₂O₂S:pr³⁺、Ce、 SCGl, HFG:Ce³⁺And C (5%)₁₄H₁₀。

25. sensors as claimed in claim 1, also include:

Basal substrate, this basal substrate supports image element circuit, photoelectric detector and flash layer；With And

Multiple photo-detector pixel, the plurality of photo-detector pixel is arranged in a regular pattern It is listed on basal substrate, wherein

Second electrode of described transmissive photon is formed for the plurality of photo-detector pixel Biasing plane.

26. sensors as claimed in claim 25, wherein a part for image element circuit is set On the basal substrate in interstitial area between adjacent photo detectors pixel.

27. sensors as claimed in claim 26, are wherein arranged on the pixel in interstitial area A described part for circuit include thin film transistor (TFT), diode, capacitor, resistor, through hole, One in trace, control line, address wire and ground plane.

28. sensors as claimed in claim 26, wherein said first electrode has in gap The angled end terminated near district.

29. sensors as claimed in claim 1, wherein at the first electrode and transmissive photon The dark current being normalized to unit photoelectric detector area between second electrode is less than 10 pA/mm²。

30. sensors as claimed in claim 1, wherein at the first electrode and transmissive photon The dark current being normalized to unit photoelectric detector area between second electrode is less than 5 pA/mm²。

31. sensors as claimed in claim 1, wherein at the first electrode and transmissive photon The dark current being normalized to unit photoelectric detector area between second electrode is less than 1 pA/mm²。

32. sensors as claimed in claim 1, wherein at the first electrode and transmissive photon The dark current being normalized to unit photoelectric detector area between second electrode is less than 0.5 pA/mm²。

33. sensors as claimed in claim 1, wherein in the sense close to described surface warp portion The electric field in region in photosphere is more than between the first pair of parallel electrode and the second electrode 60% of electric field in photosensitive layer, and less than at the first pair of parallel electrode and the second electrode Between photosensitive layer in electric field 300%.

34. sensors as claimed in claim 1, also include metallic plate, and this metallic plate is set In encapsulation on flash layer or on flash layer.