JPH08250698A - Solid-stat image sensor - Google Patents

Solid-stat image sensor

Info

Publication number
JPH08250698A
JPH08250698A JP7054344A JP5434495A JPH08250698A JP H08250698 A JPH08250698 A JP H08250698A JP 7054344 A JP7054344 A JP 7054344A JP 5434495 A JP5434495 A JP 5434495A JP H08250698 A JPH08250698 A JP H08250698A
Authority
JP
Japan
Prior art keywords
pixel electrode
photoelectric conversion
film
electrode
conversion film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7054344A
Other languages
Japanese (ja)
Inventor
Hisanori Ihara
久典 井原
Yoshiki Ishizuka
芳樹 石塚
Hidetoshi Nozaki
秀俊 野崎
Tetsuya Yamaguchi
鉄也 山口
Yoshinori Iida
義典 飯田
Akihiko Furukawa
章彦 古川
Hisashi Sakuma
尚志 佐久間
Hidefumi Oba
英史 大場
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP7054344A priority Critical patent/JPH08250698A/en
Publication of JPH08250698A publication Critical patent/JPH08250698A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To maintain excellent after-image characteristics even if pixel electrodes are microminiaturized by setting the ratio of the peripheral length to the flat surface area of the electrode to a specific value or more and specifying the edge of the electrode opposed to the photoelectric conversion film by the continuously changing surface. CONSTITUTION: A plurality of titanium pixel electrodes 20 are disposed on a second insulating layer 19 covering a signal charge storage region SD. The solid-stage image sensor comprises a photoelectric converting film 22 formed to cover the electrodes 20, and a counter electrode 23 formed on the film 22. The ratio WL,/SA of the peripheral length WL of the electrode 20 to the area SA is 0.67μm<-1> or more, and the edges ED1, ED2 of the electrodes 20 opposed to the film 22 are specified by the continuously changing surface. Thus, the edges ED1, ED2 of the electrode 20 are formed in a specific shape to eliminate the electric field concentration at the edges ED1, ED2, thereby improving the after-image characteristics.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は固体撮像装置に関し、特
に、光電変換膜を信号電荷蓄積領域等の上に積層した2
階建て構造の固体撮像装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device, and more particularly to a solid-state image pickup device in which a photoelectric conversion film is laminated on a signal charge storage region or the like.
The present invention relates to a solid-state imaging device having a floor structure.

【0002】[0002]

【従来の技術】半導体基板の主面に受光蓄積部、信号電
荷読出し部及び、信号電荷転送部を平面上に形成した従
来の一般的な固体撮像装置に代わり、近年、光電変換膜
を信号電荷蓄積領域等の上に積層した2階建て構造の固
体撮像装置が開発されている。この構造の固体撮像装置
は、感光部の開口面積を広くすることができるため、高
感度且つ低スミアという優れた特性を有する。このた
め、この構造の固体撮像装置は、HDTV(High
Definition Television)カメ
ラ、パソコン画像入力用カメラ、民生用ビデオカメラ等
への応用が期待されている。
2. Description of the Related Art In recent years, a photoelectric conversion film has been replaced with a signal charge instead of a general solid-state image pickup device in which a light receiving and accumulating section, a signal charge reading section, and a signal charge transfer section are formed on a plane surface of a semiconductor substrate. A solid-state imaging device having a two-story structure stacked on a storage area or the like has been developed. The solid-state imaging device having this structure has the excellent characteristics of high sensitivity and low smear because the opening area of the photosensitive portion can be increased. Therefore, an HDTV (High
It is expected to be applied to definition televisions, personal computer image input cameras, consumer video cameras, and the like.

【0003】[0003]

【発明が解決しようとする課題】しかし、上記構造の固
体撮像装置においては、画素電極を微細化しようとする
と、残像特性が劣化するという現象が見られる。従っ
て、本発明は、この残像特性の劣化のメカニズムを解析
し、画素電極を微細化しても良好な残像特性を維持する
ことが可能な固体撮像装置を提供することを目的とす
る。
However, in the solid-state image pickup device having the above structure, when the pixel electrode is miniaturized, the afterimage characteristic is deteriorated. Therefore, it is an object of the present invention to analyze the mechanism of deterioration of the afterimage characteristic and to provide a solid-state imaging device capable of maintaining a good afterimage characteristic even if the pixel electrode is miniaturized.

【0004】[0004]

【課題を解決するための手段】本発明の第1の視点に係
る固体撮像装置は、下地層と、前記下地層上に形成され
た複数の画素電極と、前記画素電極を覆うように形成さ
れた光電変換膜と、前記光電変換膜上に形成された対向
電極とを具備し、前記画素電極の周辺長WLと平面積S
Aとの比WL/SAが0.6μm-1以上であり、且つ前
記光電変換膜に面する前記画素電極のエッジが連続的に
変化する面により規定されることを特徴とする。
A solid-state image pickup device according to a first aspect of the present invention is formed so as to cover a base layer, a plurality of pixel electrodes formed on the base layer, and the pixel electrodes. A photoelectric conversion film, and a counter electrode formed on the photoelectric conversion film. The peripheral length WL of the pixel electrode and the plane area S are provided.
The ratio WL / SA to A is 0.6 μm −1 or more, and the edge of the pixel electrode facing the photoelectric conversion film is defined by a continuously changing surface.

【0005】本発明の第2の視点に係る固体撮像装置
は、下地層と、前記下地層上に形成された複数の画素電
極と、前記画素電極を覆うように形成された光電変換膜
と、前記光電変換膜上に形成された対向電極とを具備
し、前記画素電極の周辺長WLと平面積SAとの比WL
/SAが0.6μm-1以上であり、且つ前記光電変換膜
に面する前記画素電極のエッジが曲率半径を有するよう
に形成され、前記曲率半径Rsと前記画素電極の膜厚T
sとの比Rs/Tsが0.25以上であることを特徴と
する。
According to a second aspect of the present invention, there is provided a solid-state image pickup device, a base layer, a plurality of pixel electrodes formed on the base layer, and a photoelectric conversion film formed so as to cover the pixel electrodes. A counter electrode formed on the photoelectric conversion film, and a ratio WL of a peripheral length WL of the pixel electrode to a plane area SA.
/ SA is 0.6 μm −1 or more, and the edge of the pixel electrode facing the photoelectric conversion film is formed to have a radius of curvature, and the radius of curvature Rs and the film thickness T of the pixel electrode.
The ratio Rs / Ts with s is 0.25 or more.

【0006】本発明の第3の視点に係る固体撮像装置
は、下地層と、前記下地層上に形成された複数の画素電
極と、前記画素電極を覆うように形成された光電変換膜
と、前記光電変換膜上に形成された対向電極とを具備
し、前記画素電極の周辺長WLと平面積SAとの比WL
/SAが0.6μm-1以上であり、且つ前記光電変換膜
に面する前記画素電極のエッジの角度が95度以上であ
ることを特徴とする。
According to a third aspect of the present invention, there is provided a solid-state image pickup device, a base layer, a plurality of pixel electrodes formed on the base layer, and a photoelectric conversion film formed so as to cover the pixel electrodes. A counter electrode formed on the photoelectric conversion film, and a ratio WL of a peripheral length WL of the pixel electrode to a plane area SA.
/ SA is 0.6 μm −1 or more, and the angle of the edge of the pixel electrode facing the photoelectric conversion film is 95 ° or more.

【0007】本発明の第4の視点に係る固体撮像装置
は、下地層と、前記下地層上に形成された複数の画素電
極と、前記画素電極を覆うように形成された光電変換膜
と、前記光電変換膜上に形成された対向電極とを具備
し、前記画素電極の周辺長WLと平面積SAとの比WL
/SAが0.6μm-1以上であり、且つ前記画素電極が
実質的に矩形で、その4隅の内の少なくとも1つのエッ
ジが曲率半径を有するように形成され、前記曲率半径R
pと前記画素電極の一辺の長さLpとの比Rp/Lpが
0.125以上であることを特徴とする。
According to a fourth aspect of the present invention, there is provided a solid-state image pickup device, a base layer, a plurality of pixel electrodes formed on the base layer, and a photoelectric conversion film formed so as to cover the pixel electrodes. A counter electrode formed on the photoelectric conversion film, and a ratio WL of a peripheral length WL of the pixel electrode to a plane area SA.
/ SA is 0.6 μm −1 or more, the pixel electrode is substantially rectangular, and at least one of the four corners is formed to have a radius of curvature.
The ratio Rp / Lp of p to the length Lp of one side of the pixel electrode is 0.125 or more.

【0008】本発明の第5の視点に係る固体撮像装置
は、下地層と、前記下地層上に形成された複数の画素電
極と、前記画素電極を覆うように形成された光電変換膜
と、前記光電変換膜上に形成された対向電極とを具備
し、前記画素電極の周辺長WLと平面積SAとの比WL
/SAが0.6μm-1以上であり、且つ前記画素電極間
の距離が1.0μm以下であり、且つ前記光電変換膜の
厚さが1.6μm以下であることを特徴とする。
According to a fifth aspect of the present invention, there is provided a solid-state image pickup device, a base layer, a plurality of pixel electrodes formed on the base layer, and a photoelectric conversion film formed so as to cover the pixel electrodes. A counter electrode formed on the photoelectric conversion film, and a ratio WL of a peripheral length WL of the pixel electrode to a plane area SA.
/ SA is 0.6 μm −1 or more, the distance between the pixel electrodes is 1.0 μm or less, and the thickness of the photoelectric conversion film is 1.6 μm or less.

【0009】本発明の第6の視点に係る固体撮像装置
は、下地層と、前記下地層上に形成された複数の画素電
極と、前記画素電極を覆うように形成された光電変換膜
と、前記光電変換膜上に形成された対向電極とを具備
し、前記画素電極の周辺長WLと平面積SAとの比WL
/SAが0.6μm-1以上であり、且つ前記画素電極間
で前記下地膜に溝が形成され、前記溝の深さDsと前記
画素電極厚さTsとの比Ds/Tsが0.2以上1.0
以下であることを特徴とする。
According to a sixth aspect of the present invention, there is provided a solid-state image pickup device, a base layer, a plurality of pixel electrodes formed on the base layer, and a photoelectric conversion film formed so as to cover the pixel electrodes. A counter electrode formed on the photoelectric conversion film, and a ratio WL of a peripheral length WL of the pixel electrode to a plane area SA.
/ SA is 0.6 μm −1 or more, a groove is formed in the base film between the pixel electrodes, and a ratio Ds / Ts of the depth Ds of the groove and the pixel electrode thickness Ts is 0.2. 1.0 or more
It is characterized by the following.

【0010】[0010]

【作用】本発明の第1乃至第3視点に係る固体撮像装置
によれば、画素電極の縦断側面図に現れる上側エッジに
おける電界集中が解消され、これにより、残像特性を向
上させることが可能となる。ここで、縦断側面図に現れ
る上側エッジとは画素電極の端部で光電変換膜に面して
形成されるエッジや、画素電極の段部及び凹部で光電変
換膜に面して形成されるエッジを意味する。
According to the solid-state image pickup device according to the first to third aspects of the present invention, the electric field concentration at the upper edge appearing in the vertical sectional side view of the pixel electrode is eliminated, whereby the afterimage characteristic can be improved. Become. Here, the upper edge appearing in the vertical side view is an edge formed facing the photoelectric conversion film at the end portion of the pixel electrode or an edge formed facing the photoelectric conversion film at the stepped portion and the concave portion of the pixel electrode. Means

【0011】本発明の第4視点に係る固体撮像装置によ
れば、画素電極の平面図に現れる4隅の内の少なくとも
1つのエッジにおける電界集中が解消され、これによ
り、残像特性を向上させることが可能となる。
According to the solid-state imaging device of the fourth aspect of the present invention, electric field concentration at at least one of the four corners appearing in the plan view of the pixel electrode is eliminated, thereby improving afterimage characteristics. Is possible.

【0012】本発明の第5視点に係る固体撮像装置によ
れば、光電変換膜内、特に画素電極端部に対応する位置
での電界強度を低下させることにより、残像特性を向上
させることが可能となる。
According to the solid-state image pickup device of the fifth aspect of the present invention, it is possible to improve the afterimage characteristic by lowering the electric field intensity in the photoelectric conversion film, particularly in the position corresponding to the end portion of the pixel electrode. Becomes

【0013】本発明の第6視点に係る固体撮像装置によ
れば、画素電極の端部の下側エッジにおける電界集中
と、画素電極の端部の下側エッジと光電変換膜中の欠陥
線との相対位置とのトレードオフの関係を最適に調整す
ることができ、残像特性を向上させることが可能とな
る。
According to the solid-state imaging device of the sixth aspect of the present invention, the electric field concentration at the lower edge of the end of the pixel electrode, the lower edge of the end of the pixel electrode, and the defect line in the photoelectric conversion film are caused. It is possible to optimally adjust the trade-off relationship with the relative position of, and it is possible to improve the afterimage characteristic.

【0014】[0014]

【実施例】以下、本発明を図示の実施例を参照して詳述
する。
The present invention will be described in detail below with reference to the illustrated embodiments.

【0015】図1は本発明の第1実施例に係る固体撮像
装置を示す概略断面図である。図中11は半導体基板で
あるp型シリコン基板を示す。p型シリコン基板11の
上部には、p+ 型の素子分離層12、信号電荷蓄積領域
である蓄積ダイオードSDを構成するためのn- 型の拡
散層13、信号電荷転送領域である垂直CCDチャネル
TCを構成するためのn- 型の拡散層14が形成され
る。蓄積ダイオードと垂直CCDチャネルとの間、即ち
拡散層13、14間が信号電荷読みだし領域ROに相当
する。また、垂直CCDチャネルTC及び信号電荷読み
だし領域ROには、p型シリコン基板11上に第1絶縁
層15を介して転送電極16及び17が形成される。転
送電極16、17により、光電変換膜で発生した電荷を
蓄積した信号電荷蓄積領域SDから電荷を信号電荷転送
領域TCに転送する。
FIG. 1 is a schematic sectional view showing a solid-state image pickup device according to the first embodiment of the present invention. In the figure, 11 indicates a p-type silicon substrate which is a semiconductor substrate. Above the p-type silicon substrate 11, a p + type element isolation layer 12, an n- type diffusion layer 13 for forming a storage diode SD which is a signal charge storage region, and a vertical CCD channel which is a signal charge transfer region. An n-type diffusion layer 14 for forming TC is formed. The area between the storage diode and the vertical CCD channel, that is, the area between the diffusion layers 13 and 14 corresponds to the signal charge reading region RO. Transfer electrodes 16 and 17 are formed on the p-type silicon substrate 11 via the first insulating layer 15 in the vertical CCD channel TC and the signal charge reading region RO. The transfer electrodes 16 and 17 transfer the charges from the signal charge storage region SD in which the charges generated in the photoelectric conversion film are stored to the signal charge transfer region TC.

【0016】第1絶縁層15は垂直CCDチャネルT
C、信号電荷読みだし領域RO、及び蓄積ダイオードS
Dの一部までを覆うように形成される。第1絶縁層15
に沿って引き出し電極18が形成される。引き出し電極
18上には、第2絶縁層19が形成される。更に、引き
出し電極18及び第2絶縁層19上には、厚さ1nm〜
1000nmの画素電極20が形成され、引き出し電極
18と画素電極20は電気的に接続する。
The first insulating layer 15 is a vertical CCD channel T.
C, signal charge reading region RO, and storage diode S
It is formed so as to cover a part of D. First insulating layer 15
The extraction electrode 18 is formed along the line. A second insulating layer 19 is formed on the lead electrode 18. Further, the lead electrode 18 and the second insulating layer 19 have a thickness of 1 nm to
The pixel electrode 20 of 1000 nm is formed, and the extraction electrode 18 and the pixel electrode 20 are electrically connected.

【0017】図1においては、隣の画素の転送電極16
b、引き出し電極18b、画素電極20bも示されてい
る。
In FIG. 1, the transfer electrode 16 of the adjacent pixel is
b, the extraction electrode 18b, and the pixel electrode 20b are also shown.

【0018】画素電極20上には、光電変換膜22が形
成される。更に、光電変換膜22上には、例えばITO
からなる透明な対向電極23が形成される。なお、光電
変換膜22は、画素電極20側から順に、厚さ1nm〜
100nmのi型の水素化a−SiC層24、厚さ50
0nm〜5000nmのi型の水素化a−Si層25、
厚さ1nm〜100nmのp型の水素化a−SiC層2
6が積層されることにより構成される。i型の水素化a
−SiC層25は、高周波グロー放電分解法や、水銀増
感光CVD法等により形成することができる。
A photoelectric conversion film 22 is formed on the pixel electrode 20. Furthermore, for example, ITO is formed on the photoelectric conversion film 22.
A transparent counter electrode 23 is formed. The photoelectric conversion film 22 has a thickness of 1 nm to 1 nm in order from the pixel electrode 20 side.
100 nm i-type hydrogenated a-SiC layer 24, thickness 50
0 nm to 5000 nm i-type hydrogenated a-Si layer 25,
P-type hydrogenated a-SiC layer 2 having a thickness of 1 nm to 100 nm
It is configured by laminating 6 layers. i-type hydrogenation a
The -SiC layer 25 can be formed by a high frequency glow discharge decomposition method, a mercury-sensitized photo-assisted CVD method, or the like.

【0019】第1実施例に係る固体撮像装置は、画素電
極20のエッジにおける電界集中を解消し、残像特性を
向上させたことを特徴とする。ここで画素電極20のエ
ッジとは、電極20の縦断側面図に現れる上側エッジだ
けでなく、電極20の平面図に現れるエッジを意味す
る。縦断側面図に現れる上側エッジとしては、光電変換
膜22に面する側、即ち上側で、画素電極20の端部に
形成されるエッジED1や、電極20の段部及び凹部に
形成されるエッジED2を挙げることができる。図1に
おけるエッジED2は、画素電極20が引き出し電極1
8とコンタクトするために発生した凹部を囲むように形
成される。平面図に現れるエッジとしては、主に画素電
極20が矩形の場合にその4隅、即ち外輪郭上に形成さ
れるエッジを挙げることができる。
The solid-state image pickup device according to the first embodiment is characterized in that the electric field concentration at the edge of the pixel electrode 20 is eliminated and the afterimage characteristic is improved. Here, the edge of the pixel electrode 20 means not only the upper edge that appears in the vertical side view of the electrode 20 but also the edge that appears in the plan view of the electrode 20. The upper edge appearing in the vertical side view is the edge ED1 formed at the end of the pixel electrode 20 on the side facing the photoelectric conversion film 22, that is, the edge ED2 formed at the stepped portion and the concave portion of the electrode 20 on the upper side. Can be mentioned. In the edge ED2 in FIG. 1, the pixel electrode 20 is the extraction electrode 1
It is formed so as to surround the concave portion generated for contacting with 8. As the edges appearing in the plan view, mainly when the pixel electrode 20 is rectangular, the four corners, that is, the edges formed on the outer contour can be mentioned.

【0020】次に、残像量に対する画素電極20のエッ
ジの影響について説明する。
Next, the influence of the edge of the pixel electrode 20 on the amount of afterimage will be described.

【0021】図3のグラフは画素電極形状が異なる2つ
のサンプルA及びサンプルBにおける残像特性を調べた
結果を示す。ここで、サンプルAは図2(a)に示すよ
うに画素電極が単一の電極20からなる。サンプルBは
図2(b)に示すように画素電極が複数の電極20m、
20nからなり、上側エッジEDは概ね90度をなす。
図3から、サンプルBはサンプルAよりも、固体撮像装
置における重要な特性である残像量が大きいことが分か
る。
The graph of FIG. 3 shows the results of examining the afterimage characteristics of two samples A and B having different pixel electrode shapes. Here, in the sample A, as shown in FIG. 2A, the pixel electrode is composed of a single electrode 20. Sample B has a plurality of pixel electrodes 20m, as shown in FIG.
The upper edge ED is approximately 90 degrees.
It can be seen from FIG. 3 that Sample B has a larger afterimage amount, which is an important characteristic in the solid-state imaging device, than Sample A.

【0022】図4(a)、(b)のグラフは、夫々サン
プルA、サンプルBにおける光電変換膜中の電界強度分
布をシミュレーションした計算結果を示す。図4
(a)、(b)を比較すると分かるように、サンプルB
の画素電極の端部の上側エッジにおける電界強度は、サ
ンプルAの画素電極における電界強度の約2倍と見積も
られる。この結果は、サンプルAにおいて−14Vで発
生する残像量の増加が、サンプルBでは−7Vで発生す
ることと見事に一致する。
The graphs of FIGS. 4 (a) and 4 (b) show the calculation results obtained by simulating the electric field intensity distributions in the photoelectric conversion films of Sample A and Sample B, respectively. FIG.
As can be seen by comparing (a) and (b), sample B
The electric field strength at the upper edge of the end portion of the pixel electrode is estimated to be about twice the electric field strength at the pixel electrode of sample A. This result is in excellent agreement with the increase in the afterimage amount that occurs at -14V in sample A and at -7V in sample B.

【0023】図5のグラフは、サンプルA及びサンプル
Bの残像電流の経時変化を調べた結果を示す。図5か
ら、サンプルBはサンプルAよりも、残像電流の減少の
仕方が非常に遅いことことが分かる。図6のグラフは、
サンプルAのみを使用し、電界の強度を変えて残像電流
の経時変化を調べた結果を示す。図6中、特性線F1は
画素電極と透明な対向電極との間に1Vを印加した場合
を示し、特性線F2は画素電極と透明な対向電極との間
に20Vを印加した場合を示す。電界が強い場合は、サ
ンプルBにおいて観測された(図5参照)ように、残像
電流の減少の仕方が非常に遅くなる。このようなことか
ら、サンプルBにおける残像量の増加の原因は画素電極
の端部のエッジEDにおける電界集中にあると考えられ
る。
The graph of FIG. 5 shows the results of examining changes in afterimage currents of Sample A and Sample B with time. It can be seen from FIG. 5 that Sample B is much slower in reducing the afterimage current than Sample A. The graph in Figure 6 is
The results of investigating the change with time of the afterimage current by changing the strength of the electric field using only the sample A are shown. In FIG. 6, a characteristic line F1 shows the case where 1V is applied between the pixel electrode and the transparent counter electrode, and a characteristic line F2 shows the case where 20V is applied between the pixel electrode and the transparent counter electrode. When the electric field is strong, as observed in the sample B (see FIG. 5), the afterimage current decreases very slowly. From this, it is considered that the cause of the increase in the afterimage amount in the sample B is the electric field concentration at the edge ED at the end of the pixel electrode.

【0024】画素電極の端部における電界の集中は、積
層型の固体撮像装置において重要な問題である。画素電
極の端部における電界集中の影響が及ぶ領域の、画素電
極全体に対する割合は、1画素の面積が小さくなればな
るほど大きくなる。このため、画素電極の端部における
電界集中による残像量の増加効果は、1画素の面積が小
さくなればなるほど顕著になる。
The concentration of the electric field at the edge of the pixel electrode is an important problem in the stacked type solid-state image pickup device. The ratio of the area affected by the electric field concentration at the end of the pixel electrode to the entire pixel electrode increases as the area of one pixel decreases. Therefore, the effect of increasing the amount of afterimage due to the electric field concentration at the end of the pixel electrode becomes more remarkable as the area of one pixel becomes smaller.

【0025】図7のグラフは、画素電極の周辺長/平面
積と残像量との関係を調べた結果を示す。ここで、画素
電極としては同図に挿入画として示したように、一辺の
長さがLの正方形をなす電極を用いた。図7中、特性線
F4は、縦断側面図に現れる画素電極の端部の上側エッ
ジ及び平面図に現れる画素電極の4隅のエッジの角度が
共に概ね90度の場合の特性を示す。人が残像を感じな
い限界の基準として、3フィールド後の残像量を0.4
%以下とすると、特性線F4では、これを実現するため
に、画素電極周辺長WL=4Lと画素電極平面積SA=
2 との比WL/SAを0.6μm-1以下にする必要が
ある。即ち、このような特性の固体撮像装置では、残像
特性の劣化を考慮すると、画素の微細化が困難であり、
このことが画素密度を高める上で大きな阻害要因となっ
ている。
The graph of FIG. 7 shows the results of examining the relationship between the peripheral length / planar area of the pixel electrode and the amount of afterimage. Here, as the pixel electrode, as shown in the figure as an inset image, an electrode having a square shape with one side length L was used. In FIG. 7, the characteristic line F4 shows the characteristic when the angles of the upper edge of the end of the pixel electrode appearing in the vertical side view and the edges of the four corners of the pixel electrode appearing in the plan view are both approximately 90 degrees. The amount of afterimage after three fields is set to 0.4 as a criterion for the limit that people do not feel afterimage.
% Or less, in order to realize this, in the characteristic line F4, the pixel electrode peripheral length WL = 4L and the pixel electrode flat area SA =
The ratio WL / SA with L 2 needs to be 0.6 μm −1 or less. That is, in the solid-state imaging device having such characteristics, it is difficult to miniaturize the pixels in consideration of the deterioration of the afterimage characteristics,
This is a major impediment to increasing the pixel density.

【0026】また、図1図示のような光電変換膜22を
信号電荷蓄積領域SD等の上に積層した2階建て構造の
固体撮像装置では、画素電極20と信号電荷蓄積領域S
Dの引き出し電極18とを接続するため、画素コンタク
ト部が存在する。このため、画素電極20には、前述の
ように、段部や凹部が発生し、ここでも上側エッジ(図
1のエッジED2)が形成される。このようなエッジで
も、電極端部の上側エッジと同様に、電界の集中が発生
し、残像量を増加させる。
Further, in the solid-state image pickup device having a two-story structure in which the photoelectric conversion film 22 as shown in FIG. 1 is laminated on the signal charge storage region SD and the like, the pixel electrode 20 and the signal charge storage region S are formed.
Since it is connected to the D lead-out electrode 18, there is a pixel contact portion. Therefore, the step portion or the concave portion is generated in the pixel electrode 20 as described above, and the upper edge (edge ED2 in FIG. 1) is also formed here. Even at such an edge, the electric field is concentrated as in the case of the upper edge of the electrode end portion, and the amount of afterimage is increased.

【0027】また、同様に、図7の挿入画に示すような
矩形の平面形状を有する画素電極では、平面図に現れる
電極の4隅がエッジとなる。このようなエッジでも、縦
断側面図に現れるエッジと同様に、電界の集中が発生
し、残像量を増加させる。また、この場合、画素電極の
4隅における電界集中の影響が及ぶ領域の、画素電極全
体に対する割合は、1画素の面積が小さくなればなるほ
ど大きくなる。このため、画素電極の4隅における電界
集中による残像量の増加効果は、1画素の面積が小さく
なればなるほど顕著になる。
Similarly, in a pixel electrode having a rectangular plane shape as shown in the inset image of FIG. 7, four corners of the electrode appearing in the plan view are edges. Even with such an edge, the electric field is concentrated and the amount of afterimage is increased similarly to the edge appearing in the vertical side view. Further, in this case, the ratio of the area affected by the electric field concentration at the four corners of the pixel electrode to the entire pixel electrode increases as the area of one pixel decreases. Therefore, the effect of increasing the amount of afterimage due to the electric field concentration at the four corners of the pixel electrode becomes more remarkable as the area of one pixel becomes smaller.

【0028】次に、第1実施例に係る画素電極20のエ
ッジの形状と、その条件について説明する。
Next, the shape of the edge of the pixel electrode 20 according to the first embodiment and its condition will be described.

【0029】図8(a)は画素電極20の端部の上側エ
ッジEDsの縦断面形状を示す。ここでエッジEDs
は、残像を抑制するため、曲率半径Rsを有するように
形成される。図8(b)のグラフは、曲率半径Rsと画
素電極20の膜厚Tsとの比Rs/Tsと、残像量との
関係を調べた結果を示す。図8(b)から、比Rs/T
sを0.25以上とすれば、3フィールド後の残像量を
0.4%以下(人が残像を感じない限界の基準)にでき
ることが分かる。
FIG. 8A shows the vertical cross-sectional shape of the upper edge EDs at the end of the pixel electrode 20. Edge EDs here
Is formed to have a radius of curvature Rs in order to suppress an afterimage. The graph of FIG. 8B shows the results of examining the relationship between the ratio Rs / Ts of the radius of curvature Rs and the film thickness Ts of the pixel electrode 20 and the amount of afterimage. From FIG. 8 (b), the ratio Rs / T
It can be seen that if s is set to 0.25 or more, the afterimage amount after three fields can be 0.4% or less (a standard of the limit at which a person does not feel an afterimage).

【0030】図9(a)は画素電極20の端部の上側エ
ッジEDsの縦断面形状の変更例を示す。ここでエッジ
EDsは、残像を抑制するため、2つのエッジEDs
1、EDs2に分割され、各エッジの角度θ1、θ2、
即ちエッジを挟む2辺のなす内角は鈍角をなすように形
成される。図9(b)のグラフは、エッジの角度θと残
像量との関係を調べた結果を示す。図9(b)から、エ
ッジの角度θを95度以上にすれば、3フィールド後の
残像量を0.4%以下にできることが分かる。
FIG. 9A shows a modification of the vertical cross-sectional shape of the upper edge EDs at the end of the pixel electrode 20. Here, since the edge EDs suppresses the afterimage, the two edges EDs are
1, EDs2, and the angles θ1, θ2 of each edge,
That is, the inside angle formed by the two sides sandwiching the edge is formed to be an obtuse angle. The graph of FIG. 9B shows the result of examining the relationship between the edge angle θ and the amount of afterimage. From FIG. 9B, it can be seen that if the edge angle θ is 95 degrees or more, the afterimage amount after three fields can be 0.4% or less.

【0031】図10(a)は実質的に矩形の画素電極2
0の4隅にあるエッジEDpの平面形状を示す。ここで
エッジEDpは、残像を抑制するため、曲率半径Rpを
有するように形成される。図10(b)のグラフは、曲
率半径Rpと画素電極20の一辺の長さLpとの比Rp
/Lpと、残像量との関係を調べた結果を示す。図10
(b)から、比Rp/Lpを0.125以上とすれば、
3フィールド後の残像量を0.4%以下にできることが
分かる。
FIG. 10A shows a pixel electrode 2 having a substantially rectangular shape.
The planar shape of the edge EDp at the four corners of 0 is shown. Here, the edge EDp is formed to have a radius of curvature Rp in order to suppress an afterimage. The graph of FIG. 10B shows the ratio Rp of the radius of curvature Rp and the length Lp of one side of the pixel electrode 20.
The result of having investigated the relationship between / Lp and the amount of afterimage is shown. Figure 10
From (b), if the ratio Rp / Lp is 0.125 or more,
It can be seen that the afterimage amount after three fields can be reduced to 0.4% or less.

【0032】図11(a)〜(d)は、図8(a)或い
は図9(a)に示すような画素電極20の端部の上側エ
ッジEDsを形成するためのエッチング工程を順に示
す。ここで、画素電極20はチタン膜30から形成さ
れ、第2絶縁層19はシリコン酸化膜31から形成され
る。
FIGS. 11A to 11D sequentially show an etching process for forming the upper edge EDs at the end of the pixel electrode 20 as shown in FIG. 8A or 9A. Here, the pixel electrode 20 is formed of a titanium film 30, and the second insulating layer 19 is formed of a silicon oxide film 31.

【0033】まず、図11(a)に示すように、シリコ
ン酸化膜31上にスパッタ法や蒸着法等を用いてチタン
膜30を形成する。チタン膜30の膜厚は1nmから1
000nmとする。この際、曲率半径Rsを得たいチタ
ン膜30の上部33においては、成膜条件を変え、下部
32よりもチタンの密度の粗な組成とする。
First, as shown in FIG. 11A, a titanium film 30 is formed on the silicon oxide film 31 by a sputtering method or a vapor deposition method. The thickness of the titanium film 30 is 1 nm to 1
000 nm. At this time, in the upper portion 33 of the titanium film 30 for which the radius of curvature Rs is desired, the film forming conditions are changed so that the density of titanium is lower than that of the lower portion 32.

【0034】次に、チタン膜30上にレジスト膜34を
塗布形成し、露光工程を経て、図11(b)に示すよう
に、レジスト膜34に所定のパターンを形成する。次
に、RIE装置において、BC13 とCl2 の混合ガス
を用い、図11(c)に示すように、チタン膜30をエ
ッチングする。
Next, a resist film 34 is formed by coating on the titanium film 30, and an exposure process is performed to form a predetermined pattern on the resist film 34 as shown in FIG. 11B. Next, in the RIE apparatus, the titanium film 30 is etched using a mixed gas of BC1 3 and Cl 2 as shown in FIG. 11C.

【0035】チタン膜30は上部33と下部32とでチ
タンの密度が変わっているため、上部33の方が早くエ
ッチングされる。このため、チタン膜30の上側エッジ
は曲線状或いはテーパ状となり、図8(a)或いは図9
(a)に示すような上側エッジを形成することができ
る。エッチング後、図11(d)に示すように、剥離液
を用いてレジスト膜34を取り除く。
Since the titanium film 30 has different titanium densities between the upper portion 33 and the lower portion 32, the upper portion 33 is etched earlier. Therefore, the upper edge of the titanium film 30 has a curved shape or a tapered shape, and the upper edge of FIG.
An upper edge as shown in (a) can be formed. After the etching, as shown in FIG. 11D, the resist film 34 is removed using a stripping solution.

【0036】このようにして形成した画素電極20の画
素電極の周辺長/平面積と残像量との関係を調べた結果
を、図7のグラフ中に特性線F3で示す。ここで、縦断
側面図に現れる画素電極20の端部の上側エッジは曲率
半径を有し、曲率半径Rsと画素電極20の膜厚Tsと
の比Rs/Tsは概ね0.5であった。画素電極20の
平面形状は、図7に挿入画として示したように、一辺の
長さがLの実質的に正方形であり、また、平面図に現れ
る画素電極の4隅のエッジの曲率半径は概ね零で、その
角度は概ね90度であった。
The characteristic line F3 in the graph of FIG. 7 shows the result of examining the relationship between the peripheral length / planar area of the pixel electrode of the pixel electrode 20 thus formed and the amount of afterimage. Here, the upper edge of the end portion of the pixel electrode 20 that appears in the vertical side view has a radius of curvature, and the ratio Rs / Ts between the radius of curvature Rs and the film thickness Ts of the pixel electrode 20 was approximately 0.5. The plane shape of the pixel electrode 20 is a substantially square shape with one side length L as shown in the inset image in FIG. 7, and the curvature radii of the four corner edges of the pixel electrode appearing in the plan view are The angle was approximately zero and the angle was approximately 90 degrees.

【0037】図7の特性線F3に示すように、本発明に
係る画素電極20においては、画素電極周辺長WL=4
Lと画素電極平面積SA=L2 との比WL/SAが0.
6μm-1以上であっても、3フィールド後の残像量を
0.4%以下(人が残像を感じない限界の基準)にでき
た。ちなみに、L=1(μm)、4L/L2 =4.0
(μm-1)において、本発明に係るサンプルは残像量
0.3%を達成した。
As shown by the characteristic line F3 in FIG. 7, in the pixel electrode 20 according to the present invention, the pixel electrode peripheral length WL = 4.
The ratio WL / SA between L and the pixel electrode plane area SA = L 2 is 0.
Even after 6 μm −1 or more, the amount of afterimage after 3 fields could be 0.4% or less (the standard of the limit that humans do not feel afterimage). By the way, L = 1 (μm), 4L / L 2 = 4.0
At (μm −1 ), the sample according to the present invention achieved an afterimage amount of 0.3%.

【0038】なお、図11(a)〜(d)では実質的に
2層構造のチタン膜30を用いた形成方法について説明
したが、チタン膜30が3層構造以上の場合について
も、同形成方法は応用できる。例えば、チタン膜30が
3層構造とすると、図12に示すような、多角形状に傾
斜する上側エッジを有する画素電極も形成することがで
きる。これにより、図7に示した特性は更に改善され、
低残像が実現される。
Although the formation method using the titanium film 30 having a substantially two-layer structure has been described with reference to FIGS. 11A to 11D, the same formation is performed even when the titanium film 30 has a three-layer structure or more. The method is applicable. For example, when the titanium film 30 has a three-layer structure, a pixel electrode having an upper edge inclined in a polygonal shape as shown in FIG. 12 can also be formed. As a result, the characteristics shown in FIG. 7 are further improved,
Low afterimage is realized.

【0039】また、図8(a)或いは図9(a)に示す
ような画素電極20のエッジEDsを形成するため、図
13に示すように、ポジ型のレジストを用いた方法を採
用することもできる。
In order to form the edge EDs of the pixel electrode 20 as shown in FIG. 8A or FIG. 9A, a method using a positive type resist is adopted as shown in FIG. You can also

【0040】ポジ型のレジストは、チタンの密着性が弱
いため、レジストが除去された開口部付近でレジスト膜
34とチタン膜30との間にわずかな隙間を持たせるこ
とができる。このため、RIE装置BにおいてCl3
Cl2 の混合ガスを用いてチタン膜をエッチングする
と、レジスト膜34とチタン膜30との間の上記隙間を
介してチタン膜20の上部がエッチングされる。このた
め、曲線状或いはテーパ状の上側エッジを端部に有する
画素電極が得られる。
Since the positive type resist has weak adhesion to titanium, a slight gap can be provided between the resist film 34 and the titanium film 30 in the vicinity of the opening where the resist is removed. Therefore, when the titanium film is etched in the RIE apparatus B using a mixed gas of Cl 3 and Cl 2 , the upper portion of the titanium film 20 is etched through the gap between the resist film 34 and the titanium film 30. Therefore, a pixel electrode having a curved or tapered upper edge at its end is obtained.

【0041】また、図14(a)〜(d)に示すよう
に、不純物がドープされていないシリコン酸化膜(Si
2 )膜35を下地層として用いても、図8(a)或い
は図9(a)に示すような画素電極20のエッジEDs
を形成することができる。
Further, as shown in FIGS. 14A to 14D, a silicon oxide film (Si
Even if the O 2 ) film 35 is used as a base layer, the edge EDs of the pixel electrode 20 as shown in FIG. 8A or 9A is obtained.
Can be formed.

【0042】まず、図14(a)に示すように、SiO
2 膜35上にスパッタ法や蒸着法等を用いてチタン膜3
0を形成する。チタン膜30の膜厚は1nmから100
0nmとする。次に、チタン膜30上にレジスト膜34
を塗布形成し、露光工程を経て、図14(b)に示すよ
うに、レジスト膜34に所定のパターンを形成する。次
に、RIE装置において、BC13 とCl2 の混合ガス
を用い、図14(c)に示すように、チタン膜30をエ
ッチングする。
First, as shown in FIG. 14A, SiO
2 The titanium film 3 is formed on the film 35 by using a sputtering method or a vapor deposition method.
Form 0. The thickness of the titanium film 30 is 1 nm to 100
It is set to 0 nm. Next, a resist film 34 is formed on the titanium film 30.
Is formed by coating, and an exposure process is performed to form a predetermined pattern on the resist film 34 as shown in FIG. Next, in the RIE apparatus, the titanium film 30 is etched using a mixed gas of BC1 3 and Cl 2 as shown in FIG.

【0043】ドープされていないSiO2 膜35はチタ
ン膜30のエッチングガスであるBC13 とCl2 の混
合ガスに対して耐性が高い。このため、チタン膜30の
エッチングが進行してSiO2 膜35の表面が露出する
と、レジスト膜34の下でチタン膜30にアンダーカッ
トが発生する。このため、曲線状或いはテーパ状のエッ
ジを端部に有する画素電極が得られる。エッチング後、
図14(d)に示すように、剥離液を用いてレジスト膜
34を取り除く。
The undoped SiO 2 film 35 has a high resistance to a mixed gas of BC1 3 and Cl 2 which is an etching gas for the titanium film 30. Therefore, when the etching of the titanium film 30 progresses and the surface of the SiO 2 film 35 is exposed, an undercut occurs in the titanium film 30 under the resist film 34. Therefore, a pixel electrode having a curved or tapered edge at its end can be obtained. After etching,
As shown in FIG. 14D, the resist film 34 is removed using a stripping solution.

【0044】また、レジスト膜をオーバーエッチングす
ることにより、チタン電極の上端部にテーパ状のエッジ
を形成することもできる。また、単純な方法としてCD
Eやアッシャー等の等方性エッチングを行うことのでき
る装置を用いてもよい。この場合、等方性エッチングに
より、レジスト膜の下でチタン膜にアンダーカットが生
じ、チタン電極の上端部にテーパ状のエッジを形成する
ことができる。
By over-etching the resist film, a tapered edge can be formed on the upper end of the titanium electrode. Also, as a simple method, CD
An apparatus capable of performing isotropic etching such as E or Asher may be used. In this case, the isotropic etching causes an undercut in the titanium film under the resist film, and a tapered edge can be formed at the upper end of the titanium electrode.

【0045】図10(a)に示すような、画素電極20
の4隅に丸いエッジEDpを形成するためには、ポジ型
のレジストを用いて、画素電極パターンを形成する。こ
の際、露光時間をオーバー露光条件に設定することによ
り、画素電極形状を区画するレジスト膜のパターン自体
の4隅に曲率半径を持たせることができる。従って、こ
の様なレジスト膜パターンをマスクとしてチタン膜をエ
ッチングすれば、4隅に充分な曲率半径を有する画素電
極を得ることができる。
The pixel electrode 20 as shown in FIG.
In order to form the rounded edges EDp at the four corners, a positive electrode resist is used to form the pixel electrode pattern. At this time, by setting the exposure time to the over-exposure condition, it is possible to give the four corners of the resist film pattern itself that defines the pixel electrode shape a radius of curvature. Therefore, if the titanium film is etched using such a resist film pattern as a mask, pixel electrodes having sufficient radii of curvature at the four corners can be obtained.

【0046】上述の如く、第1実施例に係る固体撮像装
置によれば、画素電極20のエッジを特定の形状に加工
して同エッジにおける電界集中を解消することにより、
残像特性を向上させることが可能となる。
As described above, according to the solid-state image pickup device of the first embodiment, the edge of the pixel electrode 20 is processed into a specific shape to eliminate the electric field concentration at the edge.
It is possible to improve the afterimage characteristic.

【0047】次に、本発明の第2実施例に係る固体撮像
装置について説明する。第2実施例に係る固体撮像装置
の側面図の概要は、図1図示の第2実施例に係る固体撮
像装置と概ね同じであるため、図1を援用することによ
り、図示を省略する。第2実施例は、光電変換膜22の
厚さと画素電極20間の間隔との関係を特定することに
より、残像特性を向上させたことを特徴とする。
Next, a solid-state image pickup device according to the second embodiment of the present invention will be described. The outline of the side view of the solid-state imaging device according to the second embodiment is substantially the same as that of the solid-state imaging device according to the second embodiment shown in FIG. 1, and therefore the illustration is omitted by incorporating FIG. The second embodiment is characterized in that the afterimage characteristic is improved by specifying the relationship between the thickness of the photoelectric conversion film 22 and the distance between the pixel electrodes 20.

【0048】前述の如く、光電変換膜22はa−Si
C、a−Si等の非晶質材料で構成される。非晶質材料
内にはシリコンの結合が切れた多くの欠陥が存在し、こ
れらの結合欠陥は電子や正孔に対してトラップとして働
く。このため、光電変換により発生した電子及び正孔が
画素電極20に到達するまでにこの欠陥に一旦捕捉さ
れ、後から遅れてゆっくりと出てくるという現象が生
じ、これが残像を発生させる原因となる。
As described above, the photoelectric conversion film 22 is made of a-Si.
It is composed of an amorphous material such as C or a-Si. There are many defects in which the bonds of silicon are broken in the amorphous material, and these bond defects act as traps for electrons and holes. Therefore, there occurs a phenomenon in which electrons and holes generated by photoelectric conversion are temporarily captured by this defect before reaching the pixel electrode 20 and slowly come out later with a delay, which causes a residual image. .

【0049】現在の固体撮像装置における光電変換膜の
厚みは2μm程度であるが、トータルの欠陥量を減らし
て残像量を減らすため、光電変換膜の膜厚を減少させた
いという要望がある。しかし、膜厚を減少させると膜に
掛かる電界が強くなり、このため残像量が増加するとい
う問題が発生する。これは、光電変換膜が持つ特有の電
界に対する残像特性であり、画素電極側から正孔の注入
が発生することに伴う現像である。
The thickness of the photoelectric conversion film in the current solid-state image pickup device is about 2 μm, but there is a demand to reduce the film thickness of the photoelectric conversion film in order to reduce the total defect amount and the afterimage amount. However, when the film thickness is reduced, the electric field applied to the film becomes stronger, which causes a problem that the amount of afterimage increases. This is an afterimage characteristic to the electric field peculiar to the photoelectric conversion film, and is development accompanied by the injection of holes from the pixel electrode side.

【0050】図4(b)のグラフに示すように、光電変
換膜22中、電界強度が最も強くなるのは、画素電極の
端部のエッジに対応する部分である。図15のグラフ
は、隣接する2つの画素電極20の間の間隔をパラメー
タとした場合の、光電変換膜22の厚さと電界強度との
関係を調べた結果を示す。図15中、特性線F5、F
6、F7、F8は、画素電極間の間隔を夫々1.2μ
m、1.0μm、0.6μm、0.3μmとした時の特
性を示す。
As shown in the graph of FIG. 4B, the electric field strength in the photoelectric conversion film 22 is the strongest in the portion corresponding to the edge of the end portion of the pixel electrode. The graph of FIG. 15 shows the results of examining the relationship between the thickness of the photoelectric conversion film 22 and the electric field strength when the distance between two adjacent pixel electrodes 20 is used as a parameter. In FIG. 15, characteristic lines F5 and F
6, F7 and F8 have a distance between the pixel electrodes of 1.2 μm, respectively.
The characteristics when m, 1.0 μm, 0.6 μm, and 0.3 μm are shown.

【0051】図15から、電界強度を減少させるには、
画素電極間の間隔を小さくすればよいことが分かる。ま
た、電界強度を減少させるには、光電変換膜22の膜厚
の減少に合わせて画素電極間の間隔を短く設定すればよ
いことも分かる。固体撮像装置が良好な残像特性を示す
ためには、光電変換膜22内の電界強度は7×104
/cm以下とすることが望ましい。即ち、光電変換膜2
2の膜厚が1.6μmの場合は、画素電極間の間隔は
1.0μm以下にすればよいし、光電変換膜22の膜厚
が0.6μmの場合は、画素電極間の間隔は0.3μm
以下にすればよい。
From FIG. 15, to reduce the electric field strength,
It can be seen that it is sufficient to reduce the distance between the pixel electrodes. It is also understood that in order to reduce the electric field strength, the interval between the pixel electrodes may be set shorter in accordance with the decrease in the film thickness of the photoelectric conversion film 22. In order for the solid-state imaging device to exhibit good afterimage characteristics, the electric field strength in the photoelectric conversion film 22 is 7 × 10 4 V.
/ Cm or less is desirable. That is, the photoelectric conversion film 2
When the film thickness of 2 is 1.6 μm, the distance between the pixel electrodes may be 1.0 μm or less. When the film thickness of the photoelectric conversion film 22 is 0.6 μm, the distance between the pixel electrodes is 0. 0.3 μm
You can do the following:

【0052】上述の如く、第2実施例に係る固体撮像装
置によれば、光電変換膜22の厚さと画素電極20間の
間隔との関係を特定して光電変換膜22中の電界強度を
低下させることにより、残像特性を向上させることが可
能となる。また、画素電極間の間隔にマージンを持たせ
る為に、画素電極端部の上側エッジの曲率半径を、第1
実施例で述べたような範囲のものとすることにより、残
像特性を更に向上させることが可能となる。
As described above, according to the solid-state image pickup device of the second embodiment, the electric field strength in the photoelectric conversion film 22 is lowered by specifying the relationship between the thickness of the photoelectric conversion film 22 and the interval between the pixel electrodes 20. By doing so, it is possible to improve the afterimage characteristics. In addition, the radius of curvature of the upper edge of the end portion of the pixel electrode is set to
By setting the range as described in the embodiment, it is possible to further improve the afterimage characteristic.

【0053】次に、本発明の第3実施例に係る固体撮像
装置について説明する。図16は本発明の第3実施例に
係る固体撮像装置を示す概略断面図である。図16中、
図1図示の第1実施例の部分と対応する部分には同一符
号を付して説明を省略する。第3実施例は、画素電極2
0の厚さと画素電極20間で第2絶縁層19に形成され
る溝の深さとの関係を特定することにより、残像特性を
向上させたことを特徴とする。
Next, a solid-state image pickup device according to the third embodiment of the present invention will be described. FIG. 16 is a schematic sectional view showing a solid-state imaging device according to the third embodiment of the present invention. In FIG.
Portions corresponding to those of the first embodiment shown in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. In the third embodiment, the pixel electrode 2
The afterimage characteristic is improved by specifying the relationship between the thickness of 0 and the depth of the groove formed in the second insulating layer 19 between the pixel electrodes 20.

【0054】前述の如く、画素電極を形成するため、R
IE装置においてBCl3 とCl2の混合ガスによりチ
タン膜がエッチングされる。この際、下地層である第2
絶縁層19がエッチングされ、溝が形成される。図17
(a)には、電極20間で第2絶縁層19に形成された
溝27が拡大して示される。このような溝27は、電極
端部の下側エッジにおける電界強度を強めることが明ら
かになっている。
As described above, in order to form the pixel electrode, R
The titanium film is etched by the mixed gas of BCl 3 and Cl 2 in the IE apparatus. At this time, the second underlayer
The insulating layer 19 is etched to form a groove. FIG. 17
In (a), the groove 27 formed in the second insulating layer 19 between the electrodes 20 is enlarged and shown. It has been clarified that such a groove 27 enhances the electric field strength at the lower edge of the electrode end portion.

【0055】図18のグラフは、溝27の深さDsと画
素電極20の厚みTsとの比Ds/Tsと、画素電極2
0の端部の下側エッジにおける電界強度との関係を調べ
た結果を示す。図18から、比Ds/Tsが大きくなる
ほど電界強度が大きくなることが分かる。この電界強度
の増加は、溝27の有無により、誘電率が異なる光電変
換膜22と絶縁層19との位置関係が相違することに起
因して発生すると考えられる。溝27の形成に伴う画素
電極20の端部の下側エッジにおける電界強度の増加
は、画素電極20側からの正孔電流が増え、固体撮像装
置の残像量を大きくすることから非常に問題となる。
In the graph of FIG. 18, the ratio Ds / Ts between the depth Ds of the groove 27 and the thickness Ts of the pixel electrode 20 and the pixel electrode 2 are shown.
The result of having investigated the relationship with the electric field intensity in the lower edge of the end part of 0 is shown. It can be seen from FIG. 18 that the electric field strength increases as the ratio Ds / Ts increases. It is considered that this increase in the electric field intensity is caused by the difference in the positional relationship between the photoelectric conversion film 22 and the insulating layer 19 having different dielectric constants depending on the presence or absence of the groove 27. The increase in the electric field intensity at the lower edge of the end portion of the pixel electrode 20 due to the formation of the groove 27 is very problematic because the hole current from the pixel electrode 20 side increases and the afterimage amount of the solid-state imaging device increases. Become.

【0056】画素電極の端部における電界集中の影響が
及ぶ領域の、画素電極全体に対する割合は、1画素の面
積が小さくなればなるほど大きくなる。このため、画素
電極の端部の下側エッジにおける電界集中による残像量
の増加効果は、1画素の面積が小さくなればなるほど顕
著になる。これは、画素の微細化を困難にし、画素密度
を高める上で大きな阻害要因となっている。
The ratio of the area affected by the electric field concentration at the end of the pixel electrode to the entire pixel electrode increases as the area of one pixel decreases. Therefore, the effect of increasing the amount of afterimage due to the electric field concentration at the lower edge of the end portion of the pixel electrode becomes more remarkable as the area of one pixel becomes smaller. This makes it difficult to miniaturize pixels and is a major obstacle to increasing pixel density.

【0057】溝27の深さが大きくなるほど画素電極2
0の端部の下側エッジにおける電界が強くなってしまう
ので、溝27の深さは大き過ぎない方がよい。しかし、
図17(b)に示すような理由から、溝27が全くない
のも望ましくない。溝27が全くない場合、電極20の
端部の下側エッジ下端から、光電変換膜22中へ欠陥線
28が発生する。欠陥線28が丁度最も電界集中の強い
ところに発生すると、画素電極20から注入される電流
が大きくなり、残像量を増加させる。
As the depth of the groove 27 increases, the pixel electrode 2
Since the electric field at the lower edge of the end portion of 0 becomes strong, the depth of the groove 27 should not be too large. But,
For the reason as shown in FIG. 17B, it is not desirable that the groove 27 is not provided at all. If there is no groove 27, a defect line 28 is generated in the photoelectric conversion film 22 from the lower edge lower end of the end portion of the electrode 20. If the defect line 28 occurs just at the place where the electric field concentration is the strongest, the current injected from the pixel electrode 20 increases and the amount of afterimage increases.

【0058】これに対して、図17(a)に示すよう
に、溝27を形成すると、欠陥線28の始点が画素電極
20の端部の下側エッジから外れるようになる。溝27
の深さが大きいほど、画素電極20の端部の下側エッジ
と欠陥線28との距離は大きくなるが、反面、上述のよ
うに溝27の深さが大きくなると電界が強くなる。つま
り、この両者はトレードオフの関係にある。
On the other hand, as shown in FIG. 17A, when the groove 27 is formed, the starting point of the defect line 28 comes off the lower edge of the end portion of the pixel electrode 20. Groove 27
As the depth of the groove 27 increases, the distance between the lower edge of the end of the pixel electrode 20 and the defect line 28 increases, but on the other hand, as the depth of the groove 27 increases, the electric field increases. In other words, the two are in a trade-off relationship.

【0059】図19のグラフは、溝27の深さDsと画
素電極20の厚みTsとの比Ds/Tsと、残像量との
関係を調べた結果を示す。図19から、比Ds/Tsが
0.2以上1.0以下に最適範囲が存在することが分か
る。
The graph of FIG. 19 shows the result of examining the relationship between the ratio Ds / Ts of the depth Ds of the groove 27 and the thickness Ts of the pixel electrode 20 and the amount of afterimage. It can be seen from FIG. 19 that the optimum range exists when the ratio Ds / Ts is 0.2 or more and 1.0 or less.

【0060】図20(a)〜(d)は、図17(a)に
示すような溝27を画素電極20と共に形成するための
エッチング工程を順に示す。ここで、画素電極20はチ
タン膜30から形成され、第2絶縁層19は平坦性を良
くするためにBPSG、PPSG、BSG等の不純物が
ドープされたシリコン酸化膜36から形成される。
20A to 20D sequentially show an etching process for forming the groove 27 as shown in FIG. 17A together with the pixel electrode 20. Here, the pixel electrode 20 is formed of a titanium film 30, and the second insulating layer 19 is formed of a silicon oxide film 36 doped with impurities such as BPSG, PPSG, and BSG in order to improve flatness.

【0061】まず、図20(a)に示すように、ドープ
ドシリコン酸化膜36上にスパッタ法や蒸着法等を用い
てチタン膜30を形成する。チタン膜30の膜厚は1n
mから1000nmとする。次に、チタン膜30上にレ
ジスト膜34を塗布形成し、露光工程を経て、図20
(b)に示すように、レジスト膜34に所定のパターン
を形成する。次に、RIE装置において、BC13 とC
2 の混合ガスを用い、図20(c)に示すように、チ
タン膜30をエッチングする。
First, as shown in FIG. 20A, a titanium film 30 is formed on the doped silicon oxide film 36 by a sputtering method, a vapor deposition method or the like. The thickness of the titanium film 30 is 1n
m to 1000 nm. Next, a resist film 34 is formed on the titanium film 30 by coating, and an exposure process is performed.
As shown in (b), a predetermined pattern is formed on the resist film 34. Next, in the RIE device, BC1 3 and C
As shown in FIG. 20C, the titanium film 30 is etched using a mixed gas of l 2 .

【0062】BPSG、PPSG、BSG等の不純物が
ドープされたシリコン酸化膜36は、不純物がドープさ
れていないSiO2 膜と異なり、チタン膜30のエッチ
ングガスであるBC13 とCl2 の混合ガスによりエッ
チングされる。このため、チタン膜30のエッチングが
進行してシリコン酸化膜36の表面が露出すると、シリ
コン酸化膜36も幾分エッチングされ、溝27が形成さ
れる。この際、溝27の深さを上述の比Ds/Tsが
0.2以上1.0以下となるようにエッチング時間を調
整する。エッチング後、図20(d)に示すように、剥
離液を用いてレジスト膜34を取り除く。
Unlike the SiO 2 film not doped with impurities, the silicon oxide film 36 doped with impurities such as BPSG, PPSG and BSG is formed by a mixed gas of BC 1 3 and Cl 2 which is an etching gas for the titanium film 30. Is etched. Therefore, when the etching of the titanium film 30 progresses and the surface of the silicon oxide film 36 is exposed, the silicon oxide film 36 is also etched to some extent to form the groove 27. At this time, the etching time is adjusted so that the above-mentioned ratio Ds / Ts is 0.2 or more and 1.0 or less. After the etching, as shown in FIG. 20D, the resist film 34 is removed using a stripping solution.

【0063】上述の如く、第3実施例に係る固体撮像装
置によれば、画素電極20の厚さと溝27の深さとの関
係を特定することにより、画素電極20の端部の下側エ
ッジにおける電界集中と、画素電極20の端部の下側エ
ッジと光電変換膜22中の欠陥線28との相対位置との
トレードオフの関係を最適に調整することができ、残像
特性を向上させることが可能となる。
As described above, according to the solid-state imaging device of the third embodiment, by specifying the relationship between the thickness of the pixel electrode 20 and the depth of the groove 27, the lower edge of the end portion of the pixel electrode 20 can be detected. The trade-off relationship between the electric field concentration and the relative position between the lower edge of the end of the pixel electrode 20 and the defect line 28 in the photoelectric conversion film 22 can be optimally adjusted, and the afterimage characteristic can be improved. It will be possible.

【0064】なお、以上の説明において、画素電極の形
成方法としてRIEを用いた例について述べたが、これ
に代えて、エキシマレーザー、CDE、X線等の方法を
用いて微細な画素電極を形成することもできる。また、
理解を容易にするため、第1乃至第3実施例は個別に述
べたが、夫々の特徴は互いに組合わせて複合的に用いる
ことができ、これにより、より好ましい残像特性を得る
ことが可能となる。
In the above description, an example in which RIE is used as the method for forming the pixel electrode has been described, but instead of this, a fine pixel electrode is formed by using a method such as excimer laser, CDE or X-ray. You can also do it. Also,
For ease of understanding, the first to third embodiments have been described individually, but the respective features can be combined with each other to be used in a composite manner, whereby more preferable afterimage characteristics can be obtained. Become.

【0065】[0065]

【発明の効果】以上説明したように、本発明によれば、
画素電極のエッジを特定の形状に加工して同エッジにお
ける電界集中を解消することにより、残像特性を向上さ
せることが可能となる。
As described above, according to the present invention,
By processing the edge of the pixel electrode into a specific shape and eliminating the electric field concentration at the edge, the afterimage characteristic can be improved.

【0066】また、本発明によれば、光電変換膜の厚さ
と画素電極間の間隔との関係を特定して光電変換膜中の
電界強度を低下させることにより、残像特性を向上させ
ることが可能となる。
Further, according to the present invention, the afterimage characteristic can be improved by specifying the relationship between the thickness of the photoelectric conversion film and the distance between the pixel electrodes to reduce the electric field strength in the photoelectric conversion film. Becomes

【0067】また、本発明によれば、画素電極の厚さと
画素電極間の溝の深さとの関係を特定することにより、
画素電極の端部の下側エッジにおける電界集中と、画素
電極の端部の下側エッジと光電変換膜中の欠陥線との相
対位置とのトレードオフの関係を最適に調整することが
でき、残像特性を向上させることが可能となる。
Further, according to the present invention, by specifying the relationship between the thickness of the pixel electrode and the depth of the groove between the pixel electrodes,
It is possible to optimally adjust the trade-off relationship between the electric field concentration at the lower edge of the end of the pixel electrode and the relative position between the lower edge of the end of the pixel electrode and the defect line in the photoelectric conversion film, It is possible to improve the afterimage characteristic.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1実施例に係る固体撮像装置を示す
概略断面図。
FIG. 1 is a schematic cross-sectional view showing a solid-state imaging device according to a first embodiment of the present invention.

【図2】(a)及び(b)は夫々、残像特性を調べるた
めに用いた2種類のサンプルの概要を示す図。
2A and 2B are diagrams respectively showing an outline of two types of samples used for examining an afterimage characteristic.

【図3】図2図示の2種類のサンプルにおける残像特性
を示すグラフ。
FIG. 3 is a graph showing afterimage characteristics in the two types of samples shown in FIG.

【図4】(a)及び(b)は夫々、図2図示の2種類の
サンプルにおける電界強度分布を示すグラフ。
4A and 4B are graphs showing electric field intensity distributions of the two types of samples shown in FIG. 2, respectively.

【図5】図2図示の2種類のサンプルにおける残像電流
の経時変化を示すグラフ。
5 is a graph showing changes in afterimage current with time of the two types of samples shown in FIG.

【図6】図2(a)図示のサンプルにおける異なる電圧
に対する残像電流の経時変化を示すグラフ。
FIG. 6 is a graph showing changes in afterimage current with time for different voltages in the sample shown in FIG.

【図7】画素電極の周辺長4Lと平面積L2 の比4L/
2 と残像量との関係を示すグラフ。
FIG. 7 shows a ratio of the peripheral length of the pixel electrode 4L to the plane area L 2 of 4L /
Graph showing the relationship between L 2 and afterimage amount.

【図8】(a)及び(b)は夫々、画素電極の端部の上
側エッジの形状を示す縦断面図、及びその曲率半径Rs
と画素電極の膜厚Tsとの比Rs/Tsと、残像量との
関係を示すグラフ。
8A and 8B are respectively a vertical sectional view showing the shape of an upper edge of an end portion of a pixel electrode, and its radius of curvature Rs.
3 is a graph showing the relationship between the ratio Rs / Ts of the film thickness of the pixel electrode Ts and the amount of residual image.

【図9】(a)及び(b)は夫々、画素電極の端部の上
側エッジの形状の変更例を示す縦断面図、及びそのエッ
ジの角度θと残像量との関係を示すグラフ。
9A and 9B are respectively a vertical cross-sectional view showing a modified example of the shape of the upper edge of the end portion of the pixel electrode, and a graph showing the relationship between the edge angle θ and the amount of afterimage.

【図10】(a)及び(b)は夫々、実質的に矩形の画
素電極の4隅にあるエッジの形状を示す平面図、及びそ
の曲率半径Rpと画素電極の一辺の長さLpとの比Rp
/Lpと、残像量との関係を示すグラフ。
10A and 10B are plan views showing shapes of edges at four corners of a substantially rectangular pixel electrode, respectively, and a radius of curvature Rp and a length Lp of one side of the pixel electrode. Ratio Rp
The graph which shows the relationship between / Lp and the amount of afterimage.

【図11】(a)〜(d)は、図8(a)或いは図9
(a)に示すような画素電極の端部の上側エッジを形成
するためのエッチング工程を順に示す断面図。
11 (a) to (d) are the same as FIG. 8 (a) or FIG.
7A to 7C are cross-sectional views sequentially showing an etching process for forming the upper edge of the end portion of the pixel electrode as shown in FIG.

【図12】画素電極の端部の上側エッジの別の形成方法
を示す断面図。
FIG. 12 is a cross-sectional view showing another method of forming the upper edge of the end portion of the pixel electrode.

【図13】画素電極の端部の上側エッジの更に別の形成
方法を示す断面図。
FIG. 13 is a sectional view showing still another method of forming the upper edge of the end portion of the pixel electrode.

【図14】(a)〜(d)は、画素電極の端部の上側エ
ッジを更に別の方法で形成するためのエッチング工程を
順に示す断面図。
14A to 14D are cross-sectional views sequentially showing an etching process for forming the upper edge of the end portion of the pixel electrode by still another method.

【図15】画素電極の間の間隔をパラメータとした場合
の、光電変換膜の厚さと電界強度との関係を示すグラ
フ。
FIG. 15 is a graph showing the relationship between the thickness of the photoelectric conversion film and the electric field strength when the distance between pixel electrodes is used as a parameter.

【図16】本発明の第3実施例に係る固体撮像装置を示
す概略断面図。
FIG. 16 is a schematic sectional view showing a solid-state imaging device according to the third embodiment of the present invention.

【図17】(a)及び(b)は夫々、画素電極間で第2
絶縁層に形成された溝を拡大して示す断面図、及び画素
電極間で第2絶縁層に溝が形成されない状態を拡大して
示す断面図。
17 (a) and 17 (b) respectively show a second pixel electrode between pixel electrodes.
FIG. 6 is an enlarged cross-sectional view showing a groove formed in an insulating layer, and an enlarged cross-sectional view showing a state in which no groove is formed in the second insulating layer between pixel electrodes.

【図18】画素電極間の溝の深さDsと画素電極の厚み
Tsとの比Ds/Tsと、画素電極の端部の下側エッジ
における電界強度との関係を示すグラフ。
FIG. 18 is a graph showing the relationship between the ratio Ds / Ts of the depth Ds of the groove between the pixel electrodes and the thickness Ts of the pixel electrode, and the electric field strength at the lower edge of the end portion of the pixel electrode.

【図19】画素電極間の溝の深さDsと画素電極の厚み
Tsとの比Ds/Tsと、残像量との関係を示すグラ
フ。
FIG. 19 is a graph showing the relationship between the ratio Ds / Ts of the depth Ds of the groove between the pixel electrodes and the thickness Ts of the pixel electrode, and the amount of afterimage.

【図20】(a)〜(d)は、図17(a)に示すよう
な画素電極間の溝を画素電極と共に形成するためのエッ
チング工程を順に示す断面図。
20A to 20D are cross-sectional views sequentially showing an etching process for forming a groove between pixel electrodes as shown in FIG. 17A together with the pixel electrodes.

【符号の説明】[Explanation of symbols]

11…シリコン基板、12…素子分離層、13…拡散
層、14…拡散層、15…第1絶縁層、16…転送電
極、17…転送電極、18…引き出し電極、19…第2
絶縁層、20…画素電極、22…光電変換膜、23…対
向電極、24…i型の水素化a−SiC層、25…i型
の水素化a−Si層、26…p型の水素化a−SiC
層、27…溝、28…欠陥線、30…チタン膜、31…
シリコン酸化膜、32…チタン膜下部、33…チタン膜
上部、34…レジスト膜、35…不純物がドープされて
いないSiO2 膜、36…不純物がドープされたシリコ
ン酸化膜、ED…エッジ、RO…信号電荷読みだし領
域、SD…信号電荷蓄積領域、TC…信号電荷転送領
域。
11 ... Silicon substrate, 12 ... Element isolation layer, 13 ... Diffusion layer, 14 ... Diffusion layer, 15 ... First insulating layer, 16 ... Transfer electrode, 17 ... Transfer electrode, 18 ... Extraction electrode, 19 ... Second
Insulating layer, 20 ... Pixel electrode, 22 ... Photoelectric conversion film, 23 ... Counter electrode, 24 ... i-type hydrogenated a-SiC layer, 25 ... i-type hydrogenated a-Si layer, 26 ... p-type hydrogenated a-SiC
Layer, 27 ... Groove, 28 ... Defect line, 30 ... Titanium film, 31 ...
Silicon oxide film, 32 ... Titanium film lower part, 33 ... Titanium film upper part, 34 ... Resist film, 35 ... Impurity-undoped SiO 2 film, 36 ... Impurity-doped silicon oxide film, ED ... Edge, RO ... Signal charge reading area, SD ... Signal charge storage area, TC ... Signal charge transfer area.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 山口 鉄也 神奈川県川崎市幸区小向東芝町1番地 株 式会社東芝研究開発センター内 (72)発明者 飯田 義典 神奈川県川崎市幸区小向東芝町1番地 株 式会社東芝研究開発センター内 (72)発明者 古川 章彦 神奈川県川崎市幸区小向東芝町1番地 株 式会社東芝研究開発センター内 (72)発明者 佐久間 尚志 神奈川県川崎市幸区小向東芝町1番地 株 式会社東芝研究開発センター内 (72)発明者 大場 英史 神奈川県川崎市幸区小向東芝町1番地 株 式会社東芝研究開発センター内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tetsuya Yamaguchi No. 1 Komukai Toshiba Town, Saiwai-ku, Kawasaki City, Kanagawa Prefecture, Corporate Research & Development Center, Toshiba Corporation (72) Yoshinori Iida, Komukai Toshiba, Kawasaki City, Kanagawa Prefecture Town No. 1 Incorporated company Toshiba Research & Development Center (72) Inventor Akihiko Furukawa No. 1 Komukai Toshiba Town, Kouki-ku, Kawasaki City, Kanagawa Prefecture Incorporated company Toshiba Research & Development Center (72) Inventor Naoshi Sakuma Kanzaki Prefecture Kawasaki City Komukai-Toshiba-cho No. 1 Inside the Toshiba Research and Development Center, Ltd. (72) Inventor Hidefumi Oba Komukai-Toshibacho No. 1 inside the Toshiba Research and Development Center, Kawasaki City, Kanagawa Prefecture

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】下地層と、前記下地層上に形成された複数
の画素電極と、前記画素電極を覆うように形成された光
電変換膜と、前記光電変換膜上に形成された対向電極と
を具備し、前記画素電極の周辺長WLと平面積SAとの
比WL/SAが0.6μm-1以上であり、且つ前記光電
変換膜に面する前記画素電極のエッジが連続的に変化す
る面により規定されることを特徴とする固体撮像装置。
1. A base layer, a plurality of pixel electrodes formed on the base layer, a photoelectric conversion film formed so as to cover the pixel electrodes, and a counter electrode formed on the photoelectric conversion film. The ratio WL / SA of the peripheral length WL of the pixel electrode to the plane area SA is 0.6 μm −1 or more, and the edge of the pixel electrode facing the photoelectric conversion film continuously changes. A solid-state imaging device characterized by being defined by a surface.
【請求項2】下地層と、前記下地層上に形成された複数
の画素電極と、前記画素電極を覆うように形成された光
電変換膜と、前記光電変換膜上に形成された対向電極と
を具備し、前記画素電極の周辺長WLと平面積SAとの
比WL/SAが0.6μm-1以上であり、且つ前記光電
変換膜に面する前記画素電極のエッジが曲率半径を有す
るように形成され、前記曲率半径Rsと前記画素電極の
膜厚Tsとの比Rs/Tsが0.25以上であることを
特徴とする固体撮像装置。
2. A base layer, a plurality of pixel electrodes formed on the base layer, a photoelectric conversion film formed so as to cover the pixel electrodes, and a counter electrode formed on the photoelectric conversion film. The ratio WL / SA of the peripheral length WL of the pixel electrode to the plane area SA is 0.6 μm −1 or more, and the edge of the pixel electrode facing the photoelectric conversion film has a radius of curvature. And a ratio Rs / Ts between the radius of curvature Rs and the film thickness Ts of the pixel electrode is 0.25 or more.
【請求項3】下地層と、前記下地層上に形成された複数
の画素電極と、前記画素電極を覆うように形成された光
電変換膜と、前記光電変換膜上に形成された対向電極と
を具備し、前記画素電極の周辺長WLと平面積SAとの
比WL/SAが0.6μm-1以上であり、且つ前記光電
変換膜に面する前記画素電極のエッジの角度が95度以
上であることを特徴とする固体撮像装置。
3. A base layer, a plurality of pixel electrodes formed on the base layer, a photoelectric conversion film formed so as to cover the pixel electrodes, and a counter electrode formed on the photoelectric conversion film. The ratio WL / SA of the peripheral length WL of the pixel electrode to the plane area SA is 0.6 μm −1 or more, and the edge angle of the pixel electrode facing the photoelectric conversion film is 95 ° or more. The solid-state imaging device according to claim 1.
【請求項4】下地層と、前記下地層上に形成された複数
の画素電極と、前記画素電極を覆うように形成された光
電変換膜と、前記光電変換膜上に形成された対向電極と
を具備し、前記画素電極の周辺長WLと平面積SAとの
比WL/SAが0.6μm-1以上であり、且つ前記画素
電極が実質的に矩形で、その4隅の内の少なくとも1つ
のエッジが曲率半径を有するように形成され、前記曲率
半径Rpと前記画素電極の一辺の長さLpとの比Rp/
Lpが0.125以上であることを特徴とする固体撮像
装置。
4. A base layer, a plurality of pixel electrodes formed on the base layer, a photoelectric conversion film formed so as to cover the pixel electrodes, and a counter electrode formed on the photoelectric conversion film. The ratio WL / SA of the peripheral length WL of the pixel electrode to the plane area SA is 0.6 μm −1 or more, and the pixel electrode is substantially rectangular, and at least one of the four corners is One edge is formed to have a radius of curvature, and the ratio Rp / of the radius of curvature Rp and the length Lp of one side of the pixel electrode is Rp /
A solid-state imaging device having Lp of 0.125 or more.
【請求項5】下地層と、前記下地層上に形成された複数
の画素電極と、前記画素電極を覆うように形成された光
電変換膜と、前記光電変換膜上に形成された対向電極と
を具備し、前記画素電極の周辺長WLと平面積SAとの
比WL/SAが0.6μm-1以上であり、且つ前記画素
電極間の距離が1.0μm以下であり、且つ前記光電変
換膜の厚さが1.6μm以下であることを特徴とする固
体撮像装置。
5. A base layer, a plurality of pixel electrodes formed on the base layer, a photoelectric conversion film formed so as to cover the pixel electrodes, and a counter electrode formed on the photoelectric conversion film. The ratio WL / SA of the peripheral length WL of the pixel electrode to the plane area SA is 0.6 μm −1 or more, the distance between the pixel electrodes is 1.0 μm or less, and the photoelectric conversion is performed. A solid-state imaging device having a film thickness of 1.6 μm or less.
【請求項6】下地層と、前記下地層上に形成された複数
の画素電極と、前記画素電極を覆うように形成された光
電変換膜と、前記光電変換膜上に形成された対向電極と
を具備し、前記画素電極の周辺長WLと平面積SAとの
比WL/SAが0.6μm-1以上であり、且つ前記画素
電極間で前記下地膜に溝が形成され、前記溝の深さDs
と前記画素電極厚さTsとの比Ds/Tsが0.2以上
1.0以下であることを特徴とする固体撮像装置。
6. A base layer, a plurality of pixel electrodes formed on the base layer, a photoelectric conversion film formed so as to cover the pixel electrodes, and a counter electrode formed on the photoelectric conversion film. The ratio WL / SA of the peripheral length WL of the pixel electrode to the plane area SA is 0.6 μm −1 or more, and the groove is formed in the base film between the pixel electrodes, and the depth of the groove is increased. Ds
A solid-state imaging device, wherein a ratio Ds / Ts between the pixel electrode thickness Ts and the pixel electrode thickness Ts is 0.2 or more and 1.0 or less.
JP7054344A 1995-03-14 1995-03-14 Solid-stat image sensor Pending JPH08250698A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7054344A JPH08250698A (en) 1995-03-14 1995-03-14 Solid-stat image sensor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7054344A JPH08250698A (en) 1995-03-14 1995-03-14 Solid-stat image sensor

Publications (1)

Publication Number Publication Date
JPH08250698A true JPH08250698A (en) 1996-09-27

Family

ID=12968012

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7054344A Pending JPH08250698A (en) 1995-03-14 1995-03-14 Solid-stat image sensor

Country Status (1)

Country Link
JP (1) JPH08250698A (en)

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