TWI614898B - Termination structure and fabrication method thereof - Google Patents

Abstract

A semiconductor device includes a shielded gate transistor and a first polycrystalline silicon layer. The shielded gate transistor is located in an active region of a substrate, the active region is surrounded by a termination region, and the polycrystalline silicon A layer is located in the shielded gate transistor, and the first polycrystalline silicon layer extends over the termination region and enters the termination region.

Description

Termination zone structure and manufacturing method thereof

The present invention relates to a semiconductor device, and more particularly to a termination region structure of a semiconductor device and a method for manufacturing the same.

The power semiconductor device includes a split gate structure, and further includes a plurality of vertical metal-oxide-semiconductor field-effect transistors. Each of the vertical metal-oxide-semiconductor FETs includes a trench, a drain region located below the trench, and a trench. The shielded two-crystal silicon layer is located in a gate region and a source region of the shielded two-crystal silicon layer. In addition, the vertical metal-oxide-semiconductor field-effect transistors are formed in a cell region to provide a required function, and the cell region is surrounded by a termination region. In addition, the breakdown voltage of the termination region needs to be higher than the breakdown voltage of the unit region. Therefore, in the separation gate structure of some existing semiconductor devices, the source metal layer extending in the termination region is used as a field plate, and its role is to increase the breakdown voltage of the termination region.

An embodiment of the present invention discloses a semiconductor device including a shielded gate transistor and a first polycrystalline silicon layer. The shielded gate transistor is located in an active region of a substrate, and the active region is terminated by a region. Surrounding, the polycrystalline silicon layer is located in the shielded gate transistor, and the first polycrystalline silicon layer extends over the termination region and enters the termination region.

An embodiment of the present invention discloses a method for manufacturing a semiconductor device. The method includes forming a trench in an active region of a substrate and forming a patterned first polycrystalline silicon layer on the substrate. In the trench, the active region is surrounded by a termination region, and the patterned first polycrystalline silicon layer extends over the termination region and enters the termination region.

An embodiment of the present invention discloses a method for manufacturing a semiconductor device. The method includes forming a trench in an active region of a substrate, forming a patterned first polycrystalline silicon layer in the trench, and using the patterning. The first polycrystalline silicon layer is a mask to form a first doped region and a second doped region in the substrate. The active region is surrounded by a termination region.

The technical features of the present invention have been briefly described above, so that the following detailed description of the present invention can be better understood. Other technical features constituting the subject matter of the patent application scope of the present invention will be described below.

Those having ordinary knowledge in the technical field to which the present invention pertains should understand that the concepts and specific embodiments disclosed below can be used as a basis to easily modify or design other structures or processes to achieve the same purpose as the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the present invention as set forth in the appended patent application scope.

10‧‧‧Semiconductor device

10'‧‧‧Semiconductor device

11‧‧‧ substrate

13‧‧‧The first insulation layer

13'‧‧‧ patterned first insulating layer

15‧‧‧ patterned first photoresist layer

17‧‧‧ Trench

18‧‧‧ groove

19‧‧‧Second insulation layer

19'‧‧‧ patterned second insulation layer

20‧‧‧Semiconductor device

31‧‧‧The first polycrystalline silicon layer

31'‧‧‧ patterned first polycrystalline silicon layer

33‧‧‧ patterned second photoresist layer

37‧‧‧Third insulation layer

39‧‧‧Second polycrystalline silicon layer

53‧‧‧first doped region

57‧‧‧second doped region

59‧‧‧Inner dielectric layer

61‧‧‧ third doped region

69‧‧‧metal layer

79‧‧‧ patterned third photoresist layer

81‧‧‧ Termination Area

83‧‧‧shielded gate transistor

1A to 1I are schematic cross-sectional views of a semiconductor device to illustrate a method for manufacturing a semiconductor device according to an embodiment of the present invention; FIG. 1J is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention; A method for manufacturing a semiconductor device according to another embodiment of the invention.

1A to 1I are schematic cross-sectional views of a semiconductor device to illustrate a method for manufacturing a semiconductor device according to an embodiment of the present invention. In some embodiments, the semiconductor device is a power semiconductor device, wherein the semiconductor device includes a shielded gate transistor.

As shown in FIG. 1A, a substrate 11 is provided. The substrate 11 includes an N-type heavily doped layer and an N Type lightly doped epitaxial layer, the N type lightly doped epitaxial layer is located on the N type heavily doped layer. In one embodiment, the substrate 11 includes a P-type heavily doped layer and a P-type lightly doped epitaxial layer. The P-type lightly doped epitaxial layer is located on the P-type heavily doped epitaxial layer. In another embodiment, the substrate 11 includes an N-type lightly doped layer epitaxial layer and an N-type heavily doped layer. The N-type heavily doped layer is located on the N-type lightly doped layer epitaxial layer. . In still another embodiment, the substrate 11 includes a P-type lightly doped epitaxial layer and a P-type heavily doped epitaxial layer. The P-type heavily doped epitaxial layer is located on the P-type lightly doped epitaxial layer.

In an embodiment in which the substrate 11 includes an N-type heavily doped layer and an N-type lightly doped epitaxial layer, and the N-type lightly doped epitaxial layer is located on the N-type heavily doped layer, the N-type heavily doped layer The doping concentration of the doped layer is about 10 ¹⁹ cm ^-3 or higher, and the doping concentration of the N-type lightly doped epitaxial layer is about 10 ¹⁶ cm ^-3 to 10 ¹⁷ cm ^-3 . The N-type lightly doped epitaxial layer is the source of the semiconductor device. The substrate 11 includes a wafer, and the thickness of the wafer is about 725 μm (micrometer).

A first insulating layer 13 is formed on the substrate 11 by a deposition process including a chemical vapor deposition (CVD) process. The material of the first insulating layer 13 includes silicon dioxide (SiO ₂ ). The first insulating layer The thickness of 13 is about 2000Å (Ångström).

A patterned first photo resistor layer 15 is formed on the first insulating layer 13 by a lithographic process to expose a portion of the first insulating layer 13.

As shown in FIG. 1B, a patterned first photoresist layer 15 is used as a photomask in an etching process to remove the exposed portion of the first insulating layer, and a patterned first insulating layer 13 ′ is formed. Then, the patterned first photoresist layer 15 is removed.

Next, the patterned first insulating layer 13 'is used as a photomask in another etching process or an appropriate process to form the trench 17 in the substrate 11. The patterned first insulating layer 13' is then removed. . The trench 17 is located at or near a termination region of the semiconductor device and will be described later. The depth of the trench 17 is about 2 to 5 μm.

As shown in FIG. 1C, a second insulating layer 19 is formed on the surface of the substrate 11 and the trench 17 by a heat treatment process. When the voltage is 30V (Volts), the thickness of the second insulating layer 19 is about 1000Å, and when the voltage is 100V, the thickness of the second insulating layer 19 is about 3000 to 4000Å. The material of the second insulating layer 19 includes silicon dioxide (SiO ₂ ).

Next, a first polycrystalline silicon layer 31 is formed on the second insulating layer 19 by a precipitation process and an in-situ doping process, and the trench 17 is filled with the first polycrystalline silicon layer 31. The thickness of the first polycrystalline silicon layer 31 is about 10,000 to 15,000 Å. The dopant used in the field doping includes phosphorous, and the concentration of the dopant is about 10 ²⁰ to 10 ²¹ cm ^-3 .

A patterned second photoresist layer 33 is formed on the first polycrystalline silicon layer 31 by a lithography process to expose a portion of the first polycrystalline silicon layer 31.

As shown in FIG. 1D, the patterned second photoresist layer 33 is used as a photomask in an etch-back process, so that the patterned first polycrystalline silicon layer 31 ′ is formed. The patterned second photoresist layer 33 is then removed, and the patterned second insulating layer 19 ′ and the recess 18 are formed in the substrate 11 where the trench 17 is located by a wet etching process, and the trench is formed. Part of the patterned first polycrystalline silicon layer 31 'and part of the patterned second insulating layer 19' are exposed.

As shown in FIG. 1E, a third insulating layer 37 is formed on the patterned first polycrystalline silicon layer 31 ′, the patterned second insulating layer 19 ′, and the substrate 11 by a heat treatment process. The material of the third insulating layer 37 includes silicon dioxide, and the thickness of the third insulating layer 37 is about 500 Å.

Next, a second polycrystalline silicon layer 39 is formed on the third insulating layer 37 of the recess 18 by a deposition process and an immediate etching process. The second polycrystalline silicon layer 39 is a gate of the semiconductor structure. The thickness of the second polycrystalline silicon layer 39 is about 10,000 Å.

As shown in FIG. 1F, a first doped region 53 is formed on the substrate 11 by an implantation and drive in process, and a first polycrystalline silicon 31 'is patterned in the implantation process. And the drive-in diffusion process is used as a mask. The dopant used in the implantation process includes a P-type dopant, and the dosage of the P-type dopant is about 10 ¹³ ions / cm ² . The drive-in diffusion process includes heat treatment, and the drive-in diffusion has a depth of about 1 μm. The first doped region 53 is a body region of the semiconductor device.

In addition, a second doped region 57 is formed on the substrate 11 by an implantation process and a drive in process. The first polycrystalline silicon 31 'is used as a mask in the implantation process and the drive-in diffusion process. The dopants used in the implantation process include N-type dopants, and the dosage of the N-type dopants is about 10 ¹⁶ ions / cm ² . The drive-in diffusion process includes heat treatment, and the drive-in diffusion has a depth of about 0.25 to 0.3 μm. The second doped region 57 is a source region of the semiconductor device, and the first doped region 53 is located below the second doped region 57.

As shown in FIG. 1G, an inter layer dielectric layer 59 is formed on the third insulating layer 37 and the second polycrystalline silicon layer 39 by a deposition process, and then a patterned third photoresist layer is formed. 79 is formed on the inner dielectric layer 59 by a lithography process, and a part of the inner dielectric layer 59 is exposed.

As shown in FIG. 1H, the patterned third photoresist layer 79 is used as a photomask in an etching process to etch the exposed portion of the inner dielectric layer 59. When the exposed portion of the inner dielectric layer 59 is etched The third insulating layer 37, the patterned first insulating layer 13 'and the first doped region 53 are also etched at the same time, so that the patterned first polycrystalline silicon 31' and the first doped region 53 are exposed, and the pattern The third photoresist layer 79 is then removed.

Then, a third doped region 61 is formed in the second doped region 57 by an implantation process. In addition, the dopants used in the implantation process include P ⁺ type dopants.

As shown in FIG. 1I, a metal layer 69 is formed on the inner dielectric layer 59 by a deposition process, and a semiconductor device 10 is formed. The metal layer 69 contacts the first doped region 53 through the third doped region 61, the second doped region 57 and the patterned first polycrystalline silicon layer 31 '. The material of the metal layer 69 includes aluminum or copper, and the thickness of the metal layer 69 is about 4 to 6 μm.

The semiconductor device 10 shown in FIG. 1I includes a power semiconductor device, such as a power MOSFET. The semiconductor device 10 includes a shielded gate transistor 83 in an active region. The active region is Surrounded by a termination area 81, the active area is the area where the active device is formed, and the termination area 81 is a device containing non-active devices and used To protect the active area.

As shown in FIG. 1I, the patterned first polycrystalline silicon layer 31 'extends above the termination region 81 and enters the termination region. The extended patterned first polycrystalline silicon layer 31' is used as a field plate. The plate makes the width of the depleteon region of the termination region 81 of the semiconductor device 10 larger to increase the breakdown voltage of the termination region 81 of the semiconductor device 10. In addition, as described above, when forming the first doped region 53 and the second doped region 57, the patterned first polycrystalline silicon layer 31 ′ is used as a mask.

FIG. 1J is a schematic cross-sectional view of a semiconductor device 20 according to an embodiment of the present invention. As shown in FIG. 1J, the semiconductor device 20 is similar to the semiconductor device 10 shown in FIG. 1G, but the semiconductor device 20 further includes at least one trench 85, and at least one trench 85 is filled with the patterned first polycrystalline silicon layer 31 ' And it is placed in the termination region 81 of the semiconductor device 20.

2A to 2G are schematic cross-sectional views of a semiconductor device to illustrate a method for manufacturing a semiconductor device according to another embodiment of the present invention.

As shown in FIG. 2A, the substrate 11, the patterned first insulating layer 13 ', the second insulating layer 19, and the first polycrystalline silicon layer 31 have been described in FIGS. 1A to 1B. Compared with FIGS. 1A to 1B, in this embodiment, as shown in FIG. 2A, after the first polycrystalline silicon layer 31 is formed, the patterned first insulating layer 13 ′ is still retained on the substrate 11.

The patterned second photoresist layer 33 is formed on the first polycrystalline silicon layer 31 by a lithographic process to expose a portion of the first polycrystalline silicon layer 31.

As shown in FIG. 2B, the patterned second photoresist layer 33 is used as a photomask in an etch-back process to form a patterned first polycrystalline silicon layer 31 ′. The patterned second photoresist layer 33 is then removed, and the patterned second insulating layer 19 'and the groove 18 are formed in the substrate 11 where the trench 17 is located through a wet etching process, and a part of the pattern is exposed. The first polycrystalline silicon layer 31 ′ is partially patterned, the first polycrystalline silicon layer 31 ′ is partially patterned, and the second insulating layer 19 ′ is partially patterned.

As shown in FIG. 2C, the third insulating layer 37 is formed on the patterned first polycrystalline silicon layer 31 ′, the patterned second insulating layer 19 ′, and the substrate 11 by a heat treatment process. Third insulating layer The material of 37 includes silicon dioxide, and the thickness of the third insulating layer 37 is about 500Å.

Next, a second polycrystalline silicon layer 39 is formed on the third insulating layer 37 of the recess 18 by a deposition process and an immediate etching process. The second polycrystalline silicon layer 39 is a gate of the semiconductor structure. The thickness of the second polycrystalline silicon layer 39 is about 10,000 Å.

As shown in FIG. 2D, the first doped region 53 is formed on the substrate 11 by an implantation and drive in process, and the first polycrystalline silicon 31 'is patterned in the implantation process and The drive-in diffusion process is used as a photomask. The dopant used in the implantation process includes a P-type dopant, and the dosage of the P-type dopant is about 10 ¹³ ions / cm ² . The drive-in diffusion process includes heat treatment, and the drive-in diffusion has a depth of about 1 μm. The first doped region 53 is a body region of the semiconductor device.

In addition, the second doped region 57 is formed on the substrate 11 by an implantation process and a drive in process. The first polycrystalline silicon 31 'is used as a photomask in the implantation process and the drive-in diffusion process. The dopants used in the implantation process include N-type dopants, and the dosage of the N-type dopants is about 10 ¹⁶ ions / cm ² . The drive-in diffusion process includes heat treatment, and the drive-in diffusion has a depth of about 0.25 to 0.3 μm. The second doped region 57 is a source region of the semiconductor device, and the first doped region 53 is located below the second doped region 57.

As shown in FIG. 2E, the inner dielectric layer 59 is formed on the third insulating layer 37 and the second polycrystalline silicon layer 39 by a deposition process, and then the patterned third photoresist layer 79 is processed by a lithography process. It is formed on the inner dielectric layer 59 and exposes a part of the inner dielectric layer 59.

As shown in FIG. 2F, the patterned third photoresist layer 79 is used as a photomask in an etching process to etch the exposed portion of the inner dielectric layer 59. When the exposed portion of the inner dielectric layer 59 is etched, The third insulating layer 37, the patterned first insulating layer 13 'and the first doped region 53 are also etched at the same time, and the patterned first polycrystalline silicon 31' and the first doped region 53 are exposed and shown in FIG. 2F Etching stops at the dotted line shown.

Next, a third doped region 61 is formed in the second doped region 57 by an implantation process. In addition, the dopants used in the implantation process include P ⁺ type dopants. In addition, the exposed first doped region 53 is then etched until the substrate 11 is exposed, and the patterned third photoresist layer 79 is then removed.

As shown in FIG. 2G, the metal layer 69 is formed on the exposed first polycrystalline silicon layer 31 'and the exposed substrate 11 by a deposition process, and a semiconductor device 10' is formed. The material of the metal layer 69 includes aluminum or copper, and the thickness of the metal layer 69 is about 4 to 6 μm.

The semiconductor device 10 ′ shown in FIG. 2G includes a power semiconductor device, for example, a power MOSFET, and the semiconductor device 10 ′ includes a shielded gate transistor 83 in the active region of the substrate 11. The active area is surrounded by a termination area 81 of the substrate 11.

As shown in FIG. 2G, the patterned first polycrystalline silicon layer 31 'extends on the termination region 81 and enters the termination region. The extended patterned first polycrystalline silicon layer 31' serves as a field plate, and the field plate The width of the depleteon region of the termination region 81 of the semiconductor device 10 'is increased to increase the breakdown voltage of the termination region 81 of the semiconductor device 10'.

The metal layer 69 of the semiconductor device 10 ′ is in contact with the substrate 11, and the substrate 11 includes an N-type substrate. Therefore, a Schottky diode phenomenon occurs in a contact region 88 between the metal layer 69 and the substrate 11. The base-diode phenomenon provides the semiconductor device 10 'with less power consumption in the event of reverse breakdown, and enhances the switching function of the semiconductor device 10'.

The technical content and technical features of the present invention have been disclosed as above. However, those with ordinary knowledge in the technical field to which the present invention belongs should understand that without departing from the spirit and scope of the present invention as defined by the scope of the attached patent application, the teaching and disclosure of the present invention Can be used for various substitutions and modifications. For example, many of the processes disclosed above can be implemented in different ways or replaced with other processes, or a combination of the two methods described above.

In addition, the scope of rights in this case is not limited to the process, machine, manufacture, material composition, device, method or step of the specific embodiments disclosed above. Those with ordinary knowledge in the technical field to which the present invention belongs should understand that based on the teaching and disclosure of the present invention, processes, machines, manufacturing, material ingredients, devices, methods or steps, whether existing or developed in the future Or, it is the same as that disclosed in the embodiment of the present case that performs substantially the same function in substantially the same way, and achieves substantially the same result, which can also be used in the present invention. Therefore, the following patent application scope is intended to cover the components, devices, methods or steps used in such processes, machines, manufactures, substances.

10‧‧‧Semiconductor device

11‧‧‧ substrate

19'‧‧‧ patterned second insulation layer

31'‧‧‧ patterned first polycrystalline silicon layer

37‧‧‧Third insulation layer

39‧‧‧Second polycrystalline silicon layer

53‧‧‧first doped region

57‧‧‧second doped region

59‧‧‧Inner dielectric layer

61‧‧‧ third doped region

69‧‧‧metal layer

81‧‧‧ Termination Area

83‧‧‧shielded gate transistor

Claims (19)

A semiconductor device includes: a shielded gate transistor, which is located in an active region of a substrate, the active region is surrounded by a termination region; and a first polycrystalline silicon layer, which is located in the shielded gate transistor. The first polycrystalline silicon layer extends over the termination region and enters the termination region. The semiconductor device according to item 1 of the patent application scope further includes a second polycrystalline silicon layer, the second polycrystalline silicon layer is located in the shielded gate transistor, and the second polycrystalline silicon layer is the shield The gate of the gate transistor, and the first polycrystalline silicon is a field plate of the semiconductor device. The semiconductor device described in item 1 of the patent application scope further includes a metal layer, and the metal layer is in contact with the substrate. The semiconductor device according to item 3 of the patent application scope, wherein the substrate comprises an N-type substrate. The semiconductor device according to item 1 of the patent application scope further includes at least one trench, and the trench is located in the termination region. The semiconductor device according to item 5 of the application, wherein the at least one trench is filled with the first polycrystalline silicon. According to the semiconductor device described in item 1 of the patent application scope, the termination region further includes an insulating layer on the substrate. A method for manufacturing a semiconductor device includes: forming a trench in an active region of a substrate, the active region being surrounded by a termination region; and forming a patterned first polycrystalline silicon layer in the trench , The patterned first polycrystalline silicon layer Extend over the termination zone and enter the termination zone. According to the method for manufacturing a semiconductor device according to item 8 of the application, the termination region further includes forming a patterned first insulating layer on the substrate. The method for manufacturing a semiconductor device according to item 9 of the scope of patent application, further comprising forming a patterned second insulating layer extending above the first insulating layer, and the second insulating layer extending toward the termination region. The method for manufacturing a semiconductor device according to item 8 of the patent application, further comprising: forming a patterned second polycrystalline silicon layer in the trench; and using the patterned first polycrystalline silicon layer as a mask to A first doped region and a second doped region are formed in the substrate. The method for manufacturing a semiconductor device according to item 11 of the scope of patent application, further comprising forming a metal layer, the metal layer being in contact with the substrate. The method for manufacturing a semiconductor device according to claim 12, wherein the substrate includes an N-type substrate. A method for manufacturing a semiconductor device, the method comprising: forming a trench in an active region of a substrate, the active region being surrounded by a termination region; forming a patterned first polycrystalline silicon layer in the trench; and The patterned first polycrystalline silicon layer is used as a mask to form a first doped region and a second doped region in the substrate. The method for manufacturing a semiconductor device according to item 14 of the scope of patent application, wherein the patterned first polycrystalline silicon layer extends above the termination region. According to the method for manufacturing a semiconductor device according to item 14 of the patent application scope, the termination region further includes forming a patterned first insulating layer on the substrate. The method for manufacturing a semiconductor device according to item 16 of the scope of patent application, further comprising forming a patterned second insulating layer extending above the first insulating layer, and the second insulating layer extending toward the termination region. The method for manufacturing a semiconductor device according to item 14 of the scope of patent application, further comprising forming a patterned second polycrystalline silicon layer in the trench. The method for manufacturing a semiconductor device according to item 14 of the scope of patent application, further comprising forming a metal layer, the metal layer being in contact with the substrate.