TWI611546B - Package substrate - Google Patents

Abstract

A packaging substrate includes an organic material layer, an interlayer structure, a first patterned metal layer, a plurality of conductive pillars, and a plurality of conductive pads. The organic material layer has a bottom surface. The interposer structure is buried in the organic material layer, wherein the interposer structure has a top surface, and the organic material layer exposes the top surface of the interposer structure. The first patterned metal layer is disposed on the top surface. The first patterned metal layer includes a first part and a second part. The first part is used to electrically connect the first chip. The conductive pillar is disposed on the second part, and is used to electrically connect the second chip or the package structure. The conductive pad is arranged on the bottom surface and electrically connected to the interlayer structure.

Description

Package substrate

The invention relates to a packaging substrate.

The interposer structure is an integrated structure of the chip connected between the die and the package, which can reduce the pad pitch on the chip. Specifically, the interposer structure is an electronic wiring interface between the chip and the socket (Socket), the purpose of which is to spread a connection point to a wider pitch or redistribute a connection point to another circuit. The material of the interlayer structure can be silicon, glass or ceramic.

In addition, thin film layers of embedded components can be placed in the interposer structure, such as some passive components, Zener diodes and some transistors such as level shifting or buffering.

In order to further improve the characteristics of the interposer structure, related fields must be developed with great care. How to provide an interposer structure with better characteristics is one of the current important research and development topics, and it has also become an urgent target for improvement in related fields.

One technical aspect of the present invention is to provide a packaging substrate, which uses a specially designed conductive post to implement a stacked packaging technology, thereby improving the device density of semiconductor devices.

According to an embodiment of the invention, a packaging substrate includes an organic material layer, an interposer structure, a first patterned metal layer, a plurality of conductive pillars, and a plurality of conductive pads. The organic material layer has a bottom surface. The interposer structure is buried in the organic material layer, wherein the interposer structure has a top surface, and the organic material layer exposes the top surface of the interposer structure. The first patterned metal layer is disposed on the top surface. The first patterned metal layer includes a first part and a second part. The first part is used to electrically connect the first chip. The conductive pillar is disposed on the second part, and is used to electrically connect the second chip or the package structure. The conductive pad is arranged on the bottom surface and electrically connected to the interlayer structure.

In one or more embodiments of the present invention, the interposer structure includes a substrate, a plurality of connecting pillars, and a redistribution layer. The redistribution layer is disposed on the substrate, wherein the top surface of the redistribution layer is the top surface of the interposer structure. The communication post is disposed in the substrate and electrically connects the redistribution layer and the conductive pad.

In one or more embodiments of the present invention, the organic material layer further has an opening, and the opening portion exposes the bottom surface of the substrate. The package substrate further includes a second patterned metal layer, which is disposed on the bottom surface of the substrate exposed by the opening for electrically connecting the third chip.

In one or more embodiments of the present invention, the packaging substrate further includes a first wafer, a first molding compound layer, a third wafer, and a second molding compound layer. The first wafer is disposed on the first patterned metal layer. The first molding compound layer is disposed on the organic material layer, the redistribution layer, and the first patterned metal layer, and covers at least a portion of the first wafer. The third wafer is disposed on the second patterned metal layer. The second molding compound layer fills the opening and covers at least part of the third wafer or completely covers the third wafer.

In one or more embodiments of the present invention, the packaging substrate further includes a heat dissipation structure disposed on the first chip.

In one or more embodiments of the present invention, the interposer structure includes a substrate and a plurality of communication pillars. The top surface of the substrate is the top surface of the interposer structure. The communication post is disposed in the substrate and electrically connects the first patterned metal layer and the conductive pad.

In one or more embodiments of the present invention, the packaging substrate further includes a first wafer, a first molding compound layer, a third wafer, and a second molding compound layer. The first wafer is disposed on the first patterned metal layer. The first molding compound layer is disposed on the organic material layer, the substrate and the first patterned metal layer, and covers at least part of the first wafer. The third wafer is disposed on the second patterned metal layer. The second molding compound layer fills the opening and covers at least part of the third wafer or completely covers the third wafer.

According to another embodiment of the present invention, a packaging substrate includes an organic material layer, an interposer structure, a patterned metal layer, a plurality of conductive pillars, and a plurality of conductive pads. The organic material layer has a bottom surface. The interposer structure is disposed on the organic material layer. The patterned metal layer is provided on On the structure of the interposer, the patterned metal layer includes a first part and a second part. The first part is used to electrically connect the chip. The conductive pillar is disposed on the second part, and is used to electrically connect the chip or the packaging structure. The conductive pad is arranged on the bottom surface and electrically connected to the interlayer structure.

In the above embodiment of the present invention, by providing conductive pillars on the second part of the patterned metal layer, the package substrate can be electrically connected to the chip and also have the function of a transfer line (which is realized by the interposer structure and the conductive pad) At the same time, the packaging substrate can be additionally electrically connected to the packaging structure through the conductive pillars, thus achieving a stacked packaging structure, thereby improving the overall device density.

100‧‧‧Package substrate

110‧‧‧ organic material layer

111‧‧‧Bottom

112‧‧‧ opening

120‧‧‧Intermediate structure

121‧‧‧Top

122‧‧‧Substrate

122b‧‧‧Bottom

123‧‧‧Connecting column

124‧‧‧ Redistribution layer

125, 130, 160, 161‧‧‧ Patterned metal layer

171, 172‧‧‧Molding plastic layer

126‧‧‧dielectric layer

127, 191‧‧‧ Conductive blind hole

131‧‧‧Part 1

132‧‧‧Part Two

140‧‧‧conductive column

150‧‧‧conductive pad

192‧‧‧heat dissipation structure

200, 400 ‧‧‧ chips

300‧‧‧Package structure

FIG. 1 is a cross-sectional view of a package substrate according to an embodiment of the invention.

FIG. 2 is a cross-sectional view of a packaging substrate according to another embodiment of the invention.

FIG. 3 is a cross-sectional view of a packaging substrate according to another embodiment of the invention.

FIG. 4 is a cross-sectional view of a packaging substrate according to yet another embodiment of the present invention.

FIG. 5 is a cross-sectional view of a packaging substrate according to yet another embodiment of the invention.

FIG. 6 is a cross-sectional view of a package substrate according to yet another embodiment of the invention.

7 is a cross-sectional view of a packaging substrate according to yet another embodiment of the present invention.

8 is a cross-sectional view of a packaging substrate according to yet another embodiment of the present invention.

In the following, a plurality of embodiments of the present invention will be disclosed in the form of diagrams. For the sake of clarity, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present invention. That is to say, in some embodiments of the present invention, these practical details are unnecessary. In addition, in order to simplify the drawings, some conventional structures and elements will be shown in a simple schematic manner in the drawings.

In order to meet the requirements of high integration and miniaturization of semiconductor devices, the industry has developed various methods to increase the device density. For example, by using Package on Package (PoP), two or more components are vertically stacked or mounted on the back into a single component, thereby saving space on the printed circuit board. Different embodiments of the present invention provide a packaging substrate 100 which uses specially designed conductive pillars The via structure can realize the stacked packaging technology, thereby improving the device density of the semiconductor device.

FIG. 1 is a cross-sectional view of a package substrate 100 according to an embodiment of the invention. As shown in FIG. 1, the packaging substrate 100 includes an organic material layer 110, an interposer structure 120, a patterned metal layer 130, a plurality of conductive pillars 140 and a plurality of conductive pads 150. The organic material layer 110 has a bottom surface 111. The interposer structure 120 is buried in the organic material layer 110, wherein the interposer structure 120 has a top surface 121, and the organic material layer 110 exposes the top surface 121. The patterned metal layer 130 is disposed on the top surface 121. The patterned metal layer 130 includes a first part 131 and a second part 132. The first part 131 is used to electrically connect the chip 200. The conductive pillar 140 is disposed on the second portion 132 for electrically connecting the packaging structure 300. The conductive pad 150 is disposed on the bottom surface 111 and is electrically connected to the interposer structure 120.

By disposing the conductive pillar 140 on the second portion 132 of the patterned metal layer 130, the package substrate 100 can be electrically connected to the chip 200 and also have the function of a transfer line (which is realized by the interposer structure 120 and the conductive pad 150 ), at the same time, the packaging substrate 100 can be additionally electrically connected to the packaging structure 300 through the conductive pillars 140, thereby achieving a stacked packaging structure, thereby improving the overall device density.

In addition, embedding the interposer structure 120 in the organic material layer 110 can omit the soldering structure between the interposer and the organic material layer, thereby improving the reliability of the entire package substrate 100.

The line width of the conductive pillar 140 may be about 40 μm to about 60 μm, and the line spacing of the conductive pillar 140 may be about 15 μm to about 25 μm. Alternatively, the line width of the conductive pillar 140 may be about 50 microns, and the line spacing of the conductive pillar 140 may be about 20 microns. Because the conductive pillar 140 and the patterned metal layer 130 are disposed on the top surface 121 of the interposer structure 120, but not on the organic material layer 110, because the top surface 121 of the interposer structure 120 is compared with that of the organic material layer 110 The surface is relatively flat, so the line width and line spacing of the conductive pillar 140 and the patterned metal layer 130 can be made smaller, thus meeting the requirements of high integration and miniaturization of semiconductor devices.

In this embodiment, the conductive pillar 140 is electrically connected to the packaging structure 300, but it is not limited thereto. In other embodiments, the conductive pillar 140 may be used to electrically connect another wafer.

The interposer structure 120 includes a substrate 122, a plurality of communication pillars 123 and a redistribution layer 124. The redistribution layer 124 is disposed on the substrate 122, wherein the top surface of the redistribution layer 124 is the top surface 121 of the interposer structure 120. The communication pillar 123 is disposed in the substrate 122 and electrically connects the redistribution layer 124 and the conductive pad 150.

The redistribution layer 124 includes a patterned metal layer 125, a dielectric layer 126, and a conductive blind hole 127. The patterned metal layer 125 is disposed on the substrate 122 and electrically connected to the communication pillar 123. The dielectric layer 126 is disposed on the substrate 122 and the patterned metal layer 125, and the dielectric layer 126 covers the substrate 122 and the patterned metal layer 125. The patterned metal layer 130 is disposed on the dielectric layer 126. The conductive blind hole 127 is formed in the dielectric The electrical layer 126 is electrically connected to the patterned metal layers 125 and 130. The specific embodiments of the redistribution layer 124 described in this embodiment are merely examples, and are not intended to limit the present invention. In other embodiments, the redistribution layer 124 may further include other patterned metal layers disposed in the dielectric layer 126, and electrically connect the various patterned metal layers through conductive blind holes.

In this embodiment, the material of the dielectric layer 126 is a photosensitive dielectric material, but it is not limited thereto. In other embodiments, the material of the dielectric layer 126 may be a non-photosensitive dielectric material.

The substrate 122 can be made of silicon, glass or ceramic. It should be understood that the materials of the substrate 122 mentioned above are only examples and are not intended to limit the present invention. Those with ordinary knowledge in the technical field of the present invention should flexibly select the material of the substrate 122 according to actual needs.

The packaging substrate 100 further includes a patterned metal layer 160 and a conductive blind hole 191. The patterned metal layer 160 is disposed on the bottom surface 122b of the substrate 122, and is electrically connected to the communication pillar 123. The conductive blind hole 191 is formed in the organic material layer 110 and electrically connects the conductive pad 150 and the patterned metal layer 160. In addition, the conductive pad 150 can be used to electrically connect the circuit on a circuit board, so that the package substrate 100 is installed on the circuit board.

FIG. 2 is a cross-sectional view of a package substrate 100 according to another embodiment of the invention. The package substrate of this embodiment 100 is substantially the same as the aforementioned package substrate 100, and the differences are mainly described below.

As shown in FIG. 2, the organic material layer 110 further has an opening 112, and the opening 112 partially exposes the bottom surface 122 b of the substrate 122. The package substrate 100 further includes a patterned metal layer 161 disposed on the bottom surface 122 b of the substrate 122 exposed by the opening 112 for electrically connecting to the chip 400. In addition, the communication pillar 123 is electrically connected to the patterned metal layer 161.

FIG. 3 is a cross-sectional view of a package substrate 100 according to another embodiment of the invention. The package substrate 100 of this embodiment is substantially the same as the package substrate 100 of FIG. 2, and the differences are mainly described below.

As shown in FIG. 3, the packaging substrate 100 further includes molding compound layers 171 and 172. The molding compound layer 171 is disposed on the organic material layer 110, the redistribution layer 124, and the patterned metal layer 130, and covers at least a portion of the wafer 200. The molding compound layer 172 fills the opening 112 and covers at least part of the wafer 400 or completely covers the wafer 400. The package substrate 100 further includes a heat dissipation structure 192 disposed on the chip 200.

By providing the molding compound layers 171 and 172, the packaging substrate 100 can have a more stable structure. However, at the same time, the heat dissipation capability of the chip 200 will be weaker due to the coverage of the molding compound layer 171. Therefore, by disposing the heat dissipation structure 192 on the chip 200, the heat dissipation capability of the chip 200 will be enhanced.

Specifically, the heat dissipation structure 192 may be a heat dissipation fin or a heat sink. It should be understood that the specific embodiments of the heat dissipation structure 192 mentioned above are only examples, and are not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs should flexibly select the specific implementation of the heat dissipation structure 192 according to actual needs the way.

FIG. 4 is a cross-sectional view of a package substrate 100 according to yet another embodiment of the invention. The package substrate 100 of this embodiment is substantially the same as the package substrate 100 of FIG. 1, and the differences are mainly described below.

As shown in FIG. 4, the interposer structure 120 includes a substrate 122 and a plurality of communication pillars 123. The top surface of the substrate 122 is the top surface 121 of the interposer structure 120. The communication pillar 123 is disposed in the substrate 122 and electrically connected to the patterned metal layers 130 and 160.

FIG. 5 is a cross-sectional view of a package substrate 100 according to yet another embodiment of the invention. The package substrate 100 of this embodiment is substantially the same as the package substrate 100 of FIG. 2, and the differences are mainly described below.

As shown in FIG. 5, the interposer structure 120 includes a substrate 122 and a plurality of communication pillars 123. The top surface of the substrate 122 is the top surface 121 of the interposer structure 120. The communication pillar 123 is disposed in the substrate 122 and electrically connected to the patterned metal layers 130, 160, and 161.

FIG. 6 is a cross-sectional view of a package substrate 100 according to yet another embodiment of the invention. The package substrate of this embodiment 100 is substantially the same as the package substrate 100 of FIG. 3, and the differences are mainly described below.

As shown in FIG. 6, the interposer structure 120 includes a substrate 122 and a plurality of communication pillars 123. The top surface of the substrate 122 is the top surface 121 of the interposer structure 120. The communication pillar 123 is disposed in the substrate 122 and electrically connected to the patterned metal layers 130, 160, and 161. In addition, the molding compound layer 171 is disposed on the organic material layer 110, the substrate 122 and the patterned metal layer 130.

FIG. 7 is a cross-sectional view of a package substrate 100 according to yet another embodiment of the invention. The package substrate 100 of this embodiment is substantially the same as the package substrate 100 of FIG. 4, and the differences are mainly described below.

As shown in FIG. 7, the interposer structure 120 is disposed on the organic material layer 110 rather than buried in the organic material layer 110. In other words, the left and right sides of the interposer structure 120 and the left and right sides of the organic material layer 110 are aligned.

FIG. 8 is a cross-sectional view of a package substrate 100 according to yet another embodiment of the present invention. The package substrate 100 of this embodiment is substantially the same as the package substrate 100 of FIG. 1, and the differences are mainly described below.

As shown in FIG. 8, the interposer structure 120 is disposed on the organic material layer 110 rather than buried in the organic material layer 110. In other words, the left and right sides of the interposer structure 120 and the left and right sides of the organic material layer 110 are aligned.

By aligning the left and right sides of the interposer structure 120 and the left and right sides of the organic material layer 110, the overall size of the package substrate 100 can be further reduced, so the package substrate 100, the chip 200, and the package structure 300 are formed The overall size of the stacked package structure can be further reduced, thereby achieving the requirements of high integration and miniaturization of semiconductor devices.

In the above embodiment of the present invention, by providing the conductive pillar 140 on the second portion 132 of the patterned metal layer 130, the package substrate 100 can be electrically connected to the chip 200 and also have the function of a transfer line (which is composed of the interlayer structure 120 Simultaneously with the conductive pad 150), the package substrate 100 can be additionally electrically connected to the package structure 300 through the conductive pillar 140, thereby achieving a stacked package structure, thereby improving the overall device density.

Although the present invention has been disclosed as above in an embodiment, it is not intended to limit the present invention. Anyone who is familiar with this art can make various modifications and retouching without departing from the spirit and scope of the present invention, so the protection of the present invention The scope shall be as defined in the appended patent application scope.

100‧‧‧Package substrate

110‧‧‧ organic material layer

111‧‧‧Bottom

120‧‧‧Intermediate structure

121‧‧‧Top

122‧‧‧Substrate

122b‧‧‧Bottom

123‧‧‧Connecting column

124‧‧‧ Redistribution layer

125, 130, 160 ‧‧‧ patterned metal layer

126‧‧‧dielectric layer

127, 191‧‧‧ Conductive blind hole

131‧‧‧Part 1

132‧‧‧Part Two

140‧‧‧conductive column

150‧‧‧conductive pad

200‧‧‧chip

300‧‧‧Package structure

Claims (10)

An encapsulation substrate includes: an organic material layer having a bottom surface; an interposer structure embedded in the organic material layer, wherein the interposer structure has a top surface, and the organic material layer exposes the top surface; a first A patterned metal layer disposed on the top surface, wherein the first patterned metal layer includes a first part and a second part, the first part is used to electrically connect a first chip; A plurality of conductive pillars disposed on the second portion for electrically connecting a second chip or a packaging structure, wherein each of the conductive pillars has a top surface, and the height of the top surface is greater than that of the first chip The height of the installation; and a plurality of conductive pads are provided on the bottom surface and are electrically connected to the interposer structure. The package substrate according to claim 1, wherein the interposer structure includes: a substrate; a redistribution layer disposed on the substrate, wherein a top surface of the redistribution layer is the top surface of the interposer structure; and A plurality of communication pillars are disposed in the substrate and electrically connect the redistribution layer and the conductive pads. The package substrate as claimed in claim 2, wherein the organic material layer further has an opening, the opening part of which exposes a bottom surface of the substrate; and further comprising: a second patterned metal layer disposed on the exposed portion of the opening The bottom surface of the substrate is used to electrically connect a third chip. The packaging substrate according to claim 3, further comprising: a first chip disposed on the first patterned metal layer; a first molding compound layer disposed on the organic material layer, the redistribution layer and the first A patterned metal layer covering at least a portion of the first chip; a third chip disposed on the second patterned metal layer; and a second molding compound layer filling the opening and covering at least the portion Copies of the third wafer. The package substrate according to claim 4, further comprising: a heat dissipation structure, which is disposed on the first chip. The package substrate of claim 1, wherein the interposer structure comprises: a substrate, wherein a top surface of the substrate is the top surface of the interposer structure; and A plurality of communication pillars are disposed in the substrate and electrically connect the first patterned metal layer and the conductive pads. The package substrate as claimed in claim 6, wherein the organic material layer further has an opening, the opening part of which exposes a bottom surface of the substrate; and further comprising: a second patterned metal layer disposed on the exposed portion of the opening The bottom surface of the substrate is used to electrically connect a third chip. The package substrate according to claim 7, further comprising: a first chip disposed on the first patterned metal layer; and a first molding compound layer disposed on the organic material layer, the substrate and the first pattern A metallized layer and cover at least a portion of the first wafer; a third chip is disposed on the second patterned metal layer; and a second molding compound layer fills the opening and at least covers a portion of the The third wafer. The packaging substrate according to claim 8, further comprising: a heat dissipation structure, which is disposed on the first chip. A packaging substrate, comprising: an organic material layer with a bottom surface; An interposer structure is disposed on the organic material layer; a patterned metal layer is disposed on the interposer structure, wherein the patterned metal layer includes a first part and a second part, the first part Part is used to electrically connect a first chip; a plurality of conductive pillars are arranged on the second part for electrically connecting a second chip or a packaging structure, wherein each of the conductive pillars has a top surface The installation height of the top surface is greater than the installation height of the first wafer; and a plurality of conductive pads are provided on the bottom surface and electrically connected to the interposer structure.