TWI610429B - Method of fabricating complementary resistive switching memory - Google Patents

Abstract

A manufacturing method of a complementary resistive memory, comprising: sequentially forming a first conductor layer, a second conductor layer and a third conductor layer; performing a heat treatment to make the first conductor layer and the second conductor layer The interface forms a first oxide layer and a second oxide layer on the interface between the second conductor layer and the third conductor layer, and then transforms into a complementary resistive memory of one of the five-layer structure. In another embodiment, a first conductor layer, an oxide insulating layer and a third conductor layer are sequentially formed; and a heat treatment is performed to form a first oxide between the interface of the first conductor layer and the oxide insulating layer. The layer and the interface between the oxide insulating layer and the third conductor layer form a second oxide layer, thereby converting the oxide insulating layer into a second conductor layer, and then converting into a complementary resistive memory of one of the five-layer structure.

Description

Method for manufacturing complementary resistive memory

The invention relates to a method for manufacturing a resistive memory, in particular to a method for manufacturing a complementary resistive memory in which two sets of resistive memories are connected in series.

Resistive Random Access Memory (RRAM) is a new generation of non-volatile memory. It can display digital information of digits “0” and digit “1” in the high resistance state of resistive memory (High Resistive State). , HRS) and Low Resistive State (LRS) for stable digital storage and cyclic switching. The structure of the resistive memory is simple and the component size is small. Therefore, the components can be arranged in a crossbar array of crossbars at the intersection of the electrode column and the electrode column. However, the resistive memory of the crossbar array of the crossbar type In electrical operation, it will be interrupted by the sneak current of adjacent components, so each resistive memory must have excellent nonlinearity (IV Curve) characteristics to operate. The advantage of high current ratio or high resistance ratio between voltage and non-operating voltage, so that the sneak current effect of adjacent components is reduced.

In conventional applications, two sets of resistive memories can be connected in series to form a complementary Resistive Switching Memory (CRS Memory), thereby obtaining a better nonlinear current than a single resistive memory. Voltage curve characteristic, but conventional complementary Resistive memory must be fabricated by a semiconductor process with five masks, for example, five times of coating, lithography and etching processes to form complementary resistive memory, and complex and time-consuming multi-mask semiconductor process This will result in increased production costs and reduced product yield.

The invention relates to a metal/Metal/Metal (MMM) sandwich structure of the first, second and third conductor layers, which is respectively subjected to heat treatment to the metal material of the three-layer conductor layer or the metal element of the nitride conductor material respectively. The interface with the second conductor layer and the interface between the second and third conductor layers are combined with oxygen atoms to generate an oxide layer having resistive characteristics, and the two sets of back-to-back series resistance can be simultaneously completed by the semiconductor process of the three masks. The memory, and at the same time, complete the fabrication of the complementary resistive memory.

The invention relates to a Metal/Insulator/Metal (MIM) sandwich structure of a first conductor layer, an oxide insulating layer and a third conductor layer, which has an effect of migrating oxygen atoms to oxygen atoms of the oxide insulating layer by heat treatment, so that The oxygen atoms migrate to the interface between the first conductor layer and the oxide insulating layer, respectively, and the interface between the third conductor layer and the oxide insulating layer is combined with the metal ions, thereby generating an oxide layer having resistance characteristics and causing the oxide insulating layer itself. Due to the migration of oxygen atoms into a conductor layer, two sets of resistive memory connected in series can be completed simultaneously through a semiconductor process of three masks, thereby simultaneously completing the fabrication of the complementary resistive memory.

The invention provides a method for manufacturing a complementary resistive memory, wherein the semiconductor process of the three masks is reduced in the manufacturing cost of the component and the yield of the product compared to the five mask component processes of the conventional application.

In one embodiment, the present invention provides a method of fabricating a complementary resistive memory, the method comprising: forming a first conductor layer; forming a second conductor layer on the first conductor layer; forming a The third conductor layer is on the second conductor layer, wherein the third conductor layer and the first conductor layer are composed of the same material; and a heat treatment is performed to form a first oxide between the interface of the first conductor layer and the second conductor layer Forming a second oxide layer between the layer and the interface between the second conductor layer and the third conductor layer, and converting into a complementary resistive memory of the five-layer layer structure, wherein the first oxide layer and the second oxide layer are Consists of the same material.

In another embodiment, the present invention provides a method of fabricating a complementary resistive memory, the method comprising: forming a first conductor layer; forming an oxide insulating layer on the first conductor layer; forming a third conductor Laying on the oxide insulating layer, wherein the third conductor layer and the first conductor layer are composed of the same material; performing a heat treatment to form a first oxide layer and oxidizing the interface between the first conductor layer and the oxide insulating layer Forming a second oxide layer on the interface between the insulating layer and the third conductive layer, thereby converting the oxide insulating layer itself into a second conductive layer, and converting into a complementary resistive memory of a five-layer laminated structure, wherein The oxide layer and the second oxide layer are composed of the same material.

10‧‧‧Complementary Resistive Memory

10A, 10B‧‧‧Three-layer structure of resistive memory

20‧‧‧Complementary Resistive Memory

20A, 20B‧‧‧Three-layer structure of resistive memory

100‧‧‧Substrate

110‧‧‧First conductor layer

120‧‧‧Second conductor layer

130‧‧‧3rd conductor layer

140‧‧‧ heat treatment

150‧‧‧First oxide layer

152‧‧‧Second oxide layer

160‧‧‧Oxide insulation

170‧‧‧First oxide layer

172‧‧‧Second oxide layer

1 is a flow chart showing a method of manufacturing a complementary resistive memory according to a first embodiment of the present invention.

2A to 2D are schematic views of a complementary resistive memory according to a first embodiment of the present invention.

3 is a flow chart showing a method of manufacturing a complementary resistive memory according to a second embodiment of the present invention.

4A to 4D are schematic views of a complementary resistive memory according to a second embodiment of the present invention.

5 is a graph showing a non-linear current-voltage curve of a complementary resistive memory of a five-layer laminated structure of ITO/TiOy/TiNx/TiOy/ITO according to a first embodiment of the present invention.

1 is a flow chart showing a method of manufacturing a complementary resistive memory according to a first embodiment of the present invention, and FIGS. 2A to 2D are schematic views showing a complementary resistive memory according to a first embodiment of the present invention. The manufacturing method of the complementary resistive memory, the steps thereof include:

Step S102, as shown in FIG. 2A, a first conductor layer 110 is formed on a substrate 100. The first conductor layer 110 can be coated by an electroplating (Electrolytic Plating) technique, an electroless plating technique, a sputtering technique, or a thermal coating technique, and then passed through a first light. The first conductor layer 110 is formed by a semiconductor process of the mask, such as a lithography process and an etching process, but is not limited thereto; in the embodiment, the first conductor layer 110 is a lower electrode. In addition, the substrate 100 may include a semiconductor wafer substrate or any desired semiconductor component formed on the semiconductor wafer substrate, and may include a glass substrate or a flexible substrate, but is not limited thereto.

Step S104, as shown in FIG. 2B, a second conductor layer 120 is formed on the first conductor layer 110. Wherein, the second conductor layer 120 can be coated by an electroplating (Electrolytic Plating) technology, an electroless plating (Electroless Plating) technique, a sputtering (Sputtering Coating) technique or a vapor deposition (Thermal Coating) technique, and then passed through a second mask. The second conductor layer 120 is formed by a semiconductor process, such as a lithography process and an etching process, but is not limited thereto.

Step S106, as shown in FIG. 2C, a third conductor layer 130 is formed on the second conductor layer 120, wherein the third conductor layer 130 and the first conductor layer 110 are composed of the same material. The third conductor layer 130 can be coated by an electroplating (Electrolytic Plating) technique, an electroless plating technique, a sputtering technique, or a thermal coating technique, and then passed through a third mask. The third conductor layer 130 is formed by a semiconductor process, such as a lithography process and an etch process, but is not limited thereto; in the embodiment, the third conductor layer 130 is an upper electrode.

In one embodiment, one of the first conductor layer 110 and the second conductor layer 120 is an oxide conductor material, and the other of the two is a metal material or a nitride conductor material. For example, when the first conductor layer 110 is an oxide conductor material, the second conductor layer 120 is a metal material or a nitride conductor material; similarly, when the second conductor layer 120 is an oxide conductor In the case of the material, the first conductor layer 110 is a metal material or a nitride conductor material, but is not limited thereto.

In another embodiment, the oxide conductor material is indium tin oxide (ITO) or aluminum zinc oxide (AZO), and the metal material is titanium (Ti), aluminum (Al), tantalum (Ta), zirconium (Zr). ), tungsten (W) or chromium (Cr), the nitride conductor material is titanium nitride (TiN _x ), tantalum nitride (TaN _x ), zirconium nitride (ZrN _x ), tungsten nitride (WN _x ) Or chromium nitride (CrN _x ), but not limited to this.

For example, the three-layer layer structure embodiment of the first conductor layer 110, the second conductor layer 120, and the third conductor layer 130 may be ITO/Ti/ITO, Ti/ITO/Ti, ITO/TiNx/ITO or TiNx/ A laminated structure of ITO/TiNx or the like, but not limited thereto.

Step S108, as shown in FIG. 2D, a heat treatment 140 is performed to form a first oxide layer 150 and a second conductor layer 120 and a third conductor layer 130 interface between the interface of the first conductor layer 110 and the second conductor layer 120. A second oxide layer 152 is formed, which in turn is converted into a complementary resistive memory 10 of a five-layered layer structure, wherein the first oxide layer 150 and the second oxide layer 152 are composed of the same material. In addition, the heat treatment 140 is an annealing treatment, a microwave heating treatment or a laser heat treatment, and the five-layer laminated structure of the complementary resistive memory 10 is composed of three layers of resistive memory three-layer structure 10A, 10B, respectively. Formed in a back-to-back arrangement.

In one embodiment, the first oxide layer 150 and the second oxide layer 152 are titanium oxide (TiOy), aluminum oxide (AlOy), tantalum oxide (TaOy), zirconium oxide (ZrOy), and tungsten oxide (WOy). Or chromium oxide (CrOy), but not limited to this.

According to the above example, the three-layer layer structure embodiment of the first conductor layer 110, the second conductor layer 120 and the third conductor layer 130 may be ITO/Ti/ITO, Ti/ITO/Ti, ITO/TiNx/ITO or TiNx/ The stacked structure of ITO/TiNx or the like is subsequently subjected to heat treatment 140 to be converted into the first conductor layer 110, the first oxide layer 150, the second conductor layer 120, the second oxide layer 152, and the third conductor layer 130. The fifth layer layer structure embodiment may be ITO/TiOy/Ti/TiOy/ITO, Ti/TiOy/ITO/TiOy/Ti, ITO/TiOy/TiNx/TiOy/ITO or TiNx/TiOy/ITO/TiOy/TiNx, etc. The laminated structure, that is, the complementary resistive memory 10 embodiment of the five-layer laminated structure, can be composed of three layers of resistive memory, ITO/TiOy/Ti and Ti/TiOy/ITO, Ti/TiOy, respectively. /ITO is formed by ITO/TiOy/Ti, ITO/TiOy/TiNx and TiNx/TiOy/ITO, TiNx/TiOy/ITO and ITO/TiOy/TiNx in series, but not limited thereto.

Specifically, the present invention relates to the interface between the metal material of the three-layer conductor layer or the metal material of the nitride conductor material on the interface of the first and second conductor layers and the interface between the second and third conductor layers by heat treatment. The oxygen atoms are combined, wherein the first and third conductor layers are composed of the same material to avoid different ability to bond with oxygen atoms due to different activities, thereby producing an oxide layer having resistive properties, and a semiconductor process via three masks. Two sets of resistive memory connected in series can be completed at the same time, and the complementary resistive memory is simultaneously fabricated, which has better nonlinear current-voltage curve characteristics than only a single resistive memory, and has more The advantage of the current ratio between the operating voltage and the non-operating voltage is high or the resistance ratio is high, so that the sneak current effect of adjacent components is reduced. In addition, the semiconductor process of the three masks will reduce the component manufacturing cost and product yield compared to the conventional five-mask process.

3 is a flow chart showing a method of manufacturing a complementary resistive memory according to a second embodiment of the present invention, and FIGS. 4A to 4D are schematic views showing a complementary resistive memory according to a second embodiment of the present invention. The manufacturing method of the complementary resistive memory, the steps thereof include:

Step S302, as shown in FIG. 4A, a first conductor layer 110 is formed on a substrate 100. The first conductor layer 110 can be coated by an electroplating (Electrolytic Plating) technique, an electroless plating technique, a sputtering technique, or a thermal coating technique, and then passed through a first light. The first conductor layer 110 is formed by a semiconductor process of the mask, such as a lithography process and an etching process, but is not limited thereto; in this embodiment, the first The conductor layer 110 is a lower electrode. In addition, the substrate 100 may include a semiconductor wafer substrate or any desired semiconductor component formed on the semiconductor wafer substrate, and may include a glass substrate or a flexible substrate, but is not limited thereto.

Step S304, as shown in FIG. 4B, an oxide insulating layer 160 is formed on the first conductor layer 110. The oxide insulating layer 160 may be subjected to a plating process using an electroplating (Electrolytic Plating) technique, an electroless plating (Electroless Plating) technique, a sputtering (Sputtering Coating) technique, or a vapor deposition (Thermal Coating) technique, and then passing through a second mask. The semiconductor process, such as a lithography process and an etch process, forms the oxide insulating layer 160, but is not limited thereto.

Step S306, as shown in FIG. 4C, a third conductor layer 130 is formed on the oxide insulating layer, wherein the third conductor layer 130 and the first conductor layer 110 are composed of the same material. The third conductor layer 130 can be coated by an electroplating (Electrolytic Plating) technique, an electroless plating technique, a sputtering technique, or a thermal coating technique, and then passed through a third mask. The third conductor layer 130 is formed by a semiconductor process, such as a lithography process and an etch process, but is not limited thereto; in the embodiment, the third conductor layer 130 is an upper electrode.

Step S308, as shown in FIG. 4D, a heat treatment 140 is performed to form a first oxide layer 170 and an interface between the oxide insulating layer 160 and the third conductor layer 130 between the interface of the first conductor layer 110 and the oxide insulating layer 160. Forming a second oxide layer 172, thereby converting the oxide insulating layer 160 into a second conductive layer 120, and converting into a complementary layered resistive memory 20 of a five-layer laminated structure, wherein the first oxide layer 170 and the first oxide layer The dioxide layer 172 is composed of the same material. In addition, the heat treatment 140 is an annealing treatment, a microwave heating treatment or a laser heat treatment, and the five-layer laminated structure of the complementary resistive memory 20 is composed of two layers of resistive memory three-layer structure 20A, 20B, respectively. Formed in a back-to-back arrangement.

In one embodiment, the first conductor layer 110 is a metal material or a nitride conductor material, but is not limited thereto. The second conductor layer 120 is a metal element composed of an oxide insulating layer 160. For example, metal materials such as copper (Cu) or nickel (Ni) are not limited thereto.

For example, the three-layer layer structure embodiment of the first conductor layer 110, the oxide insulating layer 160, and the third conductor layer 130 may be a stacked structure of Ti/CuOx/Ti or TiNx/CuOx/TiNx, etc., but not This is limited.

In another embodiment, the oxide insulating layer 160 is copper oxide (CuOx) or nickel oxide (NiOx), and the metal material is titanium (Ti), aluminum (Al), tantalum (Ta), zirconium (Zr), Tungsten (W) or chromium (Cr), nitride conductor material is titanium nitride (TiN _x ), tantalum nitride (TaN _x ), zirconium nitride (ZrN _x ), tungsten nitride (WN _x ) or nitride Chromium (CrN _x ), of which 0.2 ≦ x ≦ 1.5, but not limited by the examples.

In still another embodiment, the first oxide layer 170 and the second oxide layer 172 are titanium oxide (TiOy), aluminum oxide (AlOy), tantalum oxide (TaOy), zirconium oxide (ZrOy), tungsten oxide (WOy). Or chromium oxide (CrOy), of which 1.3 ≦ y ≦ 2, but not limited by the examples.

According to the above example, the three-layer layer structure embodiment of the first conductor layer 110, the oxide insulating layer 160 and the third conductor layer 130 may be a stacked structure of Ti/CuOx/Ti or TiNx/CuOx/TiNx, etc., and then performed. The heat treatment 140 to be converted into the first conductor layer 110, the first oxide layer 170, the second conductor layer 120, the second oxide layer 172 and the third conductor layer 130 may be Ti/TiOy/Cu. The stacked structure of /TiOy/Ti or TiNx/TiOy/Cu/TiOy/TiNx, that is, the complementary resistive memory 20 embodiment of the five-layer laminated structure can be respectively composed of three layers of resistive memory. The structure Ti/TiOy/Cu and Cu/TiOy/Ti, TiNx/TiOy/Cu and Cu/TiOy/TiNx resistive memory are formed in a back-to-back series, but are not limited thereto.

Specifically, the present invention is to effect the migration of oxygen atoms to the oxygen atoms of the oxide insulating layer by heat treatment, so that the oxygen atoms migrate to the interface of the first conductor layer and the oxide insulating layer, respectively, and the third conductor layer and The interface of the oxide insulating layer is combined with metal ions, wherein the first and third conductor layers are composed of the same material to avoid different ability to bond with oxygen atoms due to different activities, thereby producing an oxide layer having resistance characteristics. And make the oxide insulation layer itself change due to the migration of oxygen atoms. Turning into a conductor layer, two sets of resistive memory connected in series can be completed simultaneously through a semiconductor process of three masks, thereby simultaneously completing the fabrication of a complementary resistive memory, which is superior to a single resistive memory. The characteristics of the nonlinear current-voltage curve have the advantages of high current ratio or high resistance ratio between the operating voltage and the non-operating voltage, thereby reducing the sneak current effect of adjacent components. In addition, the semiconductor process of the three masks will reduce the component manufacturing cost and product yield compared to the conventional five-mask process.

5 is a graph showing a non-linear current-voltage curve of a complementary resistive memory of a five-layer laminated structure of ITO/TiOy/TiNx/TiOy/ITO according to a first embodiment of the present invention. Wherein, the complementary resistive memory between the V _th3 and V _th1 voltages is in a higher resistance state of a digital “0” or a digit “1”, that is, one resistive memory is LRS and another resistive memory The body is HRS; in the high current section between V _th1 and V _th2 voltages and between V _th3 and V _th4 voltages, the complementary resistive memory is in the "ON" state of lower resistance, at this time two Resistive memory is LRS.

The cyclic resistance switching of the complementary resistive memory operates in the first and third quadrants of the nonlinear current-voltage graph. In the first quadrant of the half cycle, the complementary resistive memory is first in a higher resistance state. The digit “0”, the complementary resistive memory changes to “ON” as the positive bias is applied from 0V to V _th1 , and the complementary resistive memory remains “ON” when the voltage is continuously increased until the voltage reaches At V _th2 , the complementary resistive memory is switched to the state of the digital "1", and then the complementary resistive memory is maintained in the digital "1" state when the voltage is reduced until 0V.

The cyclic mode in the third quadrant is similar to that of the first quadrant. When the negative bias voltage is applied to V _th3 , the digital "1" state is switched to the "ON" state, and the "ON" state is maintained until the negative bias voltage reaches V _th4. To the digit "0", the complementary resistive memory is maintained in the digital "0" state when the negative bias voltage is reduced until 0V. Complementary RRAM than about greater than V _th1 (or | V _th3 |) when the read voltage V _READ (about 0.5V or -0.5V in the position voltage), can be distinguished as being "ON" based on the current size of element State or digit "1" state, either "ON" state or "0"state; and at V _READ /2 (approximately 0.25V or -0.25V voltage position), the component is in digit "0" or digit" There is a small current of 1", so the complementary resistive memory can obtain a more excellent nonlinear current-voltage curve.

In summary, the method for manufacturing the complementary resistive memory of the present invention is to complete two sets of resistive memories connected in series to each other through a semiconductor process and a heat treatment process of three masks, thereby simultaneously completing the complementary resistors. The production of the memory has better nonlinear current-voltage curve characteristics than the single resistive memory, and has the advantages of high current ratio or high resistance ratio at the operating voltage and the non-operating voltage, thereby The sneak current effect of adjacent components is reduced. In addition, the semiconductor process of the three masks will reduce the component manufacturing cost and product yield compared to the conventional five-mask process.

However, the specific embodiments described above are merely used to exemplify the features and functions of the present invention, and are not intended to limit the scope of the present invention, and may be applied without departing from the spirit and scope of the present invention. Equivalent changes and modifications made to the disclosure of the present invention are still covered by the scope of the following claims.

10‧‧‧Complementary Resistive Memory

10A, 10B‧‧‧Three-layer structure of resistive memory

100‧‧‧Substrate

110‧‧‧First conductor layer

120‧‧‧Second conductor layer

130‧‧‧3rd conductor layer

140‧‧‧ heat treatment

150‧‧‧First oxide layer

152‧‧‧Second oxide layer

Claims (10)

A method for manufacturing a complementary resistive memory, the method comprising: forming a first conductor layer; forming a second conductor layer on the first conductor layer; forming a third conductor layer on the second conductor layer, Wherein the third conductor layer and the first conductor layer are composed of the same material; and a heat treatment is performed to form a first oxide layer and the second conductor between the interface of the first conductor layer and the second conductor layer Forming a second oxide layer between the layer and the interface of the third conductor layer, and converting into a complementary resistive memory of a five-layer layer structure, wherein the first oxide layer and the second oxide layer are the same Made up of materials. The manufacturing method of claim 1, wherein one of the first conductor layer and the second conductor layer is an oxide conductor material, and the other of the two is a metal material. Or a nitride conductor material. The manufacturing method according to claim 2, wherein the oxide conductor material is indium tin oxide (ITO) or aluminum zinc oxide (AZO), and the metal material is titanium (Ti) or aluminum (Al). Tantalum (Ta), zirconium (Zr), tungsten (W) or chromium (Cr), the nitride conductor material is titanium nitride (TiN _x ), tantalum nitride (TaN _x ), zirconium nitride (ZrN _x ) , tungsten nitride (WN _x ) or chromium nitride (CrN _x ), of which 0.2≦x≦1.5. The manufacturing method according to claim 3, wherein the first oxide layer and the second oxide layer are titanium oxide (TiOy), aluminum oxide (AlOy), tantalum oxide (TaOy), and zirconium oxide ( ZrOy), tungsten oxide (WOy) or chromium oxide (CrOy), of which 1.3≦y≦2. A method for manufacturing a complementary resistive memory, the method comprising: forming a first conductor layer; Forming an oxide insulating layer on the first conductor layer; forming a third conductor layer on the oxide insulating layer, wherein the third conductor layer and the first conductor layer are composed of the same material; Heat treating to form a first oxide layer between the interface of the first conductor layer and the oxide insulating layer and a second oxide layer between the oxide insulating layer and the interface of the third conductor layer, thereby further forming the oxide The insulating layer is transformed into a second conductor layer, and then converted into a complementary resistive memory of one of the five-layered layer structure, wherein the first oxide layer and the second oxide layer are composed of the same material. The manufacturing method of claim 5, wherein the first conductor layer is a metal material or a nitride conductor material. The manufacturing method of claim 5, wherein the second conductor layer is a metal element within the composition of the oxide insulating layer. The manufacturing method according to claim 7, wherein the oxide insulating layer is copper oxide (CuOx) or nickel oxide (NiOx), and the metal material is titanium (Ti), aluminum (Al), or Ta), zirconium (Zr), tungsten (W) or chromium (Cr), the nitride conductor material is titanium nitride (TiN _x ), tantalum nitride (TaN _x ), zirconium nitride (ZrN _x ), nitrogen Tungsten (WN _x ) or chromium nitride (CrN _x ), of which 0.2≦x≦1.5. The manufacturing method according to claim 8, wherein the first oxide layer and the second oxide layer are titanium oxide (TiOy), aluminum oxide (AlOy), tantalum oxide (TaOy), and zirconium oxide ( ZrOy), tungsten oxide (WOy) or chromium oxide (CrOy), of which 1.3≦y≦2. The manufacturing method according to claim 1 or 5, wherein the heat treatment is an annealing treatment, a microwave heating treatment or a laser heat treatment.