TWI608325B - A low-voltage, high-accuracy current mirror circuit - Google Patents

Description

Low voltage and high accuracy current mirror circuit

The present invention relates generally to integrated circuits, and more particularly to a low voltage, high accuracy current mirror circuit design.

Integrated circuits typically include components that operate in accordance with a bandgap voltage reference (eg, buffers, amplifiers, flip-flops, etc.). Bandgap voltage reference systems are widely used in unrelated temperature and voltage reference circuits in integrated circuits. Since the bandgap circuit requires a large footprint, there may be hundreds of components operating in accordance with a bandgap voltage reference within a given circuit. Typically, each component receives information on the bandgap voltage reference over a long distance (eg, 2 mm). If the voltage is used for long-distance transmission of such information, it is difficult to ensure that the bandgap voltage is measured and converted to the same ground potential of the current. Moreover, such voltages are very expensive in terms of current conversion. If current is used to transmit this information, the current requires a point-to-point connection, thus requiring many current connections to operate over long distances. Such a connection is also expensive in terms of area.

Accordingly, there is a need in the art for a more optimized manner of providing a reference current to a plurality of components within an integrated circuit.

One implementation of the method of the present invention includes a low voltage, high accuracy current mirror circuit. The current mirror circuit includes an input circuit configured to receive an input reference current, wherein the input circuit includes a feedback channel for comparing and substantially matching the input reference current to the output current, and wherein the feedback channel is not Configuring to match an input voltage to an output voltage, and wherein the input circuit does not include a comparator having an operational amplifier that compares the input reference current to the output current; and an output circuit coupled to the input A circuit, wherein the output circuit is configured to transmit the output current to one or more components of the circuit block.

The advantage is that the disclosed method takes up a small amount of area on the integrated circuit wafer. For example, the feedback channel allows the current mirror circuit to be easily balanced (eg, it is easy to match the input current to the output current without causing oscillatory behavior) and is done at low cost (eg, without taking up a lot of space or spending Large components that are quite expensive in terms of terms, such as operational amplifiers.

100‧‧‧ computer system

102‧‧‧Central Processing Unit

103‧‧‧Device Driver

104‧‧‧System Memory

105‧‧‧Memory Bridge

106‧‧‧ bus or other communication path; path

107‧‧‧Input/Output (I/O) Bridge

108‧‧‧User input device

110‧‧‧ display device

111‧‧‧Display screen

112‧‧‧Parallel Processing Subsystem

113‧‧‧ Bus or other communication path

114‧‧‧System Disk

116‧‧‧Switch

118‧‧‧Network adapter

120, 121‧‧‧Addition card

200‧‧‧Common analog/mixed signal physical layered circuit

202‧‧‧Band voltage reference

204‧‧‧Operational Transducer

205, 205 (1), 205 (2) ~ 205 (N) ‧ ‧ circuit blocks

206‧‧‧reference voltage

208, 208 (1), 208 (2) ~ 208 (N) ‧ ‧ current mirror circuit

210, 210 (1), 210 (2) ~ 210 (N) ‧ ‧ input reference current

300A‧‧‧Common analog/mixed signal physical layered circuit

300B‧‧‧Common Analog/Mixed Signal Entity Laminated circuit

302‧‧‧Band Gap Voltage Reference

305(1), 305(2)~305(N)‧‧‧ circuit blocks

306‧‧‧Voltage

308(1)‧‧‧current mirror circuit

310(1)‧‧‧ input reference current

312(1)‧‧‧Regenerated current

314(1)‧‧‧ Output current

322(1)‧‧‧ NMOS transistor; transistor

324(1)‧‧‧ NMOS transistor; transistor

326(1)‧‧‧ PMOS transistor

334(1)‧‧‧ PMOS transistor; transistor

336(1)‧‧‧ series PMOS transistor; PMOS transistor

342(1)‧‧‧ NMOS transistor; transistor; stacked transistor

344(1)‧‧‧ NMOS transistor; transistor; stacked transistor

400‧‧‧ analog/mixed signal real volume circuits; physical layer (PHY)

402‧‧‧Band Voltage Reference

405(1), 405(2)~405(N)‧‧‧ circuit blocks

406‧‧‧reference voltage; voltage

408(1)‧‧‧current mirror circuit

410(1)‧‧‧ input reference current; current

412(1)‧‧‧ Current

414(1)‧‧‧ Output current; current

422(1)‧‧‧ NMOS transistor

424(1)‧‧‧ input circuit

424(1)‧‧‧ NMOS transistor

426(1)‧‧‧ PMOS transistor

430(1)‧‧‧ NMOS transistor

432(1)‧‧‧ feedback channel

434(1)‧‧‧ PMOS transistor

436(1)‧‧‧ series PMOS transistor; PMOS transistor

444(1)‧‧‧ Output Circuit

V _gs ‧‧ ‧ gate to source voltage

V _dd ‧‧‧Power supply voltage; reference voltage

V _ds ‧‧‧bend-to-source voltage

V _th ‧‧‧ threshold voltage

The present invention, in its broader aspects, may be described in detail, by way of a It is to be understood, however, that the invention is not limited by the scope of the invention

The first figure illustrates a block diagram of a computer system configured to perform one or more aspects of the present invention.

The second picture is a block diagram of a conventional analog/mixed signal physical layer (PHY, "Physical Layer") integrated circuit.

The third A diagram is a circuit diagram of a conventional analog/mixed signal physical layer (PHY) integrated circuit.

The third B diagram is a circuit diagram of another conventional analog/mixed signal physical layer (PHY) integrated circuit.

The fourth figure is a circuit diagram of an analog/mixed signal entity (PHY) integrated circuit in accordance with an embodiment of the present invention.

Numerous specific details are set forth in the following description in order to provide a more complete understanding of the invention. It will be apparent to those skilled in the art, however, that the invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.

System Overview

The first figure illustrates a block diagram of a computer system 100 configured to perform one or more aspects of the present invention. The computer system 100 includes a central processing unit (CPU, "Central Processing Unit") 102 and a system memory 104 that includes a device driver 103. CPU 102 and system memory 104 communicate via an interconnect path that can include a memory bridge 105. For example, the memory bridge 105 may be a north bridge wafer, through a bus bar or other communication path 106 [eg For example, a HyperTransport link or the like is connected to an input/output (I/O, "Input/output") bridge 107. For example, I/O bridge 107 may be a south bridge wafer that receives user input from one or more user input devices 108 (eg, keyboard, mouse, etc.) and will pass through path 106 and memory bridge 105. This input is forwarded to the CPU 102.

As also shown, the parallel processing subsystem 112 passes through a bus or other communication path 113 (eg, PCI Express, "Peripheral component interconnect express"), Accelerated Graphics Port (AGP), and / or super transfer chain, etc. coupled to the memory bridge 105. In one implementation, the parallel processing subsystem 112 transmits pixels to the display device 110 (eg, a conventional cathode ray tube (CRT), and/or a liquid crystal display (LCD) type). The graphics subsystem of the screen, etc. System disk 114 is also coupled to I/O bridge 107. Switch 116 provides a connection between I/O bridge 107 and other components, such as network adapter 118 and various add-on cards 120 and 121. Other components (not explicitly shown), including universal serial bus (USB, "Universal serial bus") and / or other 埠 connection, CD (CD, "Compact disc"), digital video disc (DVD, "Digital video disc" The machine, the film recording device, and the like can also be connected to the I/O bridge 107. The communication path interconnecting the various components in the first figure can be implemented using any suitable protocol, such as PCI, PCI Express (PCIe), AGP, HyperTransport, and/or any other bus or point-to-point communication protocol, and can be used Connections between different devices of different protocols are known in the art. The device is a combination of hardware or hardware and software. The components are also hardware or a combination of hardware and software.

In one implementation, parallel processing subsystem 112 incorporates circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constitutes a graphics processing unit (GPU, "Graphics processing unit"). In another implementation, parallel processing subsystem 112 incorporates circuitry optimized for general processing while retaining the underlying computing architecture described in more detail herein. In yet another implementation, parallel processing subsystem 112 may be integrated with one or more other system components, such as memory bridge 105, CPU 102, and I/O bridge 107 to form a system single chip (SoC, "System on Chip").

It should be noted that the systems shown in the text are illustrative and that variations and modifications are possible. The connection topology can be modified as needed, including the number and settings of bridges, the number of CPUs 102, and the number of parallel processing subsystems 112. For example, in some implementations, the system The memory 104 is directly connected to the CPU 102 rather than via the bridge, and other devices communicate with the system memory 104 through the memory bridge 105 and the CPU 102. In other alternative arrangements, parallel processing subsystem 112 is coupled to I/O bridge 107 or directly to CPU 102, rather than to memory bridge 105. In still other implementations, I/O bridge 107 and memory bridge 105 may be integrated into a single wafer. A large implementation may include two or more CPUs 102 and two or more parallel processing subsystems 112. The particular components shown are as needed; for example, any number of additional cards or peripheral devices may be supported. In some implementations, switch 116 is eliminated and network adapter 118 and add-on cards 120, 121 are directly connected to I/O bridge 107.

Overview of analog/mixed-signal physical layer (PHY) circuits

The second figure is a block diagram of a conventional analog/mixed signal physical layered body circuit 200 (PHY 200). PHY 200 includes a bandgap voltage reference coupled to circuit block 205, including a circuit block 205(1), circuit blocks 205(2), ..., and circuit block 205(N), where N 1. The bandgap voltage reference includes an operational amplifier (OTA, "Operational Transconductance Amplifier" 204). Each of circuit blocks 205 includes a current mirror circuit 208 of the same reference number. For example, circuit block 205(1) includes a current mirror circuit 208(1), and so on.

The bandgap voltage reference 202 is a voltage reference circuit that is independent of temperature. In the standard analog/mixed signal PHY 200, typically only one bandgap voltage reference 202 is on the integrated circuit to generate the reference voltage 206. The limitation of only one bandgap voltage reference 202 is due to the fact that the bandgap voltage reference 202 occupies a large area on the integrated circuit. Typically, the bandgap voltage reference 202 is hundreds of times larger in area than the current mirror circuit 208. The OTA 204 series amplifier has a differential input voltage that produces an input reference current. OTA 204 is a voltage controlled current source (VCCS, "Voltage controlled current source").

Accordingly, PHY 200 is configured to convert reference voltage 206 to an input reference current, including input reference current 210(1), input reference current 210(2), ..., and input reference current 210(N), where N 1. The input reference currents are then dispersed over long distances. Each input reference current corresponds to circuit block 205 of the same reference number. For example, input reference current 210(1) corresponds to circuit block 205(1), and so on.

The purpose of such current spreading is to avoid having a large OTA circuit on the PHY 200 in each instance where the integrated circuit is configured to convert the reference voltage 206 to the input reference current 210 for the target circuit block 205. Alternatively, to achieve the type of one-to-multipoint dispersion illustrated in the first figure, the integrated circuit can be configured to convert the reference voltage 206 to another form of voltage, such as a gate-to-source voltage V of the shorted transistor. _Gs . However, such a configuration results in significant inaccuracies in the current mirror 208 due to variations over long distances (e.g., 2 mm) on the wafer. Furthermore, even if the dispersed bandgap voltage is dispersed over long distances and large OTAs are used to convert the bandgap voltage into current, the architecture will still be at a long distance due to the base voltage level (for most cases the ground potential) The targets may be different and subject to inaccuracies, and such differences lead to misinterpreted scattered reference voltages.

After each circuit block 205 receives the input reference current, each circuit block 205 is configured to replicate the input reference current to regenerate the same input for biasing the block components (eg, buffer, amplifier, flip-flop, etc.) Multiple examples of reference currents. However, since N x m may exceed 100 in many configurations, it would be very difficult to directly transmit N x m reference currents from the bandgap voltage reference 202.

As explained above, the current mirror circuit (eg, current mirror circuit 208) is very important in analog/mixed signal PHYs (eg, PHY 200) where the PHY uses many circuit blocks (eg, circuit block 205). However, when the power supply voltage is low, each current mirror circuit is subject to severe defects, as explained further below with reference to Figure 3A.

The third A is a circuit diagram of a conventional analog/mixed signal physical layered circuit (PHY 300A). The PHY 300A includes a bandgap voltage reference 302 coupled to one or more circuit blocks, including circuit block 305(1). Other circuit blocks (e.g., from circuit block 305(2) to circuit block 305(N)) are not shown for simplicity. Each of the circuit blocks includes a current mirror circuit of the same reference number. For example, circuit block 305(1) includes current mirror circuit 308(1), and so on. PMOS electro-crystalline system p-type metal-oxide-semiconductor field-effect transistor, and NMOS electro-crystalline system n-type (n-type) MOS field effect transistor.

In this example of the third A diagram, the bandgap voltage reference 302 is fed to an OTA comprising a PMOS transistor 326(1). PMOS transistor 326(1) has a drain that is common to the gate of NMOS transistor 322(1) and the gate of NMOS transistor 324(1). The drain of NMOS transistor 324(1) is shared with the gate and drain of PMOS transistor 334(1) and the gate of one or more cascaded PMOS transistors 336(1). The source of PMOS transistor 334(1) and each source of PMOS transistor 336(1) are at a power sharing node configured to operate at supply voltage _Vdd . Each of the other parallel PMOS transistors 336 (1) is coupled to a component of circuit block 305 (1). The gate of NMOS transistor 324(1) shares a node with the gate of NMOS transistor 322(1). The source of the NMOS transistor 324(1) is commonly connected to the source of the NMOS transistor 322(1).

Complementary metal-oxide-semiconductor (CMOS) technology may require the supply voltage V _{dd to be} reduced to a low voltage. In the third A diagram, the low voltage is exemplified as 0.85 V (volt). In another example, the low voltage can include a voltage below about 2V, or another voltage value that is considered a low voltage for a particular circuit. Referring again to Figure 3A, the threshold voltage of a component (e.g., a component in Figure AA) may, for example, still be in the range of 400 mV (millivolts) to 500 mV. The threshold voltage inversion layer is formed at a gate voltage of an interface between an insulating layer (eg, an oxide layer) of the transistor and a substrate (eg, a body). The formation of the inversion layer allows electron flow through the gate to source junction.

The input reference current 310(1) is typically replicated by a transistor 322(1) connected by a diode that is shorted by a gate and a drain. By using this configuration, since the drain-to-source _{Vds of the} NMOS transistor 322(1) is always low after copying, the regenerated current 312(1) is always smaller than the input reference current 310 (1). ). For example, each gate-to-source voltage of the NMOS transistor 322(1) and the NMOS transistor 324(1) is 0.6V, but the NMOS transistor 322(1) has a drain-to-source voltage. V _ds is 0.6 V, and the drain-to-source voltage V _ds is 0.2 V with respect to the NMOS transistor 324 (1). This voltage difference can cause, for example, a 5 to 10% reduction in current, where severe channel length modulation occurs. Channel length modulation is a significant effect when using short gate channel lengths in recent sub-micron CMOS technology, resulting in a significant drop in the output impedance of the transistor. When a sufficient drain-to-source voltage is applied to the transistor, it is expected to behave like a constant current source. However, as the channel length is modulated, such a sufficient threshold voltage cannot ensure a constant current. For example, the threshold voltage V _th =0.5V, the gate-to-source voltage V _gs =0.6V, and the drain-to-source voltage V _ds =0.25V versus 0.6V may result in more than 10% current mismatch . Also, as shown in FIG. 3A, in each component of circuit block 305(1) (eg, amplifier, sampler, multiplexer, mixer, voltage controlled oscillator, input/output device, etc.), The output current 314(1) is received by the NMOS connected to the diode, and the output PMOS results in a mismatch of 0.6V with respect to the same _{Vds of} 0.25V. Thus, when output current 314(1) is used in each component, output current 314(1) can be as low as -20% of input reference current 310(1). As explained below with reference to Figure 3B, the conventional solution uses a series current mirror.

The third B diagram is a circuit diagram of another conventional analog/mixed signal physical layered circuit (PHY 300B). The third B diagram is similar to the third A diagram, but with the addition of the NMOS transistor 342(1) and the NMOS transistor 344(1). NMOS transistors [342(1), 322(1), 344(1), and 324(1)] are placed in the splicing current mirror to reduce the reduction in the copied input reference current. The word "cascode" is an abbreviation for "cascade to cathode". A stacked current mirror is a conventional technique in which two pairs of transistors are stacked and one of the transistors is used to control the drain voltage of the current source. For example, in the third B diagram, the transistor 342(1) is inserted between the gate and the drain of the transistor 322(1), and the other transistor 344(1) is inserted into the transistor 324(1). The drain is between the drain of the transistor 334(1). The two inserted stacked transistors [342(1) and 344(1)] have a common gate voltage that controls the drain voltages of 322(1) and 324(1). However, it is difficult to operate the splicing assembly with a very high buck-to-source voltage. For example, the transistor 324(1) with the splicing device above is 0.25V at the drain, and this 0.25V is required to be used between 324(1) and the upper splicing device. In such a configuration, the drain-to-source voltage across transistor 322(1) and transistor 324(1) is pushed down to a linear region (eg, "triode mode" or "ohm mode" (ohmic mode)"). (Compared to the third A picture.) The operating mode in which the voltage between the gate and the source of the linear region is higher than the threshold voltage and the voltage between the drain and the source is lower than the voltage between the gate and the source and the threshold voltage. . In this linear region, the transistor acts as a resistor and the current varies significantly with the drain voltage, thereby making the transistor unsuitable for use as a current source. Or an operational amplifier (not shown) may be used to accurately match the drain-to-source voltage _{Vds of the} two current sources. However, since an op amp can take up a large area, especially a compensation capacitor with stable balanced feedback, it is very expensive to use an op amp for each current mirror.

Accordingly, the following provides a circuit that operates at a low voltage and accurately reflects the reference current of the integrated circuit, and is not too expensive.

Low voltage and high accuracy current mirror circuit

The fourth figure is a kind of ratio/mixed signal according to one embodiment of the present invention. Circuit diagram of the bulk circuit (PHY 400). PHY 400 includes a bandgap voltage reference 402 coupled to one or more circuit blocks, including circuit block 405(1). Other circuit blocks (e.g., from circuit block 405(2) to circuit block 405(N)) are not shown for simplicity. Each of the circuit blocks includes a current mirror circuit of the same reference number. For example, circuit block 405(1) includes current mirror circuit 408(1), and so on.

In this example of the fourth figure, current mirror circuit 408(1) includes an input circuit 424(1) coupled to output circuit 444(1). Input circuit 424(1) includes an NMOS transistor 422(1), an NMOS transistor 424(1), and an NMOS transistor 430(1). The bandgap voltage reference 402 is coupled to the PMOS transistor 426(1). The PMOS transistor 426(1) has a drain coupled to the drain of the NMOS transistor 422(1) (eg, input reference current 410(1)) and has a gate of the NMOS transistor 424(1).

Output circuit 444(1) includes a PMOS transistor 434(1) and a series PMOS transistor 436(1). The drain of the NMOS transistor 424(1) is coupled to the gate and the drain of the PMOS transistor 434(1) and has a gate connected in series with the PMOS transistor 436(1). The source of PMOS transistor 434(1) and each source of series PMOS transistor 436(1) are coupled at a power supply configured to operate at supply voltage _Vdd . The drain of one of the series PMOS transistors 436 (1) is coupled to the drain of the NMOS transistor 430 (1) of the input circuit 424 (1). Each of the other PMOS transistors 436 (1) is coupled to a component of circuit block 405 (1). The gate of NMOS transistor 430(1) is coupled to a node having a gate of NMOS transistor 422(1). The source of the NMOS transistor 430(1), the source of the NMOS transistor 424(1), and the source of the NMOS transistor 422(1) are coupled to ground.

In the PHY 400 of the fourth figure, the transistor is labeled as either NMOS or PMOS. However, the method is not limited to this. In an alternative example, with suitable circuit connections known to those skilled in the art, a transistor labeled NMOS may instead be a PMOS transistor, and a transistor labeled PMOS may instead be an NMOS transistor.

The purpose of current mirror circuit 408(1) is to match output current 414(1) to input reference current 410(1) (e.g., substantially equal). Accordingly, current mirror circuit 408(1) is configured to compare output current 414(1) with input reference current 410(1) by adding another current mirror that includes NMOS transistor 430(1). The NMOS transistor 430(1) is configured to provide a feedback channel 432(1) to the input NMOS transistor 422(1) by coupling the NMOS transistor 430(1) to the NMOS transistor 422(1) gate.

Feedback channel 432(1) naturally allows input circuit 424(1) to operate as a high gain transimpedance amplifier having only one high impedance node at the gate of NMOS transistor 424(1) (eg, current 410(1), V _{gate (gate)} . The configuration of such feedback channel 432(1) allows current mirror circuit 408(1) to easily balance input reference current 410(1) with output current 414(1). For example, with feedback channel 432(1), current mirror circuit 408(1) is configured to have input reference current 410(1) with high accuracy and at low voltage (eg, reference voltage 406= _Vdd = 0.85V) The output current 414(1) matches (eg, substantially equal). With feedback channel 432(1), it does not matter whether the current 412(1) from the drain of PMOS transistor 434(1) is equivalent to input reference current 410(1). Similarly, with feedback channel 432(1), it does not matter if there is leakage current from the gate of series PMOS transistor 436(1).

In one example simulation of PHY 400, current mirror circuit 408(1) can receive an input reference current 410(1) of 100 μA (microamperes) and then replicate to produce an output current 414(1) of 100 μA. In contrast, in substantially the same case, a standard splicing assembly (not shown) can receive an input reference current of 100 μA and then produce 85 μA, for example, due to the aforementioned pushing of the transistor into the low drain voltage of the linear region. Does not match the output current. Assuming that there is no systematic deviation in the transistor, although this mismatch is deterministic, the accuracy of the current mirror circuit 408(1) is generally only based on random device mismatch (eg, due to manufacturing defects and/or tolerances). The limit does not match).

The advantage is that the solution described with reference to the fourth figure is a low-cost solution to the problems discussed above with reference to the second and third figures. For example, the configuration of the fourth figure allows the current mirror circuit to be easily balanced (for example, it is easy to match the input current with the output current without causing oscillatory behavior) and is done at low cost (eg, does not take up a lot of space) Large components such as additional operational amplifiers).

The invention has been described above with reference to specific embodiments. It will be understood by those skilled in the art, however, that various modifications and changes can be made in the present invention without departing from the scope of the invention. Accordingly, the foregoing description and drawings are to be regarded as

400‧‧‧ analog/mixed signal physical layered circuit; physical layer (PHY)

402‧‧‧Band Voltage Reference

405(1)‧‧‧ Circuit Blocks

406‧‧‧reference voltage; voltage

408(1)‧‧‧current mirror circuit

410(1)‧‧‧ input reference current; current

412(1)‧‧‧ Current

414(1)‧‧‧ Output current; current

422(1)‧‧‧ NMOS transistor

424(1)‧‧‧ input circuit

424(1)‧‧‧ NMOS transistor

426(1)‧‧‧ PMOS transistor

430(1)‧‧‧ NMOS transistor

432(1)‧‧‧ feedback channel

434(1)‧‧‧ PMOS transistor

436(1)‧‧‧ series PMOS transistor; PMOS transistor

444(1)‧‧‧ Output Circuit

Claims (9)

A current mirror circuit includes: an input circuit including a first transistor configured to receive an input reference current, and a second transistor configured to receive an output current, wherein the gate of the second transistor a pole is connected to a drain of the first transistor and a third transistor, wherein a drain of the third transistor is connected to a gate of the third transistor, and wherein the third transistor The gate is connected to a gate of the first transistor to form a feedback channel from the third transistor to the first transistor, wherein the feedback channel is used for the input reference current and the output The current is relatively and substantially matched; and an output circuit coupled to the input circuit and configured to generate the output current, wherein the output circuit includes two or more serially connected transistors, wherein the first series is connected A drain of the transistor is coupled to a drain of the third transistor included in the input circuit, and one of the second series of transistors is coupled to the circuit block independently of the circuit block The components of the input circuit It is provided to the output current to the conveying assembly. The current mirror circuit of claim 1, wherein the input reference current is received at the drain of the first transistor. The current mirror circuit of claim 2, wherein each of the first transistor, the second transistor, and the third transistor comprises an n-type metal oxide semiconductor (NMOS) transistor. The current mirror circuit of claim 2, wherein one source of the first transistor, one source of the second transistor, and one source of the third transistor are coupled to a ground. The current mirror circuit of claim 2, wherein the output circuit comprises a fourth transistor having a gate and a drain coupled to the second transistor included in the input circuit. One of the bungee jumping. The current mirror circuit of claim 2, wherein the feedback channel is configured to have only one high impedance node at the gate of the third transistor. The current mirror circuit of claim 1, wherein the feedback channel configures the input circuit to match the input reference current to the output current. An integrated circuit comprising: a bandgap voltage reference; At least one circuit block coupled to the bandgap voltage reference, wherein each circuit block includes one or more circuit block components and a current mirror circuit coupled to the one or more circuit blocks An assembly, wherein each current mirror circuit comprises: an input circuit including a first transistor configured to receive an input reference current, and a second transistor configured to receive an output current, wherein the second a gate of the transistor is connected to a drain of the first transistor and a third transistor, wherein a drain of the third transistor is connected to a gate of the third transistor, and wherein the gate The gate of the third transistor is coupled to a gate of the first transistor to form a feedback channel from the third transistor to the first transistor, wherein the feedback channel is used to reference the input The current is compared to the output current and substantially matched; and an output circuit coupled to the input circuit is configured to generate the output current, and wherein the output circuit includes two or more serially connected transistors, a drain of a first series of transistors is coupled to a drain of the third transistor included in the input circuit, and one of the second series of transistors is coupled to the drain Connected to a circuit block component independent of the input circuit and disposed to deliver an output current to the component. An arithmetic device comprising: at least one integrated circuit including a bandgap voltage reference; and at least one circuit block coupled to the bandgap voltage reference, wherein each circuit block includes one or more circuit block components and a current mirror circuit coupled to the one or more circuit block assemblies, wherein each current mirror circuit includes: an input circuit including a first transistor configured to receive an input reference current And a second transistor configured to receive an output current, wherein a gate of the second transistor is coupled to a drain of the first transistor and a third transistor, wherein the third transistor a drain is connected to a gate of the third transistor, and wherein the gate of the third transistor is connected to a gate of the first transistor to form from the third transistor to the gate a feedback channel of the first transistor, wherein the feedback channel is for comparing and substantially matching the input reference current with the output current; and an output circuit coupled to the input circuit, which is Disposed generate the output current, and Wherein the output circuit comprises two or more serially connected transistors, wherein a drain of a first series connected transistor is coupled to a drain of the third transistor included in the input circuit, and One of the second series of transistors is coupled to a circuit block component independent of the input circuit and disposed to transmit an output current to the component.