CN202362694U - Improved current mirror - Google Patents
Improved current mirror Download PDFInfo
- Publication number
- CN202362694U CN202362694U CN2011204034719U CN201120403471U CN202362694U CN 202362694 U CN202362694 U CN 202362694U CN 2011204034719 U CN2011204034719 U CN 2011204034719U CN 201120403471 U CN201120403471 U CN 201120403471U CN 202362694 U CN202362694 U CN 202362694U
- Authority
- CN
- China
- Prior art keywords
- transistor
- drain
- source
- current mirror
- current source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Amplifiers (AREA)
Abstract
An improved current mirror comprises a reference branch, an output branch, a feedback branch, a fifth transistor and a third auxiliary current source. The reference branch consists of a first current source and a first transistor, the output branch consists of a load and a second transistor, a grid electrode of the first transistor and a grid electrode of the second transistor are connected with each other and are controlled by the first current source, drain electrode voltage of the first transistor tracks drain electrode voltage of the second transistor by the aid of the feedback branch, the feedback branch consists of a third transistor and a fourth transistor, the third transistor is serially connected between the first current source and the first transistor, the fourth transistor is serially connected between a second auxiliary current source and the second transistor, and a grid electrode of the third transistor and a grid electrode of the fourth transistor are connected with each other and are controlled by the second auxiliary current source. The lower limit of drain-source voltage of the first transistor of the improved current mirror and the lower limit of drain-source voltage of the second transistor can be lower than the lower limit of drain-source voltage of a transistor T1 and the lower limit of drain-source voltage of a transistor T2 of a current mirror (as shown in a figure 1) in the prior art.
Description
Technical field:
The utility model relates to a kind of current mirror, particularly relates to a kind of improved current mirror.
Background technology:
U.S. Pat 5252910 has proposed a kind of current mirror, and is as shown in Figure 1.The purpose of this invention is can be greater than supply voltage V in order to obtain one
SSLow-voltage V
DSSThe current mirror of following work so is to be operated in the V with low potential difference in order to be applicable to
DDAnd V
SSBetween circuit, said circuit does not allow current mirror to have very big WV.Another purpose of this invention is that in little conduction resistance of trace branches generation of current mirror, this also is to make current mirror to be operated near V
SSA voltage under condition.
This invention realizes that these purposes are through following means: a common current mirror; Has only a transistor in its trace branches; But this current mirror has comprised Voltage Feedback, the special trace branches that is derived from current mirror of this feedback, said trace branches and load parallel connection but not cascade.
More accurately; This invention is about being operated in the current mirror under the low-voltage, and this current mirror comprises in reference arm a current source 1 and the first transistor T1 being arranged; Have a load 2 and a transistor seconds T2 at the output branch road; These two transistorized grids interconnect, and are controlled by said current source 1, in this current mirror, also comprise Voltage Feedback; For this current mirror can be worked under the high power supply voltage situation close with low supply voltage, the drain voltage of the first transistor T1 need be followed the trail of the drain voltage of transistor seconds T2.
But; In real work; The technical matters that current mirror in Fig. 1 exists is: in order to guarantee the strict proportionate relationship between current mirror output current and the reference current, current mirror requires the drain-source voltage of its first transistor T1 and the drain-source voltage of transistor seconds T2 to have than higher value.
The utility model content:
For the current mirror (being the current mirror among Fig. 1) that solves the US5252910 proposition requires the drain-source voltage of its first transistor T1 and the drain-source voltage of transistor seconds T2 to have the technical matters than higher value, the utility model proposes a kind of improved current mirror.
The technical scheme of the utility model is following:
A kind of improved current mirror comprises:
A reference arm, it comprises first current source and the first transistor;
An output branch road, it comprises a load and transistor seconds;
The grid of the first transistor and the grid of transistor seconds interconnect and are controlled by first current source;
A drain voltage that makes the first transistor is followed the tracks of the feedback branch of the drain voltage of transistor seconds, and said feedback branch comprises: the 3rd transistor, and it is connected between first current source and the first transistor; The 4th transistor, it is connected between second auxiliary current source and the transistor seconds;
The 3rd transistorized grid and the 4th transistorized grid interconnect and are controlled by second auxiliary current source;
It is characterized in that,
Said the 3rd transistor series is meant that between first current source and the first transistor the 3rd transistorized source electrode is connected in the drain electrode of the first transistor, and the 3rd transistor drain is connected in first current source; Said the 4th transistor series is meant that between second auxiliary current source and transistor seconds the 4th transistorized source electrode is connected in the drain electrode of transistor seconds, and the 4th transistor drain is connected in second auxiliary current source.
Also comprise the 5th transistor and the 3rd auxiliary current source; The 5th transistorized grid is connected in the 4th transistorized source electrode; The 5th transistorized source electrode is connected in the 3rd transistor drain; The 5th transistor drain links to each other with the grid of the first transistor and the grid of transistor seconds, and an end of the 3rd auxiliary current source links to each other with the 5th transistor drain.
Also comprise the 4th auxiliary current source, the one of which end is connected in the drain electrode of the first transistor.
Also comprise the auxiliary current mirror of realizing the 3rd auxiliary current source, the output current of said the 3rd auxiliary current source is the output current that the output branch road of said auxiliary current mirror provides.
Said auxiliary current mirror comprises:
Auxiliary current mirror reference arm, it comprises the 5th auxiliary current source and the 6th transistor;
Auxiliary current mirror output branch road, it comprises the 7th transistor;
The said the 6th transistorized grid and the 7th transistorized grid interconnect, and are controlled by the 5th auxiliary current source;
Said the 7th transistor drain is connected in the 5th transistor drain.
Said the first transistor, transistor seconds, the 3rd transistor, the 4th transistor are the N-channel MOS field effect transistor, and the 5th transistor is a P channel MOS field effect transistor.
Said the first transistor, transistor seconds, the 3rd transistor, the 4th transistor, the 6th transistor, the 7th transistor are the N-channel MOS field effect transistor, and the 5th transistor is a P channel MOS field effect transistor.
The beneficial effect of the utility model is:
1, compares and prior art (current mirror shown in Figure 1); The utility model current mirror has increased said the 5th transistor; It constitutes a collapsible operational amplifier (also being differential amplifier simultaneously) with said the 3rd transistor, the 4th transistor and the 3rd auxiliary current source; The differential amplifier that only constitutes in the current mirror shown in Figure 1 by transistor T 5 and transistor T 6; Said collapsible operational amplifier has improved Amplifier Gain; Thereby under the requirement that guarantees proportionate relationship strict between output current and the reference current, the lower limit of the drain-source voltage of the utility model current mirror the first transistor and the drain-source voltage of transistor seconds can be lower than the lower limit of the drain-source voltage of the transistor T 1 of current mirror among Fig. 1, T2.
2, said the 3rd auxiliary current source provides electric current to make the 5th transistor work in the amplification region.
3, this current mirroring circuit also comprises the 4th auxiliary current source, and the one of which end is connected between the first transistor and the 3rd transistor of said reference arm, and its effect provides the current mirror reference current.
Description of drawings:
The current mirroring circuit synoptic diagram that Fig. 1---prior art (U.S. Pat 5252910) proposes
The 1-current source, the 2-load
A kind of improved current mirroring circuit synoptic diagram that Fig. 2---the utility model proposes
Embodiment:
For the purpose, technical scheme and the advantage that make the utility model is clearer,, the utility model is further elaborated below in conjunction with accompanying drawing and embodiment.Specific embodiment described herein is only in order to explaining the utility model, and is not used in qualification the utility model.
As shown in Figure 2, a kind of improved current mirror comprises:
A reference arm; It comprises first current source and the first transistor M1; During concrete the realization, can comprise the 8th transistor M8 that is used to regulate and control said first current source current, the source electrode of said the 8th transistor M8 is connected with the first supply voltage termination VIN; The drain electrode of the 8th transistor M8 is connected with the drain electrode of the 3rd transistor M3; The grid of the 8th transistor M8 is connected in control supply voltage termination Vb, and the source electrode of the 3rd transistor M3 is connected in the drain electrode of the first transistor M1, and the source electrode of said the first transistor M1 is connected in second source voltage termination VSS; The first supply voltage termination VIN, the 8th transistor M8, the 3rd transistor M3, the first transistor M1, second source voltage termination VSS place branch road form the first current source path, and the first supply voltage VIN is higher than second source voltage VSS;
An output branch road, it comprises a load (in Fig. 2, being light emitting diode) and transistor seconds M2, and the drain electrode of said transistor seconds M2 connects said load, and the source electrode of transistor seconds M2 is connected in second source voltage termination VSS;
The grid of the grid of the first transistor M1 and transistor seconds M2 interconnects and is controlled by first current source; During concrete the realization; The grid of the grid of said the first transistor M1 and transistor seconds M2 all is connected in the drain electrode of the 5th transistor M5, and the source electrode of the 5th transistor M5 is connected in the drain electrode of the 8th transistor M8;
A drain voltage that makes the first transistor M1 is followed the tracks of the feedback branch of the drain voltage of transistor seconds M2; Said feedback branch comprises: the 3rd transistor M3; It is connected between first current source and the first transistor M1; The drain electrode of the 3rd transistor M3 is connected in the drain electrode of the 8th transistor M8, and the source electrode of the 3rd transistor M3 is connected in the drain electrode of the first transistor M1; The 4th transistor M4; It is connected between second auxiliary current source and the transistor seconds M2; During concrete the realization; Can comprise the 9th transistor M9 that is used to regulate and control the said second auxiliary current source electric current; The grid of the 9th transistor M9 is connected in said control supply voltage termination Vb, and the source electrode of the 9th transistor M9 is connected in the first power source voltage termination VIN, and the drain electrode of the 9th transistor M9 is connected in the drain electrode of the 4th transistor M4; The source electrode of the 4th transistor M4 is connected in the drain electrode of transistor seconds M2, and the first supply voltage termination VIN, the 9th transistor M9, the 4th transistor M4, transistor seconds M2, second source voltage termination VSS place branch road form the second auxiliary current source path;
The grid of the grid of the 3rd transistor M3 and the 4th transistor M4 interconnects and is controlled by second auxiliary current source, and when specifically realizing, the grid of the grid of said the 3rd transistor M3 and the 4th transistor M4 all is connected in the drain electrode of the 9th transistor M9.
It is characterized in that; Also comprise the 5th transistor M5 and the 3rd auxiliary current source; The grid of the 5th transistor M5 is connected in the drain electrode of the transistor seconds M2 of output branch road; The source electrode of the 5th transistor M5 is connected in the drain electrode of the 3rd transistor M3 of reference arm, and the drain electrode of the 5th transistor M5 links to each other with the grid of the first transistor M1 and the grid of transistor seconds M2, and an end of the 3rd auxiliary current source links to each other with the drain electrode of the 5th transistor M5.
Preferably, also comprise the 4th auxiliary current source, the one of which end is connected between the first transistor M1 and the 3rd transistor M3 of said reference arm.During concrete the realization; Comprise the tenth transistor M10 that is used to regulate and control said the 4th auxiliary current source electric current; The grid of the tenth transistor M10 is connected in said control supply voltage termination Vb; The source electrode of the tenth transistor M10 is connected in the first supply voltage termination VIN; The drain electrode of the tenth transistor M10 is connected in the drain electrode of the first transistor M1, and the source electrode of the first transistor M1 is connected in second source voltage termination VSS, and the first supply voltage termination VIN, the tenth transistor M10, the first transistor M1, second source voltage termination VSS place branch road form the 4th auxiliary current source path.
Preferably, also comprise the auxiliary current mirror of realizing the 3rd auxiliary current source, the output current of said the 3rd auxiliary current source is the output current that the output branch road of said auxiliary current mirror provides.
Said auxiliary current mirror comprises:
Auxiliary current mirror reference arm, it comprises the 5th auxiliary current source and the 6th transistor M6;
Auxiliary current mirror output branch road, it comprises the 7th transistor M7;
The grid of the grid of said the 6th transistor M6 and the 7th transistor M7 interconnects, and is controlled by the 5th auxiliary current source;
The drain electrode of said the 7th transistor M7 is connected in the drain electrode of the 5th transistor M5;
During concrete the realization; Comprise the 11 transistor M11 that is used to regulate and control said the 5th auxiliary current source electric current; The grid of said the 11 transistor M11 is connected in said control supply voltage termination Vb; The source electrode of said the 11 transistor M11 is connected in the first supply voltage termination VIN; The drain electrode of the 11 transistor M11 is connected in the drain electrode of the 6th transistor M6; The source electrode of the 6th transistor M6 is connected in second source voltage termination VSS, and the branch road at the first supply voltage joint VIN, the 11 transistor M11, the 6th transistor M6, second source voltage termination VSS place forms the 5th auxiliary current source path, and the drain electrode of the 7th transistor M7 is connected with the drain electrode of the 5th transistor M5; The source electrode of the 7th transistor M7 links to each other with second source voltage termination VSS, and the 11 transistor M11, the 6th transistor M6 and the 7th transistor M7 constitute the auxiliary current mirror makes the 5th transistor M5 work in the amplification region.
Said the first transistor M1, transistor seconds M2, the 3rd transistor M3, the 4th transistor M4, the 6th transistor M6, the 7th transistor M7 are the N-channel MOS field effect transistor, and the 5th transistor M5, the 8th transistor M8, the 9th transistor M9, the tenth transistor M10, the 11 transistor M11 are P channel MOS field effect transistor.
The principle of work of the utility model is:
The first transistor M1 and transistor seconds M2 constitute a pair of current mirror, and wherein the first transistor M1 is the MOS field effect transistor of decision reference current, and transistor seconds M2 is the MOS field effect transistor of decision output current.Present embodiment is used for the application scenario that a constant-current LED drives with said current mirror, and promptly the said load at said output branch road is a light emitting diode.The 3rd transistor M3; The 4th transistor M4; Differential amplifier of the common formation of the 5th transistor M5 and the 7th transistor M7, wherein, the source end of the 4th transistor M4 (the node A (Vcath) among Fig. 2) is the inverting input of said differential amplifier; The source end of the 3rd transistor M3 (Node B among Fig. 2 (Vtrack)) is the in-phase input end of differential amplifier, and the drain terminal of the 5th transistor M5 then is an output terminal.And the 6th transistor M6, the 8th transistor M8, the 9th transistor M9, the tenth transistor M10, the 11 transistor M11 all is used for the work of auxiliary current mirror.
The concrete course of work of the utility model current mirror is following: the inverting input of said differential amplifier and in-phase input end detect the error between the drain-source voltage Vcath of drain-source voltage Vtrack and transistor seconds M2 of the first transistor M1 of current mirror; After said then error is amplified through said differential amplifier; Deliver to the grid of M1 and M2 from the output terminal of said differential amplifier; The output terminal of said amplifier i.e. the drain terminal (node D) of the 5th transistor M5, and forcing the error of Vcath and Vtrack with this is zero.Like this; Just obtained the current mirror that precision is high: not only the grid voltage of the first transistor M1 of current mirror and transistor seconds M2 is in full accord; And the drain-source voltage Vcath of the drain-source voltage Vtrack of the first transistor M1 and transistor seconds M2 is also in full accord, thereby has guaranteed proportionate relationship strict between output current and the reference current.
Than prior art (current mirror shown in Fig. 1); The said differential amplifier of the utility model is that two-stage is amplified; The first order is the differential amplifier that the 3rd transistor M3 and the 4th transistor M4 form; The second level is the cathode-input amplifier that the 5th transistor M5 and the 7th transistor M7 form, and the gain of the two poles of the earth amplifier of the utility model is 60-80dB, and the current mirror among Fig. 1 only constitutes the one-level differential amplifier by transistor T 5, T6; Its gain is about 40dB, and the differential amplifier with two-stage enlarging function of visible the utility model is compared prior art and improved gain.
Because the utility model current mirror has adopted the higher differential amplifier of a kind of gain; Therefore; Under the requirement that guarantees proportionate relationship strict between current mirror output current and the reference current, the lower limit of the drain-source voltage of the utility model current mirror the first transistor M1 and transistor seconds M2 can be lower than the lower limit of the drain-source voltage of the transistor T 1 of current mirror among Fig. 1, T2.Concrete reason is:
For United States Patent (USP) propose current mirror (current mirror shown in Figure 1); The drain-source voltage of current mirror transistor T1 and T2 is low more; Accordingly, said transistor T 1 is operated in dark more linear zone with T2, and at this moment their output resistance is very little; This just feasible open-loop gain by the loop that differential amplifier and current mirror constituted jointly becomes very little; Thereby slackened adjustment capability, promptly be difficult to make the drain-source voltage of transistor T 1 and T2 to be consistent, thereby must bring the ratio between output current and the reference current to depart from predetermined design load the drain-source voltage of transistor T 1 and T2.And the gain that the current mirror that the utility model proposes has improved differential amplifier itself, thereby improved the open-loop gain of loop, therefore have stronger drain-source voltage and adjust consistent ability the first transistor M1 and transistor seconds M2.
What be worth simultaneously particularly pointing out is; General cathode-input amplifier needs a special biasing circuit to grid current potential to be provided; The utility model directly links to each other the grid of the drain electrode of the transistor seconds M2 of current mirror output terminal with cathode-input amplifier the 5th transistor M5; Be the grid potential of Vcath, so farthest simplified circuit as the 5th transistor M5.
Should be pointed out that the above embodiment can make those skilled in the art more fully understand the utility model, but limit the utility model never in any form.Therefore; Although this instructions has carried out detailed explanation with reference to accompanying drawing and embodiment to the utility model,, those skilled in the art are to be understood that; Still can make amendment or be equal to replacement the utility model; In a word, all do not break away from the technical scheme and the improvement thereof of the spirit and the scope of the utility model, and it all should be encompassed in the middle of the protection domain of the utility model patent.
Claims (6)
1. improved current mirror comprises:
A reference arm, it comprises first current source and the first transistor;
An output branch road, it comprises a load and transistor seconds;
The grid of the first transistor and the grid of transistor seconds interconnect and are controlled by first current source;
A drain voltage that makes the first transistor is followed the tracks of the feedback branch of the drain voltage of transistor seconds, and said feedback branch comprises: the 3rd transistor, and it is connected between first current source and the first transistor; The 4th transistor, it is connected between second auxiliary current source and the transistor seconds;
The 3rd transistorized grid and the 4th transistorized grid interconnect and are controlled by second auxiliary current source;
It is characterized in that,
Said the 3rd transistor series is meant that between first current source and the first transistor the 3rd transistorized source electrode is connected in the drain electrode of the first transistor, and the 3rd transistor drain is connected in first current source; Said the 4th transistor series is meant that between second auxiliary current source and transistor seconds the 4th transistorized source electrode is connected in the drain electrode of transistor seconds, and the 4th transistor drain is connected in second auxiliary current source,
Also comprise the 5th transistor and the 3rd auxiliary current source; The 5th transistorized grid is connected in the 4th transistorized source electrode; The 5th transistorized source electrode is connected in the 3rd transistor drain; The 5th transistor drain links to each other with the grid of the first transistor and the grid of transistor seconds, and an end of the 3rd auxiliary current source links to each other with the 5th transistor drain.
2. a kind of improved current mirror according to claim 1 is characterized in that also comprise the 4th auxiliary current source, the one of which end is connected in the drain electrode of the first transistor.
3. a kind of improved current mirror according to claim 1 is characterized in that, also comprises the auxiliary current mirror of realizing the 3rd auxiliary current source, and the output current of said the 3rd auxiliary current source is the output current that the output branch road of said auxiliary current mirror provides.
4. a kind of improved current mirror according to claim 3 is characterized in that, said auxiliary current mirror comprises:
Auxiliary current mirror reference arm, it comprises the 5th auxiliary current source and the 6th transistor;
Auxiliary current mirror output branch road, it comprises the 7th transistor;
The said the 6th transistorized grid and the 7th transistorized grid interconnect, and are controlled by the 5th auxiliary current source;
Said the 7th transistor drain is connected in the 5th transistor drain.
5. a kind of improved current mirror according to claim 1 is characterized in that said the first transistor, transistor seconds, the 3rd transistor, the 4th transistor are the N-channel MOS field effect transistor, and the 5th transistor is a P channel MOS field effect transistor.
6. a kind of improved current mirror according to claim 4; It is characterized in that; Said the first transistor, transistor seconds, the 3rd transistor, the 4th transistor, the 6th transistor, the 7th transistor are the N-channel MOS field effect transistor, and the 5th transistor is a P channel MOS field effect transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011204034719U CN202362694U (en) | 2011-10-21 | 2011-10-21 | Improved current mirror |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011204034719U CN202362694U (en) | 2011-10-21 | 2011-10-21 | Improved current mirror |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202362694U true CN202362694U (en) | 2012-08-01 |
Family
ID=46573866
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011204034719U Expired - Fee Related CN202362694U (en) | 2011-10-21 | 2011-10-21 | Improved current mirror |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202362694U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103984383A (en) * | 2013-02-11 | 2014-08-13 | 辉达公司 | Low-voltage, high-accuracy current mirror circuit |
| WO2018133374A1 (en) * | 2017-01-17 | 2018-07-26 | 京东方科技集团股份有限公司 | Current mirror circuit and driving method therefor |
| CN109696578A (en) * | 2019-01-22 | 2019-04-30 | 东莞市长工微电子有限公司 | A kind of current detection circuit and method |
-
2011
- 2011-10-21 CN CN2011204034719U patent/CN202362694U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103984383A (en) * | 2013-02-11 | 2014-08-13 | 辉达公司 | Low-voltage, high-accuracy current mirror circuit |
| WO2018133374A1 (en) * | 2017-01-17 | 2018-07-26 | 京东方科技集团股份有限公司 | Current mirror circuit and driving method therefor |
| US10496121B2 (en) | 2017-01-17 | 2019-12-03 | Boe Technology Group Co., Ltd. | Current mirror circuit and driving method of the current mirror circuit |
| CN109696578A (en) * | 2019-01-22 | 2019-04-30 | 东莞市长工微电子有限公司 | A kind of current detection circuit and method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100536332C (en) | Unilateral hysteresis comparator | |
| CN102385410B (en) | Slew-rate enhancement circuit and LDO integrating same | |
| US9817415B2 (en) | Wide voltage range low drop-out regulators | |
| CN103092239B (en) | Constant-current circuit and reference voltage circuit | |
| US8829975B2 (en) | Methods and circuits for operating a parallel DMOS switch | |
| CN202362694U (en) | Improved current mirror | |
| CN107786190B (en) | Low-on-resistance flatness analog switch with leakage current elimination technology | |
| CN110729995B (en) | Level conversion circuit and level conversion method | |
| CN105940609A (en) | Buffer circuits and methods | |
| US20180278076A1 (en) | Switching charging circuit | |
| CN102843828B (en) | Pulse width modulation (PMW) modulator circuit | |
| CN103874296A (en) | LED constant-current driving circuit of multi-path self-adaptive loads | |
| CN104793678A (en) | Voltage regulator | |
| JP5481281B2 (en) | Current driving circuit and light emitting device using the same | |
| CN104090626B (en) | A kind of high precision multi-output voltages impact damper | |
| CN103529892A (en) | Class-AB output level biasing circuit | |
| CN105577165B (en) | A kind of I/O interface level shifting circuit and I/O interface level conversion method | |
| US20130181776A1 (en) | Rail-to-rail comparator | |
| CN113157039A (en) | Low dropout regulator with fast transient response | |
| CN102395234B (en) | Low voltage CMOS constant current source circuit with high matching degree | |
| CN204270191U (en) | High-voltage cascade current mirroring circuit | |
| CN201018463Y (en) | Single side lagging comparators | |
| KR20170006910A (en) | Level shifter | |
| CN101404483B (en) | Differential amplifier | |
| CN201509190U (en) | Push-pull output level driving circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Free format text: FORMER OWNER: HAO YUEGUO Effective date: 20121210 Owner name: GUANGDONG XIDIWEI ELECTRONIC CO., LTD. Free format text: FORMER OWNER: TANG YA Effective date: 20121210 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 510663 GUANGZHOU, GUANGDONG PROVINCE TO: 528222 FOSHAN, GUANGDONG PROVINCE |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20121210 Address after: 528222, Nanhai District, Guangdong City, Nanhai District, Nanhai Town, Nanhai Software Technology Park (R & D building A) five floor, two, Foshan Patentee after: GUANGDONG HALO MICROELECTRONICS Co.,Ltd. Address before: 510663 Guangdong city of Guangzhou province Zhongshan five road No. 219 CTS commercial city 12 floor Patentee before: Tang Ya Patentee before: Hao Yueguo |
|
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120801 Termination date: 20151021 |
|
| EXPY | Termination of patent right or utility model |