TWI608276B - Display device - Google Patents

Description

Display device

The present invention relates to a display device, and more particularly to a display device having a stable common voltage.

A conventional display device, such as a liquid crystal display device, includes a display panel having a plurality of columns of pixels. When the liquid crystal display device is to be displayed, the pixels of the display data are charged column by column, so that the liquid crystal display device can be Display according to the displayed data. However, in recent years, due to the improved resolution of the liquid crystal display device, the liquid crystal display device needs to drive more columns of pixels during the display of one frame, and in order to effectively reduce the number of signal traces and the occupied area, some display devices are available. Will be used with the multiplexer to transfer the display data. When the multiplexer is in the off state, the pixel will be in a floating state after receiving the display signal, so that the stability of the common voltage is deteriorated and is easily interfered by external signals.

In order to solve the above drawbacks, the present invention provides an embodiment of a display device including a data driver, a multiplexer, a gate driver, a plurality of pixel units, and a common capacitor. The data driver is configured to output a plurality of input display data signals, and the multiplexer is electrically coupled to the data driver. The multiplexer is configured to receive the input and display data signals, and output and output a plurality of display data signals according to the input display signals. The gate driver is used to receive DC and AC voltages and output multiple gate drive signals. Each pixel unit is electrically coupled to the gate driver and the multiplexer, and each pixel unit is configured to receive a corresponding display data signal, a gate driving signal, and a first common voltage. The common capacitor has a first end and a second end, the first end of the common capacitor receives the first common voltage, and the second end of the common capacitor receives the DC voltage.

The present invention further provides a common capacitor embodiment. The common capacitor includes a gate dielectric layer, an extension electrode, a first dielectric layer, a common electrode, and a common voltage conductive layer. The gate dielectric layer has a first surface and a second surface opposite the first surface. The extension electrode is disposed on one side of the second surface of the gate dielectric layer, and the extension electrode is configured to receive the DC voltage. The first dielectric layer is disposed on one side of the gate dielectric layer, the first dielectric layer has a first surface and a second surface opposite to the first surface, and the second surface of the first dielectric layer is the first The first surface of the electrical layer is adjacent to the first surface of the gate dielectric layer. The common electrode is disposed on the second surface of the first dielectric layer for receiving the first common voltage described above. The common voltage conductive layer is disposed on one side of the first surface of the first dielectric layer, and the common voltage conductive layer extends in a first direction. The vertical projections of the extension electrode, the common electrode, and the common voltage conductive layer on a substrate overlap each other.

The present invention proposes another embodiment of a display device including a data driver, a multiplexer, a gate driver, a plurality of pixel units, and a common capacitor. The data driver is configured to output a plurality of input display data signals, and the multiplexer is electrically coupled to the data driver. The multiplexer is configured to receive the plurality of input display data signals and output a plurality of display data signals. The gate driver is used to output a plurality of gate drive signals. Each pixel unit is electrically coupled to the gate driver and the multiplexer, and each pixel unit is configured to receive a corresponding display data signal, a gate driving signal, and a first common voltage. The common capacitor has a first end and a second end, the first end of the common capacitor receives the first common voltage, and the second end of the common capacitor receives the second common voltage, wherein the first common voltage and the second common voltage have the same voltage value.

In a preferred embodiment, the display device embodiment further includes a gate dielectric layer and a first dielectric layer, the gate dielectric layer having a first surface and a second surface opposite to the first surface, a dielectric layer is disposed on one side of the gate dielectric layer, the first dielectric layer has a first surface and a second surface opposite to the first surface, and the second surface of the first dielectric layer is the first The first surface of the electrical layer is adjacent to the first surface of the gate dielectric layer. The invention further provides a common capacitor embodiment, the common capacitor comprising a first common voltage conductive layer, a second dielectric layer and a second common voltage conductive layer. The first common voltage conductive layer is disposed on one side of the first surface of the first dielectric layer, the first common voltage conductive layer extends in the first direction, and the first common voltage layer has the first common voltage described above. The second dielectric layer is disposed on one side of the first common voltage layer, the second dielectric layer has a first surface and a second surface opposite to the first surface, and the second surface of the second dielectric layer is second The first surface of the dielectric layer is adjacent to one side of the first common voltage layer. The second common voltage conductive layer is disposed on one side of the first surface of the second dielectric layer, the second common voltage conductive layer extends in the first direction, and the second common voltage conductive layer has the second common voltage. The vertical projections of the first common voltage conductive layer and the second common voltage conductive layer on a substrate overlap each other.

In a preferred embodiment, the display device embodiment further includes a power generating unit, a first operational amplifier, and a second operational amplifier. The power generating unit is configured to output a first voltage, the first operational amplifier is configured to receive the first voltage and output the first common voltage, and the second operational amplifier is configured to receive the first voltage and output the second common voltage.

As described above, since the display device of the present invention has a common capacitance, it is possible to stabilize the common voltage when the multiplexer is turned off, and to effectively reduce the occurrence of display errors. In addition, the common capacitance of the present invention can be realized with a minimum of variations in the existing circuit architecture, and is more apparently commercially useful.

The above and other objects, features, and advantages of the present invention will become more apparent from the description of the appended claims.

Please refer to FIG. 1 . FIG. 1 is an embodiment of a display device 100 of the present invention. The display device 100 includes a data driver 10 , a multiplexer 20 , a gate driver 30 , and a plurality of pixel units 40 , and a plurality of pixel units 40 . It is disposed on the display panel 50. The display device 100 is, for example, a low-temperature polysilicon liquid crystal display device, and the multiplexer 20, the gate driver 30, and the common capacitor C _COM may be disposed on the display panel 50 except for the plurality of pixel units 40, but not limited thereto. . 10 and the data driver 20 is electrically coupled to the multiplexer, the data output driver 10 is configured to display a plurality of input data signals S _I to the multiplexer 20. The multiplexer 20 is electrically coupled to each of the pixel units 40 through the data line DL. The multiplexer 20 is configured to output a plurality of display data signals S _O according to the input display data signal S _I , and the multiplexer 20 displays the data. The signal S _{O is} transmitted to the corresponding data line DL. The gate driver 30 is electrically coupled to each of the pixel units 40 through the gate line G _L. In the embodiment, the display device 100 includes a gate driver 30a and a gate driver 30b. The gate driver 30 includes a plurality of shift registers SR, for example, the gate driver 30a includes a plurality of shift registers SR ₁ , SR ₃ ... SR _N , and the gate driver 30b includes a plurality of shift registers SR ₂ , SR ₄ ... SR _M , N and M are positive integers greater than zero, but are not limited thereto. The shift register SR of the gate driver 30 is configured to receive the DC voltage V _DC and the clock signal CLK to output a plurality of gate drive signals G, such as G ₁ , G ₂ , G ₃ , G ₄ as shown in FIG. ₁ . ...G _N , G _M , wherein the DC voltage V _{DC is,} for example, a logic low voltage or a logic high voltage, but is not limited thereto. Each of the pixel units 40 receives the corresponding display data signal S _O through the electrically coupled data line DL and receives the corresponding gate driving signal G through the electrically coupled gate line G _L , in this embodiment. Each of the pixel units 40 receives the first common voltage V _COM1 , so each pixel unit 40 can display the corresponding display data according to the first common voltage V _COM1 and the voltage value corresponding to the display data signal S _O . The display panel 50 can define the display area 60 and the peripheral area 70. The pixel unit 40 can be disposed in the display area 60. The multiplexer 20, the gate driver 30, and the common capacitor C _COM can be disposed in the peripheral area 70, but This is limited to this. The common capacitance C _{COM of} this embodiment will be further described below in conjunction with the drawings.

Please refer to FIG. 2A. FIG. 2A is a schematic view showing a cross-sectional embodiment of the section line AA of FIG. In this embodiment, the display device 100 includes the substrate 110, the gate dielectric layer 120, the first dielectric layer 130, and the common voltage conductive layer 140 as an example, but is not limited thereto. The gate dielectric layer 120 is disposed on one side of the substrate 110 , and the gate dielectric layer 120 has a first surface 121 and a second surface 122 opposite to the first surface 121 . An extension electrode layer 123 is disposed on the substrate 110. The gate dielectric layer 120 is disposed on the extension electrode 123. The extension electrode 123 is disposed on a side of the second surface 122 of the gate dielectric layer 120. The extension electrode 123 is configured to receive the above. The DC voltage V _DC . The first dielectric layer 130 is disposed on one side of the gate dielectric layer 120. The first dielectric layer 130 has a first surface 131 and a second surface 132 opposite to the first surface 131. The second surface 132 is adjacent to the first surface 131 of the first dielectric layer 130 adjacent to the first surface 121 of the gate dielectric layer 120. The first dielectric layer 130 is disposed on the common electrode 133 and the shift register SR, and the common electrode 133 is disposed on the second surface 132 of the first dielectric layer 130, and the common electrode 133 is connected to the common voltage conductive layer 140. The first common voltage V _COM1 described above is received by the common voltage conducting layer 140. The shift register SR further includes a clock signal electrode 134, a DC voltage electrode 135, and a logic circuit block 136 disposed on the second surface 132 of the first dielectric layer 130. The clock signal electrode 134 is configured to receive the time. The pulse signal CLK, the DC voltage electrode 135 is configured to receive the DC voltage V _DC and the DC voltage electrode 135 and is connected to the extension electrode 123 to transmit the DC voltage V _DC to the extension electrode 123. The common voltage conductive layer 140 is disposed on one side of the first surface 131 of the first dielectric layer 130, and the common voltage conductive layer 140 extends in a first direction. The common capacitor C _{COM is} formed on the gate dielectric layer 120 between the common electrode 133 and the extension electrode 123 , and the extension electrode 123 , the common electrode 133 , and the common voltage conductive layer 140 connected to the common electrode 133 are on the substrate 110 . The vertical projections are overlapped, and the substrate 110, the gate dielectric layer 120, the first dielectric layer 130, and the common voltage conductive layer 140 are sequentially arranged in the second direction, and the first direction and the second direction are perpendicular to each other.

Please refer to FIG. 2B. FIG. 2B is a schematic diagram of a circuit embodiment of the pixel unit 40 according to FIG. 2A. In this embodiment, the electrical coupling relationship between the pixel unit 40 and the common capacitor C _COM can be illustrated in FIG. 2B. . The pixel unit 40 includes a transistor T1, a liquid crystal capacitor C _LC and a storage capacitor C _ST . The transistor T1 includes a first end, a control end and a second end. The first end of the transistor T1 is used for one of the data lines DL. Electrically coupled to receive the display data signal S _O through the data line DL. The control terminal of the transistor T1 is electrically coupled to one of the gate lines G _L and receives the gate through the gate line G _L . gate drive signals G, transistor T1 and a second terminal of the liquid crystal capacitor C _LC and a storage capacitor one end electrically coupled to C _ST, the liquid crystal capacitor C _LC and the other terminal of the storage capacitor C _ST is configured to receive a first common voltage of the above-described V _COM1 . The transistor T1 is configured to determine whether to receive the display data signal S _O and transmit the display data signal S _O to the liquid crystal capacitor C _LC and the storage capacitor C _ST according to the gate driving signal G. One end of the common capacitor C _COM is electrically coupled to the liquid crystal capacitor C _LC and the other end of the storage capacitor C _ST and receives a first common voltage V _COM1 , and the other end of the common capacitor C _COM is used to receive the DC voltage V _DC described above.

In the embodiment illustrated in FIG. 1 , FIG. 2A and FIG. 2B , the common capacitor C _{COM is} disposed in the peripheral region 70 and is generated by the DC voltage V _{DC of the} shift register circuit SR and the first common voltage V _COM1 . Capacitor C _COM , so the common capacitor C _COM can receive the required DC voltage V _DC with a minimum of traces, reducing the load effect caused by the trace, and between the DC voltage V _{DC of the} common capacitor C _COM and the first common voltage V _COM1 The differential pressure does not affect the display effect of the display area 60. In addition, the common capacitor C _COM can simultaneously regulate the DC voltage V _DC , which further increases the benefits of the present invention.

Referring to FIG. 3A, FIG. 3A is a structural embodiment of the pixel unit 40 of the present invention. In this embodiment, each pixel unit 40 receives a second common voltage V _{COM2 in} addition to the first common voltage V _COM1 . In the embodiment, the substrate 41, the first common electrode 42, the dielectric layer 43, the second common electrode 44, the pixel electrode 45, the liquid crystal molecular layer 46, the protective layer 47, and the color filter 48 may be used for each pixel unit 40. The substrate 49 is described as an example, but is not limited thereto. The first common electrode 42 is disposed between the substrate 41 and the dielectric layer 43 , and the second common electrode 44 and the pixel electrode 45 are disposed between the liquid crystal molecular layer 46 and the dielectric layer 43 , and the second common electrode 44 and the pixel electrode 45 is disposed on one side of the dielectric layer 43 adjacent to the liquid crystal molecule layer 46, the side of the pixel electrode 45 is adjacent to the second common electrode 44, and the other side of the pixel electrode 45 is adjacent to the other pixel electrode 45. The protective layer 47 is disposed between the liquid crystal layer 46 and the color filter 48, and the color filter 48 is disposed between the protective layer 47 and the substrate 49. The common capacitor C _{COM is} formed on the dielectric layer 43 between the first common electrode 42 and the second common electrode 44.

Referring to FIG. 3B, FIG. 3B is a schematic diagram of a structural embodiment of the common capacitor C _COM illustrated in FIG. 3A. In this embodiment, the display device 100 includes a substrate 110, a gate dielectric layer 120, a first dielectric layer 130, a first common voltage conductive layer 140, a second dielectric layer 150, and a second common voltage conductive layer 160. For illustrative purposes, but not limited to this. The gate dielectric layer 120 is disposed on one side of the substrate 110. The gate dielectric layer 120 has a first surface 121 and a second surface 122 opposite to the first surface 121. The second surface 122 is adjacent to the first surface 121. Substrate 110. The first dielectric layer 130 is disposed on one side of the gate dielectric layer 120. The first dielectric layer 130 has a first surface 131 and a second surface 132 opposite to the first surface 131. The second surface 132 is adjacent to the first surface 131 of the first dielectric layer 130 adjacent to the first surface 121 of the gate dielectric layer 120. The first dielectric layer 130 is disposed on the first common electrode 137 (which may correspond to the first common electrode 42 of FIG. 3A) and the second common electrode 138 (which may correspond to the first common electrode 43 of FIG. 3A). For example, the first dielectric layer 130 at least partially covers the first common electrode 137 and the second common electrode 138 , and the first common electrode 137 and the second common electrode 138 are disposed on the second surface 132 of the first dielectric layer 130 . The first common voltage conductive layer 140 is disposed on one side of the first surface 131 of the first dielectric layer 130, the first common voltage conductive layer 140 extends in the first direction, and the first common voltage conductive layer 140 and the first common electrode The 137 is connected and transmits the first common voltage V _COM1 to the first common electrode 137. The second dielectric layer 150 has a first surface 151 and a second surface 152 opposite to the first surface 151 . The second surface 152 of the second dielectric layer 150 is adjacent to the first common voltage conductive layer 140 than the first surface 151 . The second common voltage conductive layer 160 is disposed on one side of the first surface 151 of the second dielectric layer 150, and the second common voltage conductive layer 160 extends in the first direction, the second common voltage conductive layer 160 and the second The common electrode 138 is connected to transmit the second common voltage V _COM2 to the second common electrode 138. In this embodiment, the first common voltage V _COM1 and the second common voltage V _COM2 have the same voltage value. The common capacitor C _{COM is} formed by the first common voltage conductive layer 140, the second common voltage conductive layer 160, and the second dielectric layer 150 therebetween, and the common capacitor C _{COM of} the embodiment can be formed. In the display area 60 and the peripheral area 70, the first common voltage conductive layer 140 overlaps with the vertical projection of the first common electrode 137 on the substrate 110, and the second common voltage conductive layer 160 and the second common electrode 138 are on the substrate 110. The vertical projections are overlapped, and the substrate 110, the gate dielectric layer 120, the first dielectric layer 130, the first common voltage conductive layer 140, the second dielectric layer 150, and the second common voltage conductive layer 160 are second. The directions are sequentially arranged, and the first direction and the second direction are perpendicular to each other.

Referring to FIG. 3C, the display device 100 of the present invention further includes a power supply circuit 80 for providing the first common voltage V _COM1 and the second common voltage V _COM2 described in the embodiment of FIG. 3B, but not This is limited to this. The power supply circuit 80 includes a power generating circuit 81 and an operational amplifier 82a and an operational amplifier 82b. The power generating circuit 81 is electrically coupled to each operational amplifier 82. The power generating circuit 81 is configured to output the first voltage V _O to the electrical coupling. The operational amplifier 82, the operational amplifier 82 can accordingly output the first common voltage V _COM1 and the second common voltage V _COM2 , the first common voltage V _COM1 and the second common voltage V _COM2 and have the same voltage value.

Please refer to FIG. 3D. FIG. 3D is a schematic diagram of a circuit embodiment of the pixel unit 40 of FIG. 3A. In this embodiment, the electrical coupling relationship between the pixel unit 40 and the common capacitor C _COM can be illustrated in FIG. 3D. The pixel unit 40 includes a transistor T1, a liquid crystal capacitor C _LC and a storage capacitor C _ST . The transistor T1 includes a first end, a control end and a second end. The first end of the transistor T1 is used for one of the data lines DL. Electrically coupled to receive the display data signal S _O through the data line DL. The control terminal of the transistor T1 is electrically coupled to one of the gate lines G _L and receives the gate through the gate line GL. driving signal G, the second terminal of the liquid crystal capacitor C _LC and a storage capacitor C _ST is an end of transistor T1 is electrically coupled to the liquid crystal capacitor C _LC and the other terminal of the storage capacitor C _ST is the first for receiving the common voltage V _COM1 . The transistor T1 is configured to determine whether to receive the display data signal S _O and transmit the display data signal S _O to the liquid crystal capacitor C _LC and the storage capacitor C _ST according to the gate driving signal G. One end of the common capacitor C _COM is electrically coupled to the liquid crystal capacitor C _LC and the other end of the storage capacitor C _ST and receives the first common voltage V _COM1 , and the other end of the common capacitor C _COM is used for the second common voltage V _COM2 .

In the embodiment of FIG. 3A, FIG. 3B, FIG. 3C, and FIG. 3D, the present invention does not need to change the structure of the original pixel unit 40 and the display panel 50, that is, the first common voltage conductive layer 160 and the second common voltage conductive layer. 160 to generate a common capacitance C _COM . In addition, in this embodiment, the first common voltage V _COM1 and the second common voltage V _COM2 have the same voltage value, so the common capacitance C _COM located in the display area 60 is not common to the second common voltage V _{COM1 .} The voltage difference of the voltage V _COM2 affects the rotation angle of the liquid crystal molecules. In addition, the first common voltage V _COM1 and the second common voltage V _COM2 outputted by the operational amplifier 82 can not interfere with each other by the characteristic that the operational amplifier 82 has a large input impedance.

In summary, according to the common capacitor C _{COM of the} present invention, the common voltage can be prevented from being interfered by external signals, and the display error can be effectively reduced. In addition, the common capacitance C _{COM of the} present invention can be realized with minimal changes under the existing circuit architecture, and is more obviously commercially valuable.

100‧‧‧ display device
110, 41, 49‧‧‧ substrates
120‧‧‧ gate dielectric layer
121, 131, 151‧‧‧ first surface
122, 132, 152‧‧‧ second surface
123‧‧‧Extended electrode
130‧‧‧First dielectric layer
133‧‧‧Common electrode
134‧‧‧clock signal electrode
135‧‧‧DC voltage electrode
136‧‧‧Logical Circuit Blocks
140‧‧‧Common voltage conductive layer, first common voltage conductive layer
150‧‧‧Second dielectric layer
160‧‧‧Second common voltage conducting layer
10‧‧‧Data Drive
20‧‧‧Multiplexer
30, 30a, 30b‧‧‧ gate driver
40‧‧‧ pixel unit
42, 137‧‧‧ first common electrode
43‧‧‧Dielectric layer
44, 138‧‧‧ second common electrode
45‧‧‧pixel electrodes
46‧‧‧ liquid crystal molecular layer
47‧‧‧Protective layer
48‧‧‧Color Filters
50‧‧‧ display panel
60‧‧‧ display area
70‧‧‧The surrounding area
80‧‧‧Power supply circuit
81‧‧‧Power generation circuit
82, 82a, 82b‧‧‧Operational Amplifier
S _I ‧‧‧Input display data signal
S _O ‧‧‧Display data signal
DL‧‧‧ data line
G _L ‧‧‧ gate line
G, G ₁ , G ₂ , G ₃ , G ₄ , G _N , G _M ‧ ‧ gate drive signals
SR, SR ₁ , SR ₂ , SR ₃ , SR ₄ , SR _N , SR _M ‧‧‧ shift register
V _DC ‧‧‧ DC voltage
V _O ‧‧‧First voltage
CLK‧‧‧ clock signal
T1‧‧‧O crystal
V _COM1 ‧‧‧First common voltage
V _COM2 ‧‧‧second common voltage
C _LC ‧‧‧Liquid Crystal Capacitor
C _ST ‧‧‧ storage capacitor
C _COM ‧‧‧Common Capacitor

1 is a schematic view of an embodiment of a display device of the present invention. 2A is a schematic view of an embodiment of the section line AA of FIG. 1. 2B is a schematic view of an embodiment of a pixel unit of the present invention. 3A is a schematic view showing an embodiment of a pixel unit structure of the present invention. FIG. 3B is a schematic diagram of a structural embodiment of a common capacitor C _{COM according to} the present invention. 3C is a schematic diagram of an embodiment of a power supply circuit 80 of the present invention. 3D is a schematic view of another embodiment of a pixel unit of the present invention.

100‧‧‧ display device

120‧‧‧ gate dielectric layer

10‧‧‧Data Drive

20‧‧‧Multiplexer

30, 30a, 30b‧‧‧ gate driver

40‧‧‧ pixel unit

50‧‧‧ display panel

60‧‧‧ display area

70‧‧‧The surrounding area

S _I ‧‧‧Input display data signal

S _O ‧‧‧Display data signal

DL‧‧‧ data line

G _L ‧‧‧ gate line

G, G ₁ , G ₂ , G ₃ , G ₄ , G _N , G _M ‧ ‧ gate drive signals

SR, SR ₁ , SR ₂ , SR ₃ , SR ₄ , SR _N , SR _M ‧‧‧ shift register

CLK‧‧‧ clock signal

V _DC ‧‧‧ DC voltage

V _COM1 ‧‧‧First common voltage

C _COM ‧‧‧Common Capacitor

Claims (9)

A display device includes: a data driver for outputting a plurality of display data signals; a gate driver for receiving a continuous current and an alternating voltage and outputting a plurality of gate driving signals; a plurality of pixel units, each The pixel unit is electrically coupled to the gate driver and the data driver, and each of the pixel units is configured to receive the corresponding display data signal, the gate driving signal, and a first common voltage; and a common The capacitor has a first end and a second end. The first end of the common capacitor is configured to receive the first common voltage, and the second end of the common capacitor is configured to receive the DC voltage. The display device of claim 1, wherein the display device has a display area and a peripheral area, the pixel units are disposed in the display area, and the common capacitor is disposed in the peripheral area. The display device of claim 2, wherein the common capacitor comprises: a gate dielectric layer having a first surface and a second surface opposite to the first surface; an extension electrode disposed adjacent to One side of the second surface of the gate dielectric layer, the extension electrode is configured to receive the DC voltage; a first dielectric layer disposed on a side adjacent to the first surface of the gate dielectric layer The first dielectric layer has a first surface and a second surface opposite to the first surface, the second surface of the first dielectric layer being adjacent to the first surface of the first dielectric layer a first surface of the gate dielectric layer; a common electrode (COM Bus) disposed on the second surface of the first dielectric layer for receiving the first common voltage; and a common voltage conductive layer, a common voltage conductive layer is disposed on one side of the first surface of the first dielectric layer and connected to the common electrode, and the common voltage conductive layer extends along a first direction; wherein the extended electrode, the common electrode, and Vertical projection of the common voltage conductive layer on a substrate Overlapping each other. The display device of claim 1, further comprising a multiplexer electrically coupled to the data driver. A display device includes: a data driver for outputting a plurality of display data signals; a gate driver for outputting a plurality of gate drive signals; and a plurality of pixel units, each of the pixel units and the gate The pixel driver and the data driver are electrically coupled, each of the pixel units is configured to receive the corresponding display data signal, the gate driving signal, and a first common voltage; and a common capacitor having a first end And a second end, the first end of the common capacitor receives the first common voltage, and the second end of the common capacitor receives a second common voltage, wherein the first common voltage and the second common voltage have substantial The same voltage value. The display device of claim 5, comprising: a substrate; a gate dielectric layer disposed on one side of the substrate, having a first surface and a second surface opposite to the first surface And a first dielectric layer disposed on a side of the gate dielectric layer, the first dielectric layer having a first surface and a second surface opposite to the first surface, the first dielectric layer The second surface of the electrical layer is adjacent to the first surface of the first dielectric layer to the first surface of the gate dielectric layer; the common capacitor comprises: a first common voltage conductive layer disposed on the first surface One side of the first surface of a dielectric layer, the first common voltage conductive layer extends along a first direction, the first common voltage conductive layer has the first common voltage; and a second dielectric layer is disposed On a side of the first common voltage conductive layer, the second dielectric layer has a first surface and a second surface opposite to the first surface, the second surface of the second dielectric layer is different from the first surface The first surface of the second dielectric layer is adjacent to a side of the first common voltage conductive layer; And a second common voltage conductive layer disposed on one side of the first surface of the second dielectric layer, the second common voltage conductive layer extending along the first direction, the second common voltage conductive layer having the a second common voltage; wherein the vertical projections of the first common voltage conductive layer and the second common voltage conductive layer on the substrate overlap each other. The display device of claim 6, wherein the first dielectric layer further comprises: a first common electrode disposed on the second surface of the first dielectric layer and coupled to the first common voltage a conductive layer is connected, the first common electrode receives the first common voltage, and a second common electrode is disposed on the second surface of the first dielectric layer and connected to the second common voltage conductive layer. The second common electrode receives the second common voltage; wherein the first common voltage conductive layer and the vertical projection of the first common electrode on the substrate overlap, the second common voltage conductive layer and the second common electrode The vertical projections on the substrate are overlapping. The display device of claim 7, the display device further comprising: a power generating unit for outputting a first voltage; a first operational amplifier for receiving the first voltage and outputting the first common And a second operational amplifier for receiving the first voltage and outputting the second common voltage. The display device of claim 5, further comprising a multiplexer electrically coupled to the data driver.