TWI607314B - Chassis Device - Google Patents

Description

Chassis device

The present invention relates to a device, and more particularly to a chassis device.

A conventional chassis device includes a plurality of servers, and each server includes a processing unit, a chip set, a random access memory (RAM), and a read only memory (ROM). The processing unit electrically connects the chip set and the random access memory, and the chip set has a Serial Peripheral Interface (SPI) to electrically connect the read-only memory. The read-only memory stores a default Basic Input Output System (BIOS) version. In each server, when each server is powered on, the preset BIOS version stored in the read-only memory is mapped into the random access memory, so that the processing unit reads the random When the memory is accessed, the preset BIOS version is obtained to execute a boot process. For example, the processing unit performs hardware peripheral detection and Power On Self Test (POST) according to the preset BIOS version.

However, for the conventional chassis device, since the preset BIOS version is stored in the read-only memory of each server, when the read-only memory is damaged or when the read-only memory is updated In the process of storing the BIOS version in the process, if the update is aborted due to an inappropriate update, the server corresponding to the read-only memory cannot be powered on. In addition, since the read-only memory is installed inside the corresponding server, the maintenance and replacement of the read-only memory is quite inconvenient.

Accordingly, it is an object of the present invention to provide a chassis unit that allows at least one server to be powered up and has a storage unit that is easy to service and replace.

Therefore, the chassis device of the present invention comprises a transmission channel, a chassis manager, a transmission unit, at least one local server and at least one transmission control unit.

The chassis manager includes a first processing unit, a storage unit, and a first random access memory.

The storage unit is electrically connected to the first processing unit, and stores a plurality of basic input/output system versions respectively corresponding to a plurality of different address materials. The first random access memory is electrically connected to the first processing unit. The transmission unit electrically connects the first processing unit with a first transmission interface, and electrically connects the transmission channel with a second transmission interface.

The at least one transmission control unit electrically connects the transmission channel with the second transmission interface. The at least one local server corresponds to the at least one transmission control list Each local server includes a second random access memory and a second processing unit.

The second random access memory stores a corresponding identification code and a corresponding address data in the address data. The second processing unit is electrically connected to the second random access memory, and electrically connects the corresponding transmission control unit with the first transmission interface to receive a power-on signal.

In each local server, when each local server receives the power-on signal, the second processing unit reads the corresponding address data of the second random access memory in response to the power-on signal. And reading, by the corresponding transmission control unit, the transmission channel and the transmission unit, a memory block mapped to the first random access memory to obtain a basic corresponding one of the basic input/output system versions. Enter the output system version and perform a boot process.

The present invention has at least the following effects: the storage unit of the chassis manager stores the BIOS versions, and the local server utilizes mapping between random memories when booting, in addition to avoiding the local server. If the internal BIOS version is not updated properly and the update is aborted, it will not be able to boot, and it is more convenient to update and maintain the BIOS version.

1‧‧‧Transmission channel

2‧‧‧Chassis Manager

21‧‧‧First Processing Unit

22‧‧‧ storage unit

23‧‧‧First random access memory

24‧‧‧Communication Module

3‧‧‧Transmission unit

4‧‧‧Local Server

41‧‧‧Second random access memory

42‧‧‧Second processing unit

421‧‧‧ processor

422‧‧‧ chipsets

5‧‧‧Transmission Control Unit

60‧‧‧Communication network

6‧‧‧Remote Server

Other features and effects of the present invention will be apparent from the embodiments of the drawings, in which: 1 is a block diagram showing a first embodiment of a chassis device of the present invention; and FIG. 2 is a block diagram showing a second embodiment of a chassis device of the present invention.

Before the present invention is described in detail, it should be noted that in the following description, similar elements are denoted by the same reference numerals.

<First Embodiment>

Referring to FIG. 1, a first embodiment of a chassis device of the present invention comprises a transmission channel 1, a chassis manager 2, a transmission unit 3, two local servers 4, and two transmission control units 5. It should be noted that the transmission channel 1 supports a protocol of a Low Pin Count Bus (LPCB), and the number of the transmission control units 5 is the same as the number of the local servers 4. In other embodiments, the number of the local server 4 and the transmission control unit 5 may be three or more, and the chassis device may also include only one local server 4 and one transmission control unit 5.

More specifically, the chassis device is a server rack (Server Rack), and each local server 4 is a node of the server cabinet. The local server 4 and the chassis manager 2 are respectively disposed on three boards of the server cabinet, and are respectively inserted on a back board of the server cabinet, and the transmission channel 1 is also disposed at The back panel. It is particularly worth mentioning that the transmission unit 3 and the chassis manager 2 are disposed on the same board, and the transmission control units 5 respectively correspond to The local server 4 is disposed on the same board, but is not limited thereto, and the transmission unit 3 and the transmission control unit 5 may also be disposed on the backboard.

The chassis manager 2 includes a first processing unit 21, a storage unit 22, a first random access memory 23, and a communication module 24. In this embodiment, the chassis manager 2 is, for example, a server.

The storage unit 22 is electrically connected to the first processing unit 21, and stores a plurality of Basic Input Output System (BIOS) versions respectively corresponding to a plurality of different address materials. The first random access memory 23 is electrically connected to the first processing unit 21. The communication module 24 is adapted to connect to a remote server 6 via a communication network 60. The remote server 6 is configured to generate a power-on signal, and transmit the power-on signal to the communication module 24 via the communication network 60, and the remote server 6 can update the stored in the storage unit 22 BIOS version. In this embodiment, the storage unit 22 includes a flash drive, and the communication network 60 is an Ethernet, but is not limited thereto.

The transmission unit 3 electrically connects the first processing unit 21 with a first transmission interface, and electrically connects the transmission channel 1 with a second transmission interface. In this embodiment, each of the first transmission interface and the second transmission interface is a Low Pin Count Bus Interface (LPCBI). In other embodiments, the second transmission interface can support a protocol of a Peripheral Component Interconnect Express (PCIE), but is not limited thereto.

Each local server 4 receives the power-on signal from the remote server 6 via the communication module 24, the first processing unit 21, the transmission unit 3, the transmission channel 1, and the corresponding transmission control unit 5, And having a corresponding identification code and a corresponding address data in the address data, and including a second random access memory 41 and a second processing unit 42.

In each of the local servers 4, the second random access memory 41 stores the corresponding identification code and the corresponding address data, and the corresponding identification code is one of the second random access memory 41. The access address is used by the second processing unit 42 to obtain a corresponding BIOS version of the BIOS versions. The second processing unit 42 is electrically connected to the second random access memory 41, and electrically connects the corresponding transmission control unit 5 by using the first transmission interface. When receiving the power-on signal, the second processing unit 42 reads the corresponding identifier and the corresponding address data of the second random access memory 41 in response to the power-on signal, and generates a corresponding identifier. The code and the BIOS request of the corresponding address data, and the BIOS request is transmitted to the first processing unit 21 of the chassis manager 2 via at least the corresponding transmission control unit 5, the transmission channel 1 and the transmission unit 3. In this embodiment, the second processing unit 42 includes a processor 421 and a chip set 422. The chip set 422 is a south bridge chip set or a platform controller controller (PCH).

The transmission control units 5 correspond to the local servers 4, respectively. Each of the transmission control units 5 receives the power-on letter from the remote server 6. And transmit the power-on signal to a corresponding one of the local servers 4. For convenience of description, the local server 4 and one of the transmission control units 5 adjacent to the chassis manager 2 are respectively defined as a first local server 4 and a first transmission control unit 5, and the definition is defined. The other local server 4 and the other of the transmission control units 5 remote from the chassis manager 2 are the second local server 4 and the second transmission control unit 5, respectively. The first transmission control unit 5 electrically connects the first local server 4 with the first transmission interface and electrically connects the transmission channel 1 with the second transmission interface. The second transmission control unit 5 electrically connects the second local server 4 with the first transmission interface and electrically connects the transmission channel 1 with the second transmission interface. In this embodiment, each of the transmission control units 5 includes, for example, a Field Programmable Gate Array (FPGA) or an Application-Specific Integrated Circuit (ASIC). Way to achieve.

In detail, the first transmission control unit 5 has a first general-purpose input and output (GPIO) pin for outputting a power-on target setting signal and a second GPIO pin for outputting a power signal. . The chipset 422 of the first local server 4 has a first input pin electrically connected to the first GPIO pin to receive the boot target setting signal (BIOS BOOT STRAP), and an electrical connection to the second GPIO A pin receives the second input pin of the power button. The boot target setting signal is used to determine the second random memory read by the processor 421 when the first local server 4 is powered on. Whether the memory 41 is mapped to the first random access memory 23 or another read only memory (ROM) electrically connected to the chip set 422 by a serial peripheral interface (SPI) (not shown, that is, prior art) method). When the first transmission control unit 5 causes the power-on target setting signal and the power signal to have a low logic level (ie, the logic level is 0) according to the power-on signal, the first local server 4 borrows Booting from the LPCBI. When the first transmission control unit 5 causes the power-on target setting signal and the power signal to have a high logic level (ie, the logic level is 1) according to the power-on signal, the first local server 4 The SPI bus interface reads the BIOS version of the second random access memory 41 mapped to the read only memory (ROM) for booting. In other words, the boot target setting signal is used to determine that the booting is performed by mapping to different memory by the conventional SPI interface or the LPCBI interface of the present case, and the logic value of the power signal is changed by one of the servers. The power button is pressed to power on the local server. It should be noted that the connection and operation relationship between the second transmission control unit 5 and the chip set 422 of the second local server 4 and the first transmission control unit 5 and the first local servo The connection and operation relationship between the wafer sets 422 of the device 4 are the same, and thus will not be described herein.

The following describes how the chassis device of the present invention performs a boot process. The booting process executed by the first local server 4 and the first transmission control unit 5 is executed by the second local server 4 and the second transmission control unit 5 The booting procedure is the same, so the first local server 4 and the first transmission control unit 5 are taken as an example to illustrate the booting procedure of the chassis device of the present invention.

In operation, when the power-on signal sent by the remote server 6 is such that the first local server 4 is powered on according to the BIOS versions stored in the storage unit 22, the first transmission interface must be The LPCBI. In this case, the remote server 6 first transmits the power-on signal to the communication module 24 via the communication network 60, wherein the power-on signal includes a servo for specifying which local server 4 is to be turned on. The device designation code (the first local server 4 is exemplified below, but is not limited thereto). Then, the communication module 24 transmits the power-on signal to the first processing unit 21. After the first processing unit 21 receives the power-on signal, the first processing unit 21 transmits the power-on signal to the transmission control unit 5 via the transmission unit 3 and the transmission channel 1, and controls the server. The first transmission control unit 5 corresponding to the first local server 4 corresponding to the designated code causes the power-on target setting signal and the power signal to have a low logic level according to the power-on signal (ie, the same first and second potential GPIO pins are all low), while transmitting the first transmission power control unit 5 the signal to the first local server 4 of the second group of the wafer processing unit 42 422. When the chipset 422 receives the power-on signal, and the processor 421 of the second processing unit 42 of the first local server 4 generates the BIOS request in response to the power-on signal, the processor 421 processes the BIOS. Requesting that the first processing unit 21 of the chassis manager 2 is transferred via the chip set 422, the first transmission control unit 5, the transmission channel 1 and the transmission unit 3, and the first processing unit 21 receives the After the BIOS requests, the first processing unit 21 selects the corresponding BIOS version from the BIOS versions stored in the storage unit 22 according to the corresponding address data in the BIOS request, and according to the BIOS request. Corresponding to the identification code, the corresponding BIOS version is stored in a pair of memory blocks of the first random access memory 23 corresponding to the identification code. Then, when the chipset 422 receives the power-on signal, and the processor 421 generates the BIOS request and reads the second random access memory 41 to execute the booting process, the processor 421 correspondingly reads The memory block in the first random access memory 23 (ie, the corresponding BIOS version stored in the memory block of the first random access memory 23 is mapped to the second random The memory 41) is accessed to execute the boot process. In detail, the processor 421 performs the first random storage according to the corresponding identification code in the BIOS request via the chipset 422, the first transmission control unit 5, the transmission channel 1, and the transmission unit 3. Taking the corresponding BIOS version of the memory block in the memory 23 for reading, so that the processor 421 of the second processing unit 42 in the first local server 4 is based on the first random access The corresponding BIOS version in the memory 23 is used to execute the boot process.

It should be noted that, in other embodiments, the power-on signal sent by the remote server 6 can also control the first transmission control unit 5 to have the power-on target setting signal and the power signal have a high logic level. (ie, the potentials of the first and second GPIO pins are both high ) , so that the local server 4 maps the BIOS version stored in the read-only memory (ROM) to the SPI bus interface interface to The second random access memory 41 is turned on.

In addition, in other embodiments, the first transmission control unit 5 can simulate the memory of the Low Pin Count (LPC) by using the software, and store the corresponding required when the first local server 4 is powered on. BIOS version. Therefore, when the chipset 422 of the first local server 4 receives the power-on signal, the processor 421 of the first local server 4 generates the BIOS request in response to the power-on signal, and the BIOS is generated. Requesting the chip set 422 of the first local server 4 and the first transmission interface (ie, the LPCBI) to be transmitted to the first transmission control unit 5, so that the first transmission control unit 5 responds to the The BIOS requests to transfer the corresponding BIOS version temporarily stored to the processor group 421 of the first local server 4 via the first transmission interface and the chipset 422 of the first local server 4. The processor 421 of the first local server 4 executes the boot process according to the corresponding BIOS version from the first transfer control unit 5. It should be noted that the booting procedure between the second transmission control unit 5 and the second local server 4 and the first transmission control unit 5 and the first local server 4 The boot process is the same, so I won't go into details here.

<Second embodiment>

Referring to FIG. 2, the second embodiment of the chassis device of the present invention is similar to the first embodiment, except that the second embodiment omits the first embodiment. The communication module 24, the communication network 60 and the remote server 6, and the power-on signal is a power button (not shown) from the chassis device itself, but is not limited thereto.

It should be noted that the operation of the other components of the second embodiment is similar to that of the first embodiment, and details are not described herein again.

In summary, since the chassis device of the present invention can be remotely booted by the remote server 6, and the remote server 6 can update the BIOS versions stored in the storage unit 22 of the chassis manager 2. In this way, it can be avoided that the conventional server fails to boot when the update is stopped due to an inappropriate update of the internal BIOS version. In addition, the storage unit 22 is a flash flash drive and is not installed in the local server 4. Compared with the storage unit installed in the server, it has the advantages of easy maintenance and replacement. It is indeed possible to achieve the object of the invention.

However, the above is only the embodiment of the present invention, and the scope of the invention is not limited thereto, and all the equivalent equivalent changes and modifications according to the scope of the patent application and the patent specification of the present invention are still The scope of the invention is covered.

1‧‧‧Transmission channel

2‧‧‧Chassis Manager

21‧‧‧First Processing Unit

22‧‧‧ storage unit

23‧‧‧First random access memory

24‧‧‧Communication Module

3‧‧‧Transmission unit

4‧‧‧Local Server

41‧‧‧Second random access memory

42‧‧‧Second processing unit

421‧‧‧ processor

422‧‧‧ chipsets

5‧‧‧Transmission Control Unit

60‧‧‧Communication network

6‧‧‧Remote Server

Claims (6)

A chassis device includes: a transmission channel; a chassis manager, comprising a first processing unit, a storage unit electrically connected to the first processing unit, and storing a plurality of basics respectively corresponding to a plurality of different address materials An input/output system version, and a first random access memory electrically connected to the first processing unit; a transmission unit electrically connecting the first processing unit by using a first transmission interface, and electrically connecting by using a second transmission interface The transmission channel; at least one transmission control unit, each transmission control unit electrically connecting the transmission channel by using the second transmission interface; and at least one local server corresponding to the at least one transmission control unit, each local server includes a second random access memory, storing a corresponding identification code and a corresponding address data in the address data, and a second processing unit electrically connecting the second random access memory and utilizing the first A transmission interface electrically connects the corresponding transmission control unit to receive a power-on signal; wherein, in each local server, when each local server is connected When the start signal to the second processing unit in response to the read start signal Reading the corresponding address data of the second random access memory, and reading a memory block mapped to the first random access memory via the corresponding transmission control unit, the transmission channel, and the transmission unit Obtaining a corresponding basic input/output system version of the basic input/output system version, and executing a booting process, each of the first transmission interface and the second transmission interface being a low pin number bus interface (Low Pin Count Bus Interface, LPCBI). The chassis device of claim 1, wherein the second processing unit further reads the corresponding identification code of the second random access memory in response to the boot signal, and generates a corresponding identifier corresponding to the corresponding identifier The basic input/output system request of the address data, and the basic input output system request is transmitted to the first processing unit of the chassis manager at least via the corresponding transmission control unit, the transmission channel, and the transmission unit; When the processing unit receives the basic input/output system request, the first processing unit selects the basic input/output system stored in the basic input/output system request from the basic input/output system version stored in the storage unit. Corresponding basic input/output system version, and storing the corresponding basic input/output system version in the first random access memory corresponding to the memory of the identification code according to the corresponding identification code in the basic input/output system request a body block; and when the second processing unit is to read and map to the first random access memory, the second process list Based on the basic input and output system request The corresponding identification code reads the corresponding basic input/output system version of the memory block in the first random access memory via the corresponding transmission control unit, the transmission channel and the transmission unit. The chassis device of claim 1, wherein the chassis manager further comprises a communication module, wherein the communication module is adapted to connect to a remote server via a communication network, and the remote server can be updated and stored in the The basic input and output system versions in the storage unit. The chassis device of claim 3, wherein the power-on signal is generated by the remote server and transmitted to each of the transmission control units via the communication network, the chassis manager, the transmission unit, and the transmission channel. . The chassis device of claim 1, wherein the power-on signal is from a power button of the chassis device itself. The chassis device of claim 1, wherein each of the transmission control units includes a first general-purpose input and output (GPIO) pin that outputs a power-on target setting signal and an output power signal. a second GPIO pin; the second processing unit of each local server includes a first input pin electrically connected to the first universal input/output pin to receive the boot target setting signal (BIOS BOOT STRAP), and a second universal input/output pin electrically connected to receive the second input pin of the power button; and The boot target setting signal is used to determine whether the read second read random access memory is mapped to the first random access memory or the other serial serial interface (SPI) when the local server is powered on. And electrically connected to the read only memory (ROM) of the second processing unit.