TWI514281B - A sata storage device with spi interface, using this device for boot up and bios code update method thereof - Google Patents

Description

SATA storage device with SPI interface, booting method using the SATA storage device, and updating method of basic input/output system code

The present invention relates to a SATA storage device, and more particularly to an SPI storage device with an SPI interface installed in a personal computer system so that the computer system does not need to use a basic input/output system read only memory (BIOS ROM). The booting method of the storage device and the method for updating the code of the basic input/output system.

The basic input/output system memory in personal computers has evolved from the Read-only memory (ROM) used in the 1980s to the current NOR flash memory. Its capacity has also grown from the original 16KB. 128KB or higher, the computer language used to edit the BIOS has also evolved from a combined language to C. The traditional BIOS read-only memory (ROM) uses the ISA and X-BUS interface. Since 1998, the personal computer has used the LPC (Low Pin Count) bus interface, and now uses the serial (serial) column peripheral interface (SPI, Serial Peripheral). Interface) Bus. The advantage of using the SPI interface is that the pin position can save further cost. The SPI only needs 4 signals, including the main output from the input MOSI (Master Output Slave Input), the main input from the output MISO (Master Input Slave Output), the serial Clock SCK (Serial Clock) and slave SS (Slave Select).

When the computer's power is turned on for the first time T1, the CPU will read the BIOS code into the dynamic random access memory, first complete the power-on self-test POST (Power-on Self-test), the system chipset and Subsystem initialization such as memory. The BIOS code also includes diagnostics to ensure that certain important hardware components, such as keyboards, disk devices, output inputs, etc., function properly and are properly initialized. Almost all BIOSes can optionally execute CMOS memory settings; that is, save user-defined settings (time, date, hard drive details, etc.) that the BIOS will access. Finally, the BIOS code will transfer the main boot record MBR of the operating system storage device to the MBR (the second time T2), and the MBR will load all the files of the operating system into the dynamic random access memory and execute them.

And after the general computer is sold, there are often actions to update the version of the BIOS code. The way to update the BIOS version is usually that the computer user crawls the updated version from the computer manufacturer's website through the Internet. After downloading, the BIOS update program is executed (the third time T3 is turned on), and the new BIOS code is burned ( Programing) to the BIOS memory. Therefore, when burning the new BIOS code, you must erase the (Erase) BIOS memory before programming the new code. Generally speaking, it takes about several minutes to burn a new BIOS code.

At present, the flash memory can be divided into NOR flash memory (NOR flash) or NAND flash memory (hereinafter NAND flash), and its characteristics are as follows:

(a) NOR flash memory: Because the internal address is stored continuously, it is suitable for storing code and can support the processor to perform operations directly on the NOR flash memory by Execute in place (XIP). However, the structure of the NOR flash memory is complicated and complicated, and the manufacturing cost is high, and it is not suitable for storing a large-capacity (for example, more than 16 MB) file. Therefore, the current BIOS uses NOR flash memory.

(b) NAND flash memory: NAND flash memory is more suitable than NOR flash memory because of its simple production structure, large storage capacity per unit area, and fast write and erase speeds. For storing low-cost files, solid state disks (SSDs) or SATA DOMs are often implemented as arrays of NAND flash memory, and a file of the same size is written to NOR flash memory and NAND flash memory. It is obvious that NOR flash memory takes more time, usually hundreds of times.

The basic structure of SATA DOM (SATA Disk-On-Module) is the same as that of SSD. The main difference is that the capacity is different. In addition, SATA DOM usually looks like a small card structure, or a small PCBA or module, and SSD. It is usually designed to have the same form factor as a hard disk drive (HDD). In addition, the SATA DOM currently only supports the SATA interface.

Traditionally, the use of BIOS memory in personal computers has some disadvantages: one is the cost of materials and the indirect manufacturing cost of burning BIOS code, and the BIOS version is not convenient after the computer is sold. In addition, when the BIOS memory is poisoned or damaged, The computer must be repaired, and replacing the new BIOS memory is also labor intensive. In view of the problems of the prior art, a solution is needed to solve the above problems.

Therefore, how to solve the above problems and problems in the past, that is, the inventors of this case and the relevant manufacturers engaged in this industry are eager to study the direction of improvement.

Therefore, in order to effectively solve the above problems, the main object of the present invention is to provide a BIOS that uses the basic input/output system code of the internal flash memory array of the SATA storage device to replace the BIOS memory on the conventional computer host. SATA storage device with SPI interface that saves costs and updates the convenience and convenience.

Another object of the present invention is to provide a BIOS having a basic input/output system code using an internal flash memory array of the SATA storage device to replace the BIOS memory on a conventional computer host, thereby achieving cost saving and rapid maintenance. Apply the boot method of the SATA storage device.

Another object of the present invention is to provide a BIOS with a basic input/output system code of an internal flash memory array using the SATA storage device, thereby achieving cost saving and simple update convenience. And the effect of rapid maintenance is applied to the basic input/output system code update method of the SATA storage device.

To achieve the above objective, the present invention provides a SATA storage device with an SPI interface for use in a computer system without a basic input/output system read-only memory, the SATA storage device including a flash memory array and a control The flash memory array is configured to store a first basic input/output system code and an operating system. One side of the control unit is coupled to the flash memory array, and the other side is coupled to the flash memory array. a computer system, and the control unit comprises a firmware with a firmware and a random access memory, and the random access memory system is used as a temporary storage area for performing firmware programming and data as the control unit, so When booting, the control unit executes the firmware of the firmware, and moves the first basic input/output system code in the flash memory array to the random access memory, and then transmits the code to the computer system; The design of the SATA storage device with the SPI interface of the present invention can effectively replace the BIOS memory on the traditional computer host, thereby achieving cost saving and updating. Convenience and fast service of good results.

The invention further provides a booting method using the SATA storage device, which is applied to a computer system without a basic input/output system read-only memory, the SATA storage device comprises a flash memory array and a first SPI interface. a first SATA interface and a control unit coupled to the flash memory array, the flash memory array storing a first basic input/output system code and an operating system, wherein the control unit is coupled to the first An SPI interface and a first SATA interface, and comprising a firmware with a firmware and a random access memory, and the computer system includes a computer host having a central processing unit and a coupling a second SPI interface of the first SPI interface, a second SATA interface coupled to the first SATA interface, and a dynamic random access memory unit coupled to the central processing unit, the booting method first starting the computer system to boot, And the control unit executes the firmware of the firmware, and reads a first basic input/output system that is moved from the flash memory array to the random access memory. The control unit detects the SPI interface and detects the SPI interface. After the hardware system performs a hardware reset operation, the central processing unit transmits a read signal to the first SPI interface through the second SPI interface. After the SPI interface receives the transmitted read signal, the control unit transmits the first basic input/output system code in the random access memory to the central processing unit through the first SPI interface, and then the central processing The unit transmits the first basic input/output system code to the dynamic random access memory unit through the second SPI interface, and after the reading is completed, the central processing unit executes the first basic input/output system. After the code and the self-boot test and the initialization test are completed, an instruction is transmitted, and then the control unit executes the instruction received by the central processing unit, and the read is moved from the flash memory array to the random access. The operating system in the memory is transmitted to the central processing unit through the first SATA interface, and finally the central processing unit transmits the The second SATA interface loads the received operating system into the dynamic random access memory unit and executes the loaded operating system; the design of the booting method of the present invention enables the BIOS to be effectively replaced by the traditional computer host Memory, in order to achieve cost savings and rapid maintenance.

The present invention further provides a method for updating a basic input/output system code using the SATA storage device, which is applied to a computer system without a basic input/output system read-only memory, the SATA storage device comprising a flash memory array. a first SPI interface, a first SATA interface, and a control unit coupled to the flash memory array, the flash memory array is configured to store a first basic input/output system code, a second basic An input/output system code, a basic input/output system update program, and an operating system, wherein the control unit is coupled to the first SPI interface and the first SATA interface, and includes a firmware with a firmware and a random Accessing the memory, the computer system includes a computer host having a central processing unit, a second SPI interface coupled to the first SPI interface, and a second SATA interface coupled to the first SATA interface And a dynamic random access memory unit coupled to the central processing unit, the basic input/output system code update method firstly when the user wants to update to the second When the basic input/output system code is used, the control unit transmits the central processing unit to the basic input/output system update program that is moved to the flash memory through the first SATA interface, so that the central processing unit transmits a second SATA interface. Receiving and executing the basic input/output system update program, causing the basic input/output system update program to be loaded into the dynamic random access memory unit for execution, and transmitting a basic input/output system update command, and then the control unit transmits the After receiving the basic input/output system update command, the SATA interface copies the second basic input/output system code to a designated block in the flash memory, and the control unit will be in the designated block at this time The enable flag of the second basic input/output system code is set to be on, and the first basic input/output code previously in the specified block is set to be closed to complete the update; the basic input/output system is provided by the present invention. The code update method is designed to effectively replace the BIOS memory on the traditional computer host. In order to achieve cost savings, simple and convenient update, and rapid maintenance.

1‧‧‧SATA storage device

11‧‧‧Flash Memory Array

111‧‧‧First basic input and output system code

112‧‧‧Operating system

113‧‧‧Enable flag

114‧‧‧Second basic input and output system code

115‧‧‧Basic input and output system update program

13‧‧‧Control unit

14‧‧‧ Firmware

15‧‧‧ Random access memory

16‧‧‧First SPI interface

17‧‧‧First SATA interface

2‧‧‧ computer system

21‧‧‧Computer host

211‧‧‧Central Processing Unit

212‧‧‧ Dynamic Random Access Memory Unit

213‧‧‧Second SPI interface

214‧‧‧Second SATA interface

23‧‧‧Display unit

24‧‧‧ Input unit

25‧‧‧Power supply unit

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram showing a first preferred embodiment of the present invention.

2 is a block diagram showing the coupling of a SATA storage device and a computer system according to a first preferred embodiment of the present invention.

Figure 3 is a schematic diagram of the booting process of the second preferred embodiment of the present invention.

Figure 4 is a schematic diagram showing the updating process of the second preferred embodiment of the present invention.

The above object of the present invention, as well as its structural and functional features, will be described in accordance with the preferred embodiments of the drawings.

The present invention relates to a SATA storage device with an SPI interface, a booting method using the SATA storage device, and a method for updating a basic input/output system code. Please refer to the first and second embodiments, which are block diagrams of the first preferred embodiment of the present invention. The SATA storage device 1 with the SPI (Serial Peripheral Interface) interface in the preferred embodiment is a SATA electronic hard disk. (Disk On Module, DOM), which can be referred to as SPI-SATA DOM for short, but is not limited to this; in the implementation, the SATA storage device of this creation can also be selected as a SATA solid state drive or a SATA hard drive. The SATA solid state drive has an SPI interface, and the SATA hard drive has an SPI interface. The SATA storage device 1 is applied to a computer system 2 having no basic input/output system read-only memory. The SATA storage device 1 (SATA DOM) includes a flash memory array 11 and a first SPI (Serial Peripheral Interface). The interface 16 is a first SATA interface 17 and a control unit 13. The flash memory array 11 has a plurality of NAND flash memories for storing a plurality of first basic input/output systems ( Basic Input Output System, hereinafter referred to as BIOS code 111, complex enable flag 113, a second basic input/output system (BIOS) code 114, a basic input/output system (BIOS) update program 115, an operating system 112, and Other applications and data, wherein the first BIOS code 111 of the preferred embodiment is described by a plurality of BIOS codes, but is not limited thereto. In the specific implementation, the flash memory may be selected and designed. Only one first BIOS code 111 is stored in the volume array 11.

The plurality of first BIOS code 111 is stored in a designated block (or a specific memory block) of one of the NAND flash memories, and only one of the first BIOS codes 111 is first. The enable flag 113 (Boot-Flag) of the BIOS code 111 is set to be on for reading by the control unit 13; wherein the designated block of the NAND flash memory is unrecognizable by the operating system 112. Memory block. The first SPI interface 16 is a transmission interface of the first BIOS code 111 in the control unit 13. One end of the first SPI interface 16 is coupled to the computer system 2, and the other end of the first SPI interface 16 is coupled to the control unit 13. The control unit 13 transmits the first BIOS code 111 of the flash memory array 11 to the computer system 2. The first SATA interface 17 is Serial ATA (Serial ATA: Serial Advanced Technology Attachment), and includes SATA 1.0, SATA 2.0, SATA 3.0, SATA Express, e SATA, and new derivatives. One end of the first SATA interface 17 is coupled to the computer system 2, and the other end is coupled to the control unit 13.

The operating system 112 is any operating system 112 that can be operated and executed in a computer host 21 of the computer system 2, such as a Windows operating system 112 (Windows OS), Unix, Linux Android, etc. (ie, executed on a personal computer). The operating system 112), the BIOS update program 115 is an application executable in the environment of the operating system 112. After the user obtains the new version of the BIOS code (ie, the second BIOS code 114), the BIOS update program 115 is executed. The original first BIOS code 111 is replaced with a new version of the BIOS code (ie, the second BIOS code 114).

The foregoing control unit 13 is described by a microprocessor in the preferred embodiment, but is not limited thereto; in the specific implementation, it can also be selected as a programmable controller such as a microcontroller (MCU) or an integrated circuit chip. The control unit 13 can receive instructions, perform judgments, and control the flash memory array 11. One side of the control unit 13 is coupled to the flash memory array 11 and the other side of the control unit 13 is coupled to the computer system 2, that is, as shown in FIG. 2, one side of the control unit 13 is coupled. The other side of the flash memory array 11 is a computer system 2 that is electrically connected to the first SATA interface 17 through the first SPI interface 16 .

Referring to Figures 1 and 2, the control unit 13 includes a firmware 14 having a firmware and a random access memory 15 (Random Access Memory, RAM). The control unit 13 executes the firmware of the firmware 14 and the temporary storage area of the data, so when the power is turned on, the control unit 13 executes the firmware of the firmware 14 from the flash memory array 11. The first basic input/output system code 111 is transferred to the random access memory 15 and then transmitted to the computer system 2, that is, when the computer system 2 is powered on, the control unit 13 executes the firmware program. The first BIOS code 111 with the enable flag 113 set to ON in a designated block of one of the NAND flash memories is read, and then transmitted to the connected computer system 2 through the first SPI interface 16.
The computer system 2 includes the computer host 21 without a basic input/output system read only memory (BIOS ROM), a display unit 23, an input unit 24, and a power supply unit 25, and the display unit 23 (such as an LCD screen) The input unit 24 is electrically connected to the computer host 21 respectively. The power supply unit 25 is a power supply of the computer system 2, and includes a power switch and a power supply of different potentials at different levels. In other words, the power supply unit 25 is used for The power supply of the central processing unit 211, the control unit 13, the input unit 24, the dynamic random access memory unit 212, and the flash memory array 11 should be operated.
The input unit 24 can include a keyboard, a mouse, a trackball, a touch pad, and the like. The computer main unit 21 has a central processing unit 211, a dynamic random access memory unit 212, a second SPI interface 213 and a second SATA interface 214. The central processing unit 211 is a central processing unit of the computer motherboard. It is a PC compatible CPU from Intel or AMD, but it is not limited to these two products. In addition, the current CPU unit often integrates the logic of the peripheral device, which is also included in our definition, such as the Intel 3-core processor ivy-bridge processor or Sandy-bridge processor, and even includes the built-in display card chip. .

The central processing unit 211 is electrically connected to the control unit 13 and the dynamic random access memory unit 212, that is, the second SPI electrical connection of the computer host 21 is opposite to the first SPI interface 16, and the second SATA interface 214 is The central processing unit 211 is electrically connected to the control unit 13 and the central processing unit 211 is coupled to the opposite dynamic random access memory unit 212. In addition, in the actual implementation of the present invention, the SATA storage device 1 of the present invention can be directly installed (or integrated) in the computer host 21, that is, the plurality of pins of the control unit 13 of the SATA storage device 1 can be directly electrically connected. Corresponding to the plurality of pins of the central processing unit 211 of the host computer 21, the first and second SPI interfaces and the first and second SATA interfaces can be removed.
The dynamic random access memory unit 212 is composed of a plurality of DRAM Modules, which are the first BIOS code 111, the operating system 112, and the application and data operation and temporary storage. The device, that is, the dynamic random access memory unit 212 is selected to be a memory for program and data access in a personal computer such as SDRAM, DDR2, DDR3, DDR4, and the like.
Please refer to FIG. 2, so when the computer system 2 is turned on, the power supply unit 25 supplies power to the central processing unit 211, the dynamic random access memory unit 212, the control unit 13, and the flash memory array 11, so that the foregoing The control unit 13 executes the firmware program, and moves the first BIOS code 111 of the plurality of first BIOS code 111 of the flash memory array 11 to enable the flag 113 to be turned on, and first moves to the random access memory. The body 15 is then transmitted to the central processing unit 211 of the computer host 21 through the first SPI interface 16, and the central processing unit 211 receives the first BIOS with the enable flag 113 set to be turned on through the second SPI interface 213. The code 111 is stored in the dynamic random access memory unit 212 and executed, and the central processing unit 211 executes the first BIOS code 111 and performs self-boot test and initialization test. The SATA interface 214 transmits an instruction to the control unit 13 to cause the control unit 13 to receive and execute instructions from the computer system 2 to read the operating system 112 from the flash memory array 11 (e.g., the window operating system 112). Moving to the random access memory 15 and transmitting the related files in the operating system 112 to the central processing unit 211 of the computer host 21 of the computer system 2 through the first SATA interface 17, the central processing The unit 211 loads the received operating system 112 into the dynamic random access memory unit 212 through the second SATA interface 214 and executes the operating system 112.
If the first BIOS code 111 is to be updated at this time, the control unit 13 receives the BIOS update command transmitted by the central processing unit 211 through the first SATA interface 17, and then the NAND flash memory The second BIOS code 114 (ie, the new BIOS code) is copied into the designated block of the aforementioned NAND flash memory, and the control unit 13 will enable the enable flag 113 of the second BIOS code 114 in the specified block. Set to enable, and reset the first BIOS code 111 in the specified block to OFF, and then update the BIOS code, so that when the computer host 21 is turned on next time, the control unit 13 will transfer the second BIOS code 114 back to the host computer 21 until the next enable flag 113 (Boot-Flag) is turned on (On) is set in another new BIOS code. Therefore, it takes several minutes to update the traditional BIOS code. It takes only one second to update the BIOS code using the design of the device of the present invention. For example, if the BIOS code size is 64Kbyte, about 16 The page is stored, and the actual update time is about 300 microseconds x 16 = 4.8 milliseconds.

Therefore, the SATA electronic device 1 with the SPI interface and the computer system 2 without BIOS read-only memory can effectively replace the BIOS memory on the traditional computer host 21, thereby achieving cost saving and Update the effect of simple convenience and quick repair.

Please refer to FIG. 3, which is a schematic diagram showing the flow of the second preferred embodiment of the present invention, and is supplemented with reference to FIG. 2, which is mainly a SATA electronic device with an SPI interface according to the first preferred embodiment. 1 is applied to a booting method of a computer system 2 having no basic input/output system read-only memory and a method for updating a BIOS code, wherein the booting method comprises the following steps;

(300) start the computer system to boot;
The computer system 2 is turned on, and the power supply unit 25 is powered to the central processing unit 211, the dynamic random access memory unit 212, the control unit 13, and the flash memory array 11 and other units of the computer host 21 (ie, input Unit 24 and display unit 23).

(301) The control unit 13 executes the firmware program, reads the first basic input/output system code 111 moved from the flash memory array 11 into the random access memory 15, and detects the first SPI. Interface 16, and continue to step 302;

The control unit 13 executes the firmware of the firmware 14 from which the enable flag 113 is turned on in a specific block of a NAND flash memory of the flash memory array 11 The first BIOS code 111 is read into the random access memory 15 in units of pages and detects the signal of the first SPI interface 16. Generally speaking, one page (Page) is 4Kbyte (for example, Micron) or 8Kbyte (for example, Samsung), depending on the specifications of the NAND Flash manufacturer; in addition, the general control unit has its internal random access memory 15 (RAM). It is about 16Kbyte. The general BIOS code is about 64Kbytes, so if you use a page (Page) for 4Kbyte calculation, you need 16 pages of space to store, in other words, you need to move 16 times in total. The clock is sent in the 500KHz computer system 2, and the BIOS code is transmitted in about one second. The first BIOS code 111 in the preferred embodiment is read out to the random access memory 15 by using a page as a transmission unit, but is not limited thereto, and may be selected in specific implementation. The technical methods of 512 Bytes, 1 KByte, or 16 Kbyte, etc., all of which belong to the same technical method are all within the scope of the present invention.

(310) After the computer system 2 performs a hardware reset operation, the central processing unit 211 transmits a read signal to the first SPI interface 16 through the second SPI interface 213;

The central processing unit 211 transmits a read signal through the second SPI interface 213 after the computer system 2 performs the hardware reset operation and the internal buffers of the central processing unit 211 are set to the specified values. That is, the BIOS reads the signal to the first SPI interface 16, and the central processing unit 211 transmits the read signal to the first SPI interface 16 through the second SPI interface 213. In the case of an Intel CPU, the central processing unit (CPU) jumps to the first execution address of the address 0xFFFF0h and proceeds to step 311.

(302) At this time, the control unit 13 detects that the first SPI interface 16 receives the transmitted read signal, and the control unit 13 inputs the first basic input/output system code 111 in the random access memory 15 Transmitting to the central processing unit 211 through the first SPI interface 16;

At this time, after the control unit 13 detects (reads) the SPI interface receives the transmitted read signal, the control unit 13 sequentially places the first BIOS code 111 in the random access memory 15 The first BIOS code 111 of the page is sent to the central processing unit 211, and the total number of pages of the first BIOS code 111 is checked. If the transfer is not completed, the first BIOS code 111 of the next page is continued. The reading, moving and transferring are completed until the central processing unit 211 is completely sent out, and step 303 is continued.

(311) The central processing unit 211 transmits the first basic input/output system code 111 to the dynamic random access memory unit 212 through the second SPI interface 213, and the central processing is performed after all reading is completed. The unit 211 executes the first basic input/output system code 111 and performs a self-boot test and an initialization test, and then transmits an instruction;

The central processing unit 211 transmits the first basic input/output code that the enable flag 113 is turned on through the second SPI interface 213, and sequentially moves to the dynamic random access memory unit 212 in units of pages and continues. After reading the next page first BIOS code 111 until all reading is completed, the central processing unit 211 writes the first BIOS code 111 into the dynamic random access memory unit 212, and then the central processing unit 211 executes After the first BIOS code 111 performs the self-boot test and the initialization test, an instruction is sent to the control unit 13 through the second SATA interface 214, and the process proceeds to step 312.

(303) The control unit 13 executes the instruction transmitted by the central processing unit 211, reads the operating system 112 moved from the flash memory array 11 to the random access memory 15, and transmits the first SATA. Interface 17 is transmitted to the central processing unit 211;

The control unit 13 receives the instruction transmitted by the central processing unit 211 via the first SATA interface 17, and executes the first boot record that the flash memory array 11 moves to the random access memory 15 ( The Master Boot Record (MBR) primary boot loader is sent to the central processing unit 211, and then other related files of the operating system 112 are sent out until the download of the operating system 112 is completed to the central processing unit 211.

(312) The central processing unit 211 loads the received operating system 112 into the dynamic random access memory unit 212 through the second SATA interface, and executes the loaded operating system 112;

The first BIOS code 111 executed by the central processing unit 211 of the computer host 21 first reads the primary boot loader in the main boot record (MBR) and then transfers the power to the main boot record. After (MBR), the aforementioned main boot record (MBR) takes power and jumps to a second boot loader (Secondary Boot loader), which is responsible for loading the operating system 112 and loading it one after another. In the dynamic random access memory unit 212, until the download of the operating system 112 is completed, including initialization of the Kernel, Session, Winlogon, Explorer, etc., and Post Boot Activity.

In addition, after the computer system 2 is powered on, the central processing unit 211 starts after the hardware reset until the central processing unit 211 completely reads the first BIOS code 111 and executes the first BIOS code 111. When entering the operating system 112, it is referred to as the first time. The computer system 2 reads the Boot Loader after executing the first BIOS code 111 to load the entire operating system 112 into the dynamic random access memory unit 212 inside the computer host 21 and execute the computer. The system 2 is called the second time until it operates in the environment of the operating system 112, so the first time to the second time is the booting process.

Referring to FIG. 4, and referring to FIG. 2, when the user wants to update the first BIOS code 111, the basic input/output system code update method includes the following steps.

(400) start

(401) The control unit 13 transmits the central processing unit 211 via the second SATA interface 214 to the basic input/output system update program 115 that is moved into the flash memory array 11;

The control unit 13 transmits the BIOS update program 115 moved to the flash memory array 11 to the central processing unit 211 via the second SATA interface 214.

(402) The central processing unit 211 receives and executes the basic input/output system update program 115 through a second SATA interface 214, and causes the basic input/output system update program 115 to be loaded into the dynamic random access memory unit 212 for execution. And transmitting a basic input/output system update command through the second SATA interface 214;

The central processing unit 211 receives and executes the BIOS update program 115 through the second SATA interface 214, and the BIOS update program 115 is loaded into the dynamic random access memory unit 212 for execution and transmitted through the second SATA interface 214. A BIOS update command (or also referred to as a BIOS copy command) is provided to the control unit 13.

(403) after receiving the basic input/output system update command by the first SATA interface 17, the control unit 13 copies the second basic input/output system code 114 to a designated area in the flash memory array 11. In the block;

After receiving the BIOS update command, the control unit 13 copies the new BIOS code (ie, the foregoing second BIOS code 114) into a designated block in the flash memory array 11.

(404) At this time, the control unit 13 sets the enable flag 113 of the second basic input/output system code 114 in the designated block to be on, and simultaneously outputs the first basic input and output in the specified block. After the code 111 is set to off, the BIOS code update is completed;

At this time, the foregoing control unit 13 sets the enable flag 113 of the second BIOS code 114 in the specified block to ON, and activates the flag in the first BIOS code 111 of the last boot. After the 113 is set to OFF, the BIOS code update can be completed (ie, updated to the second BIOS code 114), so that when the computer host 21 is turned on next time, the control unit 13 will generate the new BIOS code ( That is, the second BIOS code 114) is transmitted back to the host computer 21, and the booting operation is completed according to the foregoing booting method.

Therefore, the SATA storage device 1 with the SPI interface of the present invention can include a plurality of different BIOS versions, and can be changed at any time. Compared with the conventional method, the basic input/output system read only memory (BIOS ROM) can only be used. There is a set of BIOS code, and the implementation method of the author BIOS update program 115 is different from the traditional BIOS update program, because the updated version of the BIOS code (ie, the second BIOS code 114) does not overwrite the original BIOS. The code (ie, the first BIOS code 111) simply sets the enable flag 113 of the original BIOS code (ie, the first BIOS code 111) to off (ie, hides the first BIOS code 111), and the new version The BIOS code (ie, the second BIOS code 114) enable flag 113 is set to enable, allowing the control unit 13 to read the design so that it can effectively prevent the update of the new version of the BIOS code and restore the original version. The effect of the BIOS code. Compared with the traditional BIOS update program, the new version of the BIOS code will be burned to the BIOS memory (NOR flash memory) to replace the old version of the BIOS code, that is, the new version of the BIOS code will be overwritten. (overwritten) The original old version of the BIOS code, if it is traditional to update the new version of the BIOS code failed, it can not be restored to the original version of the original version of the BIOS code, resulting in users have to repair and replace the new BIOS memory.

While the present invention has been described above in terms of its embodiments, it is not intended to limit the invention, and various modifications and changes can be made without departing from the spirit and scope of the invention. For example, since the designated block (block) of the flash memory array 11 can include multiple first BIOS codes 111 at the same time, the present invention can also be extended to select multiple sets of BIOS on the BIOS setting screen or the startup screen. One of the code codes is the boot BIOS code. In other words, it can be further implemented as a multi-BIOS selection technology, and the file size of each BIOS code is not limited, so the technology of this case is compared with several previous cases. The multi-BIOS booting system works well because the present invention can select one of a plurality of BIOS codes to boot without the NOR flash memory.

In addition, since the BIOS code (ie, the first and second BIOS codes 111 and 114) and the control unit 13 of the present invention are not controlled by the operating system 112, it is naturally possible to add a "system" to the flash memory array 11. The detection program (System-Debugger; not shown) is executed directly at the first time of startup, and does not need to be executed in the environment of the operating system 112. This is for the product research and development of the computer manufacturer's R&D department, and the manufacturing department. Online product overhaul and computer repair in the computer after-sales service department are more convenient, further reducing the cost of service for R&D, manufacturing and customer service of computer manufacturers.

As described above, the present invention has the following advantages over the prior art:

1. Has shortened product development time. Through the design of the invention, the editing of the BIOS of the computer manufacturing and assembly end and the product development end can be simultaneously performed, and even if the BIOS content needs to be corrected and updated during the manufacturing and assembly process, the BIOS memory does not need to be re-burned. .

2. It saves materials and manufacturing costs and improves quality. Because the BIOS code is placed in the NAND flash memory array without using the BIOS to read only the memory, the material cost is reduced, and the manufacturing cost is reduced by eliminating the process of burning the BIOS memory, and the computer system is also reduced. With fewer components, the yield of the product can be improved.

3. Has the time and risk of reducing the user's BIOS update. In general, when a user updates the BIOS, it takes a few minutes to program the BIOS code. It is often the case that the programming fails and cannot be turned on and the computer must be repaired. If the technology of the case is used, Updating the BIOS takes less than a second. In addition, there will be no update failures. Even with this method, multiple versions of the BIOS can be used.

4. After the product of the present invention is sold, since there is no BIOS memory on the motherboard of the computer system, there is no need for the BIOS memory to be damaged and replaced, and the product in the enterprise after-sales service is easier to repair.

5. The traditional BIOS code usually compresses the BIOS code due to the limitation of the memory (NOR Flash) capacity. When executed, the BIOS code is decompressed into the dynamic random access memory unit. However, such compression and decompression programs and their steps are not required in the present invention, as today's NAND flash memory typically has more than 32 GB, and flash memory manufacturers typically provide about 7% of excess capacity. For system vendors, the general BIOS code is about 128KB to 256KB, so there is a big advantage in memory space when storing BIOS code in NAND flash memory. More specifically, in addition to the cost of saving a NOR flash memory, the file size of the BIOS code (ie, the first and second BIOS code 111, 114) is not limited, in other words, use After the technology of this case, the full-color picture with the highest resolution (4K X 2K) can be seen at the first time of booting. This effect is not possible on the traditional BIOS ROM. We can prove this on the first screen of any brand computer. Usually, the first screen of their boot is a single color, usually white text such as Lenovo. , HP, acer, ASUS and other low-resolution brand logo images.

6. Having the BIOS code is not controlled by the operating system. The first BIOS code 111 and the second BIOS code 114 of the apparatus of the present invention can be placed in a designated block of the NAND flash memory array, for example, in the first block, and the NAND flash memory manufacturer guarantees this. The area can be burned 1000 times without any problems and no error correction code (ECC). In addition, since the read and write (updated versions) of the BIOS code (ie, the first and second BIOS codes 111, 114) are both controlled by the control unit 13 of the present invention, they may not be performed under the control of the operating system, in other words, Even if the operating system (OS) is damaged by the virus program, the BIOS code under the present invention can operate normally without any risk, and the present invention is obviously better than the prior art.

The above description is only a preferred embodiment of the present invention, but the features of the present invention are not limited thereto, and any changes or modifications that can be easily conceived in the field of the present invention are known to those skilled in the art. It is intended to be included in the scope of the claims of the present invention below.

1‧‧‧SATA storage device

11‧‧‧Flash Memory Array

111‧‧‧First basic input and output system code

112‧‧‧Operating system

113‧‧‧Enable flag

114‧‧‧Second basic input and output system code

115‧‧‧Basic input and output system update program

13‧‧‧Control unit

14‧‧‧ Firmware

15‧‧‧ Random access memory

16‧‧‧First SPI interface

17‧‧‧First SATA interface

Claims (10)

[Item 1] A SATA storage device with an SPI interface is applied to a computer system without a basic input/output system read-only memory. The SATA storage device includes:
a flash memory array storing a first basic input/output system code and an operating system;
a control unit, one side of which is coupled to the flash memory array, the other side of which is coupled to the computer system, and the control unit includes a firmware with a firmware and a random access memory. The access memory system is used as the control unit to execute a firmware temporary storage area of the firmware and the temporary storage area of the data; and when the power is turned on, the control unit executes the firmware program from the flash memory array The first basic input/output system code is transferred to the random access memory and then transmitted to the computer system. [Item 2] The SATA storage device of the SPI interface, wherein the SATA storage device further includes a first SPI interface and a first SATA interface, and the first SPI interface is coupled to the computer system. The other end is coupled to the control unit, and one end of the first SATA interface is coupled to the computer system, and the other end is coupled to the control unit. [Item 3] The SATA storage device with an SPI interface as described in claim 2, wherein the computer system receives the first basic input/output system code and stores it in the dynamic random access memory unit. Transmitting an instruction to the control unit, causing the control unit to receive and execute the instruction of the computer system, and the reading operation system from the flash memory array is moved into the random access memory and transmitted through the first SATA interface Give the computer system. [Item 4] The SATA storage device with an SPI interface according to claim 3, wherein the flash memory array has a plurality of NAND flash memories, and the NAND flash memory stores a plurality of first basic input/output system programs. The code, the operating system and the plurality of enable flags, and the first basic input/output system code is stored in a designated block of one of the NAND flash memories, and one of the first basic inputs and outputs The enable flag of the system code is set to ON for reading by the control unit. [Item 5] The SATA storage device with an SPI interface as described in claim 4, wherein the designated block is a memory block that is not recognized by the operating system. [Item 6] The SATA storage device with an SPI interface according to claim 4, wherein the computer system comprises a computer host having no basic input/output system read-only memory, a display unit, an input unit and a power supply unit, The display unit and the input unit are respectively electrically connected to the computer host, the computer host has a central processing unit and a dynamic random access memory unit, and the central processing unit is electrically connected to the control unit and the dynamic random access memory unit. The power supply unit is configured to supply power to the central processing unit, the control unit, the input unit, the dynamic random access memory unit, and the flash memory array. [Item 7] The SPI storage device of the SPI interface of claim 6, wherein the computer host has a second SPI interface and a second SATA interface, and the second SPI interface is electrically connected to the first SPI interface. The second SATA interface is electrically connected to the first SATA interface. [Item 8] The SATA storage device with an SPI interface as described in claim 7, wherein the NAND flash memory further stores at least a second basic input/output system code and a basic input/output system update program. After receiving the basic input/output system update command sent by the central processing unit through the first SATA interface, the control unit copies the second basic input/output system code in the NAND flash memory to the NAND flash memory. In the designated block, the control unit sets the enable flag of the second basic input/output system code in the specified block to be on, and simultaneously sets the first basic input/output system program in the specified block. The code is set to off. [Item 9] A booting method for applying a SATA storage device is applied to a computer system having no basic input/output system read-only memory, the SATA storage device comprising a flash memory array, a first SPI interface, and a first SATA interface. And a control unit coupled to the flash memory array, the flash memory array storing a first basic input/output system code and an operating system, wherein the control unit is coupled to the first SPI interface and the first The SATA interface includes a firmware program and a random access memory, and the computer system includes a computer host having a central processing unit coupled to the first SPI interface. a second SPI interface, a second SATA interface coupled to the first SATA interface, and a dynamic random access memory unit coupled to the central processing unit, the booting method includes:
Start the computer system to boot;
The control unit executes the firmware program, reads a first basic input/output system code that is moved from the flash memory array into the random access memory, and detects the first SPI interface;
After the hardware system performs a hardware reset operation, the central processing unit transmits a read signal to the first SPI interface through the second SPI interface.
After the control unit detects that the first SPI interface receives the transmitted read signal, the control unit transmits the first basic input/output system code in the random access memory to the first SPI interface through the first SPI interface. Central processing unit;
The central processing unit transmits the first basic input/output system code to the dynamic random access memory unit through the second SPI interface, and after the reading is completed, the central processing unit executes the first basic After inputting and outputting the system code and performing self-boot test and initialization test, an instruction is transmitted;
The control unit performs an instruction received by the central processing unit, reads an operating system moved from the flash memory array to the random access memory, and transmits the operating system to the central processing unit through the first SATA interface; And the central processing unit loads the received operating system into the dynamic random access memory unit through the second SATA interface, and executes the loaded operating system. [Item 10] A basic input/output system code update method for a SATA storage device is applied to a computer system having no basic input/output system read-only memory, the SATA storage device comprising a flash memory array and a first SPI interface a first SATA interface and a control unit coupled to the flash memory array, the flash memory array storing a first basic input/output system code, a second basic input/output system code, and a basic input An output system update program and an operating system, the control unit is coupled to the first SPI interface and the first SATA interface, and includes a firmware with a firmware and a random access memory, and the computer system The computer host has a central processing unit, a second SPI interface coupled to the first SPI interface, a second SATA interface coupled to the first SATA interface, and a central processing unit coupled to the central processing unit The dynamic random access memory unit, when the user wants to update the first basic input/output system code, the basic input/output system code update method Including:
The control unit transmits the basic input/output system update program moved to the flash memory array to the central processing unit through the second SATA interface;
The central processing unit receives and executes the basic input/output system update program through a second SATA interface, so that the basic input/output system update program is loaded into the dynamic random access memory unit for execution, and the second SATA interface is transmitted through the second SATA interface. Transmitting a basic input/output system update command;
After receiving the basic input/output system update command through the first SATA interface, the control unit copies the second basic input/output system code into a designated block in the flash memory array; The control unit sets the enable flag of the second basic input/output system code in the specified block to be on, and sets the first basic input/output code previously in the specified block to be closed to complete the update.