TWI605476B - Anti-vulcanization chip resistor and its manufacturing method - Google Patents

Description

Anti-vulcanized chip resistor and its preparation method

The present invention relates to a wafer electrical group and a method for manufacturing the same, and particularly to a chip resistance against vulcanization and a method for preparing the same.

The vulcanization resistance is one of the indexes for evaluating the resistance quality of the wafer, and the conventional structure of several kinds of wafer resistances will be described below.

6 shows a structure of a conventional chip resistor, comprising a substrate 80, an electrode 81, a resistive layer 82, a protective layer 83, a first end electrode layer 84 and a second end electrode layer 85. The electrode 81 is a silver electrode disposed outside the top surface of the substrate 80. The resistor layer 82 is disposed on the top surface of the substrate 80 and covers a portion of the resistive layer 82. The protective layer 82 covers the resistive layer 82. a portion of the electrode 81, the first end electrode layer 84 extends downward from a top surface of the electrode 81 not covered by the protective layer 83, and is formed on an end surface of the electrode 81 and an end surface of the substrate 80. The second end electrode A layer 85 is formed on a surface of the first terminal electrode layer 84, wherein the first end electrode layer 84 and the upper end of the second end electrode layer 85 are connected to a side surface of the protective layer 83. However, sulfur gas permeates from the first end electrode layer 84 and the interface between the upper end of the second end electrode layer 85 and the protective layer 83 to the electrode 81, causing the electrode 81 (silver electrode) to be easily vulcanized.

FIG. 7 shows the structure of another conventional chip resistor, which is substantially the same as FIG. 6, and the upper end 841 and the second end electrode layer 85 of the first end electrode layer 84 shown in FIG. 7 are compared with FIG. The upper end 851 extends further up to the top surface of the protective layer 83 to increase the path length of the sulfur gas infiltration, avoiding or delaying the curing of the electrode 81. FIG. 8 shows a structure of a conventional wafer resistor, which is substantially the same as FIG. 6. Compared with FIG. 6, FIG. 8 further includes a vulcanization resistant layer 86 disposed on the surface of the electrode 81. The boundary of the protective layer 83 is on the surface of the anti-sulfurization layer 86, and the anti-sulfurization layer 86 is transmitted to prevent the electrode 81 from directly contacting the sulfur gas infiltrated from the interface.

In addition to the conventional structures of the chip resistors shown in the foregoing FIGS. 6 to 8, there are also related patents, such as the Taiwan Patent Publication No. I300942 and the No. I395232 case, showing how to strengthen the anti-vulcanization characteristics of the chip resistors in the industry. An important topic. Therefore, the applicant has proposed the anti-vulcanization chip resistance and its preparation method through careful evaluation and multi-party considerations, and through the professional experience accumulated in this industry, through continuous sample testing and improvement.

In view of the fact that the anti-vulcanization characteristics of the chip resistor are not well known, the main purpose of the present invention is to provide a chip resistance against vulcanization and a method for preparing the same, which can effectively prevent the wafer resistance from being vulcanized.

The sheet resistance of the present invention includes: a substrate having a top surface including two outer regions and an intermediate portion between the outer regions; and two upper electrode layers respectively disposed on the outer regions of the substrate, each of the The top surface of the upper electrode layer includes a resistor overlapping region and a non-resistive overlapping region; a resistive layer is disposed on the intermediate portion of the substrate, and both ends of the resistive layer are respectively overlapped on the upper electrode layers a first protective layer partially covering the resistive layer such that the two ends of the resistive layer are exposed to the first protective layer; the two anti-vulcanization members respectively correspond to the two outer sides of the substrate a region, each of the anti-vulcanization members is disposed on a corresponding non-resistive overlapping region of the upper electrode layer, the resistive layer is exposed at an end of the first protective layer, and a top surface of the first protective layer; Covering the surface of the first anti-vulcanization member and the first protective layer, the boundary of the second protective layer is located above the non-resistive overlapping region of the two upper electrode layers; and the electrode members at both ends respectively corresponding to the substrate The two outer regions are electrically connected to the two upper resistive layers.

The method for manufacturing the anti-vulcanized chip resistor comprises: preparing a substrate, the top surface of the substrate comprises two outer regions and an intermediate region between the outer regions; and two upper electrode layers are disposed, the two upper electrode layers are respectively disposed The top surface of each of the upper electrode layers includes a resistor overlap region and a non-resistive overlap region in the two outer regions of the substrate; a resistor layer is disposed, the resistor layer is disposed in the intermediate region of the substrate, and The two ends of the resistive layer are respectively overlapped on the resistance overlapping regions of the two upper electrode layers; a first protective layer is disposed, the first protective layer partially covering the resistive layer, and the two ends of the resistive layer are respectively exposed a first protective layer; a two-resistance vulcanizing member respectively corresponding to the two outer regions of the substrate, each of the anti-vulcanization members being disposed on a corresponding non-resistive overlapping region of the upper electrode layer, a resistive layer is exposed on an end of the first protective layer and a top surface of the first protective layer; a second protective layer is disposed, the second protective layer covering the surface of the two-resistance vulcanization member and the first protective layer a side boundary of the second protective layer is located above the non-resistive overlapping area of the two upper electrode layers; and two electrode members are disposed, the two end electrode members respectively corresponding to the two outer regions of the substrate, and are respectively electrically connected The two upper resistive layers.

According to the structure of the chip resistor, the connection interface between the anti-vulcanization member and the second protection layer forms a stepped interface, and the stepped interface is located within the coverage of the second protection layer, except by the second In addition to the vulcanization of the protective layer, since the stepped interface has a plurality of turning points, it is difficult for sulfur gas to enter the inside of the chip resistor along the stepped interface, and the anti-vulcanization effect is further achieved.

Please refer to FIG. 1. FIG. 1 is a flow chart of the creation method, and the creation method includes:

Step S1: preparing a substrate, the top surface of the substrate comprising two outer regions and an intermediate region between the outer regions.

Step S2: Two upper electrode layers are disposed, and the two upper electrode layers are respectively disposed on the two outer regions of the substrate, and the top surface of each of the upper electrode layers includes a resistor overlapping region and a non-resistive overlapping region.

Step S3: A resistor layer is disposed, the resistor layer is disposed in the intermediate region of the substrate, and both ends of the resistor layer are respectively overlapped with the resistor overlap regions of the two upper electrode layers.

Step S4: A first protective layer is disposed, the first protective layer partially covering the resistive layer, and the two ends of the resistive layer are respectively exposed to the first protective layer.

Step S5: providing a two-resistance vulcanization member respectively corresponding to the two outer regions of the substrate, each of the anti-vulcanization members being disposed on a corresponding non-resistive overlapping region of the upper electrode layer, wherein the resistance layer is exposed An end of the first protective layer and a top surface of the first protective layer.

Step S6: providing a second protective layer covering the surface of the two anti-vulcanization member and the first protective layer, the side boundary of the second protective layer being located in the non-resistive overlapping region of the two upper electrode layers Above.

Step S7: The electrode members at both ends are disposed, and the two end electrode members respectively correspond to the two outer regions of the substrate, and are respectively electrically connected to the two upper resistance layers.

The following is a description of the manufacturing process to assist in the fabrication and construction of various embodiments of the present invention for resisting vulcanization of wafer resistance.

First, the first embodiment

In step S1, referring to FIG. 2A, a substrate 10 having a top surface and a bottom surface includes a plurality of outer regions 101 and an intermediate portion 102 between the outer regions 101. The substrate 10 can be an insulating substrate. For example, the substrate 10 can be a ceramic substrate. It should be noted that the component structure disposed on the top surface of the substrate 10 is the focus of the present creation.

In step S2, referring to FIG. 2A, two upper electrode layers 21 and two lower electrode layers 22 are disposed. The two upper electrode layers 21 are respectively disposed on the outer side regions 101 of the substrate 10, so that the intermediate region 102 of the substrate 10 is provided. Exposed between the two upper electrode layers 21, wherein the outer end faces of the upper electrode layers 21 are flush with the outer end faces of the substrate 10. The top surface of each of the upper electrode layers 21 includes a resistor overlapping region 211 and a non-resistive overlapping region 212. The non-resistive overlapping region 212 is away from the intermediate region 102 of the substrate 10 with respect to the resistor overlapping region 211. The junction region 211 can abut the intermediate region 102 of the substrate 10. The two lower electrode layers 22 are disposed on the bottom surface of the substrate 10, and the positions of the two lower electrode layers 22 respectively correspond to the positions of the two upper electrode layers 21. The upper electrode layer 21 and the lower electrode layer 22 may be a metal layer, a conductive resin layer or an alloy layer.

In step S3, referring to FIG. 2B, a resistive layer 30 is disposed. The resistive layer 30 is disposed on the intermediate portion 102 of the substrate 10. The two ends 31 of the resistive layer 30 are respectively attached to the upper electrode layers 21. The resistor layer 30 is electrically connected to the two upper electrode layers 21, and the non-resistive overlapping regions 212 of the two upper electrode layers 21 are exposed to the resistor layer 30.

In step S4, referring to FIG. 2C, a first protective layer 40 is disposed. The first protective layer 40 partially covers the resistive layer 30, so that the two ends 31 of the resistive layer 30 are exposed to the first protective layer. 40. In the present creation, the first protective layer 40 preferably covers an area of 50% or more and 95% or less of the resistance layer 30. As shown in FIG. 2D, an impedance adjusting trench a is formed on the first protective layer 40 and the resistive layer 30 in a laser cutting manner, so that the top surface of the substrate 10 is exposed to the impedance adjusting trench a.

In step S5, a secondary anti-vulcanization member is provided. In the first embodiment, referring to FIG. 2E, the two anti-vulcanization layers 50 are respectively disposed, and the two anti-vulcanization layers 50 respectively correspond to the two outer regions 101 of the substrate 10 shown in FIG. 2A, wherein each of the anti-vulcanization layers The layer 50 is disposed on the corresponding non-resistive overlapping region 212 of the upper electrode layer 21, the resistive layer 30 is exposed on the end portion 31 of the first protective layer 40 and the top surface of the first protective layer 40; The anti-vulcanization layer 50 is heat-treated, for example, operating at 150 degrees Celsius or higher (including 150 degrees Celsius) and 400 degrees Celsius or lower (including 400 degrees Celsius). Referring to FIG. 2F, the top of each of the anti-sulfurization layer 50 is converted into oxidation. Layer 51. Therefore, each of the anti-vulcanization members 52 is a composite layer member and includes the aforementioned anti-vulcanization layer 50 and an oxide layer 51 formed on the top of the anti-vulcanization layer 50. In the first embodiment, a metal layer or an alloy layer may be formed by physical vapor deposition (PVD), and the metal layer or the alloy layer is used as the anti-vulcanization layer 50 shown in FIG. 2E. The surface of the metal layer or the alloy layer is further converted into a metal oxide layer by using a heat treatment method, and the metal oxide layer serves as the oxide layer 51 of FIG. 2F.

As shown in FIG. 2F, in the first embodiment, each of the anti-vulcanization members 52 is disposed on the corresponding non-resistive overlapping region 212 of the upper electrode layer 21, and the resistive layer 30 is exposed on the first protective layer. The end portion 31 of the 40 and the top surface of the first protective layer 40. One end of each of the anti-vulcanization members 52 extends to the outer edge of the upper electrode layer 21, and is flush with the outer edge of the upper electrode layer 21, that is, each of the anti-vulcanization members 52 can completely cover each of the upper electrode layers 21. The resistance overlapping portion 212; the other end of each of the anti-vulcanization members 52 is formed on the surface of the first protective layer 40, and may be located above the intermediate portion 102 of the substrate 10. The two-resistance vulcanization member 52 preferably covers an area of 5% or more and 50% or less of the first protective layer 40.

In step S6, referring to FIG. 2G, a second protective layer 60 is disposed. The second protective layer 60 covers the surface of the two-resistance vulcanization member 52 and the first protective layer 40. The side boundary 61 of the side surface of the second protective layer 60 is formed on the surface of the oxide layer 51 of the anti-vulcanization member 52, and is located above the non-resistive overlapping region 212 of the two upper electrode layers 21, that is, the first The second protective layer 60 only partially covers the two-resistance vulcanization member 52, and the outer side of the two-resistance vulcanization member 52 is exposed to the second protective layer 60.

In step S7, the electrode members at both ends are disposed to complete the chip resistance, wherein each of the terminal electrode members includes a plurality of conductor layers, and the conductor layers may be electroplated members. In the first embodiment, referring to FIG. 2H, FIG. 2I and FIG. 2J, a first conductor layer 71, a second conductor layer 72 and a third conductor layer 73 are sequentially formed to constitute each of the terminal electrode members 70. . Referring to FIG. 2H, the first conductor layer 71 covers the surface of the anti-vulcanization member 52 exposed on the second protective layer 60, the end surface of the anti-vulcanization member 52, the end surface of the upper electrode layer 21, the end surface of the substrate 10, An end surface of the lower electrode layer 22 and a partial bottom surface of the lower electrode layer 22, and an upper end of the first conductor layer 71 is connected to a side surface of the second protective layer 60, and a lower end portion of the first conductor layer 71 is located at the lower electrode The surface of layer 22. Therefore, the first conductor layer 71 is electrically connected to the upper electrode layer 21 and the lower electrode layer 22.

Referring to FIG. 2I, the second conductor layer 72 can cover and electrically connect the first conductor layer 71 and the lower electrode layer 22, wherein the upper end of the second conductor layer 72 is connected to the side of the second protection layer 60. The lower end portion of the second conductor layer 72 extends to the bottom surface of the substrate 10. Referring to FIG. 2J, the third conductor layer 73 covers and electrically connects the second conductor layer 72. The upper end of the third conductor layer 73 is connected to the side of the second protective layer 60. The third conductor layer 73 The lower end portion extends to the bottom surface of the substrate 10.

As shown in FIG. 2J, the side surface of the second protective layer 60 may be a curved surface or a sloped surface, and the first conductive layer 71, the second conductive layer 72 and the end of the third conductive layer 73 are connected to the second protection. The side surface of the layer 60 is such that the upper end of each of the end electrode members 70 covers the side surface of the second protective layer 60 as a whole.

Second, the second embodiment

For the second embodiment of the present invention, please refer to FIG. 3A to FIG. 3J, which is substantially the same as the first embodiment, FIG. 3A to FIG. 3D can refer to the steps of FIG. 2A to FIG. 2D, and FIG. It is not repeated here. The second embodiment differs from the first embodiment in steps S5 and S7.

In the step S5, the second embodiment is different from the first embodiment in the connection structure between the two-resistance vulcanization member 52 and the two upper electrode layers 21. In the second embodiment, please refer to FIG. 3E. A two-resistance vulcanization layer 50 is disposed. The two anti-vulcanization layers 50 respectively correspond to the two outer regions 101 of the substrate 10 shown in FIG. 3A, and the anti-vulcanization layer 50 is disposed on the corresponding non-resistive layer of the upper electrode layer 21. The region 212, the resistive layer 30 is exposed on the end portion 31 of the first protective layer 40 and the top surface of the first protective layer 40, wherein one end of each of the anti-vulcanization layers 50 extends only to the corresponding upper electrode layer 21 The inner side of the outer side edge, rather than the first embodiment is flush with the outer side edge of the upper electrode layer 21, so that the end of the anti-vulcanization layer 50 and the outer edge of the upper electrode layer 21 has a gap 500; Then, the two-resistance vulcanization layer 50 is subjected to heat treatment, and referring to FIG. 3F, the top of each of the anti-vulcanization layers 50 is converted into the oxide layer 51. Therefore, each of the anti-vulcanization members 52 is a composite layer member and includes the aforementioned anti-vulcanization layer 50 and an oxide layer 51 formed on the top of the anti-vulcanization layer 50.

As shown in FIG. 3F, in the second embodiment, each of the anti-vulcanization members 52 is disposed on the corresponding non-resistive overlapping region 212 of the upper electrode layer 21, and the resistive layer 30 is exposed on the first protective layer. The end portion 31 of the 40 and the top surface of the first protective layer 40 have a space 500 between one end of each of the anti-vulcanization members 52 and the outer edge of the upper electrode layer 21, so that the upper electrode layer 21 is exposed at the interval. 500. Each of the anti-vulcanization members 52 covers an area of 50% or more and 95% or less of the non-resistive overlapping regions 212 of the respective upper electrode layers 21.

In step S7, the electrode members at both ends are provided to complete the chip resistance. In the second embodiment, a first conductor layer 71 as shown in FIG. 3H, a second conductor layer 72 as shown in FIG. 3I, and a third conductor layer 73 as shown in FIG. 3J are sequentially formed. The terminal electrode member 70 is configured. Referring to FIG. 3H, the first conductor layer 71 covers the surface of the anti-vulcanization member 52 exposed on the second protection layer 60, the surface of the upper electrode layer 21 exposed on the spacer 500, and the end surface of the upper electrode layer 21, An end surface of the substrate 10, an end surface of the lower electrode layer 22, and a partial bottom surface of the lower electrode layer 22, wherein an upper end of the first conductor layer 71 is connected to a side surface of the second protective layer 60; FIG. 3I and FIG. The description of the steps of FIG. 2I and FIG. 2J is not repeated here.

Third, the third embodiment

For the third embodiment of the present authoring method, please refer to FIG. 4A to FIG. 4K, which is substantially the same as the first embodiment, and FIG. 4A to FIG. 4G can refer to the steps of FIG. 2A to FIG. 2G, which are not repeatedly described in detail. The third embodiment differs from the first embodiment in step S7.

In step S7, the electrode members at both ends are disposed to complete the wafer resistance, wherein each of the terminal electrode members includes a plurality of conductor layers. In the third embodiment, an auxiliary conductor layer 74 shown in FIG. 4H, a first conductor layer 71 shown in FIG. 4I, a second conductor layer 72 shown in FIG. 4J, and FIG. 4K are sequentially formed. A third conductor layer 73 is formed to constitute each of the terminal electrode members 70.

Referring to FIG. 4H , the auxiliary conductor layer 74 may be a cured molding member of the printed conductive paste. The auxiliary conductor layer 74 is formed on a portion of the anti-vulcanization member 52 exposed to the second protective layer 60 and the second protective layer 60 . a first section 741 is formed between the end of the auxiliary conductor layer 74 and the outer edge of the anti-vulcanization member 52, so that the surface of the anti-vulcanization member 52 is exposed to the first section 741; please refer to FIG. A conductor layer 71 is electrically connected to the auxiliary conductor layer 74. The first conductor layer 71 is formed on a partial surface of the auxiliary conductor layer 74. The anti-vulcanization member 52 is exposed on the surface of the first section 741, and the upper electrode layer 21 is exposed. An end surface, an end surface of the substrate 10, an end surface of the lower electrode layer 22, and a partial bottom surface of the lower electrode layer 22, wherein an upper end of the first conductor layer 71 and a side surface of the second protective layer 60 form a first In the second section 742, the auxiliary conductor layer 74 is exposed in the second section 742. Referring to FIG. 4J, the second conductor layer 72 covers the surface of the auxiliary conductor layer 74 exposed on the second section 742, and the first conductor layer. 71 and the lower electrode layer 22, and the second guide The upper end of the layer 72 is connected to the side of the second protective layer 60. Referring to FIG. 4K, the third conductor layer 73 covers the second conductor layer 72, and the upper end of the third conductor layer 73 is connected to the second protective layer. The side of 60.

As shown in FIG. 4K, the side surface of the second protective layer 60 may be a curved surface or a sloped surface, and the auxiliary conductor layer 74, the first conductor layer 71, the second conductor layer 72 and the third conductor layer 73 are upper. The end is connected to the side surface of the second protective layer 60. Therefore, the upper end of each of the end electrode members 70 covers the side surface of the second protective layer 60 as a whole.

Fourth, the fourth embodiment

For the fourth embodiment of the present authoring method, please refer to FIG. 5A to FIG. 5I, which is substantially the same as the first embodiment, FIG. 5A to FIG. 5D may refer to the steps of FIG. 2A to FIG. 2D, and FIG. 5F to FIG. The description of the steps in Fig. 2J is not repeated here. The fourth embodiment differs from the first embodiment in step S5.

In the step S5, the fourth embodiment is different from the first embodiment in the structure of the two-resistance vulcanizing member 52. In the fourth embodiment, please refer to FIG. 5E, and reactive vapor deposition (for example, Forming a single layer of metal nitride layer or alloy nitride layer for sputtering deposition, the single layer of metal nitride layer or alloy nitride layer as each of the anti-vulcanization members 52, so the respective anti-vulcanization members of the fourth embodiment The vulcanized member 52 is a single layer member other than the composite layer member described in the first embodiment.

In summary, please refer to FIG. 2I, FIG. 3J, FIG. 4K and FIG. 5I. The sheet resistance of the present invention includes a substrate 10, two upper electrode layers 21, a resistive layer 30, a first protective layer 40, and two The vulcanization member 52, a second protective layer 60 and the electrode members 70 at both ends. The top surface of the substrate 10 includes two outer regions 101 and an intermediate portion 102 between the outer regions 101; the upper electrode layers 21 are respectively disposed on the outer regions 101 of the substrate 10, and the upper electrodes are The outer end surface of the layer 21 is flush with the outer end surface of the substrate 10. The top surface of each of the upper electrode layers 21 includes a resistor overlapping region 211 and a non-resistive overlapping region 212. The resistor layer 30 is disposed on the substrate 10. The intermediate portion 102, and the two ends 31 of the resistive layer 30 are respectively overlapped with the resistance overlapping regions 211 of the two upper electrode layers 21; the first protective layer 40 partially covers the resistive layer 30, so that the resistive layer 30 The two end portions 31 are respectively exposed on the first protective layer 40; the positions of the two anti-vulcanization members 52 respectively correspond to the two outer regions 101 of the substrate 10, and each of the anti-vulcanization members 52 is disposed on the corresponding upper electrode The non-resistive overlapping region 212 of the layer 21, the resistive layer 30 is exposed at the end portion 31 of the first protective layer 40 and the top surface of the first protective layer 40; the second protective layer 60 covers the two-resistance vulcanizing member 52 With the surface of the first protective layer 40, the boundary of the second protective layer 60 Above the non-ohmic contact region 212 overlapping the two upper electrode layer 21; the position of the member 70 across the electrodes respectively corresponding to the two outer region 101 of the substrate 10, and the two on the resistive layer 21 are electrically connected.

As shown in FIG. 2I, FIG. 3J, FIG. 4K and FIG. 5I, since the boundary of the second protective layer 60 is located above the non-resistive overlapping region 212 of the two upper electrode layers 21, the two-resistance vulcanizing member 52 is overlapped. The end portion 31 of the resistance layer 30 and the portion of the first protective layer 40 are covered in the second protective layer 60. The connection interface between the anti-vulcanization member 52 and the second protection layer 60 forms a stepped interface, that is, the stepped interface is located within the coverage of the second protection layer 60, and the stepped interface has a plurality of transition points. Therefore, it is difficult for sulfur gas to enter the inside of the chip resistor along the stepped interface to achieve the effect of resisting vulcanization.

Referring to FIG. 2J, one end of the anti-vulcanization member 52 may be flush with the outer edge of the upper electrode layer 21; or as shown in FIG. 3J, in another embodiment, one end of the anti-vulcanization member 52 only extends to correspond The inner side of the outer edge of the upper electrode layer 21. With regard to the aspect of the anti-vulcanization member 52, referring to FIG. 2J, FIG. 3J and FIG. 4K, the anti-vulcanization member 52 may be a composite layer member comprising a vulcanization resistant layer 50 and a top formed on the top of the anti-vulcanization layer 50. The oxide layer 51 is a metal oxide layer. The atomic arrangement structure of the metal oxide layer is denser than that of the original metal layer, and can effectively block the penetration of sulfur gas into the anti-vulcanization member 52. Referring to FIG. 5I, the anti-vulcanization member 52 It may also be a single layer of nitride layer, which may be a metal nitride layer or an alloy nitride layer, the metal nitride layer or the alloy nitride layer containing nitrogen, and the anti-vulcanization member 52 by nitrogen The doping can effectively improve the microstructure compactness of the metal or alloy after sputtering to prevent or delay the infiltration of sulfur gas into the anti-vulcanization member 52.

In addition, referring to FIG. 4K, each of the terminal electrode members 70 may further include the auxiliary conductor layer 74, which may be a member formed by printing a conductive paste. Compared with the first conductor layer 71, the auxiliary conductor layer 74 has a better degree of bonding to the second protective layer 60, so that the electroconductive formed first conductor layer 71 can improve the bonding stability through the auxiliary conductor layer 74. Furthermore, for the upper electrode layer 21, the auxiliary conductor layer 74 is located above the upper electrode layer 21 to further increase the path length of the sulfur gas, so the auxiliary conductor layer 74 can also be lifted to the upper electrode. The layer 21 is resistant to vulcanization.

Taking the first embodiment of FIG. 2J and the third embodiment of FIG. 4K as an example, and performing the anti-vulcanization test (ASTM-B-809) with the conventional chip resistor structure of FIG. 6, respectively, the first embodiment of the present invention, The three examples were tested with conventional wafer resistance structures at 105 ± 2 degrees Celsius for 1000 hours. According to the test results shown in the following table, the conventional chip resistor structure has been opened. The first embodiment and the third embodiment of the present invention not only have no open circuit, but the average change rate of the resistance values before and after the test is lower than 2 %. Obviously, the resistance of the wafer resistor is more excellent in vulcanization resistance than the conventional chip resistor structure.         <TABLE border="1" borderColor="#000000" width="85%"><TBODY><tr><td> </td><td> Conventional Chip Resistor Structure</td><td> First Embodiment </td><td> Third Embodiment of the Creation </td></tr><tr><td> Maximum Rate of Change of Resistance Value</td><td> Open Circuit </td><td > 8.21% </td><td> 0.94% </td></tr><tr><td> Minimum change rate of resistance value</td><td> Open circuit</td><td> -0.09% < /td><td> 0.03% </td></tr><tr><td> Mean change rate of resistance value</td><td> open circuit</td><td> 1.23% </td><td > 0.12% </td></tr></TBODY></TABLE>

10‧‧‧Substrate
101‧‧‧Outer area
102‧‧‧Intermediate area
21‧‧‧Upper electrode layer
211‧‧‧Resistance overlap area
212‧‧‧non-resistive overlapping area
22‧‧‧ lower electrode layer
30‧‧‧resistance layer
31‧‧‧ End
40‧‧‧First protective layer
50‧‧‧Anti-sulfurization layer
51‧‧‧Oxide layer
52‧‧‧Anti-vulcanization components
500‧‧‧ interval
60‧‧‧Second protective layer
61‧‧‧ Side borders
70‧‧‧End electrode assembly
71‧‧‧First conductor layer
72‧‧‧Second conductor layer
73‧‧‧3rd conductor layer
74‧‧‧Auxiliary conductor layer
741‧‧‧First interval
742‧‧‧Second interval
80‧‧‧Substrate
81‧‧‧ electrodes
82‧‧‧resistance layer
83‧‧‧Protective layer
84‧‧‧First-end electrode layer
841‧‧‧ upper end
85‧‧‧second electrode layer
851‧‧‧ upper end
86‧‧‧Anti-sulfurization layer

Figure 1: Flow chart of this creative system. 2A to 2J are schematic cross-sectional views showing the steps of the first embodiment of the present invention in the manufacturing process. 3A to 3J are schematic cross-sectional views showing the steps of the second embodiment of the present invention in the manufacturing process. 4A to 4K are schematic cross-sectional views showing the steps of the third embodiment of the present invention in the manufacturing process. 5A to 5I are schematic cross-sectional views showing the steps of the fourth embodiment of the present invention in the manufacturing process. Figure 6 is a schematic cross-sectional view of a conventional wafer resistor. Figure 7 is a schematic cross-sectional view of another conventional wafer resistor. Figure 8: A cross-sectional view of another conventional wafer resistor.

10‧‧‧Substrate

21‧‧‧Upper electrode layer

22‧‧‧ lower electrode layer

30‧‧‧resistance layer

40‧‧‧First protective layer

52‧‧‧Anti-vulcanization components

60‧‧‧Second protective layer

70‧‧‧End electrode assembly

71‧‧‧First conductor layer

72‧‧‧Second conductor layer

73‧‧‧3rd conductor layer

Claims (15)

A vulcanization resistant wafer resistor comprising: a substrate having a top surface comprising two outer regions and an intermediate region between the outer regions; and two upper electrode layers respectively disposed on the outer regions of the substrate, each of the The top surface of the upper electrode layer includes a resistor overlapping region and a non-resistive overlapping region; a resistive layer is disposed on the intermediate portion of the substrate, and both ends of the resistive layer are respectively overlapped on the upper electrode layers a first protective layer partially covering the resistive layer such that the two ends of the resistive layer are exposed to the first protective layer; the two anti-vulcanization members respectively correspond to the two outer sides of the substrate a region, each of the anti-vulcanization members is disposed on a corresponding non-resistive overlapping region of the upper electrode layer, the resistive layer is exposed at an end of the first protective layer, and a top surface of the first protective layer; Covering the surface of the first anti-vulcanization member and the first protective layer, the boundary of the second protective layer is located above the non-resistive overlapping region of the two upper electrode layers; and the electrode members at both ends respectively corresponding to the substrate The two outer regions are electrically connected to the two upper resistive layers. The vulcanization resistant chip resistance according to claim 1, wherein each of the anti-vulcanization members is a composite layer member comprising a vulcanization resistant layer and an oxide layer formed on top of the anti-sulfurization layer, and the oxide layer is a metal oxide layer . Each of the anti-vulcanization members is a single layer nitride layer as claimed in claim 1. The vulcanization resistant chip resistance according to claim 3, wherein each of the anti-vulcanization members is a nitride layer selected from the group consisting of a metal nitride layer and an alloy nitride layer. The vulcanization resistant wafer resistance according to any one of claims 1 to 4, wherein one end of each of the anti-vulcanization members is flush with an outer edge of each of the upper electrode layers. The sheet resistance of the vulcanization resistant material according to any one of claims 1 to 4, wherein a gap between one end of each of the anti-vulcanization members and an outer edge of the upper electrode layer is such that each of the upper electrode layers is exposed at the interval . The sheet resistance of the vulcanization resistant material according to claim 5, wherein each of the end electrode members comprises a plurality of conductor layers to cover a surface of each of the anti-vulcanization members exposed to the second protective layer, an end surface of each of the anti-vulcanization members, and each of the surfaces An end surface of the upper electrode layer and an end surface of each of the substrates. The sheet resistance of the vulcanization resistant material according to claim 6, wherein each of the end electrode members comprises a plurality of conductor layers to cover a surface of each of the anti-vulcanization members exposed on the second protective layer, and each of the upper electrode layers is exposed at the interval The surface, the end surface of each of the upper electrode layers, and the end surface of the substrate. The anti-vulcanized wafer resistor according to claim 7, wherein each of the terminal electrode members comprises an auxiliary conductor layer formed at a portion of each of the anti-vulcanization members exposed to the second protective layer and the second protective layer The side surface defines a section between the end of the auxiliary conductor layer and the outer edge of the anti-vulcanization member; and the conductor layers of each of the end electrode members are further formed on the surface of the anti-vulcanization member exposed to the section. The chip resistance of the vulcanization resistant material according to any one of claims 1 to 4, wherein the first protective layer covers an area of 50% or more and 95% or less of the resistance layer. The vulcanization resistant chip resistance according to any one of claims 1 to 4, wherein the two-resistance vulcanizing member covers an area of 5% or more and 50% or less of the first protective layer. The vulcanization resistant wafer resistance according to claim 6, wherein each of the anti-vulcanization members covers an area of 50% or more and 95% or less of each of the non-resistive overlapping regions of the upper electrode layer. A method for resisting vulcanization of a wafer resistor, comprising: preparing a substrate, wherein a top surface of the substrate comprises two outer regions and an intermediate region between the outer regions; and two upper electrode layers are disposed, the two upper electrode layers are respectively disposed The top surface of each of the upper electrode layers includes a resistor overlap region and a non-resistive overlap region in the two outer regions of the substrate; a resistor layer is disposed, the resistor layer is disposed in the intermediate region of the substrate, and The two ends of the resistive layer are respectively overlapped on the resistance overlapping regions of the two upper electrode layers; a first protective layer is disposed, the first protective layer partially covering the resistive layer, and the two ends of the resistive layer are respectively exposed a first protective layer; a two-resistance vulcanizing member respectively corresponding to the two outer regions of the substrate, each of the anti-vulcanization members being disposed on a corresponding non-resistive overlapping region of the upper electrode layer, a resistive layer is exposed on an end of the first protective layer and a top surface of the first protective layer; a second protective layer is disposed, the second protective layer covering the surface of the two-resistance vulcanization member and the first protective layer a side boundary of the second protective layer is located above the non-resistive overlapping area of the two upper electrode layers; and two electrode members are disposed, the two end electrode members respectively corresponding to the two outer regions of the substrate, and are respectively electrically connected The two upper resistive layers. The method for preparing a vulcanization resistant chip resistance according to claim 13, wherein the step of disposing each of the anti-vulcanization members comprises: disposing a two-resistance vulcanization layer on the two outer regions of the substrate; and subjecting the two anti-vulcanization layer to heat treatment In one embodiment, the top of each of the anti-sulfurization layers is converted into an oxide layer, and each of the anti-vulcanization members is a composite layer member comprising the aforementioned anti-sulfurization layer and the oxide layer formed on the top of the anti-sulfurization layer. The method for producing a vulcanization resistant wafer resistance according to claim 13, wherein in the step of disposing each of the anti-vulcanization members, a single layer of a nitride layer is formed by reactive vapor deposition to serve as each of the anti-vulcanization members.