CN217485176U - Chip resistor substrate layer and reinforced combination structure of resistance layer - Google Patents
Chip resistor substrate layer and reinforced combination structure of resistance layer Download PDFInfo
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- CN217485176U CN217485176U CN202221051298.5U CN202221051298U CN217485176U CN 217485176 U CN217485176 U CN 217485176U CN 202221051298 U CN202221051298 U CN 202221051298U CN 217485176 U CN217485176 U CN 217485176U
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Abstract
The utility model provides a chip resistor substrate layer and resistance layer strengthen bonding structure, it is the top surface at a substrate layer and forms a pair of top surface conductive metal layer, and forms a pair of back conductive metal layer in the bottom surface of substrate layer. A resistance layer is formed on the substrate layer and between the pair of top conductive metal layers, and is respectively electrically connected with the pair of top conductive metal layers. The reinforced bonding layer is used for enhancing the interface bonding strength between the resistor layer and the top surface of the base material layer, so that the resistor layer is not peeled off from the top surface of the base material layer in the sintering process.
Description
Technical Field
The utility model discloses a chip resistor, especially a chip resistor substrate layer and the intensive integrated configuration of resistive layer.
Background
Chip resistors have been widely used in various electronic devices, instrument devices, and communication devices. The chip resistor is divided into two types, i.e., a thick film chip resistor and a thin film chip resistor, wherein the electrode and the resistive layer of the thick film chip resistor are manufactured by Printing and sintering (Sinter) techniques, and the electrode and the resistive layer of the thin film chip resistor are manufactured by sputtering (Sputter) techniques.
In a typical conventional chip resistor structure, the chip resistor structure mainly includes a substrate layer, a pair of back conductive metal layers formed on the back of the substrate layer, a pair of top conductive metal layers formed on the top of the substrate layer, a resistor layer covering a portion of the surface of the top of the substrate layer corresponding to the top conductive metal layers, and an insulating protection layer covering the surface of the resistor layer. The two end electrodes of the substrate layer are respectively and sequentially formed with a conductive layer, a nickel layer and a tin layer.
In the above known chip resistor structure, the resistance value across the chip resistor depends on the resistance value of the resistive layer. The substrate layer is generally made of a ceramic material or an alumina material, and the resistive layer is mainly made of a metal material (e.g., Ag, Pd, Ru, Pt, NiCr, NiCrAl, CuNi, CuNiMn, FeCrAl, etc.). The preparation material of the resistance layer is formed on the surface of the substrate layer after coating and sintering processes, and is electrically communicated between two corresponding top surface conductive metal layers.
However, it has been found that, in the sintering process of the resistance layer, since the material characteristics of the base layer and the resistance layer are different (for example, the ratio of ceramic components contained in the materials of the base layer and the resistance layer), the resistance layer often fails to achieve good interface bonding with the surface of the base layer, and the resistance layer is peeled off or partially separated from the surface of the base layer in the sintering process. In this way, not only the bonding stability between the resistive layer and the base material layer in terms of mechanical characteristics but also the problem in terms of electrical characteristics of the resistive layer may be affected.
SUMMERY OF THE UTILITY MODEL
The main objective of the present invention is to provide an improved structure of a chip resistor, which can overcome the disadvantages of the prior art by improving the structure of the chip resistor.
The present invention is to provide a method for solving the problems of the prior art, in which a pair of top conductive metal layers are formed on the top surface of a substrate layer, and a pair of back conductive metal layers are formed on the back surface of the substrate layer. A resistance layer is formed on the substrate layer and located between the pair of top surface conductive metal layers, and is respectively electrically communicated with the pair of top surface conductive metal layers. The enhanced bonding layer is used for enhancing the interface bonding strength between the top surfaces of the resistance layer and the base material layer, so that the resistance layer is not peeled off from the top surface of the base material layer in the sintering process.
In order to achieve the above object, the present invention provides a reinforced combination structure of a chip resistor substrate layer and a resistor layer, comprising:
a substrate layer having two end poles;
a pair of top surface conductive metal layers respectively formed on the top surface of the substrate layer, and a space is formed between the pair of top surface conductive metal layers;
a pair of back conductive metal layers respectively formed on the back of the substrate layer, and a space is formed between the pair of back conductive metal layers;
the resistance layer is formed on the substrate layer, positioned between the pair of top surface conductive metal layers and respectively electrically communicated with the pair of top surface conductive metal layers;
wherein:
a reinforced bonding layer is also arranged between the resistor layer and the top surface of the substrate layer;
the reinforced bonding layer covers the middle section of the top surface of the substrate layer, and two uncovered sections are reserved at the two ends of the substrate layer respectively;
the pair of top surface conductive metal layers are respectively positioned on the uncovered section of the base material layer and a part of surfaces of two ends of the reinforced bonding layer;
the resistor layer is located on the surface of the strengthening bonding layer and a part of the surface corresponding to the pair of top surface conductive metal layers.
The utility model also provides a strengthening bonding structure of chip resistor substrate layer and resistance layer, include:
a substrate layer having two end poles;
a pair of top conductive metal layers respectively formed on the top surface of the substrate layer, and a space is formed between the pair of top conductive metal layers;
a pair of back conductive metal layers respectively formed on the back of the substrate layer, and a space is formed between the pair of back conductive metal layers;
the resistance layer is formed on the substrate layer, is positioned between the pair of top surface conductive metal layers and is respectively and electrically communicated with the pair of top surface conductive metal layers;
wherein:
a reinforced bonding layer is also arranged between the resistor layer and the top surface of the substrate layer;
the reinforced bonding layer covers the whole surface of the top surface of the base material layer;
the pair of top surface conductive metal layers are respectively positioned on the surfaces of two ends of the reinforced combination layer adjacent to the two end poles of the base material layer;
the resistive layer is disposed on a surface of the reinforcing bonding layer and a portion of a surface of the pair of top conductive metal layers.
The utility model also provides a chip resistor substrate layer and resistance layer strengthen bonding structure, include:
a substrate layer having two end poles;
a pair of top conductive metal layers respectively formed on the top surface of the substrate layer, and a space is formed between the pair of top conductive metal layers;
a pair of back conductive metal layers respectively formed on the back of the substrate layer, and a space is formed between the pair of back conductive metal layers;
the resistance layer is formed on the substrate layer, is positioned between the pair of top surface conductive metal layers and is respectively and electrically communicated with the pair of top surface conductive metal layers;
wherein:
a reinforced bonding layer is also arranged between the resistor layer and the top surface of the substrate layer;
the reinforced bonding layer covers the middle section of the top surface of the base material layer, and two sections which are not covered are reserved at the two ends of the base material layer respectively;
the pair of top conductive metal layers are respectively positioned on the uncovered section of the base material layer and a part of the surfaces of two ends of the reinforced bonding layer;
the resistive layer is located between the surface of the reinforcing bonding layer and the pair of top conductive metal layers.
The utility model also provides a chip resistor substrate layer and resistance layer strengthen bonding structure, include:
a substrate layer having two end poles;
a pair of top conductive metal layers respectively formed on the top surface of the substrate layer, and a space is formed between the pair of top conductive metal layers;
a pair of back conductive metal layers respectively formed on the back of the substrate layer, and a space is formed between the pair of back conductive metal layers;
the resistance layer is formed on the substrate layer, is positioned between the pair of top surface conductive metal layers and is respectively and electrically communicated with the pair of top surface conductive metal layers;
wherein:
a reinforced bonding layer is also arranged between the resistor layer and the top surface of the substrate layer;
the reinforced bonding layer covers the whole surface of the top surface of the base material layer;
the pair of top surface conductive metal layers are respectively positioned on the surfaces of two ends of the reinforced combination layer adjacent to the two end poles of the base material layer;
the resistive layer is located between the surface of the reinforcing bonding layer and the pair of top conductive metal layers.
According to a particular embodiment of the invention, wherein the reinforcing bonding layer comprises a ceramic material.
According to a specific embodiment of the present invention, wherein, this substrate layer is a ceramic material or an alumina substrate layer.
Compare in well-known technique in the structural design of the utility model, through the intensive anchor coat that forms between resistance layer and substrate layer, can effectively strengthen the interface joint intensity between the top surface of resistance layer and substrate layer, make this resistance layer not peeled off by the top surface of this substrate layer in sintering process, make resistance layer and substrate layer reach good combination between the two.
The specific structure of the present invention will be further described with reference to the following embodiments and accompanying drawings.
Drawings
Fig. 1 is a structural sectional view of embodiment 1 of the present invention.
Fig. 2 is a structural sectional view of embodiment 2 of the present invention.
Fig. 3 is a structural sectional view of embodiment 3 of the present invention.
Fig. 4 is a structural sectional view of embodiment 4 of the present invention.
Description of the symbols:
1: substrate layer
11. 12: terminal pole
2: reinforced bond ply
31. 32: back conductive metal layer
33. 34: top surface conductive metal layer
4: resistance layer
41: laser trimming groove
42: staged structure
5: glass layer
6: insulating protective layer
71: conductive layer
72: nickel layer
73: tin layer
Detailed Description
Referring to fig. 1, which is a cross-sectional view of the embodiment 1 of the present invention, the chip resistor mainly includes a substrate layer 1, and the substrate layer 1 may be a ceramic substrate layer made of a ceramic material or one of alumina substrate layers made of an alumina material.
The back side of the substrate layer 1 is printed to form a pair of back side conductive metal layers 31 and 32, and a space is formed between the pair of back side conductive metal layers 31 and 32.
The top surface of the substrate layer 1 is formed with a reinforcing bonding layer 2 in a middle section, and an uncovered section is reserved at a distance from each of two ends of the substrate layer 1, so that a corresponding pair of top conductive metal layers 33 and 34 are formed on the uncovered section of the top surface of the substrate layer 1 and a part of the surface of each of the two ends of the reinforcing bonding layer 2.
The strengthening bonding layer 2 comprises a ceramic material and glass. The reinforcing bonding layer 2 may be made of a filler (e.g., Al) 2 O 3 、ZnO、SiO 2 、TiO 2 ) Sintering aids (e.g. SiO) 2 、BaO、B 2 O 3 、Al 2 O 3 、V 2 O 5 ZnO), resin, and organic solvent, and then formed on the top surface of the base material layer 1 through a sintering process at a predetermined temperature (e.g., 900 ℃).
Then, a resistor layer 4 is covered on the surface of the reinforcing bonding layer 2 and a portion of the surface corresponding to the pair of top conductive metal layers 33, 34. Thus, both ends of the resistive layer 4 are electrically connected to the pair of top conductive metal layers 33, 34. The resistive layer 4 may include a laser trimming groove 41 therein, which precisely trims the resistive layer 4 to a set resistance value using laser energy.
The resistive layer 4 is mainly made of a metal material (e.g., Ag, Pd, Ru, Pt, NiCr, NiCrAl, CuNi, CuNiMn, FeCrAl, etc.). The resistor layer 4 is formed on the surface of the reinforcing bonding layer 2 and a part of the surface of the pair of top conductive metal layers 33 and 34 corresponding thereto by a sintering process after being coated on the reinforcing bonding layer 2 and the pair of top conductive metal layers 33 and 34.
Compared with the prior art, the structural design of the present invention can effectively enhance the interface bonding strength between the top surfaces of the resistance layer 4 and the substrate layer 1 by the reinforced bonding layer formed between the resistance layer 4 and the substrate layer 1, so that the resistance layer 4 is not peeled off by the top surface of the substrate layer 1 in the sintering process.
After the resistive layer 4 is completed, a glass layer 5 is formed on the surface of the resistive layer 4 and an insulating protection layer 6 covers a portion of the surface of the glass layer 5, the resistive layer 4, and the pair of top conductive metal layers 33 and 34.
Finally, a conductive layer 71 is formed on the side wall surfaces of the two terminals 11, 12 of the substrate layer 1 and a part of the surfaces of the back conductive metal layers 31, 32 and the top conductive metal layers 33, 34 to electrically connect the pair of back conductive metal layers 31, 32 and the pair of top conductive metal layers 33, 34, respectively, and a nickel layer 72 and a tin layer 73 are sequentially formed on the surface of the conductive layer 71.
Fig. 2 is a structural sectional view of embodiment 2 of the present invention. The constituent elements of this embodiment are substantially the same as those of embodiment 1, and the same components are denoted by the same component numbers. In the present embodiment, the substrate layer 1, the reinforcing bonding layer 2, the back conductive metal layers 31 and 32, the top conductive metal layers 33 and 34, the resistive layer 4, the glass layer 5, the insulating protective layer 6, the conductive layer 71, the nickel layer 72, the tin layer 73, and the like are also included. However, the reinforced bonding layer 2 covers the entire surface of the top surface of the substrate layer 1, the pair of top conductive metal layers 33 and 34 are respectively located on the surfaces of the two ends of the reinforced bonding layer 2 adjacent to the two end electrodes 11 and 12 of the substrate layer 1, and the resistor layer 4 is located on the surface of the reinforced bonding layer 2 and a portion of the surface corresponding to the pair of top conductive metal layers 33 and 34.
Fig. 3 is a structural sectional view of embodiment 3 of the present invention. The constituent members of this embodiment are substantially the same as those of the foregoing embodiment 1. In the present embodiment, the substrate layer 1, the reinforcing bonding layer 2, the back conductive metal layers 31 and 32, the top conductive metal layers 33 and 34, the resistive layer 4, the glass layer 5, the insulating protective layer 6, the conductive layer 71, the nickel layer 72, the tin layer 73, and the like are also included. The reinforcing bonding layer 2 also covers a middle section of the top surface of the substrate layer 1, while leaving an uncovered section away from each of the two terminals 11, 12 of the substrate layer 1. However, the pair of top conductive metal layers 33, 34 are respectively located on the uncovered section of the base material layer 1 and a part of the surfaces of both ends of the reinforcing bonding layer 2. The resistor layer 4 is located between the surface of the strengthening bonding layer 2 and the pair of top conductive metal layers 33, 34, and the surface of the resistor layer 4 and the surfaces of the pair of top conductive metal layers 33, 34 are in the same plane. In addition, the two ends of the resistive layer 4 and the connection between the pair of top conductive metal layers 33 and 34 are in a step structure 42.
Fig. 4 is a structural sectional view of embodiment 4 of the present invention. The constituent members of the present embodiment are substantially the same as those of the foregoing embodiment 2. In the present embodiment, the substrate layer 1, the reinforcing bonding layer 2, the back conductive metal layers 31 and 32, the top conductive metal layers 33 and 34, the resistive layer 4, the glass layer 5, the insulating protective layer 6, the conductive layer 71, the nickel layer 72, the tin layer 73, and the like are also included. The reinforcing bonding layer 2 covers the entire surface of the top face of the base material layer 1, and the pair of top conductive metal layers 33, 34 are respectively located at both ends of the reinforcing bonding layer 2 adjacent to the surfaces of the two end poles 11, 12 of the base material layer 1. The resistive layer 4 is located between the surface of the reinforcing bonding layer 2 and the pair of top conductive metal layers 33, 34, and the surface of the resistive layer 4 and the surfaces of the pair of top conductive metal layers 33, 34 are coplanar. In addition, the two ends of the resistive layer 4 and the connection between the pair of top conductive metal layers 33, 34 are respectively in a step structure 42.
In the above embodiments, the resistive layer is disposed on the top surface of the substrate layer as an example. In practical application, the resistor layer can be designed to be located on the back surface of the substrate layer, and a reinforcing bonding layer is also arranged between the lower resistor layer and the back surface of the substrate layer. Furthermore, the utility model discloses also can use in the product that has the bilayer resistance layer, set up resistance layer and resistance layer once respectively on the top surface of substrate layer and the back promptly, and all set up a intensive anchor coat respectively between the top surface of upper resistance layer and this substrate layer and between the back of resistance layer and this substrate layer down.
The above-mentioned embodiments are merely illustrative and not intended to limit the scope of the present invention, and all other equivalent modifications and substitutions which do not depart from the spirit of the present invention are intended to be included within the scope of the appended claims.
Claims (6)
1. A strengthened combination structure of a substrate layer and a resistance layer of a chip resistor comprises:
a substrate layer having two end poles;
a pair of top conductive metal layers respectively formed on the top surface of the substrate layer, and a space is formed between the pair of top conductive metal layers;
a pair of back conductive metal layers respectively formed on the back of the substrate layer, and a space is formed between the pair of back conductive metal layers;
the resistance layer is formed on the substrate layer, positioned between the pair of top surface conductive metal layers and respectively electrically communicated with the pair of top surface conductive metal layers;
the method is characterized in that:
a reinforced bonding layer is also arranged between the resistor layer and the top surface of the substrate layer;
the reinforced bonding layer covers the middle section of the top surface of the base material layer, and two sections which are not covered are reserved at the two ends of the base material layer respectively;
the pair of top conductive metal layers are respectively positioned on the uncovered section of the base material layer and a part of the surfaces of two ends of the reinforced bonding layer;
the resistive layer is disposed on a surface of the reinforcing bonding layer and a portion of a surface of the pair of top conductive metal layers.
2. A strengthened combination structure of a substrate layer and a resistance layer of a chip resistor comprises:
a substrate layer having two end poles;
a pair of top surface conductive metal layers respectively formed on the top surface of the substrate layer, and a space is formed between the pair of top surface conductive metal layers;
a pair of back conductive metal layers respectively formed on the back of the substrate layer, and a space is formed between the pair of back conductive metal layers;
the resistance layer is formed on the substrate layer, is positioned between the pair of top surface conductive metal layers and is respectively and electrically communicated with the pair of top surface conductive metal layers;
the method is characterized in that:
a reinforced bonding layer is also arranged between the resistor layer and the top surface of the substrate layer;
the reinforced bonding layer covers the whole surface of the top surface of the substrate layer;
the pair of top surface conductive metal layers are respectively positioned at the two ends of the reinforced bonding layer and adjacent to the surfaces of the two end electrodes of the substrate layer;
the resistive layer is disposed on a surface of the reinforcing bonding layer and a portion of a surface of the pair of top conductive metal layers.
3. A strengthened combination structure of a substrate layer and a resistance layer of a chip resistor comprises:
a substrate layer having two end poles;
a pair of top surface conductive metal layers respectively formed on the top surface of the substrate layer, and a space is formed between the pair of top surface conductive metal layers;
a pair of back conductive metal layers respectively formed on the back of the substrate layer, and a space is formed between the pair of back conductive metal layers;
the resistance layer is formed on the substrate layer, positioned between the pair of top surface conductive metal layers and respectively electrically communicated with the pair of top surface conductive metal layers;
the method is characterized in that:
a reinforced bonding layer is also arranged between the resistor layer and the top surface of the substrate layer;
the reinforced bonding layer covers the middle section of the top surface of the substrate layer, and two uncovered sections are reserved at the two ends of the substrate layer respectively;
the pair of top conductive metal layers are respectively positioned on the uncovered section of the base material layer and a part of the surfaces of two ends of the reinforced bonding layer;
the resistive layer is located between the surface of the reinforcing bonding layer and the pair of top conductive metal layers.
4. A reinforced combination structure of a chip resistor substrate layer and a resistor layer comprises the following components:
a substrate layer having two end poles;
a pair of top conductive metal layers respectively formed on the top surface of the substrate layer, and a space is formed between the pair of top conductive metal layers;
a pair of back conductive metal layers respectively formed on the back of the substrate layer, and a space is formed between the pair of back conductive metal layers;
the resistance layer is formed on the substrate layer, is positioned between the pair of top surface conductive metal layers and is respectively and electrically communicated with the pair of top surface conductive metal layers;
the method is characterized in that:
a reinforced bonding layer is also arranged between the resistor layer and the top surface of the substrate layer;
the reinforced bonding layer covers the whole surface of the top surface of the base material layer;
the pair of top surface conductive metal layers are respectively positioned on the surfaces of two ends of the reinforced combination layer adjacent to the two end poles of the base material layer;
the resistive layer is located between the surface of the reinforcing bonding layer and the pair of top conductive metal layers.
5. The chip resistor substrate layer and resistive layer reinforced bond structure of any of claims 1-4, wherein the reinforced bond layer comprises a ceramic material.
6. The chip resistor substrate layer and resistive layer reinforced combination structure as claimed in any one of claims 1-4, wherein the substrate layer is a ceramic material or alumina substrate layer.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW110208608U TWM621420U (en) | 2021-07-22 | 2021-07-22 | Reinforced bonding structure of chip resistor base material layer and resistance layer |
| TW110208608 | 2021-07-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN217485176U true CN217485176U (en) | 2022-09-23 |
Family
ID=80680705
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202221051298.5U Active CN217485176U (en) | 2021-07-22 | 2022-05-05 | Chip resistor substrate layer and reinforced combination structure of resistance layer |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP3238285U (en) |
| CN (1) | CN217485176U (en) |
| TW (1) | TWM621420U (en) |
-
2021
- 2021-07-22 TW TW110208608U patent/TWM621420U/en unknown
-
2022
- 2022-05-05 CN CN202221051298.5U patent/CN217485176U/en active Active
- 2022-05-16 JP JP2022001584U patent/JP3238285U/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| JP3238285U (en) | 2022-07-13 |
| TWM621420U (en) | 2021-12-21 |
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