TWI603654B - Circuit board and method for manufacturing the same - Google Patents

Description

Circuit board and its making method

The present invention relates to a circuit board and a method of fabricating the same.

As the development of consumer electronics has become the mainstream of technology products, such as personal computers, notebook computers, smart phones, digital cameras or other portable electronic products, and it has also received enthusiastic attention in the consumer market. Here, the development of portable electronic products is the focus of development in recent years. In response to this, the demand for circuit boards installed in portable electronic products has also increased. In the process of circuit board, the production cost of the board is related to its yield. When the yield of the produced circuit board is better, the production cost of the board can also be reduced. Therefore, improving the board's yield has become one of the most important research and development topics.

One embodiment of the present invention provides a method of fabricating a circuit board in which an automatic optical inspection of a circuit layer can be performed after forming a circuit layer, thereby determining the state of the circuit layer. Furthermore, the step of performing an automatic optical inspection of the wiring layer is earlier than the step of performing the layering process, thereby preventing The materials used in the renewal process are at risk of being scrapped.

One embodiment of the present invention provides a circuit board disposed on a substrate, wherein the circuit board includes a dielectric layer and a circuit layer. The dielectric layer is disposed on the substrate. The circuit layer is buried in the dielectric layer and has a plurality of traces, wherein each trace has an opposite first upper surface and a first lower surface, the first lower surface faces the substrate, and the first upper surface is exposed from the dielectric layer And a vertical projection area of the first upper surface on the substrate is smaller than a vertical projection area of the first lower surface on the substrate.

In some embodiments, the dielectric layer has a second upper surface, the second upper surface facing away from the substrate, wherein a minimum vertical distance between the first upper surface and the substrate is D1, and a minimum vertical distance between the second upper surface and the substrate is D2 And 2 microns ≧ (D2-D1) > 0 microns.

In some embodiments, each of the traces has at least one side surface, the side surface is located between the first upper surface and the first lower surface, and connects the first upper surface and the first lower surface, and the side surface is composed of a dielectric layer cover.

In some embodiments, the side surface is rounded near the first upper surface and covered by a dielectric layer.

An embodiment of the present invention provides a method of fabricating a circuit board, including the following steps. Forming a first metal layer on the substrate and forming a second metal layer on the first metal layer, and the first metal layer comprises a material different from the material included in the second metal layer. Forming a pattern layer on the second metal layer and forming a third metal layer on the second metal layer through the pattern layer, and the second metal layer comprises the same material as the third metal layer. The pattern layer and a portion of the second metal layer are removed, and the remaining combination of the second metal layer and the third metal layer becomes a wiring layer.

In some embodiments, the method for manufacturing the circuit board further includes The line layer performs automatic optical inspection (AOI) to determine whether to make a layering process for the circuit layer.

In some embodiments, the build-up process includes forming a dielectric layer on the wiring layer, wherein the wiring layer is coated between the first metal layer and the dielectric layer.

In some embodiments, the fabrication method further includes removing the substrate and removing the first metal layer from the wiring layer and the dielectric layer.

In some embodiments, the material of the first metal layer comprises a first metal, the material of the circuit layer comprises a second metal, and the light reflectivity of the first metal is different from the light reflectivity of the second metal.

In some embodiments, the step of removing a portion of the second metal layer includes removing a portion of the second metal layer through the etchant, and the first metal layer has an etch rate to the etchant that is less than an etch rate of the second metal layer to the solvent.

100‧‧‧ boards

102‧‧‧First substrate

104‧‧‧ peeling layer

105‧‧‧Auxiliary metal layer

106‧‧‧First metal layer

108‧‧‧Second metal layer

110‧‧‧pattern layer

112‧‧‧ Third metal layer

113‧‧‧Line layer

114‧‧‧Wiring

116‧‧‧Dielectric layer

118‧‧‧second substrate

D1, D2‧‧‧ distance

L‧‧‧beam

S1‧‧‧ first upper surface

S2‧‧‧ first lower surface

S3‧‧‧ side surface

S4‧‧‧Second upper surface

1A to 1I are side cross-sectional views showing different steps of a method for fabricating a circuit board according to some embodiments of the present invention.

The embodiments of the present invention are disclosed in the following drawings, and the details of However, it should be understood that these practical details are not intended to limit the invention. That is, in some embodiments of the invention, these practical details are not necessary. In addition, some conventional structures and components are used to simplify the drawing. The drawings will be illustrated in a simple schematic manner.

In view of the correlation between the production cost of the board and its yield, increasing the yield of the board will reduce the scrap cost of the board. In the method of fabricating the circuit board of the present invention, the circuit layer can be detected after the formation of the circuit layer, thereby judging whether the formed circuit layer is suitable for subsequent processes. Therefore, the cost of wasting subsequent processes can be avoided.

1A to 1I are side cross-sectional views showing different steps of a method for fabricating a circuit board according to some embodiments of the present invention. Please see Figure 1A. In this stage, the peeling layer 104 and the auxiliary metal layer 105 are first formed on the first substrate 102. The first substrate 102 can be used as a carrier substrate. The release layer 104 may be a colloid layer, and the material of the auxiliary metal layer 105 may comprise copper, such as a copper foil. Next, a first metal layer 106 is formed on the auxiliary metal layer 105, and a second metal layer 108 is formed on the first metal layer 106. The first metal layer 106 and the second metal layer 108 may be formed by sputtering or electroplating. The material of the first metal layer 106 may be different from the material of the second metal layer 108 such that the material properties of the first metal layer 106 are different from the material properties of the second metal layer 108. For example, the material of the first metal layer 106 may comprise titanium, and the material of the second metal layer 108 may comprise copper such that the light reflectivity of the first metal layer 106 may be different than the light reflectivity of the second metal layer 108. Alternatively, in other embodiments, the material of the first metal layer 106 may comprise a dark color metal such as titanium, nickel, chromium, manganese, or iron, whereby the copper has a significant difference in gloss.

Please see Figure 1B. In this stage, the pattern layer 110 is formed on the second metal layer 108, and a portion of the second metal layer 108 is exposed through the pattern layer 110. The material of the pattern layer 110 may be a photoresist. Specifically, it can be formed first A layer of photoresist is on the second metal layer 108. Next, the photoresist layer is subjected to a mask process to form the pattern layer 110 after development.

Please see the 1C chart and the 1D chart. In this stage, the third metal layer 112 is formed on the second metal layer 108 through the pattern layer 110. Specifically, the pattern layer 110 can serve as a mask, and the third metal layer 112 can be formed on the second metal layer 108 by electroplating. The second metal layer 108 may comprise the same material as the third metal layer 112. For example, the materials of the second metal layer 108 and the third metal layer 112 may comprise copper. In addition, the process parameters for forming the second metal layer 108 may be different from the process parameters for forming the third metal layer 112 such that the density of the third metal layer 112 is greater than the density of the second metal layer 108, or The thickness of the metal layer 112 is greater than the thickness of the second metal layer 108. After the third metal layer 112 is formed, the pattern layer 110 is removed. After the pattern layer 110 is removed, a portion of the second metal layer 108 is exposed by the third metal layer 112.

Please see Figure 1E. In this stage, the second metal layer 108 exposed by the third metal layer 112 can be removed by etching. Specifically, since the density and thickness of the third metal layer 112 are respectively greater than the density and thickness of the second metal layer 108, the second metal layer 108 exposed by the third metal layer 112 can be removed by an etchant. In addition, the etch rate of the etchant by the first metal layer 106 may be less than the etch rate of the etchant by the second metal layer 108, such that the first metal layer 106 can serve as a termination layer for the etch process, and the remaining second metal layer 108 At the junction with the first metal layer 106, it will have a rounded shape. After the etching process, the combination of the remaining second metal layer 108 and the third metal layer 112 may become the wiring layer 113, the circuit layer 113 may have a plurality of traces 114, and a portion of the first metal layer 106 may be formed by the wiring layer 113. Exposed.

Please see the 1F picture. At this stage, the wiring layer 113 and the first metal layer 106 are irradiated with the light beam L to perform automatic optical inspection (AOI) on the wiring layer 113. In the automatic optical detection, after the light beam L is irradiated, the image of the circuit layer 113 and the first metal layer 106 is extracted through a charge-coupled device (CCD). Next, through the different contrast ratios of the circuit layer 113 and the first metal layer 106 in the image, it is determined whether the circuit layer 113 has an unexpected condition, such as a short circuit or an open circuit. In other words, since the light reflectance of the first metal layer 106 is different from the light reflectance of the circuit layer 113, it can be judged whether or not the circuit layer 113 has an unexpected condition. After the automatic optical detection, when the yield performance of the circuit layer 113 falls within an appropriate condition, it is determined that the circuit layer 113 can be subjected to a subsequent process, such as a build-up process.

Please see the 1G, 1H, and 1I. In this stage, the wiring layer 113 is subjected to a build-up process, wherein the build-up process includes forming a dielectric layer 116 on the wiring layer 113 and forming a second substrate 118 on the dielectric layer 116, and the wiring layer 113 is coated on the circuit layer 113. Between the first metal layer 106 and the dielectric layer 116. The second substrate 118 can be used as a transfer substrate. Then, the first substrate 102 can be detached from the auxiliary metal layer 105 through the peeling layer 104, thereby removing the first substrate 102 and the peeling layer 104 and exposing the auxiliary metal layer 105. After the first substrate 102 is removed, the auxiliary metal layer 105 and the first metal layer 106 are removed from the circuit layer 113 and the dielectric layer 116, thereby exposing the circuit layer 113. For example, the auxiliary metal can be removed by etching. Layer 105 and first metal layer 106. Next, the combination of the wiring layer 113, the dielectric layer 116, and the second substrate 118 is reversed to obtain the circuit board 100 as shown in FIG.

The circuit board 100 fabricated through the above process can have a strong For structural strength and to improve the yield of subsequent surface mount technology (SMT) processes, please see the following instructions. As shown in FIG. 1I, the dielectric layer 116 and the wiring layer 113 of the circuit board 100 are located on the second substrate 118, and the wiring layer 113 is buried in the dielectric layer 116. Each of the traces 114 of the wiring layer 113 has a first first upper surface S1 and a first lower surface S2 and a side surface S3. The first lower surface S2 of the trace 114 faces the second substrate 118, and the first upper surface S1 of the trace 114 is exposed from the dielectric layer 116, and the first upper surface S1 of the trace 114 is perpendicular to the second substrate 118. The projected area is smaller than the vertical projected area of the first lower surface S2 of the trace 114 on the second substrate 118. The side surface S3 of the trace 114 is located between the first upper surface S1 and the first lower surface S2, and connects the first upper surface S1 and the first lower surface S2, and the side surface S3 presents a circle near the first upper surface S1. angle. The side surface S3 of the trace 114 is covered by the dielectric layer 116, and the portion of the side surface S3 of the trace 114 that is rounded is also covered by the dielectric layer 116.

In the case where the vertical projection area of the first upper surface S1 of the trace 114 on the second substrate 118 is smaller than the vertical projection area of the first lower surface S2 of the trace 114 on the second substrate 118, due to the side surface S3 of the trace 114 The portion of the rounded corner is covered by the dielectric layer 116, so that the trace 114 of the wiring layer 113 can be prevented from falling off from the dielectric layer 116, thereby improving the structural strength of the circuit board 100.

On the other hand, the dielectric layer 116 has a second upper surface S4 and the second upper surface S4 faces away from the second substrate 118. In the process of the circuit board 100, the second metal layer 108 exposed by the third metal layer 112 (see FIG. 1D and FIG. 1E) is removed by etching (see FIG. 1D and FIG. 1E). The step is earlier than the step of performing the build-up process, so that the step difference between the first upper surface S1 of the trace 114 and the second upper surface S4 of the dielectric layer 116 can be reduced. In the present embodiment, the trace 114 The minimum vertical distance between the first upper surface S1 and the second substrate 118 is the distance D1, and the minimum vertical distance between the second upper surface S4 of the dielectric layer 116 and the second substrate 118 is the distance D2, and 2 micrometers (distance D2) - Distance D1) > 0 microns. In other embodiments, the first upper surface S1 of the trace 114 and the second upper surface S4 of the dielectric layer 116 are substantially coplanar. Since the step difference between the first upper surface S1 of the trace 114 and the second upper surface S4 of the dielectric layer 116 is reduced, it is convenient to provide a solder ball (not shown) on the first upper surface S1 of the trace 114. In order to improve the yield of the subsequent surface adhesion process.

In summary, the method for fabricating the circuit board of the present invention can perform automatic optical detection on the circuit layer after forming the circuit layer, thereby judging the state of the circuit layer. Furthermore, the step of performing an automated optical inspection of the circuit layer is earlier than the step of the build-up process to prevent the risk of scrapping the materials used in subsequent processes. In addition, in the process of the circuit board, since the step of removing a portion of the second metal layer is earlier than the step of performing the build-up process, the dielectric layer can have better coverage to the trace of the circuit layer, thereby preventing the line. The traces of the layers are detached from the dielectric layer and enhance the structural strength of the board.

While the invention has been described above in terms of various embodiments, it is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application attached.

105‧‧‧Auxiliary metal layer

106‧‧‧First metal layer

113‧‧‧Line layer

L‧‧‧beam

Claims (10)

A circuit board is disposed on a substrate, and the circuit board comprises: a dielectric layer disposed on the substrate: and a circuit layer buried in the dielectric layer and having a plurality of traces, wherein each of the traces The wire has a first upper surface facing away from the substrate, the first upper surface is exposed from the dielectric layer, and a vertical projection of the first upper surface on the substrate The area is smaller than a vertical projected area of the first lower surface on the substrate. The circuit board of claim 1, wherein the dielectric layer has a second upper surface facing away from the substrate, wherein a minimum vertical distance between the first upper surface and the substrate is D1, and The minimum vertical distance between the second upper surface and the substrate is D2, and 2 microns ≧(D2-D1)>0 microns. The circuit board of claim 1, wherein each of the traces has at least one side surface between the first upper surface and the first lower surface, and connects the first upper surface and the a first lower surface, and the side surface is covered by the dielectric layer. The circuit board of claim 1, wherein the side surface is rounded near the first upper surface and covered by the dielectric layer. A method of manufacturing a circuit board, comprising: Forming a first metal layer on a substrate, and forming a second metal layer on the first metal layer, and the first metal layer comprises a material different from the material contained in the second metal layer; forming a The pattern layer is on the second metal layer, and a third metal layer is formed on the second metal layer through the pattern layer, and the second metal layer comprises the same material as the third metal layer And removing the pattern layer and a portion of the second metal layer, and the remaining combination of the second metal layer and the third metal layer becomes a wiring layer. The method for manufacturing a circuit board according to claim 5, further comprising: performing automatic optical inspection (AOI) on the circuit layer, thereby determining whether to perform a build-up process on the circuit layer. The method of fabricating a circuit board of claim 6, wherein the layering process comprises: forming a dielectric layer on the circuit layer, wherein the circuit layer is coated on the first metal layer and the dielectric layer between. The manufacturing method of the circuit board of claim 7, further comprising: removing the substrate, and removing the first metal layer from the circuit layer and the dielectric layer. The method of manufacturing the circuit board of claim 5, wherein the material of the first metal layer comprises a first metal, the material of the circuit layer comprises a second metal, and the light reflectance of the first metal is different from The light reflectivity of the second metal. The method of manufacturing the circuit board of claim 5, wherein the removing the portion of the second metal layer comprises: removing a portion of the second metal layer through an etchant, and the first metal layer is the etchant The etch rate is less than the etch rate of the etchant by the second metal layer.