CN108401361B

CN108401361B - Circuit board and manufacturing method thereof

Info

Publication number: CN108401361B
Application number: CN201710064199.8A
Authority: CN
Inventors: 黄敬皓; 李和兴; 林有成
Original assignee: Unimicron Technology Corp
Current assignee: Unimicron Technology Corp
Priority date: 2017-02-04
Filing date: 2017-02-04
Publication date: 2020-08-07
Anticipated expiration: 2037-02-04
Also published as: CN108401361A

Abstract

The invention discloses a circuit board and a manufacturing method thereof. The dielectric layer is disposed on the substrate. The circuit layer is embedded in the dielectric layer and is provided with a plurality of routing lines, wherein each routing line is provided with a first upper surface and a first lower surface which are opposite, the first lower surface faces the substrate, the first upper surface is exposed out of the dielectric layer, and the vertical projection area of the first upper surface on the substrate is smaller than that of the first lower surface on the substrate. Therefore, the wiring of the circuit layer can be prevented from falling off from the dielectric layer, and the structural strength of the circuit board is improved.

Description

Circuit board and manufacturing method thereof

Technical Field

The invention relates to a circuit board and a manufacturing method thereof.

Background

As the development of consumer electronics products becomes the mainstream of science and technology products, such as personal computers, notebook computers, smart phones, digital cameras or other portable electronic products, it has been also strongly concerned in the consumer market. In this regard, the development of portable electronic products is more important in recent years. Accordingly, the demand for circuit boards disposed in portable electronic products is also increasing. In the process of the circuit board, the production cost of the circuit board has correlation with the qualified rate thereof. When the qualification rate of the produced circuit board is better, the production cost of the circuit board can be reduced. Therefore, increasing the yield of the circuit board has become one of the important research and development issues.

Disclosure of Invention

The present invention provides a method for manufacturing a circuit board, which can perform automatic optical detection on a circuit layer after the circuit layer is formed in the manufacturing process of the circuit board so as to determine the state of the circuit layer. Moreover, the step of performing automatic optical detection on the circuit layer is earlier than the step of performing the layer-adding process, so that the risk that materials used in the subsequent process are scrapped is prevented.

One embodiment of the invention provides a circuit board disposed on a substrate, the circuit board including a dielectric layer and a circuit layer. The dielectric layer is disposed on the substrate. The circuit layer is embedded in the dielectric layer and is provided with a plurality of routing lines, wherein each routing line is provided with a first upper surface and a first lower surface which are opposite, the first lower surface faces the substrate, the first upper surface is exposed out of the dielectric layer, and the vertical projection area of the first upper surface on the substrate is smaller than that of the first lower surface on the substrate.

In some embodiments, the dielectric layer has a second upper surface facing away from the substrate, wherein a minimum vertical distance between the first upper surface and the substrate is D1, and a minimum vertical distance between the second upper surface and the substrate is D2, and 2 μm ≧ (D2-D1) >0 μm.

In some embodiments, each of the traces has at least one side surface, the side surface is located between and connects the first upper surface and the first lower surface, and the side surface is covered by the dielectric layer.

In some embodiments, the side surface is rounded proximate the first upper surface and is covered by the dielectric layer.

An embodiment of the invention provides a method for manufacturing a circuit board, including the following steps. A first metal layer is formed on a substrate, a second metal layer is formed on the first metal layer, and the material of the first metal layer is different from that of the second metal layer. And forming a pattern layer on the second metal layer, and forming a third metal layer on the second metal layer through the pattern layer, wherein the material contained in the second metal layer is the same as that contained in the third metal layer. And removing the pattern layer and part of the second metal layer, and combining the rest second metal layer and the third metal layer to form the circuit layer.

In some embodiments, the method for manufacturing a circuit board further includes performing Automatic Optical Inspection (AOI) on the circuit layer to determine whether to perform a layer adding process on the circuit layer.

In some embodiments, the build-up process includes forming a dielectric layer on the line layer, wherein the line layer is encapsulated between the first metal layer and the dielectric layer.

In some embodiments, the method further includes removing the substrate and removing the first metal layer from the circuit layer and the dielectric layer.

In some embodiments, the material of the first metal layer includes a first metal, the material of the circuit layer includes a second metal, and the light reflectivity of the first metal is different from the light reflectivity of the second metal.

In some embodiments, the step of removing the portion of the second metal layer includes removing the portion of the second metal layer by an etchant, and an etching rate of the first metal layer to the etchant is less than an etching rate of the second metal layer to the solvent.

Compared with the prior art, the invention has the advantages of preventing the wiring of the circuit layer from falling off from the dielectric layer and improving the structural strength of the circuit board.

Drawings

Fig. 1A to 1I are schematic side cross-sectional views illustrating a manufacturing method of a circuit board at different stages according to some embodiments of the invention.

Detailed Description

In the following description, numerous implementation details are set forth in order to provide a thorough understanding of the present invention. It should be understood, however, that these implementation details are not to be interpreted as limiting the invention. That is, in some embodiments of the invention, such implementation details are not necessary. In addition, for the sake of simplicity, some conventional structures and elements are shown in the drawings in a simple schematic manner.

In view of the correlation between the production cost of the circuit board and the qualification rate of the circuit board, the improvement of the qualification rate of the circuit board can reduce the scrapping cost of the circuit board. In the manufacturing method of the circuit board, the circuit layer can be detected after the circuit layer is formed, so as to judge whether the formed circuit layer is suitable for subsequent processes. Therefore, the cost spent in the subsequent process can be avoided.

Fig. 1A to 1I are schematic side cross-sectional views illustrating a manufacturing method of a circuit board at different stages according to some embodiments of the invention. Please see fig. 1A. At this stage, the peeling layer 104 and the auxiliary metal layer 105 are formed on the first substrate 102. The first substrate 102 may be used as a carrier substrate. The peeling layer 104 may be a colloidal layer, and the material of the auxiliary metal layer 105 may include copper, such as copper foil. Next, a first metal layer 106 is formed on the auxiliary metal layer 105, and a second metal layer 108 is formed on the first metal layer 106. The first metal layer 106 and the second metal layer 108 may be formed by sputtering or plating. The material of the first metal layer 106 may be different from the material of the second metal layer 108, such that the material characteristics of the first metal layer 106 are different from the material characteristics of the second metal layer 108. For example, the material of the first metal layer 106 may include titanium, and the material of the second metal layer 108 may include copper, such that the light reflectivity of the first metal layer 106 may be different from the light reflectivity of the second metal layer 108.

Please see fig. 1B. At this stage, a pattern layer 110 is formed on the second metal layer 108, and a portion of the second metal layer 108 may be exposed through the pattern layer 110. The material of the patterning layer 110 may be photoresist. Specifically, a photoresist layer may be formed on the second metal layer 108. Then, a photo-masking process is performed on the photoresist layer to form the pattern layer 110 after development.

Please see fig. 1C and fig. 1D. At this stage, a third metal layer 112 is formed on the second metal layer 108 by the pattern layer 110. Specifically, the pattern layer 110 may serve as a mask (mask), and the third metal layer 112 may be formed on the second metal layer 108 by electroplating. The material of the second metal layer 108 may be the same as the material of the third metal layer 112, for example, the material of the second metal layer 108 and the third metal layer 112 may include copper. In addition, the process parameters for forming the second metal layer 108 and the process parameters for forming the third metal layer 112 may be different, so that the density of the third metal layer 112 is greater than that of the second metal layer 108. After the third metal layer 112 is formed, the pattern layer 110 is removed. After the patterned layer 110 is removed, a portion of the second metal layer 108 is exposed by the third metal layer 112.

Please see fig. 1E. At this stage, the second metal layer 108 exposed by the third metal layer 112 may be removed by etching. Specifically, since the density of the third metal layer 112 is greater than the density and thickness of the second metal layer 108, the second metal layer 108 exposed by the third metal layer 112 can be removed by an etchant. In addition, the etching rate of the first metal layer 106 to the etchant may be smaller than that of the second metal layer 108 to the etchant, so that the first metal layer 106 may be used as a stop layer of the etching process, and the remaining second metal layer 108 may have a rounded corner shape at the interface with the first metal layer 106. After the etching process, the combination of the remaining second metal layer 108 and the third metal layer 112 may become the circuit layer 113, the circuit layer 113 has a plurality of traces 114, and a portion of the first metal layer 106 is exposed from the circuit layer 113.

At this stage, please see fig. 1f, the light beam L is irradiated on the circuit layer 113 and the first metal layer 106 to perform an Automatic Optical Inspection (AOI) on the circuit layer 113, in the automatic optical inspection, after the light beam L is irradiated, images of the circuit layer 113 and the first metal layer 106 are captured by a charge-coupled device (CCD) and then, whether an unexpected condition, such as a short circuit or an open circuit, occurs in the circuit layer 113 is determined according to different contrasts of the circuit layer 113 and the first metal layer 106 in the images, in other words, whether the unexpected condition occurs in the circuit layer 113 is determined according to a difference between a light reflectance of the first metal layer 106 and a light reflectance of the circuit layer 113, and after the automatic optical inspection, when a yield of the circuit layer 113 is in a proper condition, it is determined that a subsequent process, such as a layer adding process, may be performed on the circuit layer 113.

Please see fig. 1G, fig. 1H and fig. 1I. At this stage, a build-up process is performed on the circuit layer 113, wherein the build-up process includes forming a dielectric layer 116 on the circuit layer 113 and forming a second substrate 118 on the dielectric layer 116, and the circuit layer 113 is wrapped between the first metal layer 106 and the dielectric layer 116. The second substrate 118 may serve as a transfer substrate. Then, the first substrate 102 may be separated from the auxiliary metal layer 105 by the peeling layer 104, so that the first substrate 102 and the peeling layer 104 are removed and the auxiliary metal layer 105 is exposed. After removing the first substrate 102, the auxiliary metal layer 105 and the first metal layer 106 are removed from the circuit layer 113 and the dielectric layer 116, so as to expose the circuit layer 113, for example, the auxiliary metal layer 105 and the first metal layer 106 may be removed by etching. Then, the assembly of the circuit layer 113, the dielectric layer 116 and the second substrate 118 is inverted to obtain the circuit board 100 as shown in fig. 1I.

The circuit board 100 manufactured by the above process has a strong structural strength and can improve the yield of a Surface Mount Technology (SMT) process performed subsequently, as described below. As shown in fig. 1I, the dielectric layer 116 and the circuit layer 113 of the circuit board 100 are disposed on the second substrate 118, and the circuit layer 113 is embedded in the dielectric layer 116. Each trace 114 of the circuit layer 113 has a first upper surface S1, a first lower surface S2 and a side surface S3 opposite to each other. The first lower surface S2 of the trace 114 faces the second substrate 118, the first upper surface S1 of the trace 114 is exposed from the dielectric layer 116, and a vertical projection area of the first upper surface S1 of the trace 114 on the second substrate 118 is smaller than a vertical projection area of the first lower surface S2 of the trace 114 on the second substrate 118. The side surface S3 of the trace 114 is located between the first upper surface S1 and the first lower surface S2 and connects the first upper surface S1 and the first lower surface S2, and the side surface S3 is rounded near the first upper surface S1. The side surface S3 of the trace 114 is covered by the dielectric layer 116, and the rounded portion of the side surface S3 of the trace 114 is also covered by the dielectric layer 116.

In a case that the vertical projection area of the first upper surface S1 of the trace 114 on the second substrate 118 is smaller than the vertical projection area of the first lower surface S2 of the trace 114 on the second substrate 118, since the rounded portion of the side surface S3 of the trace 114 is covered by the dielectric layer 116, the trace 114 of the circuit layer 113 can be prevented from falling off the dielectric layer 116, thereby enhancing the structural strength of the circuit board 100.

On the other hand, the dielectric layer 116 has a second upper surface S4, and the second upper surface S4 faces away from the second substrate 118. Since the step of removing the second metal layer 108 (see fig. 1D and 1E) exposed by the third metal layer 112 (see fig. 1D and 1E) by etching is earlier than the step of performing the build-up process in the process of the circuit board 100, the step difference between the first upper surface S1 of the trace 114 and the second upper surface S4 of the dielectric layer 116 can be reduced. In this embodiment, the minimum vertical distance between the first upper surface S1 of the trace 114 and the second substrate 118 is D1, and the minimum vertical distance between the second upper surface S4 of the dielectric layer 116 and the second substrate 118 is D2, which is greater than or equal to 2 micrometers ≧ (distance D2-distance D1) >0 micrometer. In other embodiments, the first top surface S1 of the trace 114 and the second top surface S4 of the dielectric layer 116 are substantially coplanar. Since the step difference between the first top surface S1 of the trace 114 and the second top surface S4 of the dielectric layer 116 is reduced, solder balls (not shown) can be conveniently disposed on the first top surface S1 of the trace 114, thereby improving the yield of the subsequent surface mount process.

In summary, the manufacturing method of the circuit board of the invention can perform automatic optical detection on the circuit layer after the circuit layer is formed, so as to determine the state of the circuit layer. Moreover, the step of performing automatic optical detection on the circuit layer is earlier than the step of performing the layer-adding process, so that the risk that materials used in the subsequent process are scrapped is prevented. In addition, in the process of the circuit board, the step of removing part of the second metal layer is earlier than the step of performing the layer adding process, so that the dielectric layer can have better wrapping property on the routing of the circuit layer, thereby preventing the routing of the circuit layer from falling off from the dielectric layer and improving the structural strength of the circuit board.

While the present invention has been described with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A circuit board disposed on a substrate, the circuit board comprising:

a dielectric layer disposed on the substrate; and

the circuit layer is embedded in the dielectric layer and provided with a plurality of routing lines, each routing line is provided with a first upper surface and a first lower surface which are opposite, the first lower surface faces the substrate, the first upper surface is exposed out of the dielectric layer, the vertical projection area of the first upper surface on the substrate is smaller than that of the first lower surface on the substrate, the circuit layer is formed by combining a second metal layer and a third metal layer, the first upper surface is located on the second metal layer, the first lower surface is located on the third metal layer, the density of the third metal layer is larger than that of the second metal layer, each routing line is provided with at least one side surface, and the side surface is in a round angle close to the first upper surface and is covered by the dielectric layer.

2. The circuit board of claim 1, wherein the dielectric layer has a second upper surface facing away from the substrate, wherein the first upper surface is at a minimum perpendicular distance D1 from the substrate, and the second upper surface is at a minimum perpendicular distance D2 from the substrate of 2 μm ≧ (D2-D1) >0 μm.

3. The circuit board of claim 1, wherein the side surface is located between and connects the first upper surface and the first lower surface, and the side surface is covered by the dielectric layer.

4. A method for manufacturing a circuit board, comprising:

forming a first metal layer on a substrate, and forming a second metal layer on the first metal layer, wherein the material of the first metal layer is different from the material of the second metal layer;

forming a pattern layer on the second metal layer, and forming a third metal layer on the second metal layer through the pattern layer, wherein the material contained in the second metal layer is the same as the material contained in the third metal layer, and the density of the third metal layer is greater than that of the second metal layer;

removing the pattern layer and a part of the second metal layer, and combining the remaining second metal layer and the third metal layer to form a circuit layer, wherein the circuit layer has a plurality of wires, each wire has at least one side surface, each wire has a first upper surface and a first lower surface opposite to each other, the first upper surface faces the substrate, and the side surface has a rounded corner adjacent to the first upper surface;

carrying out automatic optical detection on the circuit layer so as to judge whether a layer adding process is carried out on the circuit layer or not; and

and forming a dielectric layer on the circuit layer, wherein the circuit layer is wrapped between the first metal layer and the dielectric layer, the material of the first metal layer comprises a first metal, the material of the circuit layer comprises a second metal, and the light reflectivity of the first metal is different from that of the second metal.

5. The method of manufacturing a circuit board according to claim 4, further comprising:

and removing the substrate and the first metal layer from the circuit layer and the dielectric layer.

6. The method of claim 4, wherein the step of removing a portion of the second metal layer comprises:

and removing part of the second metal layer by an etchant, wherein the etching rate of the first metal layer to the etchant is less than that of the second metal layer to the etchant.