TWI602217B - Method for thinning a wafer and thinned wafer structure - Google Patents

Method for thinning a wafer and thinned wafer structure Download PDF

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TWI602217B
TWI602217B TW105143089A TW105143089A TWI602217B TW I602217 B TWI602217 B TW I602217B TW 105143089 A TW105143089 A TW 105143089A TW 105143089 A TW105143089 A TW 105143089A TW I602217 B TWI602217 B TW I602217B
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wafer
cross
pattern
thinning method
back surface
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TW201810361A (en
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三重野文健
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上海新昇半導體科技有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30608—Anisotropic liquid etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means

Description

一種晶圓薄化方法及薄化的晶圓結構 Wafer thinning method and thinned wafer structure

本發明係關於微電子技術領域，尤其係關於一種晶圓薄化方法及薄化的晶圓結構。 The present invention relates to the field of microelectronics, and more particularly to a wafer thinning method and a thinned wafer structure.

隨著記憶體和功率裝置等應用朝著更小尺寸、更高性能的方向發展，對薄晶圓的需求也日益增長。更薄的晶圓能夠帶來眾多好處，包括超薄的封裝，以及由此帶來更小的尺寸外形，還包括改善的電氣性能和更好的散熱性能。現階段，最常規的半導體應用薄化技術為磨削。TAIKO技術是由迪思科科技有限公司開發的晶圓背面磨削技術，這項技術和以往的背面磨削不同，在對晶片進行磨削時，將保留晶片週邊的邊緣部分，只對圓內進行磨削薄型化。這種在晶圓週邊留邊的TAIKO晶圓在功率裝置和BSI型CMOS圖像感測器中有重要應用。 As applications such as memory and power devices move toward smaller sizes and higher performance, the demand for thin wafers is growing. Thinner wafers offer a number of benefits, including ultra-thin packages, and the resulting smaller form factor, including improved electrical performance and better thermal performance. At this stage, the most conventional semiconductor application thinning technology is grinding. TAIKO technology is a wafer back grinding technology developed by Di Cisco Technology Co., Ltd. This technology is different from the conventional back grinding. When the wafer is ground, the edge portion of the wafer periphery is retained, and only the inside of the circle is performed. Grinding is thinner. This TAIKO wafer with a peripheral edge around the wafer has important applications in power devices and BSI-type CMOS image sensors.

TAIKO技術需要特別精細的研磨工具，例如專利文獻JP2007173487A所記載的研磨加工裝置，該裝置的特殊設計可以對晶圓中心部分研磨，而保留晶圓週邊的邊緣。但是，IC頂層結構還有較多的製造步驟，由於結構較薄，機械研磨引發的應力很容易造成晶圓的破裂，例如功率裝置需要覆蓋大約5μm厚的聚醯亞胺，在晶圓薄化至100μm時幾乎都會 出現破裂。專利文獻JP2007335659A提供了採用濕式薄化製作TAIKO晶圓的方法，然而該方法需要的步驟較多，操作繁瑣。此外，由於太薄，這種TAIKO晶圓通常直徑相對較小，例如，200mm、150mm。這種TAIKO技術很難應用於直徑450mm以上的晶圓。 The TAIKO technology requires a particularly fine grinding tool, such as the one described in the patent document JP2007173487A, which is specially designed to grind the center portion of the wafer while retaining the edges of the periphery of the wafer. However, there are many manufacturing steps in the top structure of the IC. Due to the thin structure, the stress caused by mechanical polishing can easily cause cracking of the wafer. For example, the power device needs to cover about 5 μm thick polyimine, which is thinned in the wafer. Almost to 100μm A rupture occurred. Patent document JP2007335659A provides a method of fabricating a TAIKO wafer by wet thinning, however, the method requires many steps and is cumbersome to operate. In addition, such TAIKO wafers are typically relatively small in diameter, for example, 200 mm, 150 mm, due to being too thin. This TAIKO technology is difficult to apply to wafers with a diameter of 450 mm or more.

因此，實有必要尋求一種可減少晶圓破損、應用於較大尺寸的晶圓薄化方法。 Therefore, it is necessary to find a wafer thinning method that can reduce wafer damage and be applied to a larger size.

有鑒於此，本發明目的在於提供一種晶圓薄化方法及薄化的晶圓結構，用於解決習知TAIKO技術難以應用於直徑450mm以上晶圓的問題。 In view of the above, an object of the present invention is to provide a wafer thinning method and a thinned wafer structure for solving the problem that the conventional TAIKO technology is difficult to apply to a wafer having a diameter of 450 mm or more.

為實現上述目的及其他相關目的，本發明提供一種晶圓薄化方法，包括如下步驟：提供一晶圓，所述晶圓包括正面和背面，所述正面形成有IC裸芯；薄化所述晶圓並在所述晶圓背面形成凸出的圖形結構，所述圖形結構包括位於所述晶圓週邊邊緣的環形結構以及位於所述環形結構內的交叉圖形結構。 To achieve the above and other related objects, the present invention provides a wafer thinning method comprising the steps of: providing a wafer comprising a front side and a back side, the front side being formed with an IC bare core; The wafer also forms a convex pattern structure on the back side of the wafer, the pattern structure including an annular structure at a peripheral edge of the wafer and a cross-pattern structure located within the annular structure.

較佳地，所述圖形結構中，所述環形結構的寬度為4-7mm，所述交叉圖形結構的線條寬度為4-7mm。 Preferably, in the graphic structure, the annular structure has a width of 4-7 mm, and the cross pattern structure has a line width of 4-7 mm.

較佳地，所述圖形結構中，所述交叉圖形結構為十字形結構。 Preferably, in the graphic structure, the cross graphic structure is a cross structure.

較佳地，薄化所述晶圓並在所述晶圓背面形成凸出的圖形結構的方法包括：在所述晶圓背面形成光罩層；在所述晶圓背面的光罩層上光刻形成圖形化的光阻層，所述圖形化的光阻 層包括覆蓋所述晶圓週邊邊緣的環形部分以及位於所述環形內的交叉圖形部分；進行第一蝕刻，去除光罩層中未被所述光阻層覆蓋的部分，將所述光阻層上的圖形傳遞到所述光罩層上，然後去除所述光阻層；及進行第二蝕刻，去除所述光罩層和晶圓背面的部分區域，將所述光罩層上的圖形傳遞到所述晶圓的背面，在所述晶圓背面得到凸出的圖形結構，所述圖形結構包括位於所述晶圓週邊邊緣的環形結構以及位於所述環形結構內的交叉圖形結構。 Preferably, the method of thinning the wafer and forming a convex pattern on the back surface of the wafer comprises: forming a mask layer on the back surface of the wafer; and illuminating the mask layer on the back side of the wafer Forming a patterned photoresist layer, the patterned photoresist The layer includes an annular portion covering the peripheral edge of the wafer and a cross-pattern portion located within the ring; performing a first etching to remove a portion of the mask layer not covered by the photoresist layer, the photoresist layer Transferring the upper pattern to the mask layer, and then removing the photoresist layer; and performing a second etching to remove portions of the mask layer and the back side of the wafer to transfer the pattern on the mask layer To the back side of the wafer, a raised pattern structure is obtained on the back side of the wafer, the pattern structure including an annular structure at the peripheral edge of the wafer and a cross-pattern structure located within the annular structure.

進一步較佳地，所述光罩層為氧化矽層。 Further preferably, the photomask layer is a ruthenium oxide layer.

進一步較佳地，形成所述光罩層的方法為化學氣相沈積四乙氧基矽烷(tetraethyl orthosilicate，TEOS)材料。 Further preferably, the method of forming the photomask layer is chemical vapor deposition of a tetraethyl orthosilicate (TEOS) material.

進一步較佳地，所述第一蝕刻為採用氟化氫(HF)的濕式蝕刻。 Further preferably, the first etch is a wet etch using hydrogen fluoride (HF).

進一步較佳地，所述第二蝕刻為採用氫氧化四甲基銨(tetramethylammonium hydroxide，TMAH)的濕式蝕刻。 Further preferably, the second etching is wet etching using tetramethylammonium hydroxide (TMAH).

進一步較佳地，在所述晶圓背面形成光罩層之前，在所述晶圓背面先採用研磨或濕式蝕刻的方法將所述晶圓薄化。 Further preferably, before the photomask layer is formed on the back surface of the wafer, the wafer is thinned by grinding or wet etching on the back surface of the wafer.

進一步較佳地，在所述晶圓背面得到凸出的圖形結構之後，在所述晶圓背面繼續採用研磨的方法將所述晶圓薄化。 Further preferably, after the protruding pattern structure is obtained on the back side of the wafer, the wafer is further thinned by grinding on the back side of the wafer.

進一步較佳地，研磨所述晶圓背面的凸出的圖形結構之外的部分。 Further preferably, a portion other than the convex pattern structure on the back side of the wafer is ground.

較佳地，薄化所述晶圓並在所述晶圓背面形成凸出的圖形結 構的方法為：在所述晶圓背面進行研磨，僅保留位於所述晶圓週邊邊緣的環形區域和位於所述環形區域內的交叉繪圖區域之外的部分。 Preferably, the wafer is thinned and a convex pattern is formed on the back side of the wafer The method is as follows: grinding is performed on the back side of the wafer, leaving only the annular region located at the peripheral edge of the wafer and the portion outside the intersecting drawing region in the annular region.

進一步較佳地，採用兩個直徑不同的研磨頭進行研磨。 Further preferably, the grinding is performed using two grinding heads having different diameters.

為實現上述目的及其他相關目的，本發明還提供一種薄化的晶圓結構，其中，所述晶圓包括正面和背面；所述晶圓正面形成有IC裸芯；所述晶圓背面形成有凸出的圖形結構，所述圖形結構包括位於所述晶圓週邊邊緣的環形結構以及位於所述環形結構內的交叉圖形結構。 To achieve the above and other related objects, the present invention also provides a thinned wafer structure, wherein the wafer includes a front side and a back side; the wafer front side is formed with an IC bare core; and the wafer back surface is formed with A raised pattern structure comprising an annular structure at a peripheral edge of the wafer and a cross-sectional structure within the annular structure.

較佳地，所述圖形結構凸出的厚度為500-800nm。 Preferably, the pattern structure has a thickness of 500-800 nm.

較佳地，所述圖形結構中，所述環形結構的寬度為4-7mm，所述交叉圖形結構的線條寬度為4-7mm。 Preferably, in the graphic structure, the annular structure has a width of 4-7 mm, and the cross pattern structure has a line width of 4-7 mm.

較佳地，所述圖形結構中，所述交叉圖形結構為十字形結構。 Preferably, in the graphic structure, the cross graphic structure is a cross structure.

如上所述，本發明的晶圓薄化方法及裝置，具有以下有益效果：本發明利用薄化技術在晶圓背面形成凸出的交叉圖形結構以及環形邊緣，從而可提高晶圓強度，減少晶圓破損。利用本發明的技術方案可以實現較大尺寸的晶圓薄化和應用，例如直徑450mm以上的晶圓。 As described above, the wafer thinning method and apparatus of the present invention have the following beneficial effects: the present invention utilizes a thinning technique to form a convex cross-pattern structure and a ring-shaped edge on the back surface of the wafer, thereby improving wafer strength and reducing crystals. The circle is broken. A larger size wafer thinning and application can be realized by the technical solution of the present invention, for example, a wafer having a diameter of 450 mm or more.

S1~S2、S101~S105‧‧‧步驟 S1~S2, S101~S105‧‧‧ steps

101‧‧‧圖形結構 101‧‧‧graphic structure

1011‧‧‧環形結構 1011‧‧‧ ring structure

1012‧‧‧交叉圖形結構 1012‧‧‧cross graphic structure

第1圖為本發明提供的晶圓薄化方法的示意圖。 FIG. 1 is a schematic view of a wafer thinning method provided by the present invention.

第2圖為，依據本發明之一實施例，薄化的晶圓結構示意圖。 2 is a schematic view of a thinned wafer structure in accordance with an embodiment of the present invention.

第3圖為，依據本發明之一實施例，晶圓薄化方法的示意圖。 3 is a schematic diagram of a wafer thinning method in accordance with an embodiment of the present invention.

以下結合圖式和具體實施例對本發明進一步詳細說明。根據本案說明書及申請專利範圍，本發明的優點及特徵將更清楚。需說明的是， 圖式均採用非常簡化的形式，且均使用非精準的比例，僅用以方便、明晰地輔助說明本發明實施例的目的。 The invention is further described in detail below in conjunction with the drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the description and claims. It should be noted that The drawings are in a very simplified form, and both use non-precise proportions, and are merely for convenience and clarity of the purpose of the embodiments of the invention.

請參閱第1圖，本發明提供一種晶圓薄化方法，包括如下步驟：S1：提供一晶圓，所述晶圓包括正面和背面，所述正面形成有IC裸芯；S2：薄化所述晶圓並在所述晶圓背面形成凸出的圖形結構，所述圖形結構包括位於所述晶圓週邊邊緣的環形結構以及位於所述環形結構內的交叉圖形結構。 Referring to FIG. 1 , the present invention provides a wafer thinning method, comprising the steps of: S1: providing a wafer, the wafer includes a front side and a back side, and the front side is formed with an IC bare core; S2: thinning station The wafer is formed on the back side of the wafer to form a convex pattern structure, the pattern structure including an annular structure at a peripheral edge of the wafer and a cross-pattern structure located within the annular structure.

具體地，所述圖形結構中，所述環形結構的寬度可以為4-7mm，所述交叉圖形結構的線條寬度可以為4-7mm。所述交叉圖形結構較佳為十字形結構。 Specifically, in the graphic structure, the width of the annular structure may be 4-7 mm, and the line width of the intersecting graphic structure may be 4-7 mm. The cross-pattern structure is preferably a cross-shaped structure.

請參閱第2圖，本發明還提供一種薄化的晶圓結構，其中：所述晶圓包括正面和背面；所述晶圓正面形成有IC裸芯；所述晶圓背面形成有凸出的圖形結構101，所述圖形結構101包括位於所述晶圓週邊邊緣的環形結構1011以及位於所述環形結構內的交叉圖形結構1012。 Referring to FIG. 2, the present invention further provides a thinned wafer structure, wherein: the wafer includes a front side and a back side; the front side of the wafer is formed with an IC bare core; and the back side of the wafer is formed with a convex A graphics structure 101 includes an annular structure 1011 at a peripheral edge of the wafer and a cross-pattern structure 1012 located within the annular structure.

具體地，所述圖形結構101中，所述環形結構1011的寬度可以為4-7mm，所述交叉圖形結構1012的線條寬度可以為4-7mm。所述交叉圖形結構1012較佳為十字形結構。所述圖形結構101凸出的厚度可以為500-800nm。 Specifically, in the graphic structure 101, the width of the annular structure 1011 may be 4-7 mm, and the line width of the intersecting graphic structure 1012 may be 4-7 mm. The cross-pattern structure 1012 is preferably a cross-shaped structure. The pattern structure 101 may have a thickness of 500-800 nm.

本發明利用晶圓背面的交叉圖形結構可以提高晶圓強度，減少晶圓破損，從而實現較大尺寸的晶圓薄化和應用。 The invention utilizes the cross-pattern structure on the back side of the wafer to improve the wafer strength and reduce wafer damage, thereby achieving larger size wafer thinning and application.

下面通過具體的實例來詳細說明本發明的技術方案。 The technical solution of the present invention will be described in detail below by way of specific examples.

實施例一 Embodiment 1

請參閱第3圖，本實施例利用圖形化技術和濕式蝕刻方法薄化晶圓並在晶圓背面形成凸出的圖形結構，包括以下步驟： Referring to FIG. 3, this embodiment utilizes a patterning technique and a wet etching method to thin the wafer and form a convex pattern on the back side of the wafer, including the following steps:

S101：提供一晶圓，所述晶圓包括正面和背面，所述正面形成有IC裸芯。所述晶圓即為需要薄化處理的晶圓。通常是矽晶圓。晶圓的尺寸可以為450mm以上，本實施例以450mm直徑的晶圓為例。 S101: Providing a wafer, the wafer includes a front side and a back side, and the front side is formed with an IC bare core. The wafer is a wafer that requires thinning. Usually it is a germanium wafer. The size of the wafer may be 450 mm or more. In this embodiment, a 450 mm diameter wafer is taken as an example.

S102：在所述晶圓背面形成光罩層。所述光罩層可以為氧化矽層或其他適合作為光罩的材料層。所述光罩層可以是單層材料也可以是多層複合材料。本實施例較佳地，形成所述光罩層的方法為化學氣相沈積TEOS材料。 S102: forming a photomask layer on the back surface of the wafer. The photomask layer can be a ruthenium oxide layer or other layer of material suitable as a reticle. The photomask layer may be a single layer material or a multilayer composite material. In this embodiment, preferably, the method of forming the photomask layer is chemical vapor deposition of TEOS material.

S103：在所述晶圓背面的光罩層上光刻形成圖形化的光阻層，所述圖形化的光阻層包括覆蓋所述晶圓週邊邊緣的環形部分以及位於所述環形內的交叉圖形部分。所述光阻層即為光刻膠層。此處，光刻圖形化光刻膠的方法為本領域技術人員的習知技術，在此不作贅述。光刻圖形的尺寸可以根據實際需求進行設計和調整。本實施例中，所述環形的寬度可以為4-7mm，所述交叉圖形的線條寬度可以為4-7mm。所述交叉圖形可以為多條線條的交叉形狀，本發明對具體的交叉線條數量和交叉角度等沒有限制，本實施例中，所述交叉圖形較佳為十字形。 S103: photolithographically forming a patterned photoresist layer on the photomask layer on the back side of the wafer, the patterned photoresist layer including an annular portion covering a peripheral edge of the wafer and a cross within the ring Graphical part. The photoresist layer is a photoresist layer. Here, the method of lithographically patterning the photoresist is a well-known technique of those skilled in the art, and will not be described herein. The size of the lithographic pattern can be designed and adjusted according to actual needs. In this embodiment, the width of the ring may be 4-7 mm, and the line width of the cross pattern may be 4-7 mm. The cross-pattern may be a cross-shaped shape of a plurality of lines. The present invention has no limitation on the number of cross-lines and the angle of intersection. In the embodiment, the cross-pattern is preferably a cross.

S104：進行第一蝕刻，去除光罩層中未被所述光阻層覆蓋的部分，將所述光阻層上的圖形傳遞到所述光罩層上，然後去除所述光阻層。所述第一蝕刻可以採用濕式蝕刻技術，選用能夠去除所述光罩層材料 的腐蝕劑，以達到傳遞圖形的效果。本實施例中，所述第一蝕刻可以為採用HF的濕式蝕刻。去除所述光阻層可採用任何適合去膠方法。 S104: performing a first etching, removing a portion of the photomask layer that is not covered by the photoresist layer, transferring a pattern on the photoresist layer to the photomask layer, and then removing the photoresist layer. The first etching may be performed by a wet etching technique, and the material of the photomask layer can be removed. Corrosive agent to achieve the effect of transferring graphics. In this embodiment, the first etching may be wet etching using HF. Any suitable de-glue method can be used to remove the photoresist layer.

S105：進行第二蝕刻，去除所述光罩層和晶圓背面的部分區域，將所述光罩層上的圖形傳遞到所述晶圓的背面，在所述晶圓背面得到凸出的圖形結構，所述圖形結構包括位於所述晶圓週邊邊緣的環形結構以及位於所述環形結構內的交叉圖形結構。所述第二蝕刻可以採用濕式蝕刻技術，選用能夠去除所述光罩層材料以及晶圓材料的腐蝕劑，以達到傳遞圖形並薄化晶圓的效果。本實施例中，所述第二蝕刻較佳為採用TMAH的濕式蝕刻。通過調整蝕刻參數，如時間、腐蝕液濃度、溫度等，可以精確控制所得凸出圖形結構的厚度和晶圓薄化的程度。 S105: performing a second etching, removing a portion of the mask layer and a back surface of the wafer, transferring a pattern on the mask layer to a back surface of the wafer, and obtaining a convex pattern on a back surface of the wafer A structure comprising an annular structure at a peripheral edge of the wafer and a cross-sectional structure within the annular structure. The second etching may employ a wet etching technique, and an etchant capable of removing the mask layer material and the wafer material may be selected to achieve the effect of transferring the pattern and thinning the wafer. In this embodiment, the second etching is preferably wet etching using TMAH. By adjusting the etching parameters such as time, etching solution concentration, temperature, etc., the thickness of the resulting convex pattern structure and the degree of wafer thinning can be precisely controlled.

最終得到的薄化的晶圓可作為大尺寸的薄晶圓應用於功率裝置、BSI型CMOS圖像感測器或其他需要大尺寸薄晶圓的應用領域，其背面除了所述圖形結構以外的大部分區域可被薄化至預設厚度，週邊邊緣可以保留一定厚度，即環形結構，中心區域的交叉圖形結構也具有一定厚度，這樣可以防止晶圓的翹曲，邊緣碎裂，對大尺寸晶圓來說可以有效提高晶圓強度。 The resulting thinned wafer can be used as a large-sized thin wafer for power devices, BSI-type CMOS image sensors, or other applications requiring large-sized thin wafers, the back side of which is other than the graphic structure. Most of the area can be thinned to a preset thickness, and the peripheral edge can retain a certain thickness, that is, a ring structure, and the cross-pattern structure of the center area also has a certain thickness, thereby preventing wafer warpage, edge fragmentation, and large size. Wafers can effectively increase wafer strength.

實施例二 Embodiment 2

本實施例在實施例一的技術方案基礎上，結合研磨技術、濕式蝕刻方法薄化晶圓。與實施例一的不同之處在於，在所述晶圓背面形成光罩層之前，在所述晶圓背面採用研磨或濕式蝕刻的方法先將所述晶圓薄化一定厚度，然後再利用實施例一的方法在晶圓背面形成凸出的圖形結構，並將所述晶圓薄化至最終需要的厚度。 In this embodiment, based on the technical solution of the first embodiment, the wafer is thinned by a combination of a grinding technique and a wet etching method. The difference from the first embodiment is that before the photomask layer is formed on the back surface of the wafer, the wafer is thinned to a certain thickness by grinding or wet etching on the back surface of the wafer, and then used. The method of Example 1 forms a convex pattern on the back side of the wafer and thins the wafer to a final desired thickness.

或者是，在所述晶圓背面得到凸出的圖形結構之後，在所述晶圓背面繼續採用研磨的方法將所述晶圓薄化至最終需要的厚度。具體地，可以採用直徑較小的研磨頭對所述晶圓背面的凸出的圖形結構之外的部分進行研磨。 Alternatively, after the convex pattern is obtained on the back side of the wafer, the wafer is further thinned to the final desired thickness by grinding on the back side of the wafer. Specifically, a portion other than the convex pattern structure on the back surface of the wafer may be ground using a grinding head having a smaller diameter.

實施例三 Embodiment 3

本實施例利用研磨技術薄化所述晶圓並在所述晶圓背面形成凸出的圖形結構，具體方法為：在所述晶圓背面進行研磨，僅保留位於所述晶圓週邊邊緣的環形區域和位於所述環形區域內的交叉繪圖區域之外的部分。 In this embodiment, the wafer is thinned by a polishing technique and a convex pattern is formed on the back surface of the wafer by grinding on the back side of the wafer to retain only the ring at the peripheral edge of the wafer. A region and a portion outside the cross-plotting region within the annular region.

本實施例較佳地，可以採用兩個直徑不同的研磨頭進行研磨，可以根據所需要形成的圖形結構規劃研磨頭的研磨路徑，直徑較小的研磨頭用於研磨面積較小的區域，直徑較大的研磨頭用於研磨面積較大的區域。 Preferably, in this embodiment, two grinding heads having different diameters can be used for grinding, and the grinding path of the grinding head can be planned according to the pattern structure required to be formed, and the grinding head with a smaller diameter is used for grinding a small area, the diameter Larger grinding heads are used to grind areas with larger areas.

此外，在研磨形成所需圖形結構的基礎上，還可以結合濕式蝕刻，得到表面狀態較佳的薄化晶圓。 In addition, on the basis of grinding to form a desired pattern structure, wet etching can also be combined to obtain a thinned wafer having a better surface state.

綜上所述，本發明利用薄化技術在晶圓背面形成凸出的交叉圖形結構以及環形邊緣，從而可提高晶圓強度，減少晶圓破損。利用本發明的技術方案可以實現較大尺寸的晶圓薄化和應用，例如直徑450mm以上的晶圓。所以，本發明有效克服了現有技術中的種種缺點而具高度產業利用價值。 In summary, the present invention utilizes a thinning technique to form a convex cross-pattern structure and a ring-shaped edge on the back side of the wafer, thereby improving wafer strength and reducing wafer damage. A larger size wafer thinning and application can be realized by the technical solution of the present invention, for example, a wafer having a diameter of 450 mm or more. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

上述特定實施例之內容係為了詳細說明本發明，然而，該等實施例係僅用於說明，並非意欲限制本發明。熟習本領域之技藝者可理解， 在不悖離後附申請專利範圍所界定之範疇下針對本發明所進行之各種變化或修改係落入本發明之一部分。 The above description of the specific embodiments is intended to be illustrative of the invention, and is not intended to limit the invention. Those skilled in the art will understand that Various changes or modifications to the invention may be made without departing from the scope of the invention.

S1~S2‧‧‧步驟 S1~S2‧‧‧ steps

Claims (17)

一種晶圓薄化方法，其特徵在於，包括以下步驟：提供一晶圓，所述晶圓包括正面和背面，所述正面形成有IC裸芯；薄化所述晶圓並在所述晶圓背面形成凸出的圖形結構，所述圖形結構包括位於所述晶圓週邊邊緣的環形結構以及位於所述環形結構內的交叉圖形結構。 A wafer thinning method, comprising the steps of: providing a wafer comprising a front side and a back side, wherein the front side is formed with an IC bare core; thinning the wafer and the wafer The back side forms a convex pattern structure comprising an annular structure at the peripheral edge of the wafer and a cross-pattern structure located within the annular structure. 如申請專利範圍第1項的晶圓薄化方法，其中，所述環形結構的寬度為4-7mm，所述交叉圖形結構的線條寬度為4-7mm。 The wafer thinning method of claim 1, wherein the annular structure has a width of 4-7 mm, and the cross-pattern structure has a line width of 4-7 mm. 如申請專利範圍第1項的晶圓薄化方法，其中，所述交叉圖形結構為十字形結構。 The wafer thinning method of claim 1, wherein the cross pattern structure is a cross structure. 如申請專利範圍第1項的晶圓薄化方法，其中，所述薄化所述晶圓並在所述晶圓背面形成凸出的圖形結構係包括：在所述晶圓背面形成光罩層；在所述晶圓背面的光罩層上光刻形成圖形化的光阻層，所述圖形化的光阻層包括覆蓋所述晶圓週邊邊緣的環形部分以及位於所述環形內的交叉圖形部分；進行第一蝕刻，去除光罩層中未被所述光阻層覆蓋的部分，將所述光阻層上的圖形傳遞到所述光罩層上，然後去除所述光阻層；進行第二蝕刻，去除所述光罩層和晶圓背面的部分區域，將所述光罩層上的圖形傳遞到所述晶圓的背面，在所述晶圓背面得到凸出的圖形結 構，所述圖形結構包括位於所述晶圓週邊邊緣的環形結構以及位於所述環形結構內的交叉圖形結構。 The wafer thinning method of claim 1, wherein the thinning the wafer and forming a convex pattern structure on the back surface of the wafer comprises: forming a mask layer on a back surface of the wafer Forming a patterned photoresist layer on the photomask layer on the back side of the wafer, the patterned photoresist layer including an annular portion covering a peripheral edge of the wafer and a cross pattern in the ring a portion; performing a first etching to remove a portion of the mask layer that is not covered by the photoresist layer, transferring a pattern on the photoresist layer to the photomask layer, and then removing the photoresist layer; a second etching, removing a portion of the mask layer and the back side of the wafer, transferring the pattern on the mask layer to the back side of the wafer, and obtaining a convex pattern knot on the back side of the wafer The graphic structure includes an annular structure at a peripheral edge of the wafer and a cross-shaped structure within the annular structure. 如申請專利範圍第4項的晶圓薄化方法，其中，所述光罩層為氧化矽層。 The wafer thinning method of claim 4, wherein the photomask layer is a hafnium oxide layer. 如申請專利範圍第4項的晶圓薄化方法，其中，形成所述光罩層的方法為化學氣相沈積四乙氧基矽烷(TEOS)材料。 The wafer thinning method of claim 4, wherein the method of forming the photomask layer is chemical vapor deposition of a tetraethoxy decane (TEOS) material. 如申請專利範圍第4項的晶圓薄化方法，其中，所述第一蝕刻為採用氟化氫(HF)的濕式蝕刻。 The wafer thinning method of claim 4, wherein the first etching is wet etching using hydrogen fluoride (HF). 如申請專利範圍第4項的晶圓薄化方法，其中，所述第二蝕刻為採用氫氧化四甲基銨(TMAH)的濕式蝕刻。 The wafer thinning method of claim 4, wherein the second etching is wet etching using tetramethylammonium hydroxide (TMAH). 如申請專利範圍第4項的晶圓薄化方法，其中，在所述晶圓背面形成光罩層之前，在所述晶圓背面以研磨或濕式蝕刻將所述晶圓薄化。 The wafer thinning method of claim 4, wherein the wafer is thinned by grinding or wet etching on the back surface of the wafer before the photomask layer is formed on the back surface of the wafer. 如申請專利範圍第4項的晶圓薄化方法，其中，在所述晶圓背面得到凸出的圖形結構之後，在所述晶圓背面進一步以研磨將所述晶圓薄化。 The wafer thinning method of claim 4, wherein after the convex pattern is obtained on the back surface of the wafer, the wafer is further thinned by polishing on the back surface of the wafer. 如申請專利範圍第10項的晶圓薄化方法，其中，研磨所述晶圓背面的凸出的圖形結構之外的部分。 A wafer thinning method according to claim 10, wherein a portion other than the convex pattern structure on the back surface of the wafer is polished. 如申請專利範圍第1項的晶圓薄化方法，其中，所述薄化所述晶圓並在所述晶圓背面形成凸出的圖形結構係包括：在所述晶圓背面進行研磨，僅保留位於所述晶圓週邊邊緣的環形區域和位於所述環形區域內的交叉繪圖區域之外的部分。 The wafer thinning method of claim 1, wherein the thinning the wafer and forming a convex pattern structure on the back surface of the wafer comprises: grinding the back surface of the wafer, only An annular region located at a peripheral edge of the wafer and a portion outside the intersecting drawing region within the annular region are retained. 如申請專利範圍第12項的晶圓薄化方法，其中，所述研磨係採用兩個直徑不同的研磨頭進行研磨。 The wafer thinning method of claim 12, wherein the grinding is performed by using two grinding heads having different diameters. 一種薄化的晶圓結構，其特徵在於： 所述晶圓包括正面和背面；所述晶圓正面形成有IC裸芯；所述晶圓背面形成有凸出的圖形結構，所述圖形結構包括位於所述晶圓週邊邊緣的環形結構以及位於所述環形結構內的交叉圖形結構。 A thinned wafer structure characterized by: The wafer includes a front side and a back side; the front side of the wafer is formed with an IC bare core; the back side of the wafer is formed with a convex pattern structure, and the pattern structure includes a ring structure located at a peripheral edge of the wafer and is located A cross-sectional structure within the annular structure. 如申請專利範圍第14項的薄化的晶圓結構，其中，所述圖形結構凸出的厚度為500-800nm。 The thinned wafer structure of claim 14, wherein the patterned structure has a thickness of 500-800 nm. 如申請專利範圍第14項的薄化的晶圓結構，其中，所述環形結構的寬度為4-7mm，所述交叉圖形結構的線條寬度為4-7mm。 The thinned wafer structure of claim 14, wherein the annular structure has a width of 4-7 mm and the cross-pattern structure has a line width of 4-7 mm. 如申請專利範圍第14項的薄化的晶圓結構，其中，所述交叉圖形結構為十字形結構。 The thinned wafer structure of claim 14, wherein the cross-pattern structure is a cross-shaped structure.
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