TWI598951B - Semiconductor wafer etching device and semiconductor wafer etching method - Google Patents

Description

Etching device for semiconductor wafer and etching method for semiconductor wafer

The present invention relates to an etching apparatus for a semiconductor wafer and an etching method of the semiconductor wafer.

A semiconductor wafer such as a ruthenium wafer used as a substrate for a ruthenium device is obtained by cutting a crystal rod pulled by a Chaucer method or the like with a wire saw, and then mechanically processing, etching, or the like by brushing or the like. It is produced by processing in a plurality of stages such as polishing.

The purpose of the etching is to remove the processing distortion caused by the machining, the micro defects of the front and back surfaces of the wafer, and the deposits in a state where the flatness manufactured in the machining of the previous step is not broken. In this etching, the semiconductor wafer is immersed in a predetermined etching liquid, and rotated in this state, and the chemical material on the front and back surfaces of the semiconductor wafer is removed by a chemical reaction between the semiconductor wafer and the etching liquid.

FIG. 1 is a schematic view showing an etching apparatus 100. The etching apparatus 100 mainly includes an etching bath 101 that stores an etching liquid therein, and a wafer cassette 102 that rotatably supports and stores a plurality of semiconductor wafers W. As shown in FIG. 2, the wafer cassette 102 includes two side panels 103a and 103b which are disposed apart from each other in order to accommodate the semiconductor wafer W. Moreover, the central separation is separated between the two side panels 103a and 103b. Board 104. Further, the side panels 103a and 103b and the center partitioning plate 104 are connected and held by the main roller 106. The main roller 106 is provided with a contact support member 107. Returning to Fig. 1, the plurality of semiconductor wafers W housed inside the wafer cassette 102 are contact-supported by the contact supporting members 107, respectively. Further, the etching apparatus 100 further includes an elevating mechanism (not shown) for rotating the driving unit 108 of the semiconductor wafer and elevating the wafer cassette.

When the semiconductor wafer W is etched using the implementation device 100 having such a structure, first, a plurality of semiconductor wafers W are stored in the wafer cassette 102 in a columnar state in which the surfaces are parallel to each other. Inside the wafer cassette 102, a plurality of semiconductor wafers W are contact-supported by the contact support member 107. Then, the wafer cassette 102 accommodating the plurality of semiconductor wafers W is immersed in the etching bath 101 in a state in which the etching liquid is circulated by the lifting means.

Next, the drive unit 108 disposed in the etching apparatus 100 rotates at a predetermined speed, and the main roller 106 is rotated by various gears. Thereby, the plurality of semiconductor wafers W supported by the contact supporting member 107 provided on the main roller 106 are also rotated in conjunction. In this way, inside the wafer cassette 102, a plurality of semiconductor wafers W are rotated around the central axis to perform etching processing of the semiconductor wafer W.

However, in the above etching apparatus 100, the swirling flow generated by each of the semiconductor wafers W collides between the semiconductor wafers W, and the relative rotational flow rate between the semiconductor wafers W is relatively fast, and thus, for example, the periphery of the semiconductor wafer W is adjacent. The turbulent flow of the etching liquid occurs, and the flatness characteristic of the outer peripheral portion of the semiconductor wafer W is deteriorated.

Patent Documents 1 and 2 disclose an eclipse for arranging a plurality of separator plates The etching device is a technique for suppressing the turbulent flow of the above etching liquid.

Advanced technical literature

Patent Document 1: Japanese Laid-Open Patent Publication No. 2005-050943

Patent Document 2: Japanese Laid-Open Patent Publication No. 2006-032641

However, in the etching using the plurality of separators described in Patent Documents 1 and 2, the flatness improvement in the central portion of the semiconductor wafer W is not sufficient, and unevenness similar to the ridge is generated.

An object of the present invention is to provide an etching apparatus for a semiconductor wafer and an etching method for a semiconductor wafer, which can improve flatness after etching.

The inventors of the present invention worked hard to study the results of the flatness of the wafer after etching, and obtained the following results.

<Experiment 1>

First, etching was performed using an etching apparatus having a wafer cassette having no conventional separator, and then an experiment for confirming the flatness of the wafer was performed. A silicon wafer is prepared as a semiconductor wafer, and an acid mixed with hydrofluoric acid, nitric acid, and nitric acid is prepared as an etching liquid. The plurality of semiconductor wafers W are etched using the etching apparatus 100 shown in FIG. 1 having the wafer cassette 102 shown in FIG. 2, and the surface semiconductor wafer W is etched by a surface polishing apparatus (not shown). The surface is surface ground. Then, regarding the etched wafer after the etching and the surface polishing, a wafer surface measuring device (ADE9300: manufactured by ADE, USA) was used as a measuring machine to measure the flatness of the surface. The results are shown in Figures 3 and 4.

As shown in FIG. 3, the central portion of the etched semiconductor wafer W It is uneven and has poor flatness. Further, as shown in FIG. 4, irregularities are also formed in the central portion of the semiconductor wafer W after the surface polishing. As described above, it is understood that the flatness of the semiconductor wafer W after etching is greatly different from the flat portion of the semiconductor wafer W after the surface polishing.

<Experiment 2>

Next, when a plurality of semiconductor wafers W are etched using the etching apparatus 100 shown in FIG. 1 having the wafer cassette 102 shown in FIG. 2, wafer surface measurement is performed on the wafers in one processing. The instrument (ADE9300: manufactured by ADE, USA) was used as a measuring machine to measure the flatness of the surface. As shown in FIG. 5, the measurement of the flat portion divides the semiconductor wafer W to be measured into square cells having a side length of 25 mm, and the four cells located at the center portion of the semiconductor wafer W and the periphery of the semiconductor wafer W. The 20 units of the department calculate the flatness (SFQR). The results are shown in Figure 6. The horizontal axis of Fig. 6 shows the semiconductor wafers W according to the loading order, and the SFQR of the vertical axis indicates the average of four cells in the central portion of the semiconductor wafer W and the average of 20 cells in the outer peripheral portion of the semiconductor wafer W. . In addition, SFQR (Site Front Least Square Range) is used as a reference plane for each block, and the inner plane of the block in which the data is calculated by the least square method in the set block, and the + side of the plane (that is, the crystal The evaluation value indicated by the sum of the absolute values of the maximum displacement amounts of the upper side) and the - side (the lower side) when the main surface of the circle is placed horizontally upward.

From FIG. 6, it is obtained as a result of the difference in the flat portion of the semiconductor wafer W due to the difference in the position accommodated inside the wafer cassette 102. Specifically, it is possible to confirm the semiconductor wafer W accommodated at other positions than the semiconductor wafer W accommodated in the center and the outside of the inside of the wafer cassette 102. The flatness is deteriorated. The semiconductor wafer W accommodated in the center and the outside of the inside of the wafer cassette 102 is adjacent to the side panels 103a and 103b and the center partition plate 104, and the semiconductor wafer W accommodated at other positions has a semiconductor. The difference in the point at which the wafers W are adjacent to each other. Therefore, it is presumed that among the semiconductor wafers W that are not adjacent to the side panels 103a and 103b and the center partition plate 104, the adjacent semiconductor wafer W is a rotating body, and the turbulent flow of the etching liquid generated by the rotating semiconductor wafer W may cause The flatness of the semiconductor wafer W is deteriorated.

<Experiment 3>

As a result of the review of the above experiment 2, in order to suppress the turbulent flow of the etching liquid generated by the rotation of the adjacent semiconductor wafer W, as shown in FIG. 7, the wafer cassette 202 is prepared, and the plurality of wafers are accommodated therein. A plurality of separator plates 205 having a flat surface are disposed between the semiconductor wafers W. The plurality of semiconductor wafers W are etched using the etching apparatus 100 shown in FIG. 1 having the wafer cassette 202 shown in FIG. 7, and the surface semiconductor wafer W is etched by a surface polishing apparatus (not shown). The surface is surface ground. Then, regarding the etched wafer after the etching and the surface polishing, a wafer surface measuring device (ADE9300: manufactured by ADE, USA) was used as a measuring machine to measure the flatness of the surface. The results are shown in Figures 8 and 9. From the results shown in Figs. 8 and 9, it was confirmed that the unevenness of the ridge of the central portion of the semiconductor wafer W was reduced as compared with the results of the above Figs. 3 and 4. From this result, it was confirmed that the turbulent flow of the etching liquid can be suppressed by providing a plurality of separator plates. However, the improvement of the unevenness of the ridge of the central portion of the semiconductor wafer W is not quite sufficient.

Fig. 10 shows the flow of the etching liquid in the vicinity of the semiconductor wafer W. The semiconductor wafer W is rotated during the etching, so the etching solution of the etching bath 101 is etched. A swirling flow is generated for each of the semiconductor wafers W. In the vicinity of the outer peripheral portion of the semiconductor wafer W far from the center of rotation, the distance per fixed time due to the rotation is large, and the distance per fixed time due to the rotation in the vicinity of the central portion of the semiconductor wafer W is small. Therefore, the flow of the etching liquid in the vicinity of the outer peripheral portion of the semiconductor wafer W is fast because of the difference in the moving distance per certain time, and the flow of the etching liquid in the vicinity of the central portion of the semiconductor wafer W is slow. In particular, since the flow of the etching liquid in the vicinity of the central portion of the semiconductor wafer W is slow, it is difficult to separate the reaction product gas generated in the etching reaction from the surface layer of the semiconductor wafer W, and it is presumed that this reaction product gas hinders the progress of the etching reaction. Therefore, the unevenness of the unevenness generated in the central portion of the semiconductor wafer W is caused.

<Experiment 4>

Therefore, in order to confirm the influence of the swirling flow generated by the rotation of the semiconductor wafer W, the wafer 匣 202 shown in FIG. 7 is appropriately changed in the interval between the plurality of divided separator plates 205 to perform the semiconductor wafer W. Etching, measuring the flatness (SFQR) of the etched semiconductor wafer W. The results are shown in Figure 11. As can be seen from Fig. 11, the flatness of the central portion of the semiconductor wafer W tends to be improved as the interval between the partition plates 205 becomes narrower, and the interval between the partition plates 205 tends to be deteriorated as the interval between the partition plates 205 increases. Moreover, the flat portion of the outer peripheral portion of the semiconductor wafer W tends to be deteriorated as the interval between the partition plates 205 becomes narrower, and the interval between the partition plates 205 tends to be improved as the interval between the partition plates 205 increases.

As described above, since the interval between the partition plates 205 is changed, the flat portion of the central portion of the semiconductor wafer W and the flat portion of the outer peripheral portion are changed, because the interval between the semiconductor wafer W and the partition plate 205 varies. The flow of the etching liquid flowing to the vicinity of the semiconductor wafer W changes. This is the central part of the semiconductor wafer W The result of the difference from the etching of the outer peripheral portion. From this result, it is considered that if the flow rate of the etching liquid near the central portion of the semiconductor wafer W is almost the same as the flow rate of the etching liquid in the vicinity of the outer peripheral portion of the semiconductor wafer W, the vicinity of the central portion of the semiconductor wafer W is made. The flow of the etching liquid is faster than conventionally, and the peeling of the reaction product gas in the vicinity of the center of the semiconductor wafer W can be promoted. Therefore, it is considered that the etching reaction of the central portion and the outer peripheral portion of the semiconductor wafer W is uniformized because the peeling of the reaction product gas is too slow to hinder the progress of the etching. The present invention has been completed based on the above findings.

That is, the etching apparatus for a semiconductor wafer of the present invention includes: an etching bath for storing an etching liquid; a wafer cassette that can enter and exit the etching groove to rotatably accommodate a plurality of semiconductor wafers; and a plurality of sheets a separator disposed between the plurality of semiconductor wafers inside the wafer cassette, wherein the semiconductor wafer is rotated, and the flow rate of the etching solution is controlled by the separator to make the semiconductor wafer The flow rate of the etching liquid in the vicinity of the central portion is almost the same as the flow rate of the etching liquid in the vicinity of the outer peripheral portion of the semiconductor wafer.

According to the present invention, in a state where the semiconductor wafer is rotated, the flow rate of the etching liquid is controlled by the partition plate so that the flow rate of the etching liquid in the vicinity of the central portion of the semiconductor wafer and the flow rate of the etching liquid in the vicinity of the outer peripheral portion of the semiconductor wafer almost the same. The flow rate of the etching liquid in the vicinity of the wafer is controlled by the partition plate to promote the peeling of the reaction product gas in the vicinity of the center portion of the wafer, thereby eliminating the situation in which the etching of the reaction gas is too slow to hinder the etching. As a result, the central portion and the outer peripheral portion of the wafer are etched to almost the same extent, so that the flatness after etching can be improved. Finally, the flatness of the polished wafer as the final product after etching is also improved.

In the etching apparatus for a semiconductor wafer according to the present invention, the interval between the adjacent partition plates is smaller than the outer circumference of the outer peripheral portion of the semiconductor wafer in the central region corresponding to the central portion of the semiconductor wafer. The interval between the fields is small.

According to the invention, the interval between the adjacent partition plates is set such that the interval in the central region corresponding to the central portion of the semiconductor wafer is smaller than the interval corresponding to the outer peripheral region of the outer peripheral portion of the semiconductor wafer. Thereby, the flow rate of the etching liquid in the vicinity of the center portion of the semiconductor wafer can be controlled to be almost the same as the flow rate of the etching liquid in the vicinity of the outer peripheral portion of the semiconductor wafer.

In the etching apparatus for a semiconductor wafer of the present invention, the interval between the adjacent partition plates is 17 mm or less in the center region, and the interval in the outer peripheral region is 32 mm or more.

According to the present invention, the interval between the adjacent partition plates is 17 mm or less in the central region, and the position in the peripheral region is 32 mm or more. When the interval between the central regions of the partition plate and the interval between the outer peripheral regions are within the above range, the flow velocity of the etching liquid in the vicinity of the central portion of the semiconductor wafer can be controlled to be almost the same as the flow velocity of the etching liquid in the vicinity of the outer peripheral portion of the semiconductor wafer.

In the etching apparatus for a semiconductor wafer of the present invention, the thickness of the partition plate is preferably larger in thickness in the central region than in the outer peripheral region.

According to the present invention, the thickness of the partition plate is greater in the central region than in the outer peripheral region, whereby the flow rate of the etching liquid in the vicinity of the central portion of the semiconductor wafer and the vicinity of the outer peripheral portion of the semiconductor wafer can be controlled. Etching solution The flow rate is almost the same.

In the etching apparatus for a semiconductor wafer of the present invention, the thickness in the outer peripheral region of the separator is almost the same as the thickness of the semiconductor wafer.

According to the present invention, the thickness of the outer peripheral region of the partition plate is almost the same as the thickness of the semiconductor wafer, so that the relative rotational flow velocity between the semiconductor wafers can be appropriately buffered, and the turbulent flow of the etching liquid can be appropriately suppressed.

The etching method of the semiconductor wafer of the present invention comprises: an etching device using a semiconductor wafer, the etching device of the semiconductor wafer includes: an etching groove for storing an etching liquid; and a wafer defect which can enter and exit the etching groove to be rotatable The semiconductor wafer in which a plurality of sheets are accommodated; and a plurality of separators are disposed between the plurality of semiconductor wafers inside the wafer cassette. The method for etching a semiconductor wafer further includes: maintaining a state in which the semiconductor wafer is immersed in the etchant, and performing etching while rotating the semiconductor wafer, wherein the semiconductor wafer is rotated to utilize the separation The plate controls the flow rate of the etching solution such that the flow rate of the etching liquid in the vicinity of the central portion of the semiconductor wafer is almost the same as the flow rate of the etching liquid in the vicinity of the outer peripheral portion of the semiconductor wafer.

According to the present invention, the flow rate of the etching liquid is controlled by a partition plate using the above etching apparatus. The flow rate of the etching liquid in the vicinity of the wafer is controlled by the partition plate to promote the peeling of the reaction product gas in the vicinity of the center portion of the wafer, thereby eliminating the situation in which the etching of the reaction gas is too slow to hinder the etching. As a result, the central portion and the outer peripheral portion of the wafer are etched to almost the same extent, so that the flatness after etching can be improved. Finally, the flatness of the polished wafer as the final product after etching is also improved.

In the etching method of the semiconductor wafer of the present invention, the plurality of The rotation of the semiconductor wafer interactively performs positive and negative rotations.

According to the present invention, it is possible to alternately rotate the semiconductor wafer with positive rotation and reverse rotation, thereby further suppressing turbulent flow of the etching liquid.

10, 100‧‧‧ etching device

11, 101‧‧ ‧ etching tank

12, 102, 202‧‧‧ wafer 匣

13a, 13b, 103a, 103b‧‧‧ side panels

14, 104‧‧‧ central divider

15, 205‧‧‧ partition board

16, 106‧‧‧ main scroll wheel

17, 107‧‧‧Contact support members

18, 108‧‧‧ Drive Department

151‧‧‧Central area

152‧‧‧ Peripheral field

153‧‧‧ Highlights

154‧‧‧ Flat Department

155‧‧‧ inclined section

W‧‧‧Semiconductor Wafer

Fig. 1 is a schematic view showing a conventional etching apparatus.

Fig. 2 is a schematic view of a conventional wafer crucible.

Fig. 3 is a view showing the flatness of the wafer after etching in the etching apparatus having the wafer cassette of Fig. 2;

Fig. 4 is a view showing the flatness of the wafer after etching in the etching apparatus having the wafer crucible of Fig. 2 and performing surface polishing.

Figure 5 shows the measurement position of the flatness of the wafer.

Fig. 6 is a view showing the flatness of the wafer in the first etching process by etching in the etching apparatus having the wafer crucible of Fig. 2;

Figure 7 is a schematic diagram showing the wafer stack in which the separator is placed between a plurality of wafers.

Fig. 8 is a view showing the flatness of the wafer after etching in the etching apparatus having the wafer cassette of Fig. 7.

Fig. 9 is a view showing the flatness of the wafer after etching in the etching apparatus having the wafer cassette of Fig. 7 and performing surface polishing.

Figure 10 shows the flow of the etchant in the vicinity of the wafer.

Fig. 11 is a view showing the relationship between the interval between the partition plates and the flatness of the wafer when the interval between the partition plates of the wafer cassette of Fig. 7 is changed.

Fig. 12 is a schematic view showing an etching apparatus of the present embodiment.

Fig. 13 is a schematic view showing a wafer cassette in which a partition plate of the present embodiment is arranged.

Fig. 14 is a schematic view showing a partition plate of Fig. 13.

Fig. 15 shows the wafer flatness after etching using different separators in Comparative Example 1.

Fig. 16 shows the wafer flatness after etching using different separators in Example 1.

Fig. 17 shows the wafer flatness after polishing using different separators in Comparative Example 1.

Fig. 18 shows the wafer flatness after polishing using different partition plates in Example 1.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. First, the configuration of the etching apparatus will be described. Fig. 12 is a schematic view showing the etching apparatus 10. The etching shape 10 mainly includes an etching bath 11 that stores an etching liquid therein, and a wafer cassette 12 that rotatably supports and stores a plurality of semiconductor wafers W. As shown in FIG. 13, the wafer cassette 12 includes two side panels 13a and 13b which are disposed apart from each other in order to accommodate the semiconductor wafer W. Further, a center partitioning plate 14 is disposed between the two side panels 13a and 13b. A plurality of partition plates 15 are disposed between the side panel 13a and the center partitioning plate 14, and between the side panel 13b and the center partitioning plate 14. Further, the side panels 13a and 13b, the center partitioning plate 14, and the partitioning plate 15 are connected and held by the main roller 106. The main roller 16 is provided with a contact support member 17. Returning to Fig. 12, the plurality of semiconductor wafers W housed inside the wafer cassette 12 are contact-supported by the contact supporting members 17, respectively. Moreover, the etching apparatus 10 further includes a semiconductor wafer for rotating The driving unit 18 and the elevating mechanism for lifting the wafer cassette 12 (not shown).

<Configuration of partition plate>

Fig. 14 is a schematic view showing the shape of the partitioning plate 15 of the present embodiment. The left side of the figure is a plan view. On the right is a section view. In Fig. 14, the shape of the partitioning plate 15 is line-symmetric in view of the cross section. Therefore, only the front side will be described, and the description of the back side will be omitted. The surface of the partition plate 15 has a central portion 151 formed with a protruding portion 153 that protrudes outward from the outer peripheral region 152 as viewed in cross section. The protruding portion 153 is formed in a circular shape as viewed in plan and has a flat portion 154 and an inclined portion 155. The flat portion 154 is located at the center of the protruding portion 153, and its surface forms a flat circular shape. The inclined portion 155 connects the outer circumference of the flat portion 154 and the inner circumference of the outer peripheral region 152 with a gentle inclination. Further, when the wafer crucible 12 accommodates the semiconductor wafer W, the outer periphery of the semiconductor wafer W, the outer periphery of the protruding portion 153 (the outer circumference of the inclined portion 155), and the outer periphery of the flat portion 154 become slightly concentric. shape. The size of the protruding portion 153 is preferably 70 to 80% of the diameter of the semiconductor wafer W accommodated in the wafer cassette 12, and more preferably 75%. The size of the flat portion 154 is preferably 30 to 50% of the diameter of the semiconductor wafer W accommodated in the wafer cassette 12, and more preferably 40%. Further, in the present embodiment, polypropylene which is resistant to the etching liquid is used as the material of the partition plate 15. However, if it is a material having a certain degree of strength and acid resistance, other materials such as polyvinyl chloride may be used.

<semiconductor wafer>

The semiconductor wafers W are arranged such that the surfaces are parallel to each other and housed in the internal space of the wafer cassette 12. Here, in the etching apparatus 10 of the present embodiment, the semiconductor wafer W to be etched is, for example, a germanium wafer or a gallium arsenide wafer. Moreover, the size of these semiconductor wafers W is about 4 to 12 inches.

<etching solution>

The etching solution can be used generally. For example, an acid etching solution composed of a mixed acid solution of hydrogen fluoride (HF), nitric acid (HNO ₃ ), acetic acid (CH ₃ COOH), hydrogen peroxide (H ₂ O ₂ ), various phosphoric acid, or the like, or sodium hydroxide (NaOH). An alkali etching solution such as potassium hydroxide (KOH) or ammonia (NH ₃ ). Further, the etching liquid is adjusted to a predetermined temperature determined by a temperature adjustment mechanism (not shown).

<Method of etching semiconductor wafers>

Next, the operation of the etching apparatus 10 having the above structure will be described. First, an etching liquid is supplied to the etching bath 11. The etching solution can be supplied to the etching bath 11 at any time. The etching liquid overflowing from the upper end of the etching bath 11 is recovered by a recovery tank (not shown). The collected etching liquid is filtered by a sieve (not shown) to remove foreign matter or the like contained in the recovered etching liquid by etching. Then, the insufficient components consumed in the etching are added, and the composition is adjusted and then supplied to the etching bath 11. The etching solution is circulated in this manner. Next, the plurality of semiconductor wafers W are housed in the wafer cassette 12 in which the plurality of separators 15 are provided in advance. The accommodated semiconductor wafers W are respectively supported by the contact supporting members 17, and are formed in a columnar state in which the surfaces are parallel to each other. After the semiconductor wafer W is housed, the drive motor of the drive unit 108 is rotated to rotate the main roller 16. The semiconductor wafer W supported by the contact supporting member 17 is rotated by the rotation of the main roller 16. By controlling the number of rotations of the drive motor, the semiconductor wafer W is rotated at a speed of 10 to 60 rpm, and the rotation direction is switched to positive rotation and reverse rotation every arbitrary seconds.

In this state, the wafer crucible 12 containing the semiconductor wafer W is immersed in the etching bath 11 to etch the semiconductor wafer W. After the etching is completed, the wafer cassette 12 is pulled up from the etching bath 11, and moved to a cleaning tank (not shown) for washing.

[Other implementation types]

Further, the present invention is not limited to the above embodiment. Various modifications and changes in design may be made without departing from the spirit and scope of the invention. For example, although the protruding portion 153 of the partition plate 15 has a shape having the flat portion 154 and the inclined portion 155, the present invention is not limited thereto. For example, it is also possible to have a shape in which the inclined portion has only the flat portion 154. Further, the outer periphery of the protruding portion 153 may be formed in a semi-elliptical shape when viewed in cross section. Further, the specific configuration, shape, and the like of the embodiment of the present invention may be other configurations within the scope that can achieve the object of the present invention.

[Examples]

Next, the present invention will be described in more detail by way of examples and comparative examples, but the invention is not limited to these examples. The wafer cassette 202 shown in FIG. 7 is prepared, and a plurality of partition plates 205 having a flat surface are provided between a plurality of semiconductor wafers housed inside. The interval between adjacent partition plates 205 of the wafer cassette 202 shown in Fig. 7 is 33 mm. Further, the wafer cassette 12 shown in Fig. 13 is prepared, and a plurality of sheet separators 15 in which the central portion 151 forms the protruding portion 153 are provided. The interval between the adjacent crucibles 15 of the wafer cassette 12 shown in Fig. 13 is 17 mm at the position of the flat portion 154 of the protruding portion 153, and is 33 mm at the position of the outer peripheral region 152. As the semiconductor wafer W to be processed, a 200 mm φ tantalum wafer which has been subjected to brushing treatment is prepared. Then, using the etching apparatus 100 shown in Fig. 1 having the wafer cassette 202 shown in Fig. 7, the plurality of wafers are etched by the following conditions, and the surface polishing apparatus (not shown) is used for etching. The surface of the crucible wafer was subjected to surface grinding (Comparative Example 1). Similarly, the etching apparatus 10 shown in Fig. 12 including the wafer cassette 12 shown in Fig. 13 is used to etch a plurality of wafers under the following conditions, and the surface polishing apparatus (not shown) is used after etching. Surface of the wafer Surface grinding (Example 1).

(etching conditions)

Etching solution: mixed acid of hydrofluoric acid, nitric acid, acetic acid; number of revolutions: 30 rpm (positive and reverse alternating rotation); etching time: 180 seconds.

For the tantalum wafer after etching and surface polishing, a wafer surface measuring device (ADE9300: manufactured by ADE, USA) is used as a measuring machine to measure the flatness of the surface. As shown in Fig. 5, the flatness measurement was performed by dividing a wafer to be measured into square cells having a side length of 25 mm, and flatness (SFQR) was calculated for each cell. The results are shown in Figures 15-18. Fig. 15 shows the wafer flatness after etching in Comparative Example 1. Fig. 16 shows the wafer flatness after etching in Example 1. The numerical values shown in the respective units of Figs. 15 and 16 are relative values when the maximum value of the flatness of the etched germanium wafer of Comparative Example 1 is taken as 1. Further, Fig. 17 shows the wafer flatness after surface polishing of Comparative Example 1. Fig. 18 shows the wafer flatness after the surface polishing of Example 1. The numerical values shown in the respective units of the seventeenth and eighteenth graphs are relative values when the maximum flatness of the tantalum wafer after the surface polishing of Comparative Example 1 is regarded as 1.

As can be seen from the graphs 15 to 18, in the first embodiment, the flatness of the center of the tantalum wafer was greatly improved with respect to the comparative example 1.

10‧‧‧ etching device

11‧‧‧etching trough

12‧‧‧ Wafer

13a, 13b‧‧‧ side panels

14‧‧‧Central divider

15‧‧‧ divider

16‧‧‧Main wheel

17‧‧‧Contact support components

18‧‧‧ Drive Department

W‧‧‧Semiconductor Wafer

Claims (7)

An etching device for a semiconductor wafer, comprising: an etching groove for storing an etching liquid; a wafer cassette, which can enter and exit the etching groove, rotatably accommodate a plurality of semiconductor wafers; and a plurality of separator plates Between the plurality of semiconductor wafers inside the wafer cassette, wherein the flow rate of the etching liquid is controlled by the partition plate in a state where the semiconductor wafer is rotated, so as to be near the central portion of the semiconductor wafer The flow rate of the etching solution is almost the same as the flow rate of the etching liquid in the vicinity of the outer peripheral portion of the semiconductor wafer. An etching apparatus for a semiconductor wafer according to claim 1, wherein an interval between adjacent ones of the partition plates is greater than a corresponding interval in a central region corresponding to a central portion of the semiconductor wafer The interval between the outer peripheral regions of the outer peripheral portion of the semiconductor wafer is small. An etching apparatus for a semiconductor wafer according to claim 1 or 2, wherein the interval between the adjacent partition plates is less than 17 mm in the central region, and the interval in the peripheral region is 32mm or more. The etching apparatus for a semiconductor wafer according to any one of claims 1 to 3, wherein, in the thickness of the partition plate, a thickness in the central region is larger than a thickness in the outer peripheral region. The etching apparatus for a semiconductor wafer according to any one of claims 1 to 4, wherein a thickness of an outer peripheral region of the separator is almost the same as a thickness of the semiconductor wafer. A semiconductor wafer etching method includes: an etching device using a semiconductor wafer, the etching device of the semiconductor wafer includes: an etching groove for storing an etching liquid; and a wafer cassette which can enter and exit the etching groove and be rotatably received a plurality of semiconductor wafers; and a plurality of separator plates disposed between the plurality of semiconductor wafers inside the wafer cassette, while keeping the semiconductor wafer immersed in the etching liquid The semiconductor wafer is etched while being rotated, wherein the flow rate of the etchant is controlled by the separator in a state where the semiconductor wafer is rotated, so that the flow rate of the etchant near the central portion of the semiconductor wafer and the semiconductor The flow rate of the etching liquid in the vicinity of the outer peripheral portion of the wafer is almost the same. The method of etching a semiconductor wafer according to claim 6, wherein the rotation of the plurality of semiconductor wafers alternately performs positive rotation and reverse rotation.