JP2007149956A - Etching method for semiconductor wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an etching method for a semiconductor wafer which improves flatness and nano topography. <P>SOLUTION: In the etching method of the semiconductor wafer, a plurality of semiconductor wafers are held in a state that plate surfaces are kept opposed to each other to effect etching while rotating them. A rotary member is arranged between the semiconductor wafers. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor wafer etching method, and more particularly to a semiconductor wafer etching method in which a rotating member is disposed between a plurality of semiconductor wafers.

  In the manufacturing process of silicon wafers, a flat shape is mainly maintained while removing the work-affected layer between the slicing process of slicing the silicon ingot into the silicon wafer and the polishing process of chemical mechanical polishing (CMP) of the sliced silicon wafer. Etching is performed to achieve this.

  In recent years, due to improved processing accuracy in lapping processes, polishing processes, etc., the flatness of silicon wafers has increased, and as semiconductor devices have become increasingly finer, silicon wafers with higher flatness and less waviness have been developed. It is requested.

  In the conventional silicon wafer etching method, dozens of silicon wafers are mounted in a dedicated cage, and etching is performed by swinging the cage while rotating the wafer in an etching tank filled with an etching solution. . In such a conventional etching method, turbulent flow is generated between the wafers due to the interaction between the rotating wafers during the etching process, and further, the turbulent flow is strengthened by swinging the cage. However, this causes deterioration of flatness after etching and deterioration of nanotopography due to slight undulation.

  Also, etching is performed by rotating a number of silicon wafers immersed in the etching solution in the etching tank around their respective central axes, or when etching each silicon wafer, adjacent wafers are rotated in different directions. However, a semiconductor wafer etching method has been proposed in which an etchant flows in the space between wafers as the wafer is rotated forward and reverse (Patent Document 1).

However, both the former method and the latter method of Patent Document 1 generate turbulence between wafers, and cannot achieve high flatness and high nanotopography.
JP 2002-231690 A

  The present invention has been made in view of the above-described circumstances, and an object of the present invention is to provide a method for etching a semiconductor wafer in which flatness is improved and nanotopography is improved.

  In order to achieve the above-described object, a semiconductor wafer etching method according to the present invention is a semiconductor wafer etching method in which a plurality of semiconductor wafers are held while their plate surfaces are opposed to each other and etched while rotating. A rotating member is disposed between the two, and the rotating member is rotated together with the semiconductor wafer.

Preferably, the rotating member has a substantially disk shape.
Preferably, the rotating member is made of vinyl chloride.

  According to the semiconductor wafer etching method of the present invention, it is possible to provide a semiconductor wafer etching method in which flatness is improved and nanotopography is improved.

  Hereinafter, an embodiment of a semiconductor wafer etching method according to the present invention will be described with reference to the accompanying drawings.

  FIG. 1 is a longitudinal sectional view showing the concept of an etching apparatus used in a semiconductor wafer etching method, and FIG. 2 is a transverse sectional view thereof.

  The method for etching a semiconductor wafer according to the present invention is performed by using an etching apparatus as shown in FIGS. 1 and 2 with a plurality of semiconductor wafers W and a disk-shaped rotating member 1 facing each other with their plate surfaces facing each other. It is mounted on the wafer magazine 2 so as to rotate around its axis. The semiconductor wafer W and the rotating member 1 are supported by a main groove roller 4 provided on one rotating shaft 3 arranged every 120 ° and a driven groove roller 6 provided on two fixed shafts 5. It is done with 3 points. In this state, the wafer magazine 2 is immersed in an etching tank. Thereafter, the semiconductor wafer W is etched while rotating the plurality of semiconductor wafers W and the rotating member 1.

  In the etching process as described above, by mounting a rotating member between adjacent semiconductor wafers, the etching solution can be efficiently taken in between the semiconductor wafers, turbulent flow is suppressed, uniform etching is possible, and flatness is achieved. The degree of improvement improves nanotopography. Also, by interposing a rotating member that does not react with the etchant between the semiconductor wafers, the interaction between the semiconductor wafers that react with the etchant and generate heat can be cut off, and the etching allowance distribution can be made uniform. it can.

  The rotating member is preferably substantially disk-shaped. Thereby, rotation similar to that of the semiconductor wafer is realized, and generation of turbulence is further suppressed. The rotating member is preferably made of vinyl chloride. Thereby, the rotating member is inexpensive and does not contaminate the semiconductor wafer.

  In addition, the rotating member 1 may be provided with unevenness 1a on a plane as shown in FIG. 3, or may be provided with holes 1b as shown in FIG. Thereby, it rotates with a semiconductor wafer, a chemical | medical solution can be efficiently taken in into the center part of a semiconductor wafer, and the etching liquid replacement | exchange efficiency in the surface of a semiconductor wafer can be equalize | homogenized.

The etching solution is selected from HF, HNO ₃ , CH ₃ COOH, H ₂ O ₂ , a mixed acid solution of phosphoric acid, an alkaline etching solution such as NaOH, KOH, and ammonia.

  In this embodiment, the example in which the semiconductor wafer and the rotating member are rotated in the same direction and in the same direction has been described. However, by making the rotational speeds of the semiconductor wafer and the rotating member different, the wafer central portion can be more efficiently processed. Etching solution can be replaced. Moreover, the replacement efficiency of the etching solution can be increased by reversing the rotation directions of the semiconductor wafer and the rotating member.

  According to the semiconductor wafer etching method of the present embodiment, improvement in flatness and improvement in nanotopography are realized.

  Using the method for etching a semiconductor wafer according to the present invention, the interval between the semiconductor wafer and the rotating member was changed, and the improvement in flatness and nanotopography were examined.

  The results are shown in FIGS.

  As can be seen from FIG. 5, the flatness investigation results show that the semiconductor wafer and the rotating member tend to be deteriorated regardless of whether they are wide or narrow, and it is stable at an appropriate interval, and this interval is 10-13 mm. . Further, as can be seen from FIG. 6, the nanotopography measurement results at the optimum interval (Example) and a wider interval (Comparative Example) clearly showed a tendency to improve. Note that the non-defective product ratio in FIG. 6 is the number of good products per 100 test products.

The longitudinal cross-sectional view which shows the concept of the etching apparatus used for the etching method of the semiconductor wafer which concerns on this invention. The cross-sectional view which shows the concept of the etching apparatus used for the etching method of the semiconductor wafer which concerns on this invention. The top view of the rotating member used for the etching method of the semiconductor wafer which concerns on this invention. The top view of the rotating member of other embodiment used for the etching method of the semiconductor wafer which concerns on this invention. The result figure of the flatness test using the etching method of the semiconductor wafer which concerns on this invention. FIG. 4 is a result diagram of a nanotopography test using the semiconductor wafer etching method according to the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Rotating member 2 Wafer magazine 3 Rotating shaft 4 Main driving groove roller 5 Fixed shaft 6 Following groove roller

Claims (3)

In a semiconductor wafer etching method in which a plurality of semiconductor wafers are held in a state where their plate surfaces are opposed to each other and rotated while rotating, a rotating member is disposed between the semiconductor wafers, and the rotating member is rotated together with the semiconductor wafer. A method for etching a semiconductor wafer. The method of etching a semiconductor wafer according to claim 1, wherein the rotating member has a substantially disk shape. 3. The method for etching a semiconductor wafer according to claim 1, wherein the rotating member is made of vinyl chloride.

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