TWI597391B - Method of fabricating semiconductor sheet - Google Patents

Description

Method of manufacturing a semiconductor wafer

The present invention relates to a method of manufacturing a semonduct sheet, and in particular, to a method of kerf-free, directly manufacturing a tantalum wafer for use in manufacturing a solar cell.

For the related technical background of the present invention, please refer to the technical documents listed below: [1] EPIA, Global Market Outlook for Photovoltaics until 2014, May 2010; [2] EPIA, Global Market Outlook for Photovoltaics until 2016, May 2012; 3] RTS Newsletters, Japan, May, 2012; [4] TF Ciszek, J. Crystal Growth 66, 1984, p. 655; [5] JC Brice, Crystal Growth Processes, New York, Wiley, 1986; [6] B Chalmers, High Speed Growth of Sheet Crystals, J. Crystal Growth 70, 1984, pp. 3-10; [7] G. Hahn, A. Schonecker, A. Gutjahrm New Crystalline Si Ribbon Materials for Photovoltaics, Ch. 2 in Crystal Growth for Solar Cells, Edited by K. Nakajima and N. Usami, Springer, Berlin, 2009; [8] H. Mitsuyasu, S. Goma, R. Oishi, K. Yoshida, in Proceedings of the 23rd EU PVSEC, Valencia, 2008, p. 1497; [9] US Patent Publication No. 6521827; [10] US Patent Publication No. 7071489; [11] US Patent Publication No. 7559542; [12] U.S. Patent Publication No. 2012/0067273; [13] U.S. Patent Publication No. 5,496,416; [14] U.S. Patent Publication No. 7,572,334; [15] A. Grenko, R. Jonczyk, J. Rand, Single Wafer Casting, 2006 IEEE Solar Specialist Conference Proceeding, p. 1415; [16] A. Briglio, K. Dumas, M. Leipold, A. Morrison, Flar- Plate Solar Array Project, Final Report, JPL/DOE, Oct. 1986; [17] M. Tajima, The 4th International Conference on Crystalline Silicon Solar Cells, Taipei, 2010; [18] T. Trupke, KR McIntosh, JW Weber, W. McMillan, L. Ryves, J. Haunschild, C. Shen, H. Kampwerth, Inline Photoluminescence Imaging for Industrial Wafer- and Cell Manufacturing, the 22nd NREL Workshop on Silicon Material, July 22, 2012; and [19] Z. Yuan, WL Huang, K. Mukai, Wettability and reactivity of molten silicon with Various substrate s, Appl. Phys. A 78, 2004, pp. 617-622.

At present, most of the materials of solar cells are mainly coffins, mainly because coffins are the second most easily available elements on the earth, and they have the advantages of low material cost, no toxicity, and high stability. And it has a solid foundation in the application of semiconductors.

The solar cells based on coffins include three types: single crystal germanium, polycrystalline germanium and amorphous germanium. The use of polycrystalline germanium as a raw material for solar cells is mainly based on cost considerations because it is compared to the conventional CZ method and the floating zone method (FZ method). Crystal germanium, polycrystalline germanium prices are relatively cheaper. The use of polycrystalline germanium in the manufacture of solar cells has traditionally been produced using conventional casting processes. The cast twine ingots must be cut to obtain a tantalum wafer that can be made into a solar cell type.

Although the price of polysilicon has fallen rapidly, wafer fabrication still requires wafer growth and dicing, which makes it difficult to further reduce the cost of polysilicon wafers. In particular, the cost of cutting is currently much higher than the cost of crystal growth, which is about twice the cost of crystal growth. The cutting wire, the tantalum carbide, and the cutting liquid for cutting are expensive. In addition, the loss of the twin-crystal ingot after wafer cutting is as high as 40% or more, which is not only inefficient, high in cost, but also burdens the environment. Therefore, the technology of non-cut wafer fabrication has always been an area that is highly valued by the long crystal technology. However, the quality of existing wafers without cutting technology is mostly less than expected. For example, the String Ribbon (RS) [4-6] has been in development for 30 years and it is still difficult to gain a foothold in the market.

The non-cut wafer fabrication technology is divided into a first type and a second type according to the solidification direction of the crystal growth and the direction of movement of the wafer or the ribbon [7]. Regarding the first type, the solidification direction is parallel to the wafer moving direction, and the second type is almost perpendicular to the wafer moving direction. The more famous linear twin ribbon technology belongs to the first type of technology. The second type of non-cut wafer fabrication technology is represented by the Ribbon Growth on Substrate (RGS). First type The state of the art also commercialized the earliest Edge-Defined Film-Fed growth (EFG). However, the photoelectric conversion efficiency of the subsequent solar cells fabricated by the RS method and the EFG method is not very high, and the average is about 15%. The second type of technology is mostly in development. Since most of its crystal growth defects occur along the growth direction and deteriorate and spread, the defects are mostly parallel to the wafer surface. Since the minority carrier transfer direction of the battery is perpendicular to the wafer surface, the chances of a small number of carriers being captured are high, which may cause the battery conversion efficiency to be low. Therefore, in the past ten years, most of the newly proposed methods are based on the second type of technology, that is, the direction of defect growth is the same as that of the minority carriers. For example, Sharp's Crystalization on Dipped Substrate (CDS) [8-11] developed in 1997 and the Cast Wafer [12] proposed by 1366 are quite close. However, the biggest problem with germanium wafers fabricated by the CDS method is that the grains are too small and the defect density is too high, and the germanium wafer thickness is hard to be less than 300 μm. Of course this is closely related to its growth mechanism. Sharp proposed the patent for substrate design [9-11], which has a protrusion on the substrate, allowing the crystal to nucleate at the protruding point of the protrusion, which is grown by the growth of the point-to-face. This point contact makes the wafer It is easy to get rid of, but it also causes the problem of too small a grain. 1366's foundry wafer method is similar to Sharp's CDS method, except that the substrate is modified to use a porous material to control the adhesion of the wafer to the substrate through differential pressure [12].

In addition, GE Solar also used the technology of the Molded Wafer (early known as Silicon Film) proposed by the early AstroPower company [13-14]. This technique is characterized in that a granular ruthenium material is first coated on a substrate, and then nucleated into a columnar crystal by continuous nucleation. It is worth noting that this is a solid feed, and the long crystal interface is parallel to the direction in which the wafer is pulled out, and the germanium grains are mainly nucleated by the underlying unmelted germanium particles and grow up into columnar crystals, which is closer to the first The growth of type II technology.

In the past, the development of non-cut wafer manufacturing technology mostly emphasized productivity, however, After more than 30 years of development, the biggest problem is still the quality of the wafer [16]. In the past, when the price of polycrystalline silicon fell, and the battery processing price was still high, the germanium wafer with low photoelectric conversion efficiency of the battery became uncompetitive. In other words, the germanium wafers produced by the current non-cut wafer fabrication technology have a defect density that is too high compared to polycrystalline germanium castings. Therefore, the conversion efficiency of the battery is difficult to be compared with that of a polycrystalline silicon germanium-cut silicon wafer. Conversion efficiency is counterbalanced. However, current battery processing prices have become cheaper, but the cost of cutting is too high. Therefore, such non-cutting, direct-made wafers are gaining attention. It is only this that will further improve the crystal growth technology to obtain low defect germanium wafers.

Accordingly, the technical problem to be solved by the present invention is to provide a method of manufacturing a semiconductor wafer, particularly a method of manufacturing a germanium wafer for use in manufacturing a solar cell. The method of the present invention is a method of directly cutting a semiconductor wafer without cutting, and the crystal growth rate of the semiconductor crystal grain can be controlled, assisting in manufacturing a substrate (mold) with less contamination and easily allowing the semiconductor wafer to be easily released, and manufacturing the semiconductor wafer. Thickness and uniformity are easily controlled, and the direction of defect formation in the semiconductor wafer is parallel to the minority carrier transport of the cell (same as the second type technique).

According to a preferred embodiment of the present invention, a method of fabricating a semiconductor wafer is first formed between a first mold and a second mold to form a molten semiconductor material. The first mold provides a first forming surface and the second mold provides a second forming surface opposite the first forming surface. Next, the method of the present invention controls at least one thermal field parameter with respect to the first mode and the second mode, such that the molten semiconductor material nucleates from the first molding surface or the center of the first mode and grows into a plurality of semiconductor grains . Next, the method of the present invention continues to control at least one thermal field parameter such that the plurality of semiconductor grains continue to grow toward the second forming surface or from the inside to the outside until the molten semiconductor material is completely solidified. Finally, the method of the present invention demolds and removes the fully solidified semiconductor material to obtain a semiconductor wafer.

In one embodiment, the inner wall of the first mold and the inner wall of the second mold are coated with a release agent. In practical applications, the release agent may be tantalum nitride, boron nitride, tantalum carbide, boron carbide, tantalum oxide, boron oxide, aluminum oxide, calcium fluoride or a mixture of the above compounds.

In one embodiment, the first mode and the second mode may be made of tantalum carbide, boron carbide, graphite, boron nitride, tantalum nitride, cerium oxide, aluminum oxide or a mixture of the above compounds.

In one embodiment, the first mode and the second mode are applied to the pressure of the molten semiconductor material and controlled during the control of the at least one thermal field parameter.

In one embodiment, the molding surface of the first mold has a plurality of protrusions thereon to assist in nucleation of the plurality of semiconductor grains.

In a specific embodiment, the first molding surface of the first mold is a first porous surface to provide a first differential pressure region, such that at least a portion of the first molding surface is controlled during the control of at least one thermal field parameter The pressure is less than the pressure of the molten semiconductor material. Further, during the process of demolding and taking out the completely solidified semiconductor material, the pressure in the first differential pressure region is lowered to demold and take out the semiconductor wafer.

In a specific embodiment, the second molding surface of the second mold is a second porous surface to provide a second differential pressure region, such that at least a portion of the second molding surface is controlled during the control of the at least one thermal field parameter The pressure is less than the pressure of the molten semiconductor material.

In one embodiment, the at least one thermal field parameter may include a first temperature gradient from the first mode to the second mode, a heat transfer flux of the first mode to the second mode, and a second to a periphery of the first mode Temperature gradient...etc.

Compared to the prior art of dicing wafer fabrication, the method according to the invention The manufactured semiconductor wafer has a small amount of impurities, is easy to be released from the mold, is easy to control in thickness and uniformity, and has a defect-generating direction in parallel with the minority carrier transport of the battery, and is a semiconductor wafer of good quality.

The advantages and spirit of the present invention will be further understood from the following detailed description of the invention.

Referring to FIGS. 1 through 6, a preferred embodiment of a method of fabricating a semiconductor wafer of the present invention is schematically illustrated in a cross-sectional view. An example of an apparatus 1 for performing the method of the present invention is also illustrated in the figures. The method of the present invention can directly produce a tantalum wafer for use in the manufacture of solar cells without cutting. Here, the semiconductor wafer covers the germanium wafer.

As shown in Figs. 1 to 6, the structure of the apparatus 1 for carrying out the method of the present invention comprises an outer furnace body composed of an upper outer cover 14a and a lower outer cover 14b, and an inner furnace body composed of an upper inner cover 15a and a lower inner cover 15b. The outer furnace body composed of the upper outer cover 14a and the lower outer cover 14b may be made of stainless steel and provided with a water cooling system. The upper inner cover 15a and the lower inner cover 15b may be made of stainless steel. A slide rail 16a is attached to the outer wall of the upper inner cover 15a so that the upper outer cover 14a can be moved up and down with respect to the upper inner cover 15a. A slide rail 16b is attached to the outer wall of the lower inner cover 15b, so that the lower outer cover 14b can be moved up and down with respect to the lower inner cover 15b. A spring 19 is attached between the top of the upper inner cover 15a and the upper outer cover 14a for support. A hard insulating spacer 17a and a soft insulating spacer 18a are attached to the upper inner cover 15a. A hard insulating spacer 17b and a soft insulating spacer 18b are attached to the lower inner cover 15b. The hard insulating gasket 17a and the hard insulating gasket 17b may be made of Al ₂ O ₃ . The soft insulating gasket 18a and the soft insulating gasket 18b may be made of a graphite/carbon fiber composite material.

The apparatus 1 for carrying out the method of the invention also comprises a first mould 10 and a second mould 12. The first mold 10 provides a first forming surface 102, and the second mold 12 provides The first forming surface 102 is opposite the second forming surface 122. In FIG. 1 to FIG. 6, for convenience of description, the first mold 10 is used as the upper mold, and the second mold 12 is used as the lower mold, but the method of the present invention is not limited thereto. In FIGS. 1 to 6, the first die 10 is supported by a hard insulating spacer 17a, and the second die 12 is supported by a hard insulating spacer 17b. The apparatus 1 for carrying out the method of the invention also comprises an upper heater 13a and a lower heater 13b. The upper heater 13a penetrates between the first mold 10 and the soft insulation gasket 18a for heating the first mold 10. The lower heater 13b penetrates between the second mold 12 and the soft insulation gasket 18b for heating the second mold 12. In a specific embodiment, the upper heater 13a and the lower heater 13b may be made of graphite.

The apparatus 1 for carrying out the method of the invention also comprises an inert gas conduit L1 which extends through the upper outer casing 14a and the upper inner casing 15a, respectively, to which the end p0 of the inert gas conduit L1 is connected. The inert gas conduit L1 is provided with a differential pressure regulating valve V1 and a differential pressure regulating valve V2 for respectively regulating the pressure of the end p3 near the first die 10 and the end p1 (between the upper outer cover 14a and the upper inner cover 15a) pressure. The apparatus 1 for carrying out the method of the invention also comprises an inert gas conduit L2 which extends through the lower outer casing 14b and the lower inner casing 15b, respectively, and the end p0 of the inert gas conduit L2 is likewise connected to the vacuum pump. The inert gas conduit L2 is provided with a differential pressure regulating valve V3 for regulating the pressure of the end p2 near the second die 12.

As shown in FIGS. 1 to 3, first, the method of the present invention is between the first mold 10 and the second mold 12 to form a molten semiconductor material 22. In one example, the solid state semiconductor material 20 is placed first on the second forming surface 122 of the second mold 12, as shown in FIG. In practical applications, the solid state semiconductor feedstock 20 can be a block, scrap or granule. For example, in the case of a tantalum wafer produced by the method of the present invention, the solid semiconductor material 20 can be a high purity tantalum block, chopped material or tantalum particles. Next, the temperature of the second mold 12 rises above the melting point of the solid semiconductor material 20 to melt the solid semiconductor material 20 into the molten semiconductor material 22, as shown in FIG. Next, in FIG. 3, the first mold 10 and the second mold 12 are pressed. Hehe. In one embodiment, the configuration of the first die 10 and the second die 12 can form a cavity for filling the molten semiconductor material 22 within the cavity. In another embodiment, the first molding surface 102 of the first mold 10 and the second molding surface 122 of the second mold 12 are substantially planar, and the second molding surface 122 of the second mold 12 may have a melt-limited property. The semiconductor material 22, which is not overflowed by the semiconductor material 22, is filled in the sealed space formed by the first mold 10 and the second mold 12 when the first mold 10 and the second mold 12 are pressed together.

In another variation of the present invention, the temperature of the second mold 12 is raised to a temperature higher than the melting point of the semiconductor material 22, and then the molten semiconductor material 22 is dropped, and the first mold 10 and the second mold are pressed together. When pressed, the temperature of the forming surface 102 of the first mold 10 may be higher or lower than the melting point of the molten semiconductor material 22. The pressing of the molding surface 102 of the first mold 10 at a temperature higher than the melting point of the molten semiconductor material 22 is first formed and then solidified, but such a manufacturing rate is relatively slow. Alternatively, the temperature of the molding surface 102 of the first mold 10 may be lower than the melting point of the molten semiconductor material 22, and molding and solidification may be simultaneously performed at the time of pressing.

In another variation of the invention, the shredded solid semiconductor material 20 is placed first on the second forming surface 122 of the second mold 12. Next, the first die 10 and the second die 12 are brought into close contact to form the cavity 14. The temperature of the first mold 10 and/or the second mold 12 rises above the melting point of the solid semiconductor material 20 to melt the solid semiconductor material 20 in the cavity 14 into the molten semiconductor material 22.

Next, as shown in FIG. 4, the method of the present invention controls at least one thermal field parameter with respect to the first mold 10 and the second mold 12 such that the molten semiconductor material 22 is from the center of the first molding surface 102 or the first mold 10. The nucleation begins and grows into a plurality of semiconductor dies 24. In the example shown in FIG. 4, a plurality of semiconductor dies 24 are nucleated from the molding surface of the upper mold. In another variation of the present invention, a plurality of semiconductor dies 24 may be formed from the molding surface of the lower mold 12. At 122, nucleation began.

Next, as shown in FIG. 5, the method of the present invention continues to control at least one thermal field parameter such that the plurality of semiconductor dies 24 continue to grow toward the second molding surface 122 or from the inside to the outside until the molten semiconductor material 22 is completely solidified. The semiconductor wafer 2 is formed. In general, the semiconductor wafer 2 comprises a plurality of columnar semiconductor dies 24. By controlling the growth direction of the semiconductor die 24, the direction in which the semiconductor wafer 2 is generated is parallel to the minority carrier transmission of the subsequent battery.

Finally, as shown in FIG. 6, the method of the present invention releases and removes the completely solidified semiconductor material (semiconductor sheet 2), that is, the semiconductor wafer 2 is obtained. By the design of the first mold 10 and the second mold 12, the thickness and uniformity of the semiconductor wafer 2 can be easily controlled. By the method of the present invention, the thickness of the semiconductor wafer 2 can be 300 μm or less, or even 150 μm, and excellent uniformity is maintained.

In one embodiment, if the germanium wafer is formed by the method of the present invention, the first mold 10 and the second mold 12 may be made of tantalum carbide, boron carbide, graphite, boron nitride, tantalum nitride, tantalum oxide, and oxidation. Aluminium or a mixture of the above compounds. The above material is preferably tantalum carbide or graphite, and the first mold 10 and the second mold 12 made of tantalum carbide or graphite are low in contamination, and the solid semiconductor raw material 20 has less impurities, and the semiconductor wafer 2 having less impurities can be formed.

In one embodiment, the inner wall of the first mold 10 and the inner wall of the second mold 12 are coated with a release agent to facilitate demolding of the semiconductor wafer 2. In practical applications, the release agent may be tantalum nitride, boron nitride, tantalum carbide, boron carbide, tantalum oxide, boron oxide, aluminum oxide, calcium fluoride or a mixture of the above compounds.

In one embodiment, during the control of at least one thermal field parameter, the first mold 10 and the second mold 12 are applied to the pressure of the molten semiconductor material 22 and are controlled. The pressure applied to the molten semiconductor material 22 can lower the melting point of the molten semiconductor material 22 and contribute to solidification of the molten semiconductor material 22. However, the pressure applied to the molten semiconductor material 22 must be controlled to avoid half The conductor sheet 2 is deformed or has excessive lattice defects.

In one embodiment, the molding surface 102 of the first mold 10 has a plurality of protrusions (not shown in FIGS. 1 to 6). To assist the plurality of semiconductor dies 24 to easily nucleate at the protruding points of the protrusions.

In one embodiment, the first molding surface 102 of the first mold 10 is a first porous surface (not shown in FIGS. 1 to 6). Passing an inert gas through the first porous surface to provide a first differential pressure region such that during control of the at least one thermal field parameter, the pressure at at least a portion of the first forming surface 102 is less than the molten semiconductor material 22 The molten, molten semiconductor material 22 will adhere to the first forming surface 102. Further, during the process of demolding and taking out the completely solidified semiconductor material (semiconductor sheet 2), the pressure in the first differential pressure region is lowered to release and take out the semiconductor wafer 2.

In a specific embodiment, the second molding surface 122 of the second mold 12 is a second porous surface (not shown in FIGS. 1 to 6). Passing an inert gas through the second porous surface to provide a second differential pressure region such that during control of the at least one thermal field parameter, the pressure at least a portion of the second forming surface 122 is less than the molten semiconductor material 22 The molten, molten semiconductor material 22 will adhere to the second forming surface 122.

In one embodiment, the at least one thermal field parameter may include a first temperature gradient of the first die 10 to the second die 12, a heat transfer flux of the first die 10 to the second die 12, and a center of the first die 10. The second temperature gradient to the periphery...etc.

Compared with the prior art of the non-cut wafer fabrication, the semiconductor wafer manufactured according to the method of the present invention has less impurities, is easy to demold, and is easy to control in thickness and uniformity, and the direction of defect formation therein is parallel to the minority carrier transmission of the battery. It is a good quality semiconductor wafer.

With the details of the above preferred embodiments, it is hoped that it will be clearer. The invention is not limited by the scope of the invention as described in the preferred embodiments. On the contrary, the intention is to cover various modifications and equivalents within the scope of the invention as claimed. Therefore, the scope of the patented scope of the invention should be construed as broadly construed in the

1‧‧‧ Equipment

10‧‧‧ first model

102‧‧‧First molding surface

12‧‧‧ second mode

122‧‧‧Second molding surface

13a‧‧‧Upper heater

13b‧‧‧ Lower heater

14a‧‧‧Upper cover

14b‧‧‧ Lower cover

15a‧‧‧Upper inner cover

15b‧‧‧Under the inner cover

16a, 16b‧‧‧ slide rails

17a, 17b‧‧‧ Hard insulating gasket

18a, 18b‧‧‧soft insulation gasket

19‧‧‧ Spring

20‧‧‧Solid semiconductor raw materials

22‧‧‧fused semiconductor raw materials

24‧‧‧Semiconductor grains

2‧‧‧Semiconductor sheet

L1, L2‧‧‧ inert gas conduit

V1, V2, V3‧‧‧ differential pressure regulating valve

End of p0, p1, p2, p3‧‧

BRIEF DESCRIPTION OF THE DRAWINGS Figures 1 through 6 are cross-sectional views showing a process of a preferred embodiment of a method of fabricating a semiconductor wafer of the present invention.

1‧‧‧ Equipment

10‧‧‧ first model

102‧‧‧First molding surface

12‧‧‧ second mode

122‧‧‧Second molding surface

13a‧‧‧Upper heater

13b‧‧‧ Lower heater

14a‧‧‧Upper cover

14b‧‧‧ Lower cover

15a‧‧‧Upper inner cover

15b‧‧‧Under the inner cover

16a, 16b‧‧‧ slide rails

17a, 17b‧‧‧ Hard insulating gasket

18a, 18b‧‧‧soft insulation gasket

19‧‧‧ Spring

22‧‧‧fused semiconductor raw materials

24‧‧‧Semiconductor grains

L1, L2‧‧‧ inert gas conduit

V1, V2, V3‧‧‧ differential pressure regulating valve

End of p0, p1, p2, p3‧‧

Claims (10)

A method of fabricating a semiconductor wafer comprising the steps of: (a) forming a molten semiconductor material between a first mold and a second mold, wherein the first mold provides a first forming surface, the second The mold provides a second forming surface opposite the first forming surface; (b) controlling at least one thermal field parameter with respect to the first mold and the second mold, such that the molten semiconductor material is from the first forming surface or The center of the first mold begins to nucleate and grow into a plurality of semiconductor dies; (c) continues to control the at least one thermal field parameter such that the plurality of semiconductor dies continue to grow toward the second forming surface or from the inside to the outside The molten semiconductor material is completely solidified; and (d) the fully solidified semiconductor material is released and taken out to obtain the semiconductor wafer. The method of claim 1, wherein the inner wall of the first mold and the inner wall of the second mold are coated with a release agent. The method of claim 2, wherein the release agent is selected from the group consisting of tantalum nitride, boron nitride, tantalum carbide, boron carbide, cerium oxide, boron oxide, aluminum oxide, calcium fluoride, and a mixture of the foregoing compounds. One of the groups. The method of claim 2, wherein the first mode and the second mode are selected from the group consisting of cerium carbide, boron carbide, graphite, boron nitride, tantalum nitride, cerium oxide, aluminum oxide, and a mixture of the foregoing compounds. One of the group consisting of. The method of claim 1, wherein in step (b), the pressure applied by the first mold and the second mold to the molten semiconductor material is controlled. The method of claim 1, wherein the molding surface of the first mold has a plurality of protrusions to assist in nucleation of the plurality of semiconductor grains. The method of claim 1, wherein the first molding surface of the first mold is a first porous surface to provide a first differential pressure region, such that in the step (b), the first molding surface The pressure at at least a portion of the pressure is less than the pressure of the molten semiconductor material. The method of claim 7, wherein in the step (d), the pressure of the first differential pressure region is lowered to demold and take out the semiconductor wafer. The method of claim 1, wherein the second molding surface of the second mold is a second porous surface to provide a second differential pressure region, such that in the step (b), the second molding surface The pressure at at least a portion of the pressure is less than the pressure of the molten semiconductor material. The method of claim 1, wherein the at least one thermal field parameter comprises a first temperature gradient selected from the first mode to the second mode, a heat transfer flux of the first mode to the second mode, and One of the group consisting of the second temperature gradient of the center of the first mode to the periphery.