TWI596786B - Back contact solar cell and method for manufacturing the same - Google Patents

Description

Back contact solar cell and method of manufacturing same

This invention relates to a solar cell, and more particularly to a back contact solar cell.

At present, high-efficiency solar cells still belong to back-contact high-current solar cells and heterojunction high-voltage solar cells. In general, back contact high current solar cells have a higher short circuit current (Jsc), while heterojunction high voltage solar cells have a higher open circuit voltage (Voc).

Please refer to FIG. 1 , which is a cross-sectional view showing a conventional back contact solar cell. The back contact solar cell 100 mainly includes an n-type substrate 102, an n ⁺ type front surface field 104, a first passivation layer 106, an n ⁺ -type doping region 108, a p ⁺ -type doping region 110, and a second passivation layer. 112. The first electrode 114 and the second electrode 116.

In the back contact solar cell 100, the n-type substrate 102 has a front side 118 and a back side 120, wherein the front side 118 and the back side 120 are respectively located on opposite sides of the n-type substrate 102. The front surface 118 is generally a back surface of the light receiving surface of the solar cell 100, and is provided with a roughness 122 thereon to increase the amount of light entering the n-type substrate 102. The n ⁺ -type front electric field 104 is provided entirely within the n-type substrate 102 and on the front side 118. The first passivation layer 106 overlies the front side 118 of the n-type substrate 102.

The n ⁺ -type doped region 108 and the p ⁺ -type doped region 110 are respectively disposed in a partial region within the n-type substrate 102 and adjacent to the back surface 120 of the n-type substrate 102. The second passivation layer 112 is overlaid on the back surface 120 of the n-type substrate 102. The first electrode 114 is disposed on the second passivation layer 112 and electrically connected to the n ⁺ -type doping region 108 through the second passivation layer 112 . The second electrode 116 is also disposed on the second passivation layer 112 and electrically connected to the p ⁺ -type doping region 110 through the second passivation layer 112 .

Please refer to FIG. 2 , which is a cross-sectional view showing a conventional heterojunction solar cell. The heterojunction solar cell 200 mainly includes an n-type substrate 202, an intrinsic amorphous germanium layer 204, an n-type amorphous germanium layer 206, a transparent conductive layer 208, an intrinsic amorphous germanium layer 210, and a p-type amorphous germanium layer 212. The first electrode 214 and the second electrode 216.

In the heterojunction solar cell 200, the n-type substrate 202 has a front surface 218 and a rear surface 220 which are respectively located on opposite sides of the n-type substrate 202. The front surface 218 of the n-type substrate 202 is generally a light receiving surface of the heterojunction solar cell 200, and is provided with a roughness 222 thereon to increase the amount of light entering the n-type substrate 202. The intrinsic amorphous germanium layer 204 is provided entirely on the front side 218 of the n-type substrate 202 to provide the effect of passivating the front side 218 of the n-type substrate 202. The n-type amorphous germanium layer 206 is overlaid on the intrinsic amorphous germanium layer 204, wherein the doping concentration of the n-type amorphous germanium layer 206 is greater than the doping concentration of the n-type substrate 202. A transparent conductive layer 208 is overlaid on the n-type amorphous germanium layer 206 to provide electrical conduction, thereby improving the problem of poor electrical performance due to high impedance of the amorphous germanium material.

As shown in FIG. 2, an intrinsic amorphous germanium layer 210 is provided on the back surface 220 of the n-type substrate 202. The p-type amorphous germanium layer 212 is covered by the intrinsic amorphous germanium On layer 210. The n-type substrate 202, the intrinsic amorphous germanium layer 210 and the p-type amorphous germanium layer 212 form a heterostructure junction. The first electrode 214 is disposed on the transparent conductive layer 208 and is electrically connected to the transparent conductive layer 208. The second electrode 216 is disposed on the p-type amorphous germanium layer 212 and is electrically connected to the p-type amorphous germanium layer 212.

Therefore, an object of the present invention is to provide a back contact solar cell and a method of fabricating the same, which form an intrinsic type and a second conductivity type amorphous semiconductor layer which are sequentially stacked on the back surface of the first conductive type substrate, and thus are intrinsic The second conductive type amorphous semiconductor layer can form a heterojunction junction with the first conductive type substrate, whereby the open circuit voltage of the solar cell can be effectively improved. In addition, the solar cell has a back contact electrode design that enhances the short circuit current of the solar cell.

Another object of the present invention is to provide a back contact solar cell and a method of fabricating the same, which are provided with a transparent conductive oxide layer on the back surface of the first conductive type substrate as electrical conduction, thereby improving the resistance of the amorphous semiconductor layer Higher problem. Further, the arrangement of the transparent conductive oxide layer can also enhance the adhesion between the metal electrode and the amorphous semiconductor layer. Furthermore, the transparent conductive oxide layer can serve as a seed layer not only for the subsequent plating of the metal electrode, but also for preventing the diffusion of the metal.

It is still another object of the present invention to provide a method of fabricating a back contact solar cell that utilizes ion implantation techniques to directly dope in a pre-formed region to form a front electric field and a bask surface field. Therefore, the method can reduce the number of process steps compared to the conventional furnace tube diffusion process.

According to the above object of the present invention, a method of manufacturing a back contact solar cell is proposed. In this method, a back surface electric field of the homojunction is formed in a first region of the back surface of the semiconductor substrate, wherein the electric field on the back surface of the homojunction and the semiconductor substrate are both of the first conductivity type. Forming a first passivation layer covers the back surface electric field of the aforementioned homojunction. Forming a second region of the back surface of the amorphous semiconductor layer, wherein the amorphous semiconductor layer comprises a first sub-layer and a second sub-layer on the first sub-layer, the first sub-layer being intrinsic, the second sub-layer It is a second conductivity type. A contact opening is formed in the aforementioned first passivation layer. Forming a transparent conductive oxide layer, wherein the transparent conductive oxide layer comprises a first block and a second block separated from the first block, the first block being connected to the back surface electric field of the homojunction via the contact window opening, The second block covers the second sub-layer. Forming the two electroplated metal electrodes are respectively located on the first block and the second block of the transparent conductive oxide layer.

According to an embodiment of the present invention, the method for fabricating the back contact solar cell further includes: forming a front electric field in a front surface of the semiconductor substrate; and forming a second passivation layer covering the front electric field, wherein each of the first passivation layer and the second passivation The layer comprises a tantalum oxide layer and a tantalum nitride layer, and the tantalum oxide layer of the first passivation layer and the tantalum oxide layer of the second passivation layer are simultaneously formed in a thermal oxidation process after the formation of the front electric field.

According to another embodiment of the present invention, the tantalum nitride layer of the first passivation layer and the tantalum nitride layer of the second passivation layer are respectively formed in a two deposition process.

According to still another embodiment of the present invention, before the step of forming the front electric field, the method for manufacturing the back contact solar cell further includes a semiconductor An etching step is performed on the front side of the substrate to form a pyramid-like structure on the front surface.

According to still another embodiment of the present invention, the step of forming the first passivation layer includes forming a passivation material layer covering the back surface of the semiconductor substrate, and removing a portion of the passivation material layer.

According to still another embodiment of the present invention, the step of forming the amorphous semiconductor layer includes: forming a first sub-material layer covering the back surface of the first passivation layer and the semiconductor substrate; forming a second sub-material layer covering the first sub-material layer; And removing a portion of the first sub-material layer and a portion of the second sub-material layer to form a first sub-layer and a second sub-layer sequentially stacked on the second region.

According to still another embodiment of the present invention, the step of forming a transparent conductive oxide layer comprises: forming a transparent conductive oxide material layer covering the second sub-layer and the first passivation layer, wherein the transparent conductive oxide material layer is from the second sub-layer Extending to the first passivation layer; forming a barrier layer on the transparent conductive oxide material layer between the first block and the second block before the step of forming the plated metal electrode; and after forming the step of forming the plated metal electrode And removing the transparent conductive oxide material layer under the barrier layer and the barrier layer to form the first block and the second block separated from each other.

According to still another embodiment of the present invention, the step of forming a plated metal electrode includes, after the step of forming a barrier layer, using a transparent conductive oxide material layer as the plating seed layer.

According to still another embodiment of the present invention, the transparent conductive oxide material layer under the removal of the barrier layer utilizes an etch back process using a plated metal electrode as a plurality of etch masks.

According to the above object of the present invention, a back contact solar cell is further proposed. The back contact solar cell comprises a semiconductor substrate, a homogenous junction back surface electric field, a passivation layer, an amorphous semiconductor layer, a transparent conductive oxide layer, and a two-plated metal electrode. The electric field on the back surface of the homojunction is disposed in the first region of the back surface of the semiconductor substrate, wherein the electric field on the back surface of the homojunction and the semiconductor substrate are both of the first conductivity type. The passivation layer covers the back surface electric field of the homojunction, wherein the passivation layer comprises a tantalum oxide layer and a tantalum nitride layer which are sequentially stacked, and the passivation layer has a contact window opening. The amorphous semiconductor layer is disposed on the second region of the back surface, wherein the amorphous semiconductor layer comprises a first sub-layer and a second sub-layer on the first sub-layer, the first sub-layer is of an essential type, the second sub- The layer is of the second conductivity type. The transparent conductive oxide layer comprises a first block and a second block separated from the first block, wherein the first block is connected to the back surface electric field of the homojunction via the contact window opening, and the second block is located at the second block On the second sub-layer. The two electroplated metal electrodes are respectively located on the first block and the second block of the transparent conductive oxide layer.

100‧‧‧Back contact solar cells

102‧‧‧n type substrate

104‧‧‧n ⁺ type front electric field

106‧‧‧First passivation layer

108‧‧‧n ⁺ doped area

110‧‧‧p ⁺ doped region

112‧‧‧Second passivation layer

114‧‧‧First electrode

116‧‧‧Second electrode

118‧‧‧ positive

120‧‧‧Back

122‧‧‧Rough structure

200‧‧‧Hexual junction solar cells

202‧‧‧n type substrate

204‧‧‧ Essential amorphous layer

206‧‧‧n type amorphous layer

208‧‧‧Transparent conductive layer

210‧‧‧ Essential amorphous layer

212‧‧‧p-type amorphous germanium layer

214‧‧‧First electrode

216‧‧‧second electrode

218‧‧‧ positive

220‧‧‧Back

300‧‧‧ Back contact solar cells

302‧‧‧Semiconductor substrate

304‧‧‧Homogeneous junction back surface electric field

306‧‧‧ Passivation layer

308‧‧‧Amorphous semiconductor layer

310‧‧‧Transparent conductive oxide layer

312‧‧‧Electroplated metal electrodes

314‧‧‧Electroplated metal electrodes

316‧‧‧ positive

318‧‧‧ back

320‧‧‧Rough structure

322‧‧‧First area

324‧‧‧Oxide layer

326‧‧‧layer of tantalum nitride

328‧‧‧Contact window opening

330‧‧‧Second area

332‧‧‧ first sub-layer

334‧‧‧ second sub-layer

336‧‧‧ first block

338‧‧‧Second block

340‧‧‧ front electric field

342‧‧‧ Passivation layer

344‧‧‧Oxide layer

346‧‧‧ layer of tantalum nitride

400‧‧‧Back contact solar cell

402‧‧‧Semiconductor substrate

404‧‧‧ positive

406‧‧‧Back

408‧‧‧Rough structure

410‧‧‧Homogeneous junction back surface electric field

412‧‧‧First area

414‧‧‧ front electric field

416‧‧‧ Passivation material layer

418‧‧‧Oxide layer

420‧‧‧ tantalum nitride layer

422‧‧‧Second passivation layer

424‧‧‧Oxide layer

426‧‧‧ layer of tantalum nitride

428‧‧‧First passivation layer

430‧‧‧ etching mask

432‧‧‧Oxide layer

434‧‧‧layer of tantalum nitride

436‧‧‧Amorphous semiconductor material layer

438‧‧‧First child material layer

440‧‧‧Second sub-material layer

442‧‧‧Amorphous semiconductor layer

444‧‧‧Second area

446‧‧‧ etching mask

448‧‧‧ first sub-layer

450‧‧‧Second sub-layer

452‧‧‧Contact window opening

454‧‧‧Transparent conductive oxide material layer

456‧‧‧Barrier

458‧‧‧Electroplated metal electrode

460‧‧‧Electroplated metal electrode

462‧‧‧Transparent conductive oxide layer

464‧‧‧First block

466‧‧‧Second block

The above and other objects, features, advantages and embodiments of the present invention will become more <RTIgt; <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; Is a schematic cross-sectional view of a conventional heterojunction solar cell; [Fig. 3] is a schematic cross-sectional view of a back contact solar cell according to an embodiment of the present invention; 4A to 4H are schematic cross-sectional views showing a process of a back contact solar cell according to an embodiment of the present invention.

Please refer to FIG. 3 , which is a cross-sectional view of a back contact solar cell according to an embodiment of the present invention. The back contact solar cell 300 is a heterogeneous/homogeneous hybrid junction back contact solar cell. In some examples, the back contact solar cell 300 primarily includes a semiconductor substrate 302, a homojunction back surface electric field 304, a passivation layer 306, an amorphous semiconductor layer 308, a transparent conductive oxide layer 310, and two plated metal electrodes 312 and 314.

The semiconductor substrate 302 may be a first conductive type crystal system substrate, for example, a substrate formed of an n-type crystal germanium. The semiconductor substrate 302 has a front side 316 and a back side 318 opposite the front side 316. In some exemplary examples, the front side 316 of the semiconductor substrate 302 may be roughened by etching or the like, but has a plurality of roughness structures 320. For example, these roughness structures 320 can be pyramid-like structures.

The homojunction back surface electric field 304 is disposed in the first region 322 of the back surface 318 of the semiconductor substrate 302. The homojunction back surface electric field 304 can be a doped portion, such as a phosphorus doped portion. The homojunction back surface electric field 304 is the same as the conductivity type of the semiconductor substrate 302, for example, an n-type, and the doping concentration of the homojunction back surface electric field 304 is higher than that of the semiconductor substrate 302.

The passivation layer 306 is located on the back side 318 of the semiconductor substrate 302 and covers the homojunction back surface electric field 304. In some examples, passivation layer 306 includes a hafnium oxide layer 324 and a tantalum nitride layer 326 that are sequentially stacked on a homojunction back surface electric field 304. As shown in FIG. 3, the passivation layer 306 has at least one contact opening. 328. The contact opening 328 extends through the passivation layer 306, sequentially through the tantalum nitride layer 326 and the hafnium oxide layer 324, exposing a portion of the homojunction back surface electric field 304.

The amorphous semiconductor layer 308 is provided on the second region 330 of the back surface 318 of the semiconductor substrate 302. In the present embodiment, the first region 322 of the back surface 318 and the second region 330 do not overlap, and the amorphous semiconductor layer 308 includes a first sub-layer 332 and a second sub-layer 334 on the first sub-layer 332, wherein The first sub-layer 332 is interposed between the back side 318 and the second sub-layer 334. The first sub-layer 332 is an intrinsic amorphous semiconductor layer, and the second sub-layer 334 is a second-conductivity-type amorphous semiconductor layer. The second conductivity type may be, for example, a p-type.

In some examples, the transparent conductive oxide layer 310 includes a first block 336 and a second block 338, wherein the first block 336 and the second block 338 are separated from one another. As shown in FIG. 3, the first block 336 is disposed on the passivation layer 306 and is in contact with the exposed portion of the homojunction back surface electric field 304 via the contact window opening 328. The second block 338 overlies the second sub-layer 334 of the amorphous semiconductor layer 308. The plated metal electrodes 312 and 314 are respectively located on the first block 336 and the second block 338 of the transparent conductive oxide layer 310. Since the first block 336 is separated from the second block 338, the plated metal electrodes 312 and 314 located on the first block 336 and the second block 338, respectively, are also separated from each other.

The back contact solar cell 300 has both a back contact structure and a heterojunction structure. The back contact structure can increase the amount of light absorption of the back contact solar cell 300, and can increase the short circuit current of the element. On the other hand, the heterojunction structure can obtain a higher electric field and can increase the open circuit voltage of the component. Therefore, the back contact solar cell 300 has both high short-circuit current and high open circuit voltage characteristics.

Referring again to FIG. 3, the back contact solar cell 300 further includes a front electric field 340 that is formed entirely in the front side 316 of the semiconductor substrate 302. The front electric field 340 has the same conductivity type as the substrate 302. In some examples, the back contact solar cell 300 can further include a passivation layer 342 on the front side 316 of the semiconductor substrate 302 and overlying the front electric field 340. In some exemplary examples, passivation layer 342 may include a hafnium oxide layer 344 and a tantalum nitride layer 346 that are sequentially stacked on front electric field 340.

4A to 4H are schematic cross-sectional views showing a process of a back contact solar cell according to an embodiment of the present invention. In some examples, when the back contact solar cell 400 as shown in FIG. 4H is fabricated, the semiconductor substrate 402 may be provided first. The semiconductor substrate 402 may be a first conductive type crystal system substrate, for example, a substrate formed of an n-type crystal germanium. The semiconductor substrate 402 has a front side 404 and a back side 406 opposite the front side 404. In some exemplary examples, as shown in FIG. 4A, the front side 404 of the semiconductor substrate 402 may be selectively etched according to product requirements to roughen the front side 404 and form a plurality of roughness structures 408 on the front side 404. For example, these roughness structures 408 can be pyramid-like structures.

Next, as shown in FIG. 4B, a homojunction back surface electric field 410 is formed in the first region 412 of the back surface 406 of the semiconductor substrate 402 using, for example, an ion implantation process. The homogenous junction back surface electric field 410 may be doped with a plurality of dopants, such as phosphorus, after the ion implantation process. Homogeneous junction back surface electric field 410 and semiconducting The body substrates 402 may all be of a first conductivity type, such as an n-type. The doping concentration of the homojunction back surface electric field 410 can be higher than that of the semiconductor substrate 402. In some exemplary embodiments, when the homojunction back surface electric field 410 is formed, a mask layer (not shown) may be first covered in a region other than the first region 412 of the back surface 406 to prevent the dopant from being implanted outside the first region 412. The back 406 area.

Referring again to FIG. 4B, the front electric field 414 can be formed within the entire front side 404 of the semiconductor substrate 402 using, for example, an ion implantation process after the roughness 408 is formed. The conductivity type of the front electric field 414 is the same as that of the semiconductor substrate 402. When the conductivity type of the semiconductor substrate 402 is n-type, the front electric field 414 can be formed by doping phosphorus with an ion implantation process. In some examples, the front electric field 414 can be formed after the homojunction back surface electric field 410 is formed. In other examples, the front electric field 414 can be formed prior to the formation of the homojunction back surface electric field 410. Since the front electric field 414 and the homojunction back surface electric field 410 can be formed by the ion implantation process, the present embodiment can reduce the process steps of defining the back surface electric field by, for example, lithography and etching, compared to the conventional furnace tube diffusion process.

As shown in FIG. 4C, a passivation material layer 416 is formed overlying the entire back surface 406 of the semiconductor substrate 402. In some examples, passivation material layer 416 includes a hafnium oxide layer 418 and a tantalum nitride layer 420 that are sequentially stacked on back side 406. For example, the yttrium oxide layer 418 can be fabricated using a thermal oxidation process, and the tantalum nitride layer 420 can be fabricated using a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD) process.

Referring again to FIG. 4C, in some examples, a second passivation layer 422 can be formed over the front side 404 of the semiconductor substrate 402 and overlying the front electric field 414. In some examples, the second passivation layer 422 includes sequentially stacked in a positive The tantalum oxide layer 424 and the tantalum nitride layer 426 on the face 404. For example, the yttrium oxide layer 424 can be fabricated using a thermal oxidation process, and the tantalum nitride layer 426 can be fabricated using a chemical vapor deposition process or a physical vapor deposition process. In some exemplary examples, the hafnium oxide layer 418 of the passivation material layer 416 and the hafnium oxide layer 424 of the second passivation layer 422 may be simultaneously formed in a thermal oxidation process after the formation of the front electric field 414. In addition, the tantalum nitride layer 420 of the passivation material layer 416 and the tantalum nitride layer 426 of the second passivation layer 422 can be formed in a two-pass deposition process, respectively.

In some examples, referring also to FIGS. 4C and 4D, the passivation material layer 416 can be defined using, for example, a lithography and etching process, while the first passivation layer 428 is formed to cover the homojunction back surface electric field 410. For example, the operation of defining the passivation material layer 416 includes forming a passivation material layer 416 over the homojunction back surface electric field 410 using a lithography process to form an etch mask 430, and then removing the unetched mask 430 by an etch process. Portions of the material layer 416 are passivated while exposing a portion of the back side 406 of the semiconductor substrate 402. The step of removing the portion of the passivation material layer 416 includes removing a portion of the hafnium oxide layer 418 and a portion of the tantalum nitride layer 420 to form a hafnium oxide layer 432 and a tantalum nitride layer 434, respectively. Thereby, the formed first passivation layer 428 includes a tantalum oxide layer 432 and a tantalum nitride layer 434 which are sequentially covered on the homojunction back surface electric field 410. After the first passivation layer 428 is completed, the etch mask 430 can be removed by etching or stripping.

Next, as shown in FIG. 4E, an amorphous semiconductor material layer 436 is formed to cover the back surface 406 of the semiconductor substrate 402 and the first passivation layer 428. In an exemplary embodiment, the step of forming the amorphous semiconductor material layer 436 includes forming a first sub-material layer 438 overlying the first passivation layer 428 and the semiconductor substrate 402. The back side 406 then forms a second sub-material layer 440 overlying the first sub-material layer 438. The material of the first sub-material layer 438 is an intrinsic amorphous semiconductor such as an intrinsic amorphous germanium. The material of the second sub-material layer 440 is a second-conductivity-type amorphous semiconductor, for example, a second-conductivity-type amorphous germanium. For example, the step of forming the first sub-material layer 438 and the second sub-material layer 440 may utilize a plasma assisted chemical vapor deposition (PECVD) technique.

In some examples, referring to FIG. 4E and FIG. 4F simultaneously, the amorphous semiconductor material layer 436 can be defined by, for example, a lithography and etching process, and the amorphous semiconductor layer 442 is formed to cover the second region of the back surface 406 of the semiconductor substrate 402. 444. In the example shown in FIG. 4F, the first region 412 and the second region 444 of the back surface 406 do not overlap. For example, the operation of defining the amorphous semiconductor material layer 436 includes forming a portion of the amorphous semiconductor material layer 436 over the second region 444 of the back surface 406 by a lithography process etch mask 446, and then using an etch process The first passivation layer 428 is exposed except for portions of the amorphous semiconductor material layer 436 that are not masked by the etch mask 446. The step of removing the portion of the amorphous semiconductor material layer 436 includes removing a portion of the first sub-material layer 438 and a portion of the second sub-material layer 440 to form a first sub-layer 448 and a second sub-layer 450, respectively. Thereby, the formed amorphous semiconductor layer 442 includes the first sub-layer 448 and the second sub-layer 450 sequentially covering the second region 444 of the back surface 406.

In the present embodiment, since the process temperature of the first sub-material layer 438 and the second sub-material layer 440 forming the amorphous semiconductor material layer 436 is preferably not more than 200 ° C, the homogenization in the process temperature exceeds 200 ° C. After the surface back electric field 410 and the front electric field 414 are completed, the first sub-form is formed. The material layer 438 and the second sub-material layer 440 ensure the quality of the amorphous semiconductor material layer 436.

After the amorphous semiconductor layer 442 is completed, the etch mask 446 can be removed by etching or stripping. Next, referring again to FIG. 4F, the first passivation layer 428 is defined by, for example, a lithography and etching process to remove a portion of the ruthenium oxide layer 432 of the first passivation layer 428 and a portion of the tantalum nitride layer 434. A contact opening 452 is formed in the first passivation layer 428 through the yttrium oxide layer 432 and the tantalum nitride layer 434. The contact window opening 452 exposes a portion of the homogenous junction back surface electric field 410.

Next, as shown in FIG. 4G, a transparent conductive oxide material layer 454 is formed to cover the second sub-layer 450 of the amorphous semiconductor layer 442 and the first passivation layer 428 by, for example, sputtering deposition or chemical vapor deposition. A layer of transparent conductive oxide material 454 extends from the second sub-layer 450 to the first passivation layer 428 and fills the contact opening 452 in the first passivation layer 428 to interface with the homojunction back surface electric field 410. The material of the transparent conductive oxide material layer 454 may be, for example, bismuth oxide (SbO).

Subsequently, a barrier layer 456 is formed on the transparent conductive oxide material layer 454 over the region where the amorphous semiconductor layer 442 is adjacent to the first passivation layer 428. When the material of the barrier layer 456 is a dielectric material, the barrier layer 456 can be formed by deposition, lithography, and etching techniques. When the material of the barrier layer 456 is photoresist, the barrier layer 456 can be formed by spin coating and lithography. Next, the transparent conductive oxide material layer 454 can be a plated seed layer, and the two plated metal electrodes 458 and 460 are formed on the transparent conductive oxide material layer 454 by electroplating. Due to the arrangement of the barrier layer 456, the second electroplated gold The genus electrodes 458 and 460 are respectively located on the two sides of the barrier layer 456 and are separated by the barrier layer 456 as shown in FIG. 4G. The transparent conductive oxide material layer 454 prevents diffusion of the metal during the electroplating process of the plated metal electrodes 458 and 460.

As shown in FIG. 4H, after the plated metal electrodes 458 and 460 are formed, the barrier layer 456 and the transparent conductive oxide material layer 454 under the barrier layer 456 are removed to form the first block 464 and the second region separated from each other. The transparent conductive oxide layer 462 of block 466 substantially completes the fabrication of the back contact solar cell 400. In some exemplary examples, when the barrier layer 456 and the underlying transparent conductive oxide material layer 454 are removed, the barrier layer 456 is removed using, for example, an etch or strip process, and the plated metal electrodes 458 and 460 are used as an etch mask. The transparent conductive oxide material layer 454 under the barrier layer 456 is removed using an etch back process. It can be seen that the barrier layer 456 is previously formed on the transparent conductive oxide material layer 454 between the first block 464 and the second block 466, and the plated metal electrodes 458 and 460 are located in the first block 464 and the first Block 2 is on 466.

In the transparent conductive oxide layer 462, the first block 464 is located on a portion of the first passivation layer 428 and is in contact with the homojunction back surface electric field 410 via the contact window opening 452, and the second block 466 is covered by the amorphous semiconductor. The second sub-layer 450 of layer 442 is on. The transparent conductive oxide layer 462 can be used as an electrical conduction, thereby improving the problem of higher resistance of the amorphous semiconductor layer 442, and the second block 466 can also provide the effect of passivating the second sub-layer 450, and The adhesion between the plated metal electrode 460 and the second sub-layer 450 is enhanced.

It is obvious from the above embodiments that an embodiment of the present invention forms a sequential stack on the back surface of the first conductive type substrate. The intrinsic type and the second conductive type amorphous semiconductor layer, and thus the intrinsic type and the second conductive type amorphous semiconductor layer can form a heterojunction junction with the first conductive type substrate, thereby effectively improving the open circuit voltage of the solar cell . In addition, the solar cell has a back contact electrode design that enhances the short circuit current of the solar cell.

According to the above embodiments, another advantage of the present invention is that the transparent conductive oxide layer is disposed on the back surface of the first conductive type substrate as the electrical conduction, thereby improving the resistance of the amorphous semiconductor layer. Higher problem. Further, the arrangement of the transparent conductive oxide layer can also enhance the adhesion between the metal electrode and the amorphous semiconductor layer. Furthermore, the transparent conductive oxide layer can serve as a seed layer not only for the subsequent plating of the metal electrode, but also for preventing the diffusion of the metal.

According to the above embodiments, another advantage of the present invention is that the embodiment of the present invention can utilize the ion implantation technique to directly dope in the pre-formed region to form the front electric field and the back surface electric field of the homojunction. In a conventional furnace tube diffusion process, embodiments of the present invention can reduce process steps.

While the present invention has been described above by way of example, it is not intended to be construed as a limitation of the scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

300‧‧‧ Back contact solar cells

302‧‧‧Semiconductor substrate

304‧‧‧Homogeneous junction back surface electric field

306‧‧‧ Passivation layer

308‧‧‧Amorphous semiconductor layer

310‧‧‧Transparent conductive oxide layer

312‧‧‧Electroplated metal electrodes

314‧‧‧Electroplated metal electrodes

316‧‧‧ positive

318‧‧‧ back

320‧‧‧Rough structure

322‧‧‧First area

324‧‧‧Oxide layer

326‧‧‧layer of tantalum nitride

328‧‧‧Contact window opening

330‧‧‧Second area

332‧‧‧ first sub-layer

334‧‧‧ second sub-layer

336‧‧‧ first block

338‧‧‧Second block

340‧‧‧ front electric field

342‧‧‧ Passivation layer

344‧‧‧Oxide layer

346‧‧‧ layer of tantalum nitride

Claims (10)

A method for manufacturing a back contact solar cell, comprising: forming a back surface electric field of a homojunction in a first region of a back surface of a semiconductor substrate, wherein the electric field on the back surface of the homojunction and the semiconductor substrate are both of a first conductivity type; Forming a first passivation layer covering the back surface electric field of the homojunction; forming an amorphous semiconductor layer covering a second region of the back surface, wherein the amorphous semiconductor layer comprises a first sub-layer, and the first sub-layer a second sub-layer, the first sub-layer is of an intrinsic type, the second sub-layer is of a second conductivity type; forming a contact opening in the first passivation layer; forming a transparent conductive oxide layer, wherein The transparent conductive oxide layer includes a first block and a second block separated from the first block, and the first block is connected to the back surface electric field of the homojunction via the contact window opening, a second block overlying the second sub-layer; and forming a second electroplated metal electrode on the first block and the second block of the transparent conductive oxide layer, respectively. The method for manufacturing a back contact solar cell according to claim 1, further comprising: forming a front electric field in a front surface of the semiconductor substrate; and forming a second passivation layer covering the front electric field, wherein each of the first The passivation layer and the second passivation layer comprise a tantalum oxide layer and a tantalum nitride layer, and the tantalum oxide layer of the first passivation layer and the tantalum oxide layer of the second passivation layer are formed after the front electric field is formed Formed simultaneously in a thermal oxidation process. The method of manufacturing a back contact solar cell according to claim 2, wherein the tantalum nitride layer of the first passivation layer and the tantalum nitride layer of the second passivation layer are respectively formed in a two deposition process. The manufacturing method of the back contact solar cell of claim 2, before the step of forming the front electric field, further comprising: performing an etching step on the front surface of the semiconductor substrate to form a plurality of pyramid-like shapes on the front surface structure. The method of manufacturing a back contact solar cell according to claim 1, wherein the step of forming the first passivation layer comprises: forming a passivation material layer covering the back surface of the semiconductor substrate; and removing a portion of the passivation material layer. The manufacturing method of the back contact solar cell of claim 1, wherein the forming the amorphous semiconductor layer comprises: forming a first sub-material layer covering the first passivation layer and the back surface of the semiconductor substrate; forming a a second sub-material layer covering the first sub-material layer; and removing a portion of the first sub-material layer and a portion of the second sub-material layer to form the first sub-stack stacked on the second region a layer and the second sublayer. The method of manufacturing the back contact solar cell of claim 1, wherein the step of forming the transparent conductive oxide layer comprises: forming a transparent conductive oxide material layer covering the second sub-layer and the first passivation layer, wherein The transparent conductive oxide material layer extends from the second sub-layer to the first passivation layer; Forming a barrier layer on the transparent conductive oxide material layer between the first block and the second block before the step of forming the plated metal electrodes; and after the step of forming the plated metal electrodes Removing the barrier layer from the transparent conductive oxide material layer under the barrier layer to form the first block and the second block separated from each other. The method for manufacturing a back contact solar cell according to claim 7, wherein the step of forming the plated metal electrode comprises the step of forming the barrier layer, and using the transparent conductive oxide material layer as a plating seed layer. The method for manufacturing a back contact solar cell according to claim 7 , wherein removing the transparent conductive oxide material layer under the barrier layer utilizes an etch back process using the plated metal electrodes as one of a plurality of etching masks . A back contact solar cell comprising: a semiconductor substrate; a back surface electric field of a homojunction, disposed in a first region of a back surface of the semiconductor substrate, wherein the electric field on the back surface of the homojunction and the semiconductor substrate are both first conductive a passivation layer covering the back surface electric field of the homojunction, wherein the passivation layer comprises one of a tantalum oxide layer and a tantalum nitride layer stacked in sequence, and the passivation layer has a contact opening; an amorphous semiconductor layer Provided on a second region of the back surface, wherein the amorphous semiconductor layer includes a first sub-layer and is located in the first sub- a second sub-layer on the layer, the first sub-layer being of an intrinsic type, the second sub-layer being of a second conductivity type; a transparent conductive oxide layer comprising a first block, and the first block Separating a second block, wherein the first block is connected to the back surface electric field of the homojunction via the contact window opening, the second block is disposed on the second sub-layer; and the second electroplated metal electrode, The first block and the second block of the transparent conductive oxide layer are respectively located.