JP2015159198A - Photovoltaic element, manufacturing method therefor and manufacturing apparatus therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a photovoltaic element having a high fill factor, and to provide a manufacturing method and a manufacturing apparatus therefor.SOLUTION: A photovoltaic element including an n-type single crystal silicon substrate 1 having a first principal surface and a second principal surface, where light impinges on the first principal surface, and a p-type amorphous silicon layer 11 forming a pn junction on the first or second principal surface, has first and second electrodes, respectively, on the first and second principal surfaces. The first electrode includes an electroless Ni plating layer 18, as an underlying conductor layer, formed so as to wrap around from the first principal surface to the second principal surface, and an electrolyte Cu plating layer 19 formed thereon.

Description

  The present invention relates to a photovoltaic device, a manufacturing method thereof, and a manufacturing apparatus thereof, and more particularly to a photovoltaic device using a plating electrode.

  Current crystalline silicon solar cells are the most common photovoltaic devices, diffused solar cells with an impurity semiconductor layer formed by diffusion on the light-receiving surface side, and heterojunctions with an impurity semiconductor layer formed by a thin film such as amorphous silicon There is a back junction solar cell in which impurity semiconductor layers of the same and different conductivity types as the substrate and the substrate are arranged in a comb shape on the back side, and both types of solar cells are manufactured at a mass production level.

  Among these, a diffusion type solar cell uses a p-type crystalline silicon substrate having a thickness of about 200 μm, and has a surface texture, an n-type diffusion layer, an antireflection film and a surface electrode (for example, comb-shaped silver ( Ag) electrode) is sequentially formed on the light-receiving surface side of the substrate, and a back electrode (for example, an aluminum (Al) electrode) is formed on the non-light-receiving surface side of the substrate by screen printing. Generally, it is manufactured by baking with. In such firing, the solvent content of the front electrode and the back electrode volatilizes, and the comb Ag electrode penetrates the antireflection film on the light receiving surface side of the substrate and is connected to the n-type diffusion layer. On the surface side, a part of Al of the Al electrode diffuses into the substrate to form a back surface field layer (BSF: Back Surface Field).

  As cell structures that further improve the conversion efficiency, Patent Documents 1 to 3 disclose technologies relating to heterojunction solar cells in which a junction made of an impurity-doped silicon layer or a BSF layer is formed on a crystalline silicon substrate via a thin intrinsic semiconductor layer. ing. In this structure, the concentration distribution of the impurity doped layer can be freely set by forming the impurity doped layer as a thin film. Further, since this impurity-doped layer is thin, recombination of carriers and light absorption in the film can be suppressed. In addition, since the intrinsic semiconductor layer inserted between them can suppress impurity diffusion between the junctions and form a junction having a steep impurity profile, a high open-circuit voltage can be obtained by forming a good junction interface. Further, since the intrinsic semiconductor layer and the impurity doped layer can be formed at a low temperature of about 200 ° C., stress generated in the substrate due to heat and warpage of the substrate can be reduced even if the substrate is thin. In addition, it can be expected that a decrease in substrate quality can be suppressed even for a crystalline silicon substrate that is easily deteriorated by heat. The electrode in the solar cell of this system is formed at 200 ° C. or lower using a low-temperature sintered Ag electrode in order to prevent deterioration of the characteristics of the heterojunction portion.

  As described above, the collector electrode composed of the grid electrode and bus electrode of these solar cells mainly uses silver or aluminum by the screen printing method, but the line width of the electrode by this screen printing method is about 80 μm or more, The light loss at the electrode on the light receiving surface is large. In addition, the wiring formed by firing the printing paste is an aggregate of small particles and includes a glass component and a resin component, and therefore has a specific resistance several times that of pure metal silver. For this reason, when the wiring formed by baking such a printing paste is thinned, the wiring resistance and the contact resistance are increased.

Many electrode forming methods by plating have been studied as electrodes other than screen printing. In a conventional solar cell in which an antireflection film such as a silicon nitride (SiN) film is formed on a diffusion junction, an electrode forming portion is opened using a method such as irradiating a laser to the SiN film, and an exposed diffusion layer is formed. A plating electrode is formed by performing electroless plating, electrolytic plating, or the like. In addition, in a heterojunction solar cell, an insulating film such as SiN or SiO ₂ is formed on a translucent conductive film, a patterning opening is formed in the insulating film, and a plating electrode is formed on the exposed translucent conductive film. (Patent Documents 4 and 5). When these solar cells are plated through an insulating film, the plating grows isotropically, so that the electrodes spread in the lateral direction and become thicker than the openings.

  Patent Document 6 discloses a technique for making a thin line without a lateral spread by digging into a contact portion formed by a MOCVD (Metal Organic Chemical Deposition) method and growing a plating electrode therein. Has been. In electroplating, an electrode terminal is directly connected to a conductive layer formed on a substrate, and a current is applied to give a negative charge to metal ions to deposit as a metal. Therefore, normally, a power feeding terminal is brought into contact with a portion for forming a thick electrode such as a collecting electrode, particularly a bus electrode, formed on a surface on which a plating electrode is formed. In configuring the apparatus, it is possible to reduce the length of the terminal when the power feeding terminal is brought into contact with the peripheral portion of the wafer rather than being brought into contact with the center of the wafer.

  Patent Document 7 describes the contents of supplying power to the bus electrode by arranging the bus electrode at the peripheral part so that power is easily supplied at the peripheral part. Further, in Patent Document 8, when power is supplied directly to a current collecting electrode such as a bus electrode, the contacted terminal portion is not plated, resulting in a non-uniform portion of the plating thickness and the non-uniform portion at the time of tab electrode formation. Since the wafer is cracked, the content of forming the power feeding portion for plating is described separately from the collecting electrode.

JP-A-4-130671 Japanese Patent No. 2614561 Japanese Patent No. 3469729 JP 2000-058885 A JP 2011-199045 A JP 2012-023232 A JP 2000-294819 A International Publication No. 2013/046351

  According to the above conventional technique, as described above, a power feeding unit is required to form a collecting electrode by electrolytic plating. However, as described in Patent Document 8, when the power feeding portion is formed in the collecting electrode forming portion, a portion where the thickness of the collecting electrode is not uniform is generated. Moreover, even if a power feeding part is provided separately from the current collecting electrode as in Patent Document 8, plating is deposited on the power feeding terminal, and the metal deposited on the plated film and the connecting terminal is deposited in some cases due to the thickening of the power feeding terminal. In some cases, they may be coupled via. In that case, the metal of the deposited power supply terminal needs to be frequently removed because it causes cracking of the wafer when the power supply terminals bonded after plating are separated. In addition, if the power feeding portion is far away from a thick power feeding electrode such as a bus electrode, a resistance loss occurs when a current flows, and the plating film thickness becomes non-uniform. In addition, since this power supply unit does not contribute to current collection, it is necessary to give a certain degree of margin to the positional accuracy when connecting the power supply terminal, so it needs to have a large area, for example, about 1 mmΦ or more, The area of the electrode part that does not contribute to power generation is increased more than necessary, leading to a decrease in characteristics (short-circuit current).

  This invention is made | formed in view of the above, Comprising: It aims at obtaining the photovoltaic element with a high fill factor, its manufacturing method, and its manufacturing apparatus.

  In order to solve the above-described problems and achieve the object, the present invention has a first conductive type crystalline semiconductor substrate having a first main surface and a second main surface, and light is incident from the first main surface. And a semiconductor layer of a second conductivity type different from that of the crystalline semiconductor substrate so as to form a pn junction on the first or second principal surface of the crystalline semiconductor substrate, and the first and second principal surfaces are respectively provided with the first and second principal surfaces. 1 is a photovoltaic device having first and second electrodes. Here, the first electrode includes a base conductor layer formed so as to go from the first main surface to the second main surface, and a plating layer formed on the base conductor layer.

  According to the present invention, at least the entire first main surface can be used as a light receiving region, and the fill factor can be improved. In addition, a power feeding portion can be provided on the second main surface, which is the back surface, so that a non-uniform portion of the plating thickness due to contact with the power feeding terminal can be eliminated, and deterioration in characteristics due to formation of the power feeding portion on the light receiving surface can also be prevented. . Further, the collecting electrode can be formed on the side wall portion of the wafer that does not contribute to normal power generation. As a result, the density of forming the collecting electrode (bus electrode) on the light receiving surface can be reduced. As a result, the light receiving area can be increased, and the fill factor can be further improved.

FIGS. 1A and 1B are diagrams showing a cell surface structure and a back surface structure in the first embodiment. FIG. 2 is a diagram showing an end face structure of a cell in the first embodiment. FIG. 3 is a flowchart showing a cell formation process in the first embodiment. 4A to 4D are process cross-sectional views illustrating the cell formation process in the first embodiment. 5A to 5C are process cross-sectional views illustrating the cell formation process in the first embodiment. FIG. 6 is a diagram showing an exposure mask pattern in the first embodiment. FIG. 7 is a bus pattern comparison diagram between the first embodiment and the conventional solar cell. FIG. 8 is an enlarged view of a main part of the plating apparatus according to the first embodiment, and is a diagram showing a wafer end face portion arrangement diagram at the time of plating. FIG. 9 is a diagram showing a layout of a plating apparatus in the first embodiment. FIGS. 10A and 10B are diagrams showing the cell surface structure and the back surface structure in the second embodiment. FIG. 11 is a diagram showing a cell structure in the second embodiment. FIG. 12 is a flowchart showing a cell formation process in the second embodiment. 13A to 13C are process cross-sectional views illustrating the cell formation process in the second embodiment. 14A to 14C are process cross-sectional views illustrating the cell formation process in the second embodiment. FIG. 15 is an enlarged view of a main part of the plating apparatus according to the second embodiment, and is a diagram showing a wafer end face portion arrangement diagram during plating.

  DESCRIPTION OF EMBODIMENTS Embodiments of a photovoltaic element, a manufacturing method thereof, and a manufacturing apparatus according to the present invention will be described below in detail with reference to the drawings. In addition, this invention is not limited by this embodiment, In the range which does not deviate from the summary, it can change suitably. In the drawings shown below, the scale of each layer or each member may be different from the actual for easy understanding, and the same applies to the drawings. Further, even a plan view may be hatched to make the drawing easy to see.

Embodiment 1 FIG.
FIGS. 1A and 1B are diagrams showing a cell surface structure and a back surface structure of a first embodiment of a solar battery cell constituting a photovoltaic element according to the present invention. 2 is a cross-sectional structure of the cell end surface, FIG. 3 is a flowchart showing the formation process, and FIGS. 4A to 4D and 5A to 5C are process cross-sectional views. In the process of forming a photovoltaic cell as a photovoltaic element in the present embodiment, the conductive layer that is the base of the plating is made to wrap around to the back surface (the surface opposite to the surface on which the plating electrode is formed). The power supply is performed from the back side by pressing the power supply terminal. Here, as shown in FIG. 1, the solar cell has a heterostructure film composed of an i-type amorphous silicon layer 10 and a p-type amorphous silicon layer 11 as a light-receiving surface side structure on the front side of the n-type single crystal silicon substrate 1. And p-type region portion 2 having a laminated structure of translucent conductive film 12 made of ITO, and this p-type region portion 2 wraps around to a region having a distance a of about 2 mm at the peripheral edge of the back surface. Further, the peripheral electrode portion 5 formed on the end portion of the n-type single crystal silicon substrate 1 (wafer) and the light receiving surface electrode (bus electrode 3, grid electrode 4) are formed on the p-type region portion 2, and are electroless Ni plated. The bus electrode 3, the grid electrode 4, and the peripheral electrode 5, which have a laminated structure of the layer 18 and the electrolytic Cu (copper) plating layer 19, have a continuous structure. Further, as a back surface structure, a hetero film made of an i-type amorphous silicon layer 15 and an n-type amorphous silicon layer 16 and a transparent film made of ITO are sandwiched between the wrapping p-type region portion 2 and a pn isolation portion 14. An n-type region portion 6 having a laminated structure of a photoconductive film 17, an electroless Ni plating layer 18, and a displacement plating layer 19e thereon is formed.

  The cell cross-sectional structure of FIG. 2 is a structural diagram of the wafer edge when viewed from the longitudinal direction of the grid electrode 4 in FIGS. 1A and 1B, and corresponds to the cross section AA in FIG. FIG. In FIG. 2, the region composed of the i-type amorphous silicon layer 10, the p-type amorphous silicon layer 11, and the translucent conductive film 12 includes the electroless Ni plating layer 18 and the electrolytic Cu plating layer 19. 1 corresponds to the p-type region portion 2 in FIG. Further, a region composed of the i-type amorphous silicon layer 15, the n-type amorphous silicon layer 16, the translucent conductive film 17, and the electroless Ni plating layer 18 corresponds to the n-type region portion 6 in FIG. To do. Further, the electroless Ni plating layer 18, the electrolytic Cu plating layer 19, and the displacement plating 19e thereon correspond to the bus electrode 3 and the grid electrode 4 in the surface structure of FIG. However, the bus electrode 3 has the same film configuration as the grid electrode 4, but is not shown in FIG. 2 because it is orthogonal to the grid electrode 4.

  Next, the manufacturing method of the photovoltaic cell of this Embodiment is demonstrated. FIG. 3 is a flowchart showing the manufacturing method, and FIGS. 4A to 4D and FIGS. 5A to 5C are process sectional views showing the manufacturing process.

  First, wire saw damage at the time of slicing in an alkaline solution was removed from a (100) n-type single crystal silicon substrate 1 having a specific resistance of 1 Ωcm at 156 mm □ (slice damage removal step S101). Thereafter, the substrate was immersed in an alkaline solution to which isopropyl alcohol was added to form a texture in which pyramidal protrusions were randomly arranged on both sides of the substrate (step S102).

  Thereafter, the n-type single crystal silicon substrate 1 was cleaned by RCA cleaning, and the surface oxide film was removed with dilute hydrofluoric acid. In order not to form a film up to a distance a of about 2 mm from the end surface of the n-type single crystal silicon substrate 1, a range of about 2 mm from the end surface opposite to the film forming surface is not in close contact with the substrate, and the inner side is on the substrate. The substrate was placed on a stage that was in close contact, and a laminated film of the i-type amorphous silicon layer 10 and the p-type amorphous silicon layer 11 was formed in the plasma CVD chamber as follows (FIG. 4A). : Step S103). Here, since the CVD film has good coverage, the film is formed in the same manner as the electrode side if it is not in close contact with the stage even on the side opposite to the film forming surface where plasma is formed.

As the i-type amorphous silicon layer 10, an oxygen-doped i-type amorphous silicon layer 10 of about 2 to 3 nm was formed in an RF plasma CVD chamber of 13.56 to 60 MHz. At this time, the film formation conditions are as follows: RF output 20 to 100 mW / cm ² , substrate temperature 100 to 200 ° C., gas pressure 400 to 600 Pa, reaction gas flow rate of silane 10 to 100 sccm, hydrogen 500 to 1000 sccm, carbon dioxide gas 5 -20 sccm.

Subsequently, a p-type amorphous silicon layer 11 having a thickness of about 20 nm was formed on the i-type amorphous silicon layer 10 in a 13.56-60 MHz RF plasma CVD chamber. At that time, the film formation conditions were as follows: RF output 20 to 100 mW / cm ² , substrate temperature 100 to 200 ° C., gas pressure 400 to 600 Pa, and reactive gas flow rate to silane 5 to 50 sccm, hydrogen 500 to 2000 sccm, 1%. Diborane diluted with hydrogen was adjusted to 10 to 50 sccm.

Next, a laminated film of an i-type amorphous silicon layer 15 and an n-type amorphous silicon layer 16 was formed on the back surface opposite to the light-receiving surface on which the p-type amorphous silicon layer 11 was formed (see FIG. 4 (b): Step S104). At that time, a range of 2 mm from the end face of the film forming surface is not formed so that the laminated film of the i-type amorphous silicon layer 15 and the n-type amorphous silicon layer 16 is not formed in a region 2 mm from the end face of the substrate. The film was formed using a mask that adhered to the wafer. The i-type amorphous silicon layer 15 is an RF plasma CVD chamber of 13.56 to 60 MHz, and the i-type amorphous silicon layer 15 on the back surface side having a film thickness of about 2 nm to 3 nm is formed on the back surface of the n-type single crystal silicon substrate 1. Formed. Under the atmosphere of RF output 20-100 mW / cm ² , substrate temperature 100-200 ° C., gas pressure 400-600 Pa, the flow rate of the reaction gas was silane 10-100 sccm and hydrogen 500-1000 sccm.

Further, in the RF plasma CVD chamber of 13.56 to 60 MHz, the n-type amorphous silicon layer 16 which is a high-concentration impurity-doped silicon layer on the back surface side having a film thickness of about 20 nm is formed on the back-side i-type amorphous silicon layer 15. A BSF structure was formed on the back side of the n-type single crystal silicon substrate 1. Film formation conditions are as follows: RF output 20 to 100 mW / cm ² , substrate temperature 100 to 200 ° C., gas pressure 400 to 600 Pa, reaction gas flow rate of silane 5 to 50 sccm, hydrogen 50 to 200 sccm, hydrogen diluted to 1% The phosphine was 10-50 sccm.

  Thereafter, heat treatment was performed at 200 ° C. for 10 minutes in a forming gas (inert gas atmosphere containing 5% hydrogen).

  Next, ITO (indium tin oxide) having a thickness of about 70 to 90 nm was formed on the p-type amorphous silicon layer 11 as the light-transmitting conductive film 12 on the light-receiving surface side by a sputtering method (step S105). In addition, ITO (indium tin oxide) having a thickness of about 70 to 90 nm was also formed on the n-type amorphous silicon film 16 as the light-transmitting conductive film 17 on the back side by sputtering (FIG. 4C: Step S106). Then, the pn region was separated between the p-type region portion 2 and the n-type region portion 6 wrapping around the back surface by a short wavelength laser that absorbs ITO (FIG. 4 (d): pn separation). Step S107). In this embodiment, pn separation is performed by laser. However, the ITO film may be removed by etching by applying an etching paste to the pn separation portion by screen printing or the like, drying at 200 ° C. or less, and washing with water. In this embodiment, ITO is formed by sputtering, but a CVD method may be used in order to make the ITO film wrap around the side surface more reliably.

Thereafter, a photosensitive film having a thickness of 20 μm was attached to the light-receiving surface side surface as a translucent insulator film 9 by a film laminator (FIG. 5A: step S108). A photosensitive film is a film that can be patterned by photolithography as in the case of a photoresist, and is used in a process of a liquid crystal device. As such a translucent insulator film 9, for example, MB series manufactured by Hitachi Chemical Co., Ltd. can be used. An exposure mask having a grid electrode 4 with a width of 30 μm and a bus electrode 3 with a width of 1 mm as shown in FIG. 6 is transferred to the translucent insulator film 9 having photosensitivity, and developed with a developing solution. An electrode pattern was formed on the translucent insulator film 9 (FIG. 5B: step S109). At this time, the translucent insulator film 9 is formed so as not to cover the end face of the substrate, and the electrode pattern of the grid electrode with respect to the wafer installation position (dotted line portion in FIG. 6) as shown in FIG. If the photosensitive film is a negative type so as to expose the pattern P ₄ and the pattern other than the patterning opening of the bus electrode pattern P ₃ , a mask pattern is formed so as to shield the electrode forming portion. The lengths of the grid electrode pattern P ₄ and the bus electrode pattern P _{3 in} the longitudinal direction are longer than one side of the wafer and continue to the end of the wafer without interruption. Thereby, when the plating layer is formed in the opening h of the translucent insulator film 9, the grid electrode 4 and the bus electrode 3 are connected to the plating layer formed on the wafer end portion respectively, and the peripheral plating layer Has an effect as the bus electrode 3 for collecting current from the grid electrode 4.

By the way, in a typical crystalline solar cell, as shown in FIG. 7B, an example of bus electrode patterns is used so that the areas where current is collected by several bus electrodes 3 on the wafer are the same. If there are two, the bus electrodes 3 are formed at two locations outside the region obtained by dividing the wafer light receiving surface into four. However, as shown in FIG. 7A, the cell according to the present embodiment also has a collecting electrode arranged at the peripheral portion. Therefore, if the number of buses is two, the light receiving surface of the wafer is divided into three equal parts. The bus electrode 3 may be arranged as described above. At this time, the current collecting areas R _A and R _B of the bus electrodes A and B may be reduced by the current collecting area R _R by the current collecting electrodes in the peripheral portion. That is, with this structure, the area where the buses per current are collected is smaller than that of the conventional cell, so that each grid electrode 4 and each bus electrode 3 can be connected without increasing the number of bus electrodes that shield the light receiving surface. The total amount of flowing current is reduced, and the fill factor can be improved.

  Thereafter, an electroless Ni plating layer 18 is formed on the peripheral edge portion of the wafer including the area corresponding to the bus electrode 3 and the grid electrode 4 serving as a current collecting electrode of the wafer and the grid electrode 4 opened in the translucent insulator film 9, and the back surface portion. (FIG. 5C: Step S110). The electroless plating uses Ni electroless plating. Since electroless Ni plating grows using palladium as a catalyst, the entire front and back surfaces of the wafer with the film opened are immersed in a palladium catalyst solution as plating pretreatment. Since the palladium catalyst is dispersed in the catalyst solution as positive ions, it is selectively adsorbed on the light-transmitting conductive film that is an oxide. When the entire front and back surfaces were immersed in an electroless Ni plating solution, electroless Ni plating was selectively grown on a portion not covered with the translucent insulator film 9 (lower electrode formation step S111 by electroless plating). The electroless Ni plating was performed at a temperature of 70 ° C., and the immersion time was adjusted so that the thickness was about 1 μm. At this time, the back surface was used as a back reflection film by electroless Ni plating on the entire surface. About the pn separation part 14 which formed the pn separation groove with the laser in the position about 2 mm from the end surface of the back surface, it was made to prevent Ni plating of a back surface and an end surface from contacting by apply | coating insulating resin beforehand. Further, although electroless Ni plating is used in the present embodiment, electrolytic Ni plating may be used.

  Thereafter, the wafer is placed on a plate-like support portion 20 having an adsorption portion as shown in FIG. 8, and immersed in a plating apparatus for performing copper sulfate-based electrolytic Cu plating shown in FIG. The plating layer 19 was formed (upper layer electrode formation step S112 by electrolytic plating). By this step, the peripheral electrode portion 5, the grid electrode 4, and the bus electrode 3 are formed.

  FIG. 8 is an enlarged view of a main part of the plating apparatus used here, and FIG. 9 is a schematic diagram. The plating apparatus used here includes a plating tank 23S filled with an electrolytic solution 23, a copper anode electrode 25 serving as a first power supply terminal immersed in the plating tank 23S, and a wafer 1W in the plating tank 23S. And a support portion 20 provided with a probe 21 as a second power supply terminal for supporting the wafer 1W and supplying power to the wafer 1W. The support unit 20 includes a suction unit 22 that contacts the wafer 1W and sucks the wafer 1W. The probe 21 is embedded in the suction part 22 and comes into contact with the power feeding part of the wafer 1W. Reference numeral 24 denotes a power source for plating.

As shown in FIG. 8, in the plating step, the wafer 1W is adsorbed and installed on the support portion 20 while pressing the probe 21 against the end portion on the back surface side of the wafer 1W, and the anode electrode 25 is immersed as shown in FIG. The support portion 20 constituting the adsorption plate is immersed in the plating tank 23S, and a negative voltage is applied to the probe 21 which is the power feeding portion on the back surface, and a positive voltage is applied to the anode electrode 25 to perform electrolytic Cu (copper) plating. Layer 19 was formed. Electrolytic Cu plating was performed under a current of 1 A / cm ² , and the Cu plating thickness was slightly thinner than the surface of the film, and was adjusted to a thickness such that no electrode protruded from the film. Here, since the support portion 20 constituting the suction plate is in close contact with the entire back surface of the wafer 1W, the Cu plating is formed only on the exposed light receiving surface and the side surface of the wafer peripheral portion. Therefore, there is no shadow loss on the light receiving surface side other than the bus electrode 3 and the grid electrode 4. Further, in order to prevent oxidation of the surface of the Cu plating electrode, the wafer 1W was dipped in the Sn plating tank in the same manner to form the Sn substitution plating layer 19e shown in FIG.

  By using such a plating apparatus, a plating layer can be formed only on the light receiving surface and the collector electrode on the side wall by covering the entire back surface of the wafer support portion 20, so that no extra stress is generated in the peripheral portion of the wafer. In addition, since the back surface of the wafer 1W is protected by the support part 20 constituting the suction plate, the plating layer is not excessively circulated and a plating layer is not formed on conductive layers of different conductivity types.

  As Comparative Example 1, it is produced by the same process as described above until after the formation of the light-transmitting conductive film, and instead of the plating electrode, the arrangement shown in a typical solar battery cell as shown in FIG. No electrode is formed on the periphery of the wafer, the light receiving surface has two buses made of Ag printing paste, and the grid electrodes 4 made of the same number of Ag printing paste as in the first embodiment, and the back surface is made of Ni plating. Instead, a sample in which a Ni film was formed by sputtering was formed. The printing paste of Ag was a low-temperature sintered type, the grid electrode 4 had a printing width of 80 μm, and was sintered at 200 ° C. after printing.

When the current-voltage characteristic of each solar battery cell was evaluated, the cell of Cu / Ni plating in this embodiment as shown in FIG. 7A and the comparative example 1 using printed Ag as an electrode were shown. Although the open-circuit voltage of the cell was the same value, the short-circuit current of the cell in this embodiment was about 0.6 mA / cm ² higher than that of the cell of Comparative Example 1, and the fill factor of Comparative Example 1 Is 0.78, whereas the fill factor of the example is 0.79, which is 1/100 higher. The increase in the short-circuit current is due to the fact that the grid electrode width is narrowed to 30 μm compared to 80 μm in the comparative example. In addition, the increase in the fill factor is due to the fact that the current collecting electrode by plating is formed in the peripheral part, so that the area where the grid electrode and the current collecting electrode collect current is narrowed, and the resistance caused by the current collection is reduced. It is thought that it contributed to this.

Embodiment 2. FIG.
10A and 10B show the cell surface structure and the back surface structure formed in this embodiment. FIG. 11 is a diagram showing a cross-sectional structure of the cell end surface, FIG. 12 is a flowchart showing the formation process, and FIGS. 13A to 13C and FIGS. 14A to 14C are process cross-sectional views. FIG. 11 is a cross-sectional view taken along the line SA-SA in FIG. In the first embodiment, the heterojunction solar cell has been described. In the present embodiment, a diffusion solar cell will be described. As shown in FIGS. 10A and 10B, the solar battery cell in the present embodiment is a stacked layer of an n-type diffusion layer 31 and a silicon nitride film 33 as a light-receiving surface side structure on the front side of a p-type single crystal silicon substrate 1p. The structure including the electroless Ni plating layer 18 and the electrolytic Cu plating layer 19 corresponds to the n-type region 2n in FIGS. 10A and 10B. The n-type region 2n wraps around a region having a distance a = 2 mm at the peripheral edge of the back surface. The peripheral electrode portion 5n and the light-receiving surface electrode (bus electrode 3n, grid electrode 4n) formed on the edge of the wafer are formed on the n-type region portion 2n, and the electroless Ni plating layer 18 and the electrolytic Cu plating layer 19 are formed. The bus electrode 3n, the grid electrode 4n, and the peripheral electrode portion 5n having a stacked structure have a continuous structure. Further, as the back surface structure, the p-type region portion 6p formed by the Al printed electrode 34 and the back surface electric field layer 35 formed by the Al printed electrode 34 with the pn separating portion 14 sandwiched inside the wraparound n-type region portion 2n. Is formed.

  The cell cross-sectional structure shown in FIG. 11 is a structural diagram of the wafer edge when viewed from the longitudinal direction of the grid electrode 3n in FIGS. 10 (a) and 10 (b), but from the phosphorus diffusion layer (n-type diffusion layer) 31. This region corresponds to the n-type region 2n in FIGS. 10 (a) and 10 (b). Further, the region composed of the Al printed electrode 34 and the back surface electric field layer 35 corresponds to the p-type region portion 6p in FIGS. 10 (a) and 10 (b). Further, the electroless Ni plating layer 18, the electrolytic Cu plating layer 19, and the displacement plating 19e thereon correspond to the bus electrode 3n and the grid electrode 4n in FIGS. 10 (a) and 10 (b). However, the bus electrode 3n has the same film configuration as the grid electrode 4n, but is not shown in FIG. 11 because it is orthogonal to the grid electrode 4n.

  Next, the manufacturing method of the photovoltaic cell of this Embodiment is demonstrated. FIG. 12 is a flowchart showing the manufacturing method, and FIGS. 13A to 13C and FIGS. 14A to 14C are process sectional views showing the manufacturing process.

  First, wire saw damage at the time of slicing in an alkaline solution was removed from a (100) p-type single crystal silicon substrate 1p having a specific resistance of 1 Ωcm and 156 mm □ (slice damage removal step S201). Thereafter, it was immersed in an alkaline solution to which isopropyl alcohol was added to form pyramidal textures on both sides of the wafer (step S202).

Thereafter, heat treatment was performed at 800 ° C. in a POCl ₃ gas atmosphere to form the n-type diffusion layer 31 as a bonding layer having a conductivity type opposite to that of the substrate, and the phosphorus glass formed on the surface was removed (step S203). At this time, the substrate is placed on the susceptor S and phosphorous diffusion is performed so that the n-type diffusion layer 31 is not formed in the region in contact with the susceptor S. Thereafter, a silicon nitride film 33 was formed on the light-receiving surface side by plasma CVD using silane and ammonia as raw materials as an antireflection film and a passivation film (FIG. 13A: step S204). The silicon nitride film 33 was formed to a thickness of 80 nm.

  Furthermore, an Al printing electrode 34 on the back surface was formed by applying and baking an Al printing paste so as to leave an area of about 2 mm from the end of the back surface (FIG. 13B). At that time, the phosphorus diffusion layer that became n-type by diffusing Al into silicon by firing was inverted to p-type, and the back surface electric field layer 35 was formed (FIG. 13C: step S205). Further, a pn isolation portion 14 was formed by providing a groove by laser irradiation between the region where Al was formed and the region where the end portion was not formed (FIG. 14A: step S206).

After that, as in Embodiment 1, a photosensitive film having a thickness of 20 μm was attached to the light-receiving surface side surface as a translucent insulator film 9 by a film laminator (FIG. 14B: step S207). In the same manner as shown in FIG. 6, an exposure mask having a grid electrode having a width of 30 μm and a bus electrode having a width of 1 mm is transferred to the light-transmitting insulator film 9 made of this photosensitive film, and developed with a developing solution. An opening h was formed on the photo-insulator film 9 to form an electrode pattern (collecting electrode opening step S208). Thereafter, the silicon nitride film 33 exposed from the opening h by hydrofluoric acid is removed (step S209). At this time, the translucent insulator film 9 is formed so as not to cover the end face, and the electrode pattern is a grid electrode with respect to the wafer installation position (dotted line portion in FIG. 6) as shown in FIG. If the photosensitive film is a negative type, the mask pattern is formed so as to shield the electrode forming portion so that the pattern P ₄ and the pattern opening of the bus electrode pattern P ₃ are exposed. In addition, the grid electrode pattern and the bus electrode pattern have a length in the longitudinal direction that is longer than one side of the wafer and continues without interruption to the edge of the wafer. As a result, when the plating electrode is formed in the opening of the translucent insulator film 9, the grid electrode and the bus electrode are connected to the plating electrode formed on the edge of the wafer, and the peripheral plating electrode is connected to the grid electrode. It will have the effect as a bus electrode that collects electricity from. Accordingly, in the crystalline solar cell of the present embodiment, as in the case of the heterojunction solar cell of the first embodiment, as shown in FIG. In order to make the current collecting areas of several bus electrodes the same, if the number of buses is two, the bus electrodes are formed at two locations outside the wafer light receiving surface divided into four. However, in the cell according to the present embodiment, current collecting electrodes are also arranged in the peripheral portion. Therefore, as shown in FIG. 7A, if the number of buses is two, the light receiving surface of the wafer is divided into three equal parts. The bus electrodes may be arranged as described above. With this structure, the area where each bus collects current is smaller than that of the conventional cell, so the total amount of current flowing through each grid electrode and each bus electrode is reduced, and the fill factor can be improved. .

  Thereafter, the wafer opened in the translucent insulator film 9 is immersed in the electroless plating catalyst solution (step S210). Then, an electroless Ni plating layer 18 was formed on the peripheral edge of the wafer including the region corresponding to the bus electrode 3n and the grid electrode 4n serving as current collecting electrodes, the side wall portion, and the back surface portion (FIG. 14 (c): lower layer by electroless plating). Electrode formation step S211). The electroless plating was Ni (nickel) electroless plating, but the electroless Ni plating layer 18 was grown using palladium as a catalyst. Therefore, the entire front and back surfaces of the wafer with the film opened were immersed in a palladium catalyst solution as plating pretreatment. . Since the palladium catalyst is dispersed as positive ions in the catalyst solution, it is selectively adsorbed on the n-type phosphorus diffusion layer. When the entire front and back surfaces were immersed in an electroless Ni plating solution, the electroless Ni plating layer 18 was selectively grown only on the opening h and the wafer end surface. Ni plating was performed at a temperature of 70 ° C., and the immersion time was adjusted so that the thickness was about 1 μm. At this time, a Ni electroplating layer was formed on the Al electrode on the back surface. For the groove that was pn-separated by laser at a position of about 2 mm from the end surface on the back surface, an insulating resin was applied in advance to the pn separation groove 14 so that the back surface and the electroless Ni plating layer 18 on the end surface did not contact each other. . Further, although electroless Ni plating is used in the present embodiment, electrolytic Ni plating may be used.

Thereafter, the wafer was dipped in the copper sulfate-based electrolytic Cu plating apparatus shown in FIG. 9 in the same manner as in Embodiment 1 to form an electrolytic Cu plating layer 19. As shown in FIG. 15, an enlarged view of the main part of the electroplating apparatus is provided with a wafer 1W. Similar to the first embodiment, as shown in FIG. Electrolytic Cu plating was performed by applying a positive voltage (upper layer electrode forming step S212 by electrolytic plating). Cu plating was performed under a current of 1 A / cm ² , and the Cu plating thickness was slightly thinner than the surface of the film, and the thickness was adjusted such that no electrode protruded from the film. Further, in order to prevent oxidation of the surface of the electrolytic Cu plating layer, it was immersed in a Sn substitution plating solution to form a substitution plating layer 19e. Since the support portion 20 composed of the suction plate is in close contact with the entire back surface of the wafer 1W, the Cu plating is formed only on the exposed light receiving surface and the side surface of the wafer peripheral portion. Therefore, there is no shadow loss on the light receiving surface side other than the bus electrode 4 and the grid electrode 3.

  As Comparative Example 2, after a silicon nitride film is formed on the light receiving surface of the wafer 1W, a high-temperature sintered Ag paste having a width of 80 μm is applied to the light receiving surface of the wafer 1W, and an aluminum paste is applied to the back surface. A sample fired at 800 ° C. was formed.

When the current-voltage characteristics of each solar cell were evaluated, the open-circuit voltage of the cell using Cu / Ni plating as an electrode and the cell of Comparative Example 1 using printed Ag as an electrode in this embodiment were the same value. However, the short-circuit current of the cell in this embodiment is about 0.6 mA / cm ² higher than that of the cell of Comparative Example 1, and the fill factor of Comparative Example 1 is 0.79, whereas The factor was 0.80, 1/100 higher. The increase in the short-circuit current is due to the fact that the grid electrode width is narrowed to 30 μm compared to 80 μm in the comparative example. In addition, the increase in the fill factor is due to the fact that the current collecting electrode by plating is formed in the peripheral part, so that the area where the grid electrode and the current collecting electrode collect current is narrowed, and the resistance caused by the current collection is reduced. It contributed to that.

  In addition, according to the present embodiment, the second conductivity type semiconductor layer is formed by vapor phase diffusion, so that a sufficient film thickness can be ensured around the side surface and the back surface.

  In the first and second embodiments, the electroless plating layer is formed as the base conductor layer for forming the plating layer. However, the electroless plating layer is not necessarily used, and a metal film formed by a sputtering method is used. Any process may be used as long as it is a process for making the surface conductive.

  Furthermore, in the first and second embodiments, the conductive semiconductor layer that forms the pn junction is passed around to the second main surface, and the underlying conductor layer is formed thereon. However, the conductive semiconductor layer is not necessarily formed. The base conductor layer only needs to be electrically connected on the first and second main surface sides without going around to the second main surface. That is, it is only necessary that either the base conductor layer or the conductive semiconductor layer is continuously formed so as to wrap around from the first main surface to the second main surface through at least one side surface. In this manner, in the plating step, the first main surface side plating layer can be formed by supplying power from the second main surface, that is, the back conductor layer on the back surface side. Then, the underlying conductor layer or the conductive semiconductor layer on the side surface portion may be removed by dicing or the like when completed as a solar battery cell. In the case of a solar battery cell obtained by dicing as described above, the end surface of the base conductor layer or the conductive semiconductor layer coincides with the end surface of the substrate.

  In the first and second embodiments, the case where the substrate and the wafer are used equally and the photovoltaic element composed of one solar cell is formed by one wafer has been described. That is, in the first embodiment, the n-type single crystal silicon substrate 1 is a wafer, and in the second embodiment, the p-type single crystal silicon substrate 1p is a wafer, and these are used as solar cells as they are. On the other hand, it is also effective when a plurality of cells are formed on a wafer and one or more solar cells are formed by dicing, and the plating layer on the side wall is removed on at least one side surface. Needless to say. Alternatively, when performing electroplating, by using a suction plate (support) that covers at least one side wall of the wafer, it is possible to prevent an electroplating layer from being formed on the side wall of the wafer. . By forming the plating layer on the side wall only on the connection side with the adjacent cells in this way and using it for the connection between the solar cells, the light receiving surface side can be interconnected without providing an interconnector. It is also possible to realize a module design with a small shadow loss.

  In any of the first and second embodiments, the semiconductor substrate is a crystal including a silicon compound substrate such as a silicon carbide substrate in addition to a crystalline silicon substrate such as a single crystal silicon substrate or a polycrystalline silicon substrate. It is applicable to a system semiconductor substrate. As for the intrinsic or conductive amorphous silicon thin film, a crystalline thin film such as a microcrystalline silicon thin film or a polycrystalline silicon thin film, or a doping layer formed by thermal diffusion may be used.

  Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

1 n type single crystal silicon substrate, 1pp type single crystal silicon substrate, 2,6pp type region portion, 3,3n bus electrode, 4,4n grid electrode, 5,5n peripheral electrode portion, 2n, 6 n type region portion , 9 Translucent insulator film, 10 i-type amorphous silicon layer, 11 p-type amorphous silicon layer, 12 translucent conductive film, 14 pn separator, 15 i-type amorphous silicon layer, 16 n Type amorphous silicon layer, 17 translucent conductive film, 18 electroless Ni plating layer (back electrode), 19 electrolytic Cu plating layer, 19e displacement plating layer, 20 support part, 21 probe, 22 suction part, 23 electrolyte , 23S plating tank, 24 power source for plating, 25 anode electrode, 31 n-type diffusion layer, 33 silicon nitride film, 34 Al printed electrode, 35 back surface electric field layer, h opening.

Claims (16)

A first conductive type crystalline semiconductor substrate having a first main surface and a second main surface, wherein the first main surface is a light incident surface;
A semiconductor layer of a second conductivity type different from that of the crystalline semiconductor substrate so as to form a pn junction on the first or second main surface of the crystalline semiconductor substrate;
A photovoltaic device having first and second electrodes on the first and second main surfaces, respectively,
The first electrode includes a base conductor layer formed so as to go from the first main surface to the second main surface;
A photovoltaic device comprising: a plating layer formed on the base conductor layer.   2. The photovoltaic element according to claim 1, wherein the underlying conductor layer is continuously formed so as to wrap around from the first main surface to the second main surface through a side surface. The semiconductor layer of the second conductivity type is continuously formed so as to go around from the first main surface to the second main surface,
The photovoltaic element according to claim 2, wherein the base conductor layer is formed on the semiconductor layer of the second conductivity type. The second-conductivity-type semiconductor layer is a second-conductivity-type non-stacked layer formed via an intrinsic amorphous semiconductor layer continuously formed so as to extend from the first main surface to the second main surface. A crystalline semiconductor layer,
The first electrode includes a translucent conductive film formed on the second conductive type amorphous semiconductor layer and an electroless layer as the base conductor layer formed on the translucent conductive film. A plating layer;
The photovoltaic device according to claim 3, comprising an electroplating layer formed on the electroless plating layer.   The photovoltaic device according to claim 4, wherein the second electrode includes an electroless plating layer formed in the same process as the first electrode, and an electrolytic plating layer. The second conductivity type semiconductor layer is a second conductivity type impurity diffusion layer continuously formed so as to extend from the first main surface to the second main surface,
The first electrode includes an electroless plating layer as the base conductor layer formed on the impurity diffusion layer of the second conductivity type,
The photovoltaic device according to claim 3, comprising an electroplating layer formed on the electroless plating layer. A pn junction is formed on the first or second main surface of the first conductive type crystalline semiconductor substrate having a first main surface and a second main surface, the first main surface being a light incident surface. Forming a second conductivity type semiconductor layer different from the crystalline semiconductor substrate;
Forming a first electrode on the first main surface;
Forming a second electrode on the second main surface,
The step of forming the first electrode includes:
Forming a base conductor layer so as to go from the first main surface to the second main surface;
A method of manufacturing a photovoltaic device including a step of forming an electroplating layer using, as a feeding region, a region of the base conductor layer that extends to the second main surface. Prior to the step of forming the base conductor layer,
Including a step of forming a protective film in a region excluding the collecting electrode forming region of the first main surface,
The step of forming the base conductor layer includes:
The photovoltaic element according to claim 7, further comprising a step of forming the current collector electrode formation region on the first main surface so as to reach a peripheral portion of the second main surface via a side surface of the semiconductor substrate. Manufacturing method. The step of forming the base conductor layer includes:
The manufacturing of the photovoltaic device according to claim 7, further comprising a step of forming the current collecting electrode formation region on the first main surface so as to cover the entire second main surface through the side surface of the semiconductor substrate. Method.   The method for manufacturing a photovoltaic element according to claim 8 or 9, wherein the step of forming the base conductor layer is an electroless plating step. The step of forming the electrolytic plating layer includes:
Forming an electroplating layer on the underlying conductor layer that continuously covers the second main surface from the first main surface, from the collector electrode forming region on the first main surface to the side surface of the semiconductor substrate; A plating layer is formed so as to cover the entire second main surface via
After the electrolytic plating step,
11. The method for manufacturing a photovoltaic device according to claim 9, further comprising a step of removing the base conductor layer and the plating layer and forming a pn isolation groove at a certain distance inside from an end surface of the second main surface. The step of forming the second conductivity type semiconductor layer includes:
Forming a second conductive type amorphous semiconductor layer continuously so as to extend from the first main surface to the second main surface;
Prior to the step of forming the first electrode,
The method for manufacturing a photovoltaic element according to claim 11, comprising a step of forming a translucent conductive film on the second conductive type amorphous semiconductor layer. The step of forming the second conductivity type semiconductor layer includes:
Forming a second conductivity type impurity diffusion layer continuously so as to extend from the first main surface to the second main surface;
Prior to the step of forming the first electrode,
The method for manufacturing a photovoltaic element according to claim 7, comprising a step of forming a second electrode on the second main surface.   The method of manufacturing a photovoltaic element according to claim 13, wherein the step of forming the impurity diffusion layer is a vapor phase diffusion step. A plating tank filled with an electrolyte,
A first power supply terminal immersed in the plating tank;
In the plating tank, comprising at least a part of the back surface of the substrate to be processed and supporting the substrate to be processed and having a second power supply terminal for supplying power to the substrate to be processed,
The support unit includes a suction unit that contacts the substrate to be processed and sucks the substrate to be processed.
The second power supply terminal is an apparatus for manufacturing a photovoltaic element embedded in the suction portion.   The photovoltaic device manufacturing apparatus according to claim 15, wherein the suction portion is formed smaller than the substrate to be processed so as to expose a peripheral portion of the substrate to be processed.

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