TWI596729B - Chip package structure - Google Patents

Chip package structure Download PDF

Info

Publication number
TWI596729B
TWI596729B TW105141562A TW105141562A TWI596729B TW I596729 B TWI596729 B TW I596729B TW 105141562 A TW105141562 A TW 105141562A TW 105141562 A TW105141562 A TW 105141562A TW I596729 B TWI596729 B TW I596729B
Authority
TW
Taiwan
Prior art keywords
bump
bumps
window opening
package structure
pin
Prior art date
Application number
TW105141562A
Other languages
Chinese (zh)
Other versions
TW201824485A (en
Inventor
陳崇龍
曾伯強
Original Assignee
南茂科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 南茂科技股份有限公司 filed Critical 南茂科技股份有限公司
Priority to TW105141562A priority Critical patent/TWI596729B/en
Priority to CN201710127732.0A priority patent/CN108231715B/en
Application granted granted Critical
Publication of TWI596729B publication Critical patent/TWI596729B/en
Publication of TW201824485A publication Critical patent/TW201824485A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Structure Of Printed Boards (AREA)

Description

晶片封裝結構Chip package structure

本發明是有關於一種封裝結構，且特別是有關於一種晶片封裝結構。The present invention relates to a package structure, and more particularly to a chip package structure.

現行薄膜覆晶(chip on film)封裝結構為了因應越來越高腳數的需求，但又受限於可撓性薄膜上表面的佈線空間，已開始利用可撓性薄膜的下表面設置引腳。然而，由於薄膜覆晶封裝結構於訊號輸入端與訊號輸出端的腳數需求差異頗大，訊號輸出端的腳數較訊號輸入端的腳數多出許多，因此，一般而言於訊號輸出端側較需要利用可撓性薄膜下表面的空間設置下表面引腳。當可撓性薄膜下表面的引腳為選擇性地局部設置時，下表面的平坦度變差，也就是局部區域具有金屬的支撐，而局部區域則無。因此，在晶片透過壓合方式使晶片上的凸塊分別接合於可撓性薄膜上表面的引腳的過程中，不平整的下表面極可能導致受力不均的情況，使得這些凸塊與這些引腳接合不良。The current chip on film package structure has begun to use the lower surface of the flexible film to provide pins in order to meet the increasing demand for the number of feet, but limited by the wiring space on the upper surface of the flexible film. . However, since the film flip-chip package structure has a large difference in the number of pins at the signal input end and the signal output end, the number of pins at the signal output end is much larger than the number of pins at the signal input end. Therefore, it is generally required on the signal output end side. The lower surface pins are placed using the space of the lower surface of the flexible film. When the pins on the lower surface of the flexible film are selectively partially disposed, the flatness of the lower surface is deteriorated, that is, the local regions have metal support, and the partial regions are absent. Therefore, in the process of bonding the bumps on the wafer to the leads on the upper surface of the flexible film by the press-bonding method, the uneven lower surface may extremely cause uneven force, so that the bumps and the bumps These pins are not properly bonded.

本發明提供一種晶片封裝結構，其能提高晶片上的凸塊與可撓性薄膜上的引腳的接合良率。The present invention provides a wafer package structure that improves the bonding yield of bumps on a wafer to pins on a flexible film.

本發明提出一種晶片封裝結構，其包括可撓性薄膜、多個第一引腳、多個第二引腳、晶片以及圖案化金屬層。可撓性薄膜具有第一表面、相對於第一表面的第二表面以及位於第一表面上的晶片接合區。這些第一引腳設置於第一表面上，且延伸至晶片接合區內。這些第二引腳設置於第二表面上。晶片設置於第一表面上的晶片接合區內，其中晶片具有第一側邊、相對於第一側邊的第二側邊、多個第一凸塊以及多個第二凸塊。這些第一凸塊鄰近於並沿著第一側邊設置，且這些第二凸塊鄰近於並沿著第二側邊設置。這些第一引腳分別對應接合於這些第一凸塊與這些第二凸塊。圖案化金屬層設置於第二表面上。圖案化金屬層的位置與部分第一引腳與這些第一凸塊或這些第二凸塊的接合處重疊，其中圖案化金屬層具有第一開窗區與鄰接第一開窗區的支撐部。第一開窗區暴露出至少一個第一引腳與對應的第一凸塊或第二凸塊的接合處的局部，且支撐部與第一開窗區所暴露出的至少一個第一引腳與對應的第一凸塊或第二凸塊的接合處相重疊。The present invention provides a wafer package structure including a flexible film, a plurality of first leads, a plurality of second leads, a wafer, and a patterned metal layer. The flexible film has a first surface, a second surface opposite the first surface, and a wafer bonding region on the first surface. The first pins are disposed on the first surface and extend into the wafer bonding region. These second pins are disposed on the second surface. The wafer is disposed in the wafer bonding region on the first surface, wherein the wafer has a first side, a second side opposite the first side, a plurality of first bumps, and a plurality of second bumps. The first bumps are disposed adjacent to and along the first side, and the second bumps are disposed adjacent to and along the second side. The first pins are respectively coupled to the first bumps and the second bumps. The patterned metal layer is disposed on the second surface. Positioning the patterned metal layer and a portion of the first pin and the junction of the first bumps or the second bumps, wherein the patterned metal layer has a first window opening region and a support portion adjacent to the first window opening region . The first window opening region exposes a portion of the junction of the at least one first pin and the corresponding first bump or the second bump, and the support portion and the at least one first pin exposed by the first window opening region Overhanging the junction of the corresponding first bump or second bump.

基於上述，本發明的晶片封裝結構於可撓性薄膜的第一表面上設置第一引腳，並於相對於第一表面的第二表面上設置第二引腳。晶片設置於第一表面上並透過凸塊與第一引腳對應接合，另於第二表面上設置有圖案化金屬層以作為支撐結構，其中圖案化金屬層的位置與部分第一引腳與第一凸塊或第二凸塊的接合處重疊。一般而言，圖案化金屬層會位於設置有第二引腳的區域之外，特別是較大區塊未設置有第二引腳的區域。透過圖案化金屬層補強可撓性薄膜上未設置有第二引腳處的結構強度，並提高其第二表面的表面平坦度。因此，當晶片上的第一凸塊和第二凸塊與第一引腳以壓合方式接合時，可避免因第一表面上與第二表面上的金屬(第一引腳及第二引腳)分佈不均勻而導致受力不均的情況，有助於提高第一凸塊和第二凸塊與第一引腳的接合良率。另一方面，圖案化金屬層可具有至少一開窗區，用以判斷第一引腳相對於第一凸塊或第二凸塊的偏移程度，以確認第一凸塊或第二凸塊與第一引腳的接合情況是否符合製程規範。Based on the above, the chip package structure of the present invention is provided with a first pin on the first surface of the flexible film and a second pin on the second surface opposite to the first surface. The wafer is disposed on the first surface and correspondingly coupled to the first lead through the bump, and the patterned metal layer is disposed on the second surface as a support structure, wherein the position of the patterned metal layer and a portion of the first pin are The junction of the first bump or the second bump overlaps. In general, the patterned metal layer will be outside the area where the second pin is disposed, particularly where the larger block is not provided with the second pin. The structural strength of the flexible film is not reinforced by the patterned metal layer, and the surface flatness of the second surface is improved. Therefore, when the first bump and the second bump on the wafer are joined to the first lead in a press-fit manner, the metal on the first surface and the second surface (the first lead and the second lead) can be avoided. The uneven distribution of the feet causes uneven force, which helps to improve the bonding yield between the first bump and the second bump and the first lead. In another aspect, the patterned metal layer can have at least one open window region for determining the degree of offset of the first pin relative to the first bump or the second bump to confirm the first bump or the second bump Whether the engagement with the first pin conforms to the process specifications.

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the invention will be apparent from the following description.

圖1是本發明一實施例的晶片封裝結構的俯視示意圖。圖2A是圖1的晶片封裝結構的底視示意圖。圖2B與圖2C分別是圖2A中的區域A的局部放大示意圖。圖3是圖1的晶片封裝結構沿線段A-A的局部剖面示意圖。圖4是圖1的晶片封裝結構沿線段B-B的局部剖面示意圖。為求清楚表示與便於說明，圖1的晶片140以透視的方式繪示，並省略繪示封裝膠體。請參考圖1至圖4，在本實施例中，晶片封裝結構100例如是薄膜覆晶封裝結構，其包括可撓性薄膜110、多個第一引腳120a與120b、多個第二引腳130、晶片140以及圖案化金屬層150。可撓性薄膜110的材質可為聚醯亞胺(PI)或聚酯樹脂(PET)，其具有彼此相對的第一表面111與第二表面112以及位於第一表面111上的晶片接合區113。這些第一引腳120a與120b設置於第一表面111上，其中這些第一引腳120a與120b分別延伸至晶片接合區113內，且這些第二引腳130設置於第二表面112上。1 is a top plan view of a chip package structure in accordance with an embodiment of the present invention. 2A is a bottom plan view of the chip package structure of FIG. 1. 2B and 2C are partially enlarged schematic views of a region A in Fig. 2A, respectively. 3 is a partial cross-sectional view of the wafer package structure of FIG. 1 taken along line A-A. 4 is a partial cross-sectional view of the wafer package structure of FIG. 1 taken along line B-B. For clarity and convenience of explanation, the wafer 140 of FIG. 1 is shown in a see-through manner, and the encapsulant is omitted. Referring to FIG. 1 to FIG. 4 , in the embodiment, the chip package structure 100 is, for example, a thin film flip chip package structure, including a flexible film 110 , a plurality of first pins 120 a and 120 b , and a plurality of second pins. 130, wafer 140 and patterned metal layer 150. The material of the flexible film 110 may be polyimine (PI) or polyester resin (PET) having a first surface 111 and a second surface 112 opposite to each other and a wafer bonding region 113 on the first surface 111. . The first pins 120a and 120b are disposed on the first surface 111, wherein the first pins 120a and 120b respectively extend into the wafer bonding region 113, and the second pins 130 are disposed on the second surface 112.

晶片140設置於第一表面111上，且位於晶片接合區113內。在本實施例中，晶片140具有對應於輸入端110a的第一側邊141與對應於輸出端110b的第二側邊142，即第一側邊141與第二側邊142彼此相對。晶片140還具有鄰近於並沿著第一側邊141設置的多個第一凸塊143以及鄰近於並沿著第二側邊142設置的多個第二凸塊144，且這些第一凸塊143與這些第二凸塊144面向可撓性薄膜110的第一表面111。這些第一引腳120a穿過第一側邊141的下方並延伸至晶片接合區113內，而與這些第一凸塊143相接合。這些第一引腳120a可包含訊號引腳、電源引腳、接地引腳或虛置凸塊，且這些第一凸塊143可包含訊號凸塊、電源凸塊、接地凸塊或虛置凸塊。另一方面，這些第一引腳120b穿過第二側邊142的下方並延伸至晶片接合區113內，而與這些第二凸塊144相接合。這些第一引腳120b可包含訊號引腳、接地引腳或虛置引腳，且這些第二凸塊144可包含訊號凸塊、接地凸塊或虛置凸塊。The wafer 140 is disposed on the first surface 111 and is located within the wafer bonding region 113. In the present embodiment, the wafer 140 has a first side 141 corresponding to the input end 110a and a second side 142 corresponding to the output end 110b, ie, the first side 141 and the second side 142 are opposite each other. The wafer 140 further has a plurality of first bumps 143 disposed adjacent to and along the first side 141 and a plurality of second bumps 144 disposed adjacent to and along the second side 142, and the first bumps The second protrusion 144 faces the first surface 111 of the flexible film 110. These first pins 120a pass under the first side 141 and extend into the wafer bonding region 113 to be bonded to the first bumps 143. The first pins 120a may include signal pins, power pins, ground pins or dummy bumps, and the first bumps 143 may include signal bumps, power bumps, ground bumps or dummy bumps. . On the other hand, the first leads 120b pass under the second side 142 and extend into the wafer bond region 113 to engage the second bumps 144. The first pins 120b may include signal pins, ground pins or dummy pins, and the second bumps 144 may include signal bumps, ground bumps or dummy bumps.

這些第二引腳130自晶片接合區113正投影於第二表面112的區域內向外延伸至輸入端110a或輸出端110b，本實施例是以第二引腳130延伸至輸出端110b作說明，或稱這些第二引腳130自輸出端110b延伸至晶片接合區113正投影於第二表面112的區域內，且這些第二引腳130可包含訊號引腳、接地引腳或虛置引腳。如圖2A所示，圖案化金屬層150設置於第二表面112上，其中圖案化金屬層150的材質可為銅、其他適用的金屬或合金，也可與第二引腳130以相同材質且於同一製程中形成，圖案化金屬層150的至少部分位於晶片接合區113正投影至第二表面112的區域內，且圖案化金屬層150位於設置有這些第二引腳130的區域之外。在本實施例中，圖案化金屬層150包括分離的第一圖案150a與第二圖案150b，分別對應第一凸塊143及部分的第二凸塊144。The second lead 130 extends from the area where the wafer bonding area 113 is projected in the second surface 112 to the input end 110a or the output end 110b. This embodiment is described by extending the second pin 130 to the output end 110b. Or these second pins 130 extend from the output terminal 110b to the area where the wafer bonding region 113 is projected on the second surface 112, and the second pins 130 may include a signal pin, a ground pin or a dummy pin. . As shown in FIG. 2A, the patterned metal layer 150 is disposed on the second surface 112. The material of the patterned metal layer 150 may be copper, other suitable metals or alloys, or may be the same material as the second leads 130. Formed in the same process, at least a portion of the patterned metal layer 150 is located within a region of the wafer bond region 113 that is orthographically projected to the second surface 112, and the patterned metal layer 150 is located outside of the region where the second pins 130 are disposed. In the present embodiment, the patterned metal layer 150 includes a separated first pattern 150a and a second pattern 150b corresponding to the first bump 143 and a portion of the second bump 144, respectively.

詳細而言，第一圖案150a的位置與部分第一引腳120a與對應的部分第一凸塊143的接合處重疊，第二圖案150b的位置與部分第一引腳120b與對應的部分第二凸塊144的接合處重疊，由於圖案化金屬層150可提供支撐並補強可撓性薄膜110上未設置有第二引腳130處的結構強度，且提高第二表面112的表面平坦度，因此在使第一凸塊143與第二凸塊144透過熱壓合的方式接合於第一引腳120a與120b的過程中，不易產生受力不均的情況，有助於提高第一凸塊143與第二凸塊144和第一引腳120a與120b的接合良率。In detail, the position of the first pattern 150a overlaps with the junction of the partial first pin 120a and the corresponding partial first bump 143, the position of the second pattern 150b and the partial first pin 120b and the corresponding portion second The junction of the bumps 144 overlaps, since the patterned metal layer 150 can provide support and reinforce the structural strength at the second pin 130 on the flexible film 110, and increase the surface flatness of the second surface 112, In the process of bonding the first bumps 143 and the second bumps 144 to the first leads 120a and 120b through thermal compression bonding, uneven force is less likely to occur, which helps to improve the first bumps 143. Bonding yield with the second bump 144 and the first leads 120a and 120b.

第一圖案150a可具有第一開窗區151a1與151a2以及鄰接第一開窗區151a1與151a2的支撐部152a，第二圖案150b可具有第一開窗區151b以及鄰接第一開窗區151b的支撐部152b，其中第一開窗區151a1、151a2以及151b分別位於晶片接合區113正投影至第二表面112的區域內，且第一開窗區151a1與151a2分別暴露出至少一個第一引腳120a與對應的第一凸塊143的接合處的局部，而第一開窗區151b暴露出至少一個第一引腳120b與對應的第二凸塊144的接合處的局部。另一方面，支撐部152a與第一開窗區151a1、151a2所暴露出的第一引腳120a與對應的第一凸塊143的接合處相重疊，且支撐部152a的至少部分位於晶片接合區113正投影至第二表面112的區域內，而支撐部152b與第一開窗區151b所暴露出的第一引腳120b與對應的第二凸塊144的接合處相重疊，且支撐部152b的至少部分位於晶片接合區113正投影至第二表面112的區域內。The first pattern 150a may have first window opening regions 151a1 and 151a2 and a supporting portion 152a adjacent to the first window opening regions 151a1 and 151a2, and the second pattern 150b may have a first window opening region 151b and an adjacent first window opening region 151b. The support portion 152b, wherein the first window opening regions 151a1, 151a2, and 151b are respectively located in a region where the wafer bonding region 113 is projected onto the second surface 112, and the first window opening regions 151a1 and 151a2 respectively expose at least one first pin A portion of the junction of 120a with the corresponding first bump 143, and the first window opening region 151b exposes a portion of the junction of the at least one first pin 120b and the corresponding second bump 144. On the other hand, the support portion 152a overlaps the junction of the first lead 120a exposed by the first window opening regions 151a1, 151a2 and the corresponding first bump 143, and at least part of the support portion 152a is located at the wafer bonding region. 113 is projected into the area of the second surface 112, and the support portion 152b overlaps with the junction of the first pin 120b exposed by the first window opening region 151b and the corresponding second bump 144, and the support portion 152b At least a portion of the wafer bonding region 113 is projected into the region of the second surface 112.

由於第一圖案150a與第二圖案150b的設計原則大致相似或相同，因此以下僅就第二圖案150b舉例說明。如圖2A至圖2C所示，第一開窗區151b是以能夠暴露出至少一個第一引腳120b的端部(即內引腳的末端)與對應的第二凸塊144的至少一角落為原則，且支撐部152b與第一開窗區151b所暴露出的第一引腳120b與對應的第二凸塊144的接合處相重疊的面積A2是以不小於第一引腳120b與對應的第二凸塊144的接合處的面積A1的1/3為原則(即A2≧⅓A1)。基於此，不僅能透過第二圖案150b的第一開窗區151b確認第一引腳120b與對應的第二凸塊144的接合情況，也能透過第二圖案150b的支撐部152b於壓合時提供第一引腳120b與對應的第二凸塊144足夠的支撐效果。Since the design principles of the first pattern 150a and the second pattern 150b are substantially similar or identical, only the second pattern 150b will be exemplified below. As shown in FIG. 2A to FIG. 2C, the first window opening region 151b is at least one corner of the end portion (ie, the end of the inner lead) capable of exposing the at least one first pin 120b and the corresponding second bump 144. In principle, the area A2 of the support portion 152b and the junction of the first pin 120b and the corresponding second bump 144 exposed by the first window opening region 151b is not less than the first pin 120b and corresponding The 1/3 of the area A1 of the joint of the second bumps 144 is a principle (ie, A2≧1⁄3A1). Based on this, it is possible to confirm not only the first pin 120b and the corresponding second bump 144 but also the support portion 152b of the second pattern 150b through the first opening 151b of the second pattern 150b. A sufficient supporting effect of the first pin 120b and the corresponding second bump 144 is provided.

詳細而言，使第一開窗區151b暴露出至少一個第一引腳120b的端部(即內引腳的末端)與對應的第二凸塊144的至少一角落的設計原則，主要是為能透過第一開窗區151b觀察到第二凸塊144的兩鄰接的側邊(例如長邊與短邊)與對應的第一引腳120b的兩鄰接的側邊(即端部與鄰接的長邊)的相對位置，因此可同時判斷引腳於X及Y方向的偏移程度，以確認第一引腳120b與對應的第二凸塊144的接合面積是否符合製程規範。In detail, the design principle of exposing the first window opening region 151b to the end of the at least one first pin 120b (ie, the end of the inner pin) and at least one corner of the corresponding second bump 144 is mainly The two adjacent sides (eg, the long side and the short side) of the second bump 144 and the two adjacent sides of the corresponding first pin 120b can be observed through the first window opening area 151b (ie, the end and the adjacent side) The relative position of the long side can be determined at the same time to determine the degree of offset of the pin in the X and Y directions to confirm whether the joint area of the first pin 120b and the corresponding second bump 144 conforms to the process specification.

請繼續參考圖1、圖2A以及圖3，在本實施例中，晶片140還具有多個第三凸塊145，其中這些第三凸塊145鄰近於並沿著第二側邊142設置，且這些第三凸塊145與這些第二凸塊144彼此交錯排列。在其他實施例中，第三凸塊可以是鄰近於並沿著晶片的第一側邊設置，且第三凸塊與第一凸塊也可彼此交錯排列。除上述第三凸塊可與第一凸塊或第二凸塊交錯排列的實施態樣外，第三凸塊也可與第一凸塊或第二凸塊沿一直線排列，而未彼此交錯排列。另一方面，晶片封裝結構100更包括多個線路160與多個導電件170，其中這些線路160的數量與這些導電件170的數量一致，每一線路160與每一導電件170成對設置，且彼此電性連接。這些線路160設置於第一表面111上，其中各個線路160的至少局部位於晶片接合區113內，且這些第三凸塊145分別接合於這些線路160。With reference to FIG. 1 , FIG. 2A and FIG. 3 , in the embodiment, the wafer 140 further has a plurality of third bumps 145 , wherein the third bumps 145 are disposed adjacent to and along the second side 142 , and These third bumps 145 and the second bumps 144 are staggered with each other. In other embodiments, the third bumps may be disposed adjacent to and along the first side of the wafer, and the third bumps and the first bumps may also be staggered with each other. In addition to the embodiment in which the third bumps may be staggered with the first bumps or the second bumps, the third bumps may also be aligned with the first bumps or the second bumps without being staggered with each other. . On the other hand, the chip package structure 100 further includes a plurality of lines 160 and a plurality of conductive members 170, wherein the number of the lines 160 is consistent with the number of the conductive members 170, and each line 160 is disposed in pairs with each of the conductive members 170. And electrically connected to each other. The lines 160 are disposed on the first surface 111 with at least portions of the respective lines 160 located within the wafer land 113 and the third bumps 145 are bonded to the lines 160, respectively.

這些導電件170可以是貫通第一表面111與第二表面112的導電通孔，且這些導電件170分別與這些線路160及這些第二引腳130電性連接。也就是說，每一個導電件170落在對應的線路160與第二引腳130重疊處，以導通分別位於可撓性薄膜110的相對第一表面111與第二表面112的線路160與第二引腳130，使得位於第二表面112上的第二引腳130電性連接至第三凸塊145。另一方面，由於這些第三凸塊145與這些第二凸塊144彼此交錯排列，這些第一引腳120b分別對應於這些第二凸塊144設置，且這些第二引腳130分別對應於這些第三凸塊145設置，因此這些第一引腳120b與這些第二引腳130彼此交錯排列。The conductive members 170 may be conductive vias penetrating the first surface 111 and the second surface 112 , and the conductive members 170 are electrically connected to the lines 160 and the second leads 130 , respectively. That is, each of the conductive members 170 falls at a position where the corresponding line 160 overlaps with the second lead 130 to turn on the line 160 and the second of the opposite first surface 111 and the second surface 112 of the flexible film 110, respectively. The pin 130 is electrically connected to the third bump 145 on the second surface 112 . On the other hand, since the third bumps 145 and the second bumps 144 are staggered with each other, the first pins 120b are respectively disposed corresponding to the second bumps 144, and the second pins 130 respectively correspond to the second bumps 144. The third bumps 145 are disposed such that the first pins 120b and the second pins 130 are staggered with each other.

以下將列舉其他實施例以作為說明。在此必須說明的是，下述實施例沿用前述實施例的元件標號與部分內容，其中採用相同的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，下述實施例不再重複贅述。Other embodiments are listed below for illustration. It is to be noted that the following embodiments use the same reference numerals and parts of the above-mentioned embodiments, and the same reference numerals are used to refer to the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted portions, reference may be made to the foregoing embodiments, and the following embodiments are not repeated.

圖5是本發明另一實施例的晶片封裝結構的底視示意圖。請參考圖5，本實施例的晶片封裝結構100A與上述實施例的晶片封裝結構100的差異在於：第一圖案150a1還具有第二開窗區153a，第一開窗區151a1與第二開窗區153a分別位於支撐部152a的相對兩側，且第二開窗區153a較第一開窗區151a1接近第一側邊141或者是與第一側邊141相重疊。暴露於第一開窗區151a1的至少一個第一引腳120a與對應的第一凸塊143同樣地局部暴露於相對於第一開窗區151a1設置的第二開窗區153a，且第二開窗區153a暴露出第一引腳120a與對應的第一凸塊143的接合處的局部。FIG. 5 is a bottom plan view of a chip package structure according to another embodiment of the present invention. Referring to FIG. 5, the wafer package structure 100A of the present embodiment is different from the chip package structure 100 of the above embodiment in that the first pattern 150a1 further has a second window opening region 153a, a first window opening region 151a1 and a second window opening. The regions 153a are respectively located on opposite sides of the support portion 152a, and the second window opening region 153a is closer to the first side edge 141 than the first window opening region 151a1 or overlaps the first side edge 141. The at least one first pin 120a exposed to the first window opening region 151a1 is partially exposed to the second window opening region 153a disposed with respect to the first window opening region 151a1, and is secondly opened, similarly to the corresponding first bump 143. The window region 153a exposes a portion of the junction of the first pin 120a and the corresponding first bump 143.

在本實施例中，第一開窗區151a1暴露出第一引腳120a的端部(即內引腳的末端)與對應的第一凸塊143較靠近第一引腳120a的端部的兩個角落，而第二開窗區153a暴露出前述第一凸塊143的另外兩個角落。透過第一開窗區151a1與第二開窗區153a可觀察到第一凸塊143的四個角落與第一引腳120a的端部，除了可判斷第一引腳120a相對於第一凸塊143在X及Y方向的偏移程度，也可判斷第一引腳120a是否產生彎折或轉向，進而能更清楚地確認第一引腳120a與對應的第一凸塊143的接合情況。於其他實施態樣中，第二開窗區153a可對應於第一開窗區151a2設置，或者是第一圖案150a1可具有兩個第二開窗區153a，且前述兩個第二開窗區153a分別對應於第一開窗區151a1與151a2設置。 In the present embodiment, the first window opening region 151a1 exposes the end of the first pin 120a (ie, the end of the inner pin) and the corresponding first bump 143 are closer to the end of the first pin 120a. The corners and the second window opening area 153a expose the other two corners of the first bump 143. The four corners of the first bump 143 and the end of the first pin 120a are observed through the first window opening area 151a1 and the second window opening area 153a, except that the first pin 120a can be determined relative to the first bump 143, in the X and Y directions, it is also possible to determine whether the first pin 120a is bent or turned, and the bonding of the first pin 120a and the corresponding first bump 143 can be more clearly confirmed. In other implementations, the second window opening area 153a may be disposed corresponding to the first window opening area 151a2, or the first pattern 150a1 may have two second window opening areas 153a, and the foregoing two second window opening areas 153a are respectively provided corresponding to the first window opening areas 151a1 and 151a2.

另一方面，第二圖案150b1還具有第二開窗區153b，其中第二開窗區153b對應於第一開窗區151b設置，且第一開窗區151b與第二開窗區153b分別位於支撐部152b的相對兩側，且第二開窗區153b較第一開窗區151b接近第二側邊142或者是與第二側邊142相重疊。其中第二圖案150b1的第一開窗區151b與第二開窗區153b和其所暴露出的至少一個第一引腳120b與對應的第二凸塊144的位置關係可參照上述第一圖案150a1的相關說明，於此不再贅述。 On the other hand, the second pattern 150b1 further has a second window opening area 153b, wherein the second window opening area 153b is disposed corresponding to the first window opening area 151b, and the first window opening area 151b and the second window opening area 153b are respectively located The opposite sides of the support portion 152b, and the second window opening region 153b are closer to the second side edge 142 than the first window opening portion 151b or overlap the second side edge 142. The positional relationship between the first window opening area 151b and the second window opening area 153b of the second pattern 150b1 and the exposed at least one first pin 120b and the corresponding second protrusion 144 may refer to the first pattern 150a1. The relevant description will not be repeated here.

圖6是本發明又一實施例的晶片封裝結構的底視示意圖。請參考圖6，本實施例的晶片封裝結構100B與上述實施例的晶片封裝結構100的差異在於：晶片封裝結構100B的圖案化金屬層150c為佈設於第二表面112上且相連的一整片圖案，且覆蓋於設置有第二引腳130的區域之外。詳細而言，圖案化金屬層150c可具有開窗區151c~151f，其中開窗區151c~151f位於晶片接合區113正投影至第二表面112的區域內。開窗區151c與151d分別暴露出至少一個第一引腳120a與對應的第一凸塊143的接合處的局部，開窗區151f暴露出第一引腳120b與對應的第二凸塊144的接合處的局部，其中開窗區151e與圖5的第二開窗區153a相似。開窗區151e與開窗區151d分別位於支撐部152c的相對兩側，開窗區151e較開窗區151d接近第一側邊141或者是與第一側邊141 相重疊，且開窗區151e暴露出開窗區151d所暴露出的第一引腳120a與對應的第一凸塊143的接合處的局部。本實施例的開窗區151c~151f和其所暴露出的第一引腳120a、120b與對應的第一凸塊143、第二凸塊144的位置關係可參照上述實施例中的相關說明，於此不再贅述。 6 is a bottom plan view of a chip package structure according to still another embodiment of the present invention. Referring to FIG. 6, the wafer package structure 100B of the present embodiment is different from the chip package structure 100 of the above embodiment in that the patterned metal layer 150c of the chip package structure 100B is a whole piece connected to the second surface 112 and connected. The pattern is overlaid outside the area where the second pin 130 is disposed. In detail, the patterned metal layer 150c may have windowing regions 151c to 151f, wherein the windowing regions 151c to 151f are located in a region where the wafer bonding region 113 is projected onto the second surface 112. The window opening regions 151c and 151d respectively expose portions of the joint of the at least one first pin 120a and the corresponding first bump 143, and the window opening region 151f exposes the first pin 120b and the corresponding second bump 144. A portion of the joint where the window opening region 151e is similar to the second window opening region 153a of FIG. The window opening area 151e and the window opening area 151d are respectively located on opposite sides of the supporting portion 152c, and the window opening area 151e is closer to the first side edge 141 or the first side edge 141 than the window opening area 151d. The overlaps, and the window opening region 151e exposes a portion of the junction of the first pin 120a and the corresponding first bump 143 exposed by the window opening region 151d. For the positional relationship between the window opening areas 151c to 151f of the present embodiment and the first pins 120a and 120b exposed thereto and the corresponding first bumps 143 and 144, refer to the related description in the above embodiments. This will not be repeated here.

由於圖案化金屬層150c在第二表面112上的所佔面積較大，大幅地提高第二表面112的表面平坦度，因此能於壓合第一引腳120a、120b與對應的第一凸塊143、第二凸塊144時提供更為顯著的支撐效用、降低晶片封裝結構100B的翹曲量，並增加散熱效果。另一方面，開窗區151c~151f可用以確認第一引腳120a與對應的第一凸塊143及第一引腳120b與對應的第二凸塊144的接合情況。 Since the occupied area of the patterned metal layer 150c on the second surface 112 is large, the surface flatness of the second surface 112 is greatly improved, so that the first pins 120a, 120b and the corresponding first bumps can be pressed together. 143. The second bump 144 provides a more significant support effect, reduces the amount of warpage of the chip package structure 100B, and increases the heat dissipation effect. On the other hand, the window opening regions 151c to 151f can be used to confirm the engagement of the first pin 120a and the corresponding first bump 143 and the first pin 120b with the corresponding second bump 144.

綜上所述，本發明的晶片封裝結構於可撓性薄膜的第一表面上設置第一引腳，並於相對於第一表面的第二表面上設置第二引腳。晶片設置於第一表面上並透過凸塊與第一引腳對應接合，另於第二表面上設置有圖案化金屬層以作為支撐結構，其中圖案化金屬層的位置與部分第一引腳與第一凸塊或第二凸塊的接合處重疊。一般而言，圖案化金屬層會位於設置有第二引腳的區域之外，特別是較大區塊未設置有第二引腳的區域。透過圖案化金屬層補強可撓性薄膜上未設置有第二引腳處的結構強度，並提高第二表面的表面平坦度。因此，當晶片上的第一凸塊和第二凸塊與第一引腳以壓合方式接合時，可避免因第一表面上與第二表面上的金屬(第一引腳及第二引腳)分佈不均勻而導致受力不均的情況，有助於提高第一凸塊或第二凸塊與第一引腳的接合良率。另一方面，圖案化金屬層可具有至少一開窗區，用以判斷第一引腳相對於第一凸塊或第二凸塊的偏移程度，以確認第一凸塊或第二凸塊與第一引腳的接合情況是否符合製程規範。In summary, the chip package structure of the present invention is provided with a first pin on a first surface of the flexible film and a second pin on a second surface opposite to the first surface. The wafer is disposed on the first surface and correspondingly coupled to the first lead through the bump, and the patterned metal layer is disposed on the second surface as a support structure, wherein the position of the patterned metal layer and a portion of the first pin are The junction of the first bump or the second bump overlaps. In general, the patterned metal layer will be outside the area where the second pin is disposed, particularly where the larger block is not provided with the second pin. The structural strength of the second film is not provided on the flexible film through the patterned metal layer, and the surface flatness of the second surface is improved. Therefore, when the first bump and the second bump on the wafer are joined to the first lead in a press-fit manner, the metal on the first surface and the second surface (the first lead and the second lead) can be avoided. The uneven distribution of the feet causes uneven force, which helps to improve the bonding yield of the first bump or the second bump to the first lead. In another aspect, the patterned metal layer can have at least one open window region for determining the degree of offset of the first pin relative to the first bump or the second bump to confirm the first bump or the second bump Whether the engagement with the first pin conforms to the process specifications.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100、100A~100B‧‧‧晶片封裝結構
110‧‧‧可撓性薄膜
110a‧‧‧輸入端
110b‧‧‧輸出端
111‧‧‧第一表面
112‧‧‧第二表面
113‧‧‧晶片接合區
120a、120b‧‧‧第一引腳
130‧‧‧第二引腳
140‧‧‧晶片
141‧‧‧第一側邊
142‧‧‧第二側邊
143‧‧‧第一凸塊
144‧‧‧第二凸塊
145‧‧‧第三凸塊
150、150c‧‧‧圖案化金屬層
150a、150a1‧‧‧第一圖案
150b、150b1‧‧‧第二圖案
151a1、151a2、151b‧‧‧第一開窗區
152a、152b、152c‧‧‧支撐部
153a、153b‧‧‧第二開窗區
151c~151f‧‧‧開窗區
160‧‧‧線路
170‧‧‧導電件
A‧‧‧區域
A1、A2‧‧‧面積100, 100A~100B‧‧‧ chip package structure
110‧‧‧Flexible film
110a‧‧‧ input
110b‧‧‧output
111‧‧‧ first surface
112‧‧‧ second surface
113‧‧‧ wafer junction area
120a, 120b‧‧‧ first pin
130‧‧‧second pin
140‧‧‧ wafer
141‧‧‧ first side
142‧‧‧ second side
143‧‧‧First bump
144‧‧‧second bump
145‧‧‧ third bump
150, 150c‧‧‧ patterned metal layer
150a, 150a1‧‧‧ first pattern
150b, 150b1‧‧‧ second pattern
151a1, 151a2, 151b‧‧‧ first window area
152a, 152b, 152c‧‧‧ support
153a, 153b‧‧‧ second window area
151c~151f‧‧‧window area
160‧‧‧ lines
170‧‧‧Electrical parts
A‧‧‧ area
A1, A2‧‧‧ area

圖1是本發明一實施例的晶片封裝結構的俯視示意圖。 圖2A是圖1的晶片封裝結構的底視示意圖。 圖2B與圖2C分別是圖2A中的區域A的局部放大示意圖。 圖3是圖1的晶片封裝結構沿線段A-A的局部剖面示意圖。 圖4是圖1的晶片封裝結構沿線段B-B的局部剖面示意圖。 圖5是本發明另一實施例的晶片封裝結構的底視示意圖。 圖6是本發明又一實施例的晶片封裝結構的底視示意圖。1 is a top plan view of a chip package structure in accordance with an embodiment of the present invention. 2A is a bottom plan view of the chip package structure of FIG. 1. 2B and 2C are partially enlarged schematic views of a region A in Fig. 2A, respectively. 3 is a partial cross-sectional view of the wafer package structure of FIG. 1 taken along line A-A. 4 is a partial cross-sectional view of the wafer package structure of FIG. 1 taken along line B-B. FIG. 5 is a bottom plan view of a chip package structure according to another embodiment of the present invention. 6 is a bottom plan view of a chip package structure according to still another embodiment of the present invention.

100‧‧‧晶片封裝結構 100‧‧‧ Chip package structure

110‧‧‧可撓性薄膜 110‧‧‧Flexible film

110a‧‧‧輸入端 110a‧‧‧ input

110b‧‧‧輸出端 110b‧‧‧output

112‧‧‧第二表面 112‧‧‧ second surface

113‧‧‧晶片接合區 113‧‧‧ wafer junction area

120a、120b‧‧‧第一引腳 120a, 120b‧‧‧ first pin

130‧‧‧第二引腳 130‧‧‧second pin

140‧‧‧晶片 140‧‧‧ wafer

141‧‧‧第一側邊 141‧‧‧ first side

142‧‧‧第二側邊 142‧‧‧ second side

143‧‧‧第一凸塊 143‧‧‧First bump

144‧‧‧第二凸塊 144‧‧‧second bump

145‧‧‧第三凸塊 145‧‧‧ third bump

150‧‧‧圖案化金屬層 150‧‧‧ patterned metal layer

150a‧‧‧第一圖案 150a‧‧‧first pattern

150b‧‧‧第二圖案 150b‧‧‧second pattern

151a1、151a2、151b‧‧‧第一開窗區 151a1, 151a2, 151b‧‧‧ first window area

152a、152b‧‧‧支撐部 152a, 152b‧‧‧ support

160‧‧‧線路 160‧‧‧ lines

170‧‧‧導電件 170‧‧‧Electrical parts

A‧‧‧區域 A‧‧‧ area

Claims (10)

一種晶片封裝結構，包括： 一可撓性薄膜，具有一第一表面、相對於該第一表面的一第二表面以及位於該第一表面上的一晶片接合區； 多個第一引腳，設置於該第一表面上，且延伸至該晶片接合區內； 多個第二引腳，設置於該第二表面上； 一晶片，設置於該第一表面上的該晶片接合區內，其中該晶片具有一第一側邊、相對於該第一側邊的一第二側邊、多個第一凸塊以及多個第二凸塊，該些第一凸塊鄰近於並沿著該第一側邊設置，且該些第二凸塊鄰近於並沿著該第二側邊設置，該些第一引腳分別對應接合於該些第一凸塊與該些第二凸塊；以及 一圖案化金屬層，設置於該第二表面上，該圖案化金屬層的位置與部分該些第一引腳與該些第一凸塊或該些第二凸塊的接合處重疊，其中該圖案化金屬層具有一第一開窗區與鄰接該第一開窗區的一支撐部，該第一開窗區暴露出至少一該第一引腳與對應的該第一凸塊或該第二凸塊的接合處的局部，且該支撐部與該第一開窗區所暴露出的至少一該第一引腳與對應的該第一凸塊或該第二凸塊的接合處相重疊。A chip package structure comprising: a flexible film having a first surface, a second surface opposite to the first surface, and a wafer bonding region on the first surface; a plurality of first leads, And disposed on the first surface and extending into the wafer bonding region; a plurality of second pins disposed on the second surface; a wafer disposed in the wafer bonding region on the first surface, wherein The wafer has a first side, a second side opposite the first side, a plurality of first bumps, and a plurality of second bumps, the first bumps being adjacent to and along the first One side is disposed, and the second bumps are disposed adjacent to and along the second side, the first pins are respectively correspondingly coupled to the first bumps and the second bumps; a patterned metal layer disposed on the second surface, the patterned metal layer is overlapped with a portion of the first lead and the first bump or the second bump, wherein the pattern The metal layer has a first window opening area and a support portion adjacent to the first window opening area, An open window region exposes at least one portion of the joint of the first pin and the corresponding first bump or the second bump, and the support portion and at least one exposed by the first window opening region The first pin overlaps with a corresponding junction of the first bump or the second bump. 如申請專利範圍第1項所述的晶片封裝結構，其中該圖案化金屬層還具有一第二開窗區，該第一開窗區與該第二開窗區分別位於該支撐部的相對兩側，且該第二開窗區暴露出該第一開窗區所暴露出的至少一該第一引腳與對應的該第一凸塊或該第二凸塊的接合處的局部。The chip package structure of claim 1, wherein the patterned metal layer further has a second window opening area, wherein the first window opening area and the second window opening area are respectively located at opposite sides of the supporting portion a side, and the second window opening area exposes a portion of the junction of the at least one first pin and the corresponding first bump or the second bump exposed by the first window opening region. 如申請專利範圍第2項所述的晶片封裝結構，其中該第一開窗區暴露出至少一該第一引腳的端部與對應的該第一凸塊或該第二凸塊的至少一角落，且該第二開窗區暴露出該第一凸塊或該第二凸塊的至少另一角落。The chip package structure of claim 2, wherein the first window opening region exposes at least one end of the first pin and at least one of the corresponding first bump or the second bump a corner, and the second window opening area exposes at least another corner of the first bump or the second bump. 如申請專利範圍第1項所述的晶片封裝結構，其中該些第二引腳延伸至該晶片接合區投影於該第二表面的區域內。The chip package structure of claim 1, wherein the second leads extend to a region where the wafer bonding region is projected on the second surface. 如申請專利範圍第4項所述的晶片封裝結構，其中該圖案化金屬層位於設置有該些第二引腳的區域之外。The chip package structure of claim 4, wherein the patterned metal layer is located outside a region where the second pins are disposed. 如申請專利範圍第1項所述的晶片封裝結構，其中該晶片還具有多個第三凸塊，且該些第三凸塊鄰近於該第一側邊或該第二側邊設置。The chip package structure of claim 1, wherein the wafer further has a plurality of third bumps, and the third bumps are disposed adjacent to the first side or the second side. 如申請專利範圍第6項所述的晶片封裝結構，更包括： 多個線路，設置於該第一表面上，各該線路的至少局部位於該晶片接合區內，且該些第三凸塊分別接合於該些線路；以及 多個導電件，貫通該第一表面與該第二表面，且該些導電件分別與該些線路及該些第二引腳電性連接。The chip package structure of claim 6, further comprising: a plurality of wires disposed on the first surface, at least part of each of the wires being located in the wafer bonding region, and the third bumps respectively And the plurality of conductive members are connected to the first surface and the second surface, and the conductive members are electrically connected to the wires and the second pins respectively. 如申請專利範圍第6項所述的晶片封裝結構，其中該些第三凸塊鄰近於並沿著該第二側邊設置，且與該些第二凸塊彼此交錯排列，並且接合於該些第二凸塊的該些第一引腳與該些第二引腳彼此交錯排列。The chip package structure of claim 6, wherein the third bumps are disposed adjacent to and along the second side, and are staggered with the second bumps, and are bonded to the second bumps The first pins and the second pins of the second bump are staggered with each other. 如申請專利範圍第1項所述的晶片封裝結構，其中該第一開窗區暴露出至少一該第一引腳的端部與對應的該第一凸塊或該第二凸塊的至少一角落。The chip package structure of claim 1, wherein the first window opening region exposes at least one end of the first pin and at least one of the corresponding first bump or the second bump corner. 如申請專利範圍第1項所述的晶片封裝結構，其中該支撐部與該第一開窗區所暴露出的至少一該第一引腳與對應的該第一凸塊或該第二凸塊的接合處相重疊的面積不小於至少一該第一引腳與對應的該第一凸塊或該第二凸塊的接合處的面積的1/3。The chip package structure of claim 1, wherein the support portion and the at least one first pin exposed by the first window opening region and the corresponding first bump or the second bump The area where the joint overlaps is not less than 1/3 of the area of the joint of the at least one first lead and the corresponding first bump or the second bump.
TW105141562A 2016-12-15 2016-12-15 Chip package structure TWI596729B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW105141562A TWI596729B (en) 2016-12-15 2016-12-15 Chip package structure
CN201710127732.0A CN108231715B (en) 2016-12-15 2017-03-06 Chip packaging structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW105141562A TWI596729B (en) 2016-12-15 2016-12-15 Chip package structure

Publications (2)

Publication Number Publication Date
TWI596729B true TWI596729B (en) 2017-08-21
TW201824485A TW201824485A (en) 2018-07-01

Family

ID=60189389

Family Applications (1)

Application Number Title Priority Date Filing Date
TW105141562A TWI596729B (en) 2016-12-15 2016-12-15 Chip package structure

Country Status (2)

Country Link
CN (1) CN108231715B (en)
TW (1) TWI596729B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI673845B (en) * 2018-04-19 2019-10-01 南茂科技股份有限公司 Chip-on-film package structure

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10777525B1 (en) * 2019-03-27 2020-09-15 Himax Technologies Limited Filp chip package
TWI726675B (en) * 2020-04-09 2021-05-01 南茂科技股份有限公司 Chip-on-film package structure
TWI804103B (en) * 2021-12-14 2023-06-01 南茂科技股份有限公司 Chip on film package structure

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200634952A (en) * 2005-03-30 2006-10-01 Advanced Semiconductor Eng Stackable back-to-back flip chip package

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100399557C (en) * 2005-08-17 2008-07-02 南茂科技股份有限公司 Flexible base palte in use for packing semiconductor, and onload packaging structure
JP2009094118A (en) * 2007-10-04 2009-04-30 Panasonic Corp Lead frame, electronic component with the same, and manufacturing method thereof
TWI501360B (en) * 2008-04-17 2015-09-21 Samsung Electronics Co Ltd Tape for heat dissipating member, chip on film type semiconductor package including heat dissipating member, and electronic apparatus including the same
JP5214753B2 (en) * 2011-02-23 2013-06-19 シャープ株式会社 Semiconductor device and manufacturing method thereof
KR101990148B1 (en) * 2015-04-14 2019-06-19 에스케이하이닉스 주식회사 Semiconductor package

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200634952A (en) * 2005-03-30 2006-10-01 Advanced Semiconductor Eng Stackable back-to-back flip chip package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI673845B (en) * 2018-04-19 2019-10-01 南茂科技股份有限公司 Chip-on-film package structure

Also Published As

Publication number Publication date
TW201824485A (en) 2018-07-01
CN108231715B (en) 2019-10-11
CN108231715A (en) 2018-06-29

Similar Documents

Publication Publication Date Title
TWI596729B (en) Chip package structure
JP4971769B2 (en) Flip chip mounting structure and manufacturing method of flip chip mounting structure
JP2008159956A (en) Substrate incorporating electronic component
TWI236077B (en) Stack package and fabricating method thereof
TW201407699A (en) Package assembly and methods for forming the same
JP2011166051A (en) Semiconductor device and method of manufacturing the same
CN109390306A (en) Electronic package
KR102511832B1 (en) Semiconductor package device
JP2011077108A (en) Semiconductor device
US20150163908A1 (en) Circuit board and manufacturing method thereof
TWI584425B (en) Fan-out wafer level package structure
TWI461128B (en) Enhanced flip chip structure using copper column interconnect
US8098496B2 (en) Wiring board for semiconductor device
KR20070105853A (en) Mounting substrate
JP4556671B2 (en) Semiconductor package and flexible circuit board
JP7232123B2 (en) Wiring board, electronic device, and method for manufacturing wiring board
TWI673845B (en) Chip-on-film package structure
KR100874923B1 (en) Multi-stack package, manufacturing method thereof and semiconductor package mold for manufacturing same
JP2009283835A (en) Semiconductor device and method of manufacturing the same
JP2008277457A (en) Multilayer semiconductor device and package
JP4737995B2 (en) Semiconductor device
JP2005026630A (en) Semiconductor device and its manufacturing method
TWI488273B (en) Manufacturing method of semiconductor and semiconductor structure thereof
JP2007059547A (en) Semiconductor chip and method of manufacturing semiconductor chip
JP2014212356A (en) Semiconductor device and manufacturing method of the same