CN108231715A - Chip packaging structure - Google Patents
Chip packaging structure Download PDFInfo
- Publication number
- CN108231715A CN108231715A CN201710127732.0A CN201710127732A CN108231715A CN 108231715 A CN108231715 A CN 108231715A CN 201710127732 A CN201710127732 A CN 201710127732A CN 108231715 A CN108231715 A CN 108231715A
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- Prior art keywords
- convex block
- chip
- pin
- area
- packaging structure
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 39
- 239000002184 metal Substances 0.000 claims abstract description 39
- 229910052751 metal Inorganic materials 0.000 claims abstract description 39
- 239000010408 film Substances 0.000 description 18
- 238000003825 pressing Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000002787 reinforcement Effects 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000012856 packing Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229920001225 polyester resin Polymers 0.000 description 2
- 239000004645 polyester resin Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 239000000084 colloidal system Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000007731 hot pressing Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/171—Disposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
- H01L2224/331—Disposition
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
- Structure Of Printed Boards (AREA)
Abstract
The invention provides a chip packaging structure which comprises a flexible film, a plurality of first pins, a plurality of second pins, a chip and a patterned metal layer. The chip and the first pins are arranged on a first surface of the flexible film, and the patterned metal layer and the second pins are arranged on a second surface of the flexible film, which is opposite to the first surface. The first leads are respectively jointed with the first bumps and the second bumps of the chip. The position of the patterned metal layer is overlapped with the joint of part of the first pins and the first bumps or the second bumps, the first windowing area of the patterned metal layer exposes a part of the joint of at least one first pin and the corresponding first bump or second bump, and the supporting part of the patterned metal layer is overlapped with the joint. The chip packaging structure can improve the joint yield of the lug on the chip and the pin on the flexible film.
Description
Technical field
The present invention relates to a kind of encapsulating structure, and more particularly to a kind of chip-packaging structure.
Background technology
Existing membrane of flip chip (chip on film) encapsulating structure is limited to adapt to the demand of increasingly high pin count
Wiring space in flexible film upper surface has started with the lower surface setting pin of flexible film.However, due to thin
Film composite packing structure is quite big in the foot number demand difference of signal input part and signal output end, and the foot number of signal output end is relatively believed
The foot number of number input terminal is much more, therefore, it is however generally that relatively needs to utilize flexible film lower surface in signal output end side
Space setting lower surface pin.When the pin of flexible film lower surface is selectively local setting, lower surface is put down
It is smooth degree be deteriorated, that is, regional area have metal support, and regional area then without.Therefore, pass through pressing mode in chip
Make during the convex block on chip is individually coupled to the pin of flexible film upper surface, the lower surface of out-of-flatness is most probably led
Cause the situation of unbalance stress so that these convex blocks engage bad with these pins.
Invention content
The present invention provides a kind of chip-packaging structure, can improve the convex block on chip and the pin on flexible film
Engage yield.
The present invention proposes a kind of chip-packaging structure, draws including flexible film, multiple first pins, multiple second
Foot, chip and patterned metal layer.Flexible film has first surface, the second surface relative to first surface and position
In the chip bonding area on first surface.These first pins are set on first surface, and extend in chip bonding area.This
A little second pins are set on second surface.Chip is set in the chip bonding area on first surface, and chips have the
A side, relative to the second side of first side, multiple first convex blocks and multiple second convex blocks.These first convex blocks are neighbouring
It is set in and along first side, and these second convex blocks are adjacent to and are set along second side.These first pins are distinguished
Correspondence is engaged in these first convex blocks and these second convex blocks.Patterned metal layer is set on second surface.Pattern metal
The position of layer is Chong Die with the joint of these first convex blocks or these the second convex blocks with the first pin of part, wherein pattern metal
Floor has the support portion in the first windowing area and adjacent first windowing area.First windowing area expose at least one first pin with it is right
The first convex block answered or the part of the joint of the second convex block, and support portion and the first windowing area exposed at least one the
One pin overlaps with the joint of corresponding first convex block or the second convex block.
Based on above-mentioned, of the invention chip-packaging structure in setting the first pin on the first surface of flexible film, and
In setting second pin on the second surface relative to first surface.Chip is set on first surface and passes through convex block and first
Pin corresponds to engagement, separately in being provided with patterned metal layer on second surface using as support construction, wherein patterned metal layer
Position and the first pin of part it is Chong Die with the joint of the first convex block or the second convex block.In general, patterned metal layer meeting
Positioned at being provided with except the region of second pin, particularly larger block is not provided with the region of second pin.Pass through patterning
The structural strength being not provided on metal layer reinforcement pliability film at second pin, and the surface for improving its second surface is flat
Degree.Therefore, it when the first convex block on chip and the second convex block are engaged with the first pin with pressing mode, can avoid because of the first table
The situation of unbalance stress is unevenly distributed and caused with the metal (the first pin and second pin) on second surface on face, is helped
In the first convex block of raising and the engagement yield of the second convex block and the first pin.On the other hand, patterned metal layer can have at least
One windowing area, to judge degrees of offset of first pin relative to the first convex block or the second convex block, with confirm the first convex block or
Whether the engagement situation of the second convex block and the first pin meets Manufacturing Process.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and it is detailed that attached drawing is coordinated to make
Carefully it is described as follows.
Description of the drawings
Fig. 1 is the schematic top plan view of the chip-packaging structure of one embodiment of the invention.
Fig. 2A is the bottom view of the chip-packaging structure of Fig. 1.
Fig. 2 B and Fig. 2 C are the close-up schematic view of the region A in Fig. 2A respectively.
Fig. 3 is partial cutaway schematic of the chip-packaging structure of Fig. 1 along line segment A-A.
Fig. 4 is partial cutaway schematic of the chip-packaging structure of Fig. 1 along line segment B-B.
Fig. 5 is the bottom view of the chip-packaging structure of another embodiment of the present invention.
Fig. 6 is the bottom view of the chip-packaging structure of further embodiment of this invention.
Reference sign：
100：Chip-packaging structure
110：Flexible film
110a：Input terminal
110b：Output terminal
112：Second surface
113：Chip bonding area
120a、120b：First pin
130：Second pin
140：Chip
141：First side
142：Second side
143：First convex block
144：Second convex block
145：Third convex block
150：Patterned metal layer
150a：First pattern
150b：Second pattern
151a1、151a2、151b：First windowing area
152a、152b：Support portion
160：Circuit
170：Conduct piece
A：Region
Specific embodiment
Fig. 1 is the schematic top plan view of the chip-packaging structure of one embodiment of the invention.Fig. 2A is the chip-packaging structure of Fig. 1
Bottom view.Fig. 2 B and Fig. 2 C are the close-up schematic view of the region A in Fig. 2A respectively.Fig. 3 is the chip package of Fig. 1
Partial cutaway schematic of the structure along line segment A-A.The chip-packaging structure that Fig. 4 is Fig. 1 is illustrated along the part section of line segment B-B
Figure.Represent that the chip 140 of Fig. 1 is illustrated in a manner of perspective, and illustration omitted packing colloid with being convenient for explanation for clarity.Please
Referring to figs. 1 to Fig. 4, in the present embodiment, chip-packaging structure 100 is, for example, package structure membrane of flip chip package, including pliability
Film 110, multiple first pin 120a and 120b, multiple second pins 130, chip 140 and patterned metal layer 150.It can
The material of flexible thin film 110 can be polyimides (PI) or polyester resin (PET), with each other relative first surface 111
Chip bonding area 113 with second surface 112 and on first surface 111.These the first pin 120a and 120b is set
In on first surface 111, wherein these the first pin 120a and 120b is extended respectively in chip bonding area 113, and these the
Two pins 130 are set on second surface 112.
Chip 140 is set on first surface 111, and in chip bonding area 113.In the present embodiment, chip 140
With the first side 141 corresponding to input terminal 110a and the second side 142 corresponding to output terminal 110b, i.e. first side
141 is relative to each other with second side 142.Chip 140, which also has, to be adjacent to and is set along first side 141 multiple first convex
Block 143 and multiple second convex blocks 144 for being adjacent to and being set along second side 142, and these first convex blocks 143 and these
Second convex block 144 is towards the first surface 111 of flexible film 110.These first pins 120a is passed through under first side 141
Side is simultaneously extended in chip bonding area 113, and is engaged with these first convex blocks 143.These first pins 120a may include letter
Number pin, power pins, grounding pin or dummy convex block, and these first convex blocks 143 may include signal convex block, power supply convex block,
It is grounded convex block or dummy convex block.On the other hand, these first pins 120b passes through the lower section of second side 142 and extends to chip
In bonding land 113, and engaged with these second convex blocks 144.These first pins 120b may include signal pins, grounding pin
Or dummy pin, and these second convex blocks 144 may include signal convex block, ground connection convex block or dummy convex block.
These second pins 130 extend to defeated from inside to outside from 113 orthographic projection of chip bonding area in the region of second surface 112
Enter to hold 110a or output terminal 110b, the present embodiment be with second pin 130 extend to output terminal 110b explain or these
Two pins 130 extend to 113 orthographic projection of chip bonding area in the region of second surface 112 from output terminal 110b, and these
Two pins 130 may include signal pins, grounding pin or dummy pin.As shown in Figure 2 A, patterned metal layer 150 is set to
On two surfaces 112, wherein the material of patterned metal layer 150 can be copper, other applicable metal or alloy, can also draw with second
Foot 130 is formed with phase same material and in same processing procedure, and patterned metal layer 150 is at least partially disposed at chip bonding area 113
In orthographic projection to the region of second surface 112, and patterned metal layer 150 is located at the region for being provided with these second pins 130
Except.In the present embodiment, patterned metal layer 150 includes the first pattern 150a and the second pattern 150b of separation, right respectively
Answer the first convex block 143 and the second partial convex block 144.
Specifically, the position of the first pattern 150a and part the first pin 120a and corresponding the first convex block of part 143
Joint overlapping, the position of the second pattern 150b and part the first pin 120b connect with corresponding the second convex block of part 144
It is overlapped at conjunction, second pin is not provided in support and reinforcement pliability film 110 since patterned metal layer 150 can provide
Structural strength at 130, and the surface flatness of second surface 112 is improved, therefore make the first convex block 143 and the second convex block
During 144 are engaged in the first pin 120a and 120b by way of hot pressing, the situation of unbalance stress is not likely to produce, is had
Help improve the first convex block 143 and the engagement yield of the second convex block 144 and the first pin 120a and 120b.
First pattern 150a can have the first windowing area 151a1 and 151a2 and adjacent first windowing area 151a1 with
The support portion 152a, the second pattern 150b of 151a2 can have the branch of the first windowing area 151b and adjacent first windowing area 151b
Support part 152b, wherein first windowing area 151a1,151a2 and 151b is located at 113 orthographic projection of chip bonding area to the second table respectively
In the region in face 112, and first windowing area 151a1 exposed respectively with 151a2 at least one first pin 120a with it is corresponding
The part of the joint of first convex block 143, and first windowing area 151b expose at least one first pin 120b with it is corresponding
The part of the joint of second convex block 144.On the other hand, support portion 152a and first windowing area 151a1,151a2 is exposed
The first pin 120a overlap with the joint of corresponding first convex block 143, and support portion 152a is at least partially disposed at core
In 113 orthographic projection to the region of second surface 112 of chip bonding area, and what the windowings of support portion 152b and first area 151b was exposed
First pin 120b overlaps with the joint of corresponding second convex block 144, and support portion 152b is at least partially disposed at chip
In 113 orthographic projection to the region of second surface 112 of bonding land.
Since the first pattern 150a and the design principle of the second pattern 150b are substantially similar or identical, below only with regard to the
Two pattern 150b are illustrated.As shown in Fig. 2A to Fig. 2 C, the first windowing area 151b is can expose at least one first
The end end of pin (i.e. in) and an at least corner for corresponding second convex block 144 of pin 120b is principle, and support portion
152b and the first windowing area 151b the first pin 120b exposed and the joint of corresponding second convex block 144 are equitant
Area A2 is to be not less than the 1/3 of the first pin 120b and the area A1 of the joint of corresponding second convex block 144 for principle (i.e.
A2≧1/3A1).Based on this, can not only by the second pattern 150b first windowing area 151b confirm the first pin 120b with it is right
The engagement situation of the second convex block 144 answered also can provide first when pressing by the support portion 152b of the second pattern 150b and draw
Support effect enough with corresponding second convex block 144 foot 120b.
Specifically, the first windowing area 151b is made to expose the end (pin in i.e. of at least one first pin 120b
End) design principle with an at least corner for corresponding second convex block 144, mainly seen for the first windowing area 151b can be passed through
Observe the side (such as long side and short side) of two adjoinings of the second convex block 144 and the side of the two of corresponding first pin 120b adjoinings
The relative position on side (i.e. end and adjacent long side), therefore pin can be judged simultaneously in X and the degrees of offset of Y-direction, with true
Whether the bonding area for recognizing the first pin 120b with corresponding second convex block 144 meets Manufacturing Process.
Please continue to refer to Fig. 1, Fig. 2A and Fig. 3, in the present embodiment, chip 140 also has multiple third convex blocks 145,
Wherein these third convex blocks 145 are adjacent to and are set along second side 142, and these third convex blocks 145 are second convex with these
144 arrangement interlaced with each other of block.In other embodiments, third convex block can be adjacent to and set along the first side of chip
It puts, and third convex block interlaced with each other can also be arranged with the first convex block.Except above-mentioned third convex block can be with the first convex block or the second convex block
Outside staggered embodiment, third convex block also can along a straight line be arranged with the first convex block or the second convex block, and not handed over each other
Mistake arrangement.On the other hand, chip-packaging structure 100 further includes multiple circuits 160 and multiple conduct pieces 170, wherein these circuits
160 quantity is consistent with the quantity of these conduct pieces 170, and each circuit 160 is arranged in pairs, and each other with each conduct piece 170
It is electrically connected.These circuits 160 are set on first surface 111, wherein each circuit 160 is located at least partially within chip engagement
In area 113, and these third convex blocks 145 are individually coupled to these circuits 160.
These conduct pieces 170 can be the conductive through hole that first surface 111 and second surface 112 is connected, and these are conductive
Part 170 is electrically connected respectively with these circuits 160 and these second pins 130.That is, each conduct piece 170 is fallen
Corresponding circuit 160 and 130 overlapping of second pin, the opposite first surface 111 for being located at flexible film 110 respectively is connected
With the circuit 160 of second surface 112 and second pin 130 so that the second pin 130 on second surface 112 electrically connects
It is connected to third convex block 145.On the other hand, due to these third convex blocks 145 and these 144 arrangements interlaced with each other of the second convex block, this
A little first pin 120b correspond respectively to these second convex blocks 144 and set, and these second pins 130 correspond respectively to these
Three convex blocks 145 are set, therefore these the first pin 120b and these 130 arrangements interlaced with each other of second pin.
Other embodiment will be enumerated below using as explanation.It should be noted that, following embodiments continue to use aforementioned reality herein
The element numbers and partial content of example are applied, represent identical or approximate element wherein adopting and being denoted by the same reference numerals, and be omitted
The explanation of same technique content.Explanation about clipped can refer to previous embodiment, and following embodiment will not be repeated herein.
Fig. 5 is the bottom view of the chip-packaging structure of another embodiment of the present invention.Fig. 5 is please referred to, the present embodiment
The difference of the chip-packaging structure 100 of chip-packaging structure 100A and above-described embodiment is：First pattern 150a1 also has the
Two windowing area 153a, the first windowing area 151a1 and the second windowing area 153a is respectively positioned at the opposite sides of support portion 152a, and the
Two windowing area 153a either overlap compared with the first windowing area 151a1 close to first side 141 with first side 141.It is exposed to
It is locally exposed in the same manner as at least one first pin 120a and corresponding first convex block 143 of first windowing area 151a1 opposite
In first windowing area 151a1 setting second windowing area 153a, and second windowing area 153a expose the first pin 120a with it is right
The part of the joint of the first convex block 143 answered.
In the present embodiment, the first windowing area 151a1 exposes the end (end of pin in i.e.) of the first pin 120a
With two corners of the end of corresponding first convex block, 143 closer first pin 120a, and second windowing area 153a expose
Other two corner of aforementioned first convex block 143.It can be observed first by the first windowing area 151a1 and the second windowing area 153a
Four corners of convex block 143 and the end of the first pin 120a, in addition to can determine whether the first pin 120a relative to the first convex block 143
In X and the degrees of offset of Y-direction, it also can determine whether the first pin 120a generates bending or steering, and then can more clearly really
Recognize engagement situations of the first pin 120a with corresponding first convex block 143.In other embodiment, the second windowing area 153a can
Can have there are two the second windowing area 153a corresponding to the first windowing area 151a2 settings or the first pattern 150a1, it is and aforementioned
Two second windowing area 153a correspond respectively to the first windowing area 151a1 and 151a2 and set.
On the other hand, the second pattern 150b1 also has the second windowing area 153b, wherein the second windowing area 153b corresponds to the
One windowing area 151b settings, and the first windowing area 151b and the second windowing area 153b are respectively positioned at opposite the two of support portion 152b
Side, and the second windowing area 153b either overlaps compared with the first windowing area 151b close to second side 142 with second side 142.
The first windowing area 151b of wherein the second pattern 150b1 opens a window area 153b and its at least one first drawing of being exposed with second
Foot 120b can refer to the related description of above-mentioned first pattern 150a1 with the position relationship of corresponding second convex block 144, in this no longer
It repeats.
Fig. 6 is the bottom view of the chip-packaging structure of further embodiment of this invention.Fig. 6 is please referred to, the present embodiment
The difference of the chip-packaging structure 100 of chip-packaging structure 100B and above-described embodiment is：The figure of chip-packaging structure 100B
Case metal layer 150c is the whole piece pattern for being laid on second surface 112 and being connected, and is covered in and is provided with second pin
Except 130 region.Specifically, patterned metal layer 150c can have windowing area 151c~151f, wherein windowing area 151c
~151f is located in 113 orthographic projection to the region of second surface 112 of chip bonding area.Windowing area 151c and 151d exposes respectively
The part of at least one first pin 120a and the joint of corresponding first convex block 143, windowing area 151f expose first and draw
The part of foot 120b and the joint of corresponding second convex block 144, wherein second windowing area's 153a phases of windowing area 151e and Fig. 5
Seemingly.The area 151e and area 151d that opens a window that opens a window is located at the opposite sides of support portion 152c, windowing area 151e relatively windowing area 151d respectively
It either overlaps close to first side 141 with first side 141, and the area 151e that opens a window exposes windowing area 151d and exposed
The first pin 120a and the part of the joint of corresponding first convex block 143.The windowing area 151c~151f of the present embodiment and
Its first pin 120a, 120b exposed can refer to the position relationship of corresponding first convex block 143, the second convex block 144
Related description in above-described embodiment, repeats no more in this.
Since occupied areas of the patterned metal layer 150c on second surface 112 is larger, second surface is significantly increased
112 surface flatness, therefore can be in first pin 120a, 120a of pressing and corresponding first convex block 143, the second convex block 144
When significantly more support effectiveness is provided, reduces the amount of warpage of chip-packaging structure 100B, and increase heat dissipation effect.The opposing party
Face, windowing area 151c~151f can be used to confirm the first pin 120a and corresponding first convex block, 143 and first pin 120b and
The engagement situation of corresponding second convex block 144.
In conclusion the chip-packaging structure of the present invention is in setting the first pin on the first surface of flexible film, and
In setting second pin on the second surface relative to first surface.Chip is set on first surface and passes through convex block and first
Pin corresponds to engagement, separately in being provided with patterned metal layer on second surface using as support construction, wherein patterned metal layer
Position and the first pin of part it is Chong Die with the joint of the first convex block or the second convex block.In general, patterned metal layer meeting
Positioned at being provided with except the region of second pin, particularly larger block is not provided with the region of second pin.Pass through patterning
The structural strength being not provided on metal layer reinforcement pliability film at second pin, and the surface for improving second surface is flat
Degree.Therefore, it when the first convex block on chip and the second convex block are engaged with the first pin with pressing mode, can avoid because of the first table
The situation of unbalance stress is unevenly distributed and caused with the metal (the first pin and second pin) on second surface on face, is helped
In the first convex block of raising or the engagement yield of the second convex block and the first pin.On the other hand, patterned metal layer can have at least
One windowing area, to judge degrees of offset of first pin relative to the first convex block or the second convex block, with confirm the first convex block or
Whether the engagement situation of the second convex block and the first pin meets Manufacturing Process.
Although the present invention is disclosed as above with embodiment, however, it is not to limit the invention, any technical field
Technical staff, without departing from the spirit and scope of the present invention, when can make a little change with retouching, therefore the present invention protection model
It encloses subject to ought being defined depending on claims.
Claims (10)
1. a kind of chip-packaging structure, which is characterized in that including：
Flexible film has first surface, relative to the second surface of the first surface and positioned at the first surface
On chip bonding area；
Multiple first pins, are set on the first surface, and extend in the chip bonding area；
Multiple second pins are set on the second surface；
Chip is set in the chip bonding area on the first surface, wherein the chip has first side, opposite
In the second side of the first side, multiple first convex blocks and multiple second convex blocks, the multiple first convex block is adjacent to
And set along the first side, and the multiple second convex block is adjacent to and is set along the second side, it is described more
Correspondence is engaged in the multiple first convex block and the multiple second convex block to a first pin respectively；And
Patterned metal layer is set on the second surface, the position of the patterned metal layer and part the multiple the
One pin is Chong Die with the joint of the multiple first convex block or the multiple second convex block, wherein the patterned metal layer has
There is the support portion in the first windowing area and the adjacent first windowing area, the first windowing area exposes the multiple first pin
It is at least one with corresponding first convex block or the part of the joint of second convex block, and the support portion with it is described
At least one and corresponding first convex block or described second of the multiple first pin that first windowing area is exposed
The joint of convex block overlaps.
2. chip-packaging structure according to claim 1, which is characterized in that the patterned metal layer also has second to open
Window area, the first windowing area is located at the opposite sides of the support portion with the described second windowing area respectively, and described second opens
Window area exposes at least one with corresponding described first of the multiple first pin that is exposed of the first windowing area
The part of the joint of convex block or second convex block.
3. chip-packaging structure according to claim 2, which is characterized in that the first windowing area exposes the multiple
An at least corner, and described at least one end of first pin and corresponding first convex block or second convex block
Second windowing area exposes at least another corner of first convex block or second convex block.
4. chip-packaging structure according to claim 1, which is characterized in that the multiple second pin extends to the core
Chip bonding area is projected in the region of the second surface.
5. chip-packaging structure according to claim 4, which is characterized in that the patterned metal layer has been located at setting
Except the region for stating multiple second pins.
6. chip-packaging structure according to claim 1, which is characterized in that the chip also has multiple third convex blocks,
And the multiple third convex block is adjacent to the first side or second side setting.
7. chip-packaging structure according to claim 6, which is characterized in that further include：
Multiple circuits are set on the first surface, and each circuit is located at least partially in the chip bonding area, and
The multiple third convex block is individually coupled to the multiple circuit；And
Multiple conduct pieces, are connected the first surface and the second surface, and the multiple conduct piece respectively with it is the multiple
Circuit and the multiple second pin are electrically connected.
8. chip-packaging structure according to claim 6, which is characterized in that the multiple third convex block be adjacent to and along
Second side setting, and with the multiple second convex block arrangement interlaced with each other, and be engaged in the multiple second convex block
The multiple first pin and the arrangement interlaced with each other of the multiple second pin.
9. chip-packaging structure according to claim 1, which is characterized in that the first windowing area exposes the multiple
An at least corner at least one end of first pin and corresponding first convex block or second convex block.
10. chip-packaging structure according to claim 1, which is characterized in that the support portion and the described first windowing area
At least one engagement with corresponding first convex block or second convex block of the multiple first pin exposed
Locate at least one and corresponding first convex block or described second that equitant area is not less than the multiple first pin
The 1/3 of the area of the joint of convex block.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW105141562 | 2016-12-15 | ||
| TW105141562A TWI596729B (en) | 2016-12-15 | 2016-12-15 | Chip package structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108231715A true CN108231715A (en) | 2018-06-29 |
| CN108231715B CN108231715B (en) | 2019-10-11 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710127732.0A Active CN108231715B (en) | 2016-12-15 | 2017-03-06 | Chip packaging structure |
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| Country | Link |
|---|---|
| CN (1) | CN108231715B (en) |
| TW (1) | TWI596729B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111755394A (en) * | 2019-03-27 | 2020-10-09 | 奇景光电股份有限公司 | Flip chip package |
| CN113517252A (en) * | 2020-04-09 | 2021-10-19 | 南茂科技股份有限公司 | Thin film flip chip packaging structure |
| CN113540010A (en) * | 2020-04-16 | 2021-10-22 | 南茂科技股份有限公司 | Thin film flip chip packaging structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI673845B (en) * | 2018-04-19 | 2019-10-01 | 南茂科技股份有限公司 | Chip-on-film package structure |
| TWI804103B (en) * | 2021-12-14 | 2023-06-01 | 南茂科技股份有限公司 | Chip on film package structure |
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| CN113540010B (en) * | 2020-04-16 | 2024-07-16 | 南茂科技股份有限公司 | Thin film flip chip package structure |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201824485A (en) | 2018-07-01 |
| TWI596729B (en) | 2017-08-21 |
| CN108231715B (en) | 2019-10-11 |
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