TWI594264B - Array structure having local decoders - Google Patents

Description

Array architecture with region decoder

The present invention relates to an array architecture having a region decoder.

An array architecture, such as a memory array in a memory device, typically includes a plurality of array elements, a plurality of bit lines, a plurality of source lines, and a plurality of word lines. The array unit, such as a memory cell, may be located at the intersection of the word line and the bit line.

One of the efforts is how to select/decode the array architecture with a simple architecture to reduce circuit area and slow down RC latency.

SUMMARY OF THE INVENTION The present invention is directed to an array architecture having a region decoder that is also selected when associated word lines are selected, so that no additional decoding control/selection circuitry is required.

According to an embodiment of the present invention, an array architecture is provided, including: a plurality of first signal lines; and a plurality of sub-arrays sharing the first signal lines. Each of the sub-arrays includes: a second signal line; a plurality of third signal lines; a plurality of fourth signal lines; and a plurality of area decoders located at the first signal lines, the second signal lines, and the third signals Each intersection of the lines; and a plurality of array elements located at the The intersections of the first signal lines, the third signal lines, and the fourth signal lines. The individual control terminals of the area decoders are composed of the first signal lines. In response to the selection of one of the first signal line and the second signal line, one of the regional decoders selects one of the third signal lines.

According to another embodiment of the present invention, an array architecture is provided, including: a plurality of first signal lines, each of the first signal lines running through the array structure in a first direction; and a plurality of second signal lines, each of the plurality The second signal line runs through the array structure in a second direction; a plurality of third signal lines, each of the third signal lines extending in the first direction but not extending through the array structure; and a plurality of fourth signal lines extending In the second direction, a plurality of area decoders are located at intersections of the first signal lines, the second signal lines, and the third signal lines; and a plurality of array units are located at the first a intersection of the signal line, the third signal line, and the fourth signal lines. The first signal lines control whether the area decoders are turned on. The area decoders decode a voltage application condition of the first signal lines and the second signal lines to select one of the third signal lines.

In order to provide a better understanding of the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings

Figure 1

100‧‧‧Array Architecture

110-130‧‧‧Subarray

C1-CNM‧‧‧Array unit

CSL1-CSL3‧‧‧Common source line

WL1-WL2N‧‧‧ character line

LSL1-LSL3N‧‧‧ regional source line

LD1-LD3N‧‧‧ area decoder

BL1-BL3M‧‧‧ bit line

3A, 3B

MOS1, MOS2‧‧‧ transistor

D1, D2‧‧‧汲 contact

S1‧‧‧ source contact

L‧‧‧Diffusion layer

I‧‧‧current

4A, 4B

MOS3, MOS4‧‧‧ transistor

L’‧‧‧ diffusion layer

D3, D4‧‧‧汲 contact

S2‧‧‧ source contact

Figure 1 shows a schematic diagram of an array architecture in accordance with an embodiment of the present invention.

2A and 2B are diagrams showing decoding/selection of a sub-array of an array architecture in accordance with an embodiment of the present invention.

3A and 3B are diagrams showing a layout and an equivalent circuit diagram of a region decoder according to an embodiment of the present invention.

4A and 4B are diagrams showing a layout and an equivalent circuit diagram of an array unit according to an embodiment of the present invention.

The technical terms of the present specification refer to the idioms in the technical field, and some of the terms are explained or defined in the specification, and the explanation of the terms is based on the description or definition of the specification.

Reference is now made to Fig. 1, which shows a schematic diagram of an array architecture in accordance with an embodiment of the present invention. As shown in FIG. 1, the array architecture 100 includes a plurality of array elements C1-CNM (both N and M are positive integers), a plurality of common source lines CSL1-CSL3, and a plurality of word lines WL1- WL2N, a plurality of local source lines (LSL1-LSL3N), a plurality of local decoders (Local Decoder) LD1-LD3N, and a plurality of bit lines BL1-BL3M.

The array unit is located at the intersection of the bit line and the word line. For example, the array cell C1 is located at the intersection of the bit line BL1 and the word line WL1-WL2.

The bit lines BL1-BL3M extend through the entire array structure 100 from the vertical direction of FIG. 1, and the word lines WL1-WL2N penetrate the entire array structure 100 from the horizontal direction of FIG. In addition, although the regional source lines LSL1-LSL3N penetrate through the corresponding sub-array, they do not extend through the entire array structure. For example, the regional source line LSL1 runs through the first sub-array 110, the regional source line LSLN+1 passes through the second sub-array 120, the regional source line LSL2N+1 runs through the third sub-array 130, and the regional source line LSL1 Disconnected from the regional source line LSLN+1 and the regional source line LSL2N+1.

Please note that FIG. 1 illustrates the example in which the array architecture 100 includes three sub-arrays 110-130, and the present invention is not limited thereto. The array architecture may include more or fewer sub-arrays, which is still within the spirit of the present case.

The word lines WL1-WL2N of the array architecture 100 are shared by the three sub-arrays 110-130, and each sub-array 110-130 includes: a common source line, a region decoder, a region source line, a bit line and Array unit.

The area decoders LD1-LD3N are located at the intersection of the common source line, the word line, and the area source line. For example, the region decoder LD1 is located at the intersection of the common source line CLS1, the word line WL1-WL2, and the area source line LSL1.

Referring now to Figures 2A and 2B, there is shown a schematic diagram of decoding/selecting a sub-array of an array architecture in accordance with an embodiment of the present invention. It is assumed here that the first sub-array is decoded/selected. As shown in FIG. 2A, when an array unit (such as a memory cell) on the word line WL8 is to be selected, a word line voltage V _{WL is} applied to the word line WL8 and applied to the associated common source line CSL1. High voltage VS. Such a bias voltage will cause the region decoder associated with word line WL8 to be turned on (but the remaining region decoders are not turned on), and current I can flow from the common source line CSL1 through the region decoder to the associated region source line. LSL4, as shown in Figure 2B.

Referring now to Figures 3A and 3B, there are shown layout and equivalent circuit diagrams of a region decoder in accordance with an embodiment of the present invention. As shown in FIG. 3A, the region decoder includes two switches (such as, but not limited to, a transistor). For convenience of explanation, the regional decoder includes two transistors MOS1 and MOS2 as an example. The gate of the transistor MOS1 is a word line (for example, the word line WL8), and the gate of the transistor MOS2 is another word line (for example, the word line WL7). That is, in the process, the gate of the transistor of the word line and the area decoder is simultaneously completed by the same process, that is, the word line can be regarded as the gate of the transistor of the area decoder (control) end). The drain contact D1 of the transistor MOS1 can be electrically connected to the common source line (for example, CSL1); and the gate contact D2 of the transistor MOS2 can be electrically connected to the same common source line. (for example, CSL1). That is to say, through the common source line, the gate contact D1 of the transistor MOS1 can be electrically connected to the gate contact D2 of the transistor MOS2. The transistors MOS1 and MOS2 share the source contact S1, wherein the common source contact S1 of the transistors MOS1 and MOS2 can be electrically connected to the regional source line (for example, LSL4). Reference symbol L is a diffusion region of the transistors MOS1 and MOS2.

The common source line is, for example but not limited to, a metal line or a diffusion layer such as an N+ germanium (Si) diffusion layer. Similarly, the regional source line can be formed, for example, but not limited to, by a metal line or a diffusion layer.

If the common source line and the area source line are formed by a metal layer, the common source line may be located in the first layer, and the area source line may be located in the second layer, and other layers may be used as a jump if necessary. For the use of the line.

The operation of the area decoder will now be explained. As shown in FIGS. 3A and 3B, since the common source line CSL1 is applied with the high voltage VS and the word line WL8 is also applied with the high voltage V _WL , the transistor MOS1 can be turned on. On the other hand, since the common source line CSL1 is applied with the high voltage VS, but the word line WL7 is applied with 0 V, the transistor MOS 2 is turned off. Since the transistor MOS1 is turned on, the current I flows from the common source line CSL1 to the region source line LSL4. When the word line is turned on, the corresponding area decoder is also turned on to select the corresponding area source line. In the embodiment of the present invention, the area source line and the array unit thereon can be selected by the area decoder without additional control/selection/decoding circuitry. Therefore, the embodiment of the invention can reduce the circuit area and has the advantages of simple structure.

Referring now to FIGS. 4A and 4B, there are shown layout and equivalent circuit diagrams of an array unit in accordance with an embodiment of the present invention. For convenience of explanation, FIGS. 4A and 4B illustrate an array unit located on the word lines WL7 and WL8 as an example. As shown in FIGS. 4A and 4B, the array unit may include two switches, such as but not limited to two transistors MOS3 and MOS4. The gate (control terminal) of the transistor MOS3 is a word line (for example, the word line WL8), and the gate of the transistor MOS4 is another word line (for example, the word line WL7). That is, in the process, the gates of the transistor of the word line and the array unit are simultaneously completed by the same process, that is, the word line can be regarded as the gate of the transistor of the array unit. The gate contact D3 of the transistor MOS3 can be electrically connected to the bit line (for example, BL1); and the gate contact D4 of the transistor MOS4 can be electrically connected to the same bit line (for example, BL1). That is to say, through the bit line, the gate contact D3 of the transistor MOS3 can be electrically connected to the gate contact D4 of the transistor MOS4. The transistor MOS3 and the MOS4 share the source contact S2, wherein the common source contact S2 of the transistor MOS3 and the MOS4 can be electrically connected to the regional source line (for example, LSL4). Source of the array unit The contact S2 and the drain contacts D3 and D4 form a diffusion layer L'.

The source contact S2 of the array unit is connected to the diffusion layer L' and the regional source line; the drain contacts D3 and D4 are connected to the diffusion layer L' and the bit line.

The operation of the array unit will now be explained. As shown in Figures 4A and 4B, if the selected array unit is to be reset or read, the selected common source line (e.g., CSL1) is applied with 0V (but the unselected common source line). (such as CSL2 and CSL3) is also applied 0V), the selected bit line (such as bit line BL1) is to be applied with a high voltage (but the unselected bit line is grounded), and the selected word line WL8 The high voltage V _WL is also applied, so the transistor MOS3 can be turned on. On the other hand, the selected bit line (e.g., bit line BL1) is to be applied with a high voltage VD, but the unselected word line WL7 is applied with 0 V, so that the transistor MOS 4 is turned off. Via such a bias method, the transistor MOS3 located at the intersection of the word line WL8 and the bit line BL1 can be selected.

If the setting is made (current is flowed back from the regional source line to the bit line), in the embodiment of the invention, the selected common source line (eg CSL1) is applied with a high voltage VS (but not the common source) The epipolar lines (such as CSL2 and CSL3) are applied with 0V), and the selected bit line (such as bit line BL1) is to be applied with 0V, but is located in the same sub-array as the common source line (for example, CSL1). The remaining unselected bit lines are applied with a high voltage VS to prevent the transistors on the unselected bit lines from being turned on. The bit lines of other sub-arrays that are not selected (such as the sub-array in which CSL2 and CSL3 are located) are applied with 0V. The selected word line WL8 is also applied with the high voltage V _WL , so the transistor MOS3 can be turned on. On the other hand, the selected bit line (e.g., bit line BL1) is to be applied with 0V, but the unselected word line WL7 is applied with 0V, so that the transistor MOS4 is turned off. Via such a bias voltage method, the transistor MOS3 located at the intersection of the word line WL8 and the bit line BL1 can be selected to allow current to flow from the area source line back to the bit line to complete the setting operation.

In the embodiment of the present invention, the area decoder and the array unit can reduce the circuit area if a twin cell layout is applied, because the dual unit layout can share the source contact.

In the embodiment of the present invention, since the source line is divided into a plurality of shorter region source lines, the length of the source lines of each region is shorter. Therefore, the resistance value of the regional source line can be reduced, thereby slowing down the RC delay problem. In addition, because the resistance value of the source line of the region is low, the voltage drop on the source line of the region can also be lowered, so that the body effect is lowered. Therefore, the negative influence on the gate-source voltage VGS of the transistor is less, and further has less negative influence on the on current of the transistor.

In the embodiment of the present invention, a plurality of array units share the same area decoder, so that the number of area decoders is small, which can reduce circuit area and circuit cost.

In the embodiment of the present invention, since the effective capacitance value of the regional source line is also lowered, the RC delay problem can be further reduced.

In the current technology, when the setting operation is performed to allow current to flow back from the source line of the entire array structure back to the bit line, all unselected bit lines must be applied except that the selected bit line is applied with 0V. The bias voltage is high to avoid conduction of the transistor on the unselected bit line. In this case, the total leakage current of all unselected transistors is very impressive.

Conversely, in an embodiment of the invention, the entire array architecture is partitioned into multiple sub-arrays. When a set operation is performed to allow current to flow back from the (region) source line back to the bit line, a common source line of the selected sub-array applies a high voltage while a common source line of the other unselected sub-arrays can apply 0V. Except that 0V is applied to the selected bit line of the selected sub-array, all unselected bit lines of the selected sub-array must also be biased at a high potential, but all bit lines of the remaining unselected sub-arrays can be applied with 0V. Just fine. That is, the number of unselected bit lines biased at a high potential in the embodiment of the present invention is, for example, only about 1/3 of the unselected bit line biased at a high potential in the prior art (if An array architecture is split into 3 sub-arrays). Therefore, in the embodiment of the present invention, the total leakage current of the unselected transistor is much reduced (about 1/3 or so) compared with the prior art. It is thus known that the embodiments of the present invention can effectively reduce the occurrence of leakage current and also reduce power loss.

In an embodiment of the invention, if the array architecture is applied to a memory device, the array architecture may be, for example but not limited to, a NOR type memory array. The array unit is, for example but not limited to, a floating-gate memory unit, a charging trapping memory unit, a ferroelectric memory unit, and a resistance change memory. Body unit (for example, phase change memory unit, resistive memory unit, magnetic memory).

In the embodiment of the present invention, the transistor used in the array unit is, for example but not limited to, an NMOS transistor, a PMOS transistor, an NPN BJT (Bipolar Junction Transistor), a PNP BJT, or other types. The transistor.

Although the above embodiment of the present invention has been described as being applied to a memory device, the present invention is not limited thereto. The invention is applicable to any application having an array architecture. For example, the array architecture of the embodiments of the present invention can also be applied to a light sensor array, which can be applied to image processing. When the array architecture of the embodiment of the present invention is applied to a light sensor array, the light sensor can be regarded as an array unit, and a plurality of light sensors can be arranged in an array structure. The light sensor to be read can be selected by the area decoder, the details of which are as described above, and will not be repeated here. This is also within the spirit of the invention.

In other possible embodiments of the present invention, the array architecture can also be regarded as a light source array architecture, and the light source unit is regarded as an array unit. The light source unit to be illuminated can be selected by using the area decoder, the details of which are as described above, and will not be repeated here. This is also within the spirit of the invention.

In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100‧‧‧Array Architecture

110-130‧‧‧Subarray

C1-CNM‧‧‧Array unit

CSL1-CSL3‧‧‧Common source line

WL1-WL2N‧‧‧ character line

LSL1-LSL3N‧‧‧ regional source line

LD1-LD3N‧‧‧ area decoder

BL1-BL3M‧‧‧ bit line

Claims (11)

An array structure includes: a plurality of first signal lines; and a plurality of sub-arrays sharing the first signal lines, each sub-array comprising: a second signal line; a plurality of third signal lines; and a plurality of fourth signal lines a plurality of area decoders located at intersections of the first signal lines, the second signal lines, and the third signal lines, wherein each of the area decoders is at least two of the first signal lines The first signal lines are shared by the strips; and a plurality of array units are located at intersections of the first signal lines, the third signal lines, and the fourth signal lines; wherein individual control of the area decoders The terminal is formed by the first signal lines, and by controlling a plurality of signals applied to the first signal lines and controlling a signal applied to the second signal line, one of the area decoders is controlled to Select one of the third signal lines. The array structure of claim 1, wherein the first signal lines are a plurality of word lines, the word lines are extending through the array structure; and the second signal lines are a common source line; The third signal lines are a plurality of regional source lines; The fourth signal lines are a plurality of bit lines. The array architecture of claim 1, wherein, in response to the one of the first signal lines and the second signal line being selected, one of the area decoders is turned on by a corresponding area decoder to Select the selected third signal line. The array architecture of claim 1, wherein each of the area decoders includes a plurality of switches, the switches sharing a first contact, and the switches are located at the second signal line and the first signal lines An intersection of an associated first signal line, and responsive to one of the first signal lines being selected, one of the switches is turned on and the remaining switches are turned off to select the second signal line One of the currents is directed to one of the selected third signal lines. The array structure of claim 4, wherein each of the switches comprises: the first contact, a second contact and the control end, the second contact is electrically connected to the second signal a second signal line, the second contacts of the switches are electrically connected to each other; and the first contact is electrically connected to one of the third signal lines and the third signal line. The array structure of claim 1, wherein the second signal line is formed by a metal line or a diffusion layer; and each of the third signal lines is formed by a metal line or a diffusion layer. An array structure includes: a plurality of first signal lines, each of the first signal lines running through the array structure in a first direction; a plurality of second signal lines, each of the second signal lines running through a second direction The array structure; the plurality of third signal lines, each of the third signal lines extending in the first direction but not extending through the array structure; the plurality of fourth signal lines extending in the second direction; the plurality of regions a decoder, located at each of the first signal lines, the second signal lines, and the third signal lines, wherein each of the area decoders is first by at least two of the first signal lines The signal lines are shared; and a plurality of array units are located at intersections of the first signal lines, the third signal lines, and the fourth signal lines; wherein the first signal lines control the area decoding Whether the device is turned on, and the area decoders decode the voltage application of the first signal line and the second signal lines to select one of the third signal lines. The array structure of claim 7, wherein the first signal lines form an individual control end of the area decoders; the first signal lines are a plurality of word lines; the second signals The line is a plurality of common source lines; the third signal lines are a plurality of regional source lines; The fourth signal lines are a plurality of bit lines. The array architecture of claim 7, wherein one of the first signal lines and one of the second signal lines are selected, and one of the area decoders is corresponding to the area decoder Turn on to select the selected third signal line. The array architecture of claim 7, wherein each of the area decoders comprises a plurality of switches, the switches sharing a first contact, and each switch is located at one of the second signal lines and associated with the second signal line. Intersection with the first signal line associated with one of the first signal lines, and responsive to one of the first signal lines being selected, coupled to one of the switches of the selected one of the first signal lines The other switches are turned on to turn the current of one of the selected second signal lines to the selected third signal line. The array structure of claim 10, wherein each of the switches comprises: the first contact, a second contact and the control end, the second contact is electrically connected to the second signal a second signal line, the second contacts of the switches are electrically connected to each other; and the first contact is electrically connected to one of the third signal lines and the third signal line.