TWI593109B - Semiconductor device - Google Patents

Description

Semiconductor device

The present disclosure relates to semiconductor devices, and more particularly to a junction field effect transistor.

A power supply is required for any integrated circuit to operate, but the external power supply may not fully comply with the voltage required for the operation of the integrated circuit, so voltage conversion is required. The voltage conversion conversion circuit requires a starting component to allow the power supply to be introduced to allow the voltage conversion circuit to operate. Among them, the junction field effect transistor (JFET) is a useful starting element.

The junction field effect transistor mainly changes the electric field near the carrier channel by controlling the signal (the voltage of the gate), causing the channel characteristics to change, resulting in a change in current (between the source and the drain). The field effect transistor can be used as a voltage controlled variable resistor or voltage controlled current source (VCCS). The working principle of the junction field effect transistor (JFET) is mainly to utilize the width of the depletion region between the gate and the source/drain between the PN junctions as a function of the reverse bias to change the channel by changing the width of the depletion region. width.

In the junction field effect transistor, when a voltage is applied to the drain and the depletion region of the PN junction becomes large, the thickness of the channel becomes small. When the buckling voltage is as large as a critical value, part of the depletion region will be wide enough to make the channel completely disappear. At this time, the channel is said to be pinch off, the resistance value becomes large, and the gate voltage value at this time is called Pinch-off voltage.

However, although semiconductor devices such as junction field effect transistors have been applied in various aspects, current semiconductor devices (e.g., junction field effect transistors) are not satisfactory in all respects. Therefore, the industry still needs a semiconductor device that can further increase the application range of the system voltage (VDD) and increase the voltage operating range of the output voltage (Vout).

The present disclosure provides a semiconductor device including: a substrate; a source region and a drain region disposed in the substrate; and a first conductive type doped region disposed in the substrate and disposed between the source region and the drain region The region between the source region and the drain region is divided into a first sub-region adjacent to the drain region and a second sub-region adjacent to the source region, and the first conductive type doped region in the first sub-region The first conductivity type dopant is more than the first conductivity type dopant in the first conductivity type doping region; the second gate region is disposed in the substrate and is disposed in the first conductivity type The two sides of the impurity region; and the second conductive type channel region are disposed in the substrate, wherein the second conductive type channel region is disposed between the source region and the drain region, and is disposed between the two gate regions, wherein The first conductivity type is different from the second conductivity type.

In order to make the features and advantages of the present disclosure more comprehensible, the preferred embodiments are described below, and are described in detail below with reference to the accompanying drawings.

100‧‧‧Semiconductor device

102‧‧‧Substrate

104‧‧‧Second Conductive Well Area

106‧‧‧First Conductive Well Area

108‧‧‧ source area

108S1‧‧‧ edge

108S2‧‧‧ edge

110‧‧‧Bungee Area

Edge of 110S1‧‧

Edge of 110S2‧‧

112‧‧‧First Conductive Doped Area

112S1‧‧‧ first side

112S2‧‧‧ second side

112A‧‧‧Area

112B‧‧‧Area

112C‧‧‧Area

112D‧‧‧Area

114A‧‧‧Gate

114B‧‧‧The gate area

116‧‧‧ Vacant Zone

118‧‧‧Protective layer

120‧‧‧Area

120A‧‧‧First subregion

120B‧‧‧Second subregion

120S1‧‧‧ edge

120S2‧‧‧ edge

120S3‧‧‧ edge

120L‧‧‧ center line

200‧‧‧Semiconductor device

300‧‧‧Semiconductor device

400A‧‧‧Semiconductor device

400B‧‧‧Semiconductor device

400C‧‧‧Semiconductor device

D1‧‧‧ distance

D2‧‧‧ distance

D3‧‧‧ distance

A1‧‧ Direction

A2‧‧‧ direction

I‧‧‧ current path

1B-1B’‧‧‧ segment

2B-2B’‧‧‧ segment

3B-3B’‧‧‧ Segment

Figure 1A is a top plan view of a semiconductor device in accordance with some embodiments.

Fig. 1B is a cross-sectional view taken along line 1B-1B' of Fig. 1A.

2A is a top view of a semiconductor device in accordance with still other embodiments.

Fig. 2B is a cross-sectional view taken along line 2B-2B' of Fig. 2A.

Figure 3A is a top plan view of a semiconductor device in accordance with still other embodiments.

Fig. 3B is a cross-sectional view taken along line 3B-3B' of Fig. 3A.

4A is a top plan view of a semiconductor device in accordance with still other embodiments.

4B is a top view of a semiconductor device in accordance with still other embodiments.

Figure 4C is a top plan view of a semiconductor device in accordance with still other embodiments.

The semiconductor device of the present disclosure will be described in detail below. It will be appreciated that the following description provides many different embodiments or examples for implementing the various aspects of the disclosure. The specific elements and arrangements described below are merely illustrative of the disclosure. Of course, these are only used as examples and not as a limitation of the disclosure. Moreover, repeated numbers or labels may be used in different embodiments. These repetitions are merely for the purpose of simplicity and clarity of the disclosure, and are not intended to be a limitation of the various embodiments and/or structures discussed. Furthermore, when a first material layer is on or above a second material layer, the first material layer is in direct contact with the second material layer. Alternatively, it is also possible to have one or more layers of other materials interposed, in which case there may be no direct contact between the first layer of material and the second layer of material.

It must be understood that the elements or devices of the drawings may be in various forms well known to those skilled in the art. In addition, when a layer is "on" another layer or substrate, it may mean "directly" on another layer or substrate, or a layer on another layer or substrate, or between other layers or substrates. Other layers.

In addition, relative terms such as "lower" or "bottom" and "higher" or "top" may be used in the embodiments to describe the relative relationship of one element of the drawing to another. It can be understood that if the device of the figure is to be If you flip it upside down, the component described on the "lower" side will become the component on the "higher" side.

Here, the terms "about", "about" and "major" generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or 3 Within %, or within 2%, or within 1%, or within 0.5%. The quantity given here is an approximate quantity, that is, in the absence of specific descriptions of "about", "about" and "major", the meanings of "about", "about" and "major" may still be implied.

It will be understood that the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and/or portions, such elements, components, and regions. The layers, and/or portions are not to be limited by the terms, and the terms are used to distinguish different elements, components, regions, layers, and/or parts. Therefore, a first element, component, region, layer, and/or portion discussed below may be referred to as a second element, component, region, layer, and/or without departing from the teachings of the disclosure. section.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning meaning It will be understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the relevant art and the context or context of the present disclosure, and should not be in an idealized or overly formal manner. Interpretation, unless specifically defined herein.

The embodiments of the present disclosure can be understood in conjunction with the drawings, and the drawings of the present disclosure are also considered as part of the disclosure. It should be understood that the drawings of the present disclosure are not shown in the form of actual devices and components. The shapes and thicknesses of the embodiments may be exaggerated in the drawings in order to clearly illustrate the features of the present disclosure. In addition, the knot in the drawing The device and the device are shown in a schematic manner to clearly illustrate the features of the present disclosure.

In this disclosure, relative terms such as "lower", "upper", "horizontal", "vertical", "lower", "above", "top", "bottom", etc. shall be understood as The orientation shown in the paragraph and related schemas. This relative term is used for convenience of description only, and does not mean that the device described therein is to be manufactured or operated in a particular orientation. Terms such as "joining" and "interconnecting", etc., unless otherwise defined, may mean that two structures are in direct contact, or that two structures are not in direct contact, and other structures are provided here. Between the two structures. The term "joining and joining" may also include the case where both structures are movable or both structures are fixed.

It should be noted that the term "substrate" may be used hereinafter to include formed elements on a semiconductor wafer and various film layers overlying the wafer, and any desired semiconductor elements may have been formed thereon, but here Simplified drawing, represented only by a flat substrate. In addition, the "substrate surface" includes the uppermost and exposed film layer on the semiconductor wafer, such as a germanium surface, an insulating layer, and/or metal lines.

The embodiment of the present disclosure is to make the first conductive type doped region disposed between the source region and the drain region different from the source region and the drain region, or/and to make the first conductive The doped region has a gradually changing doping concentration such that the first conductive region in the region between the source region and the drain region is closer to the portion of the drain region (ie, the subsequent first sub-region) The number of first conductivity type dopants in the doped region is greater than the number of first conductivity type dopants in the first conductivity type doped region in the portion closer to the source region (ie, the subsequent second subregion) Jam the device The absolute value of the pinch-off voltage is smaller than the absolute value of the cut-off voltage, and can further increase the application range of the system voltage (VDD) of the semiconductor device and make its output voltage (Vout) The voltage operating range becomes larger, increasing the performance of the device.

First, referring to Figs. 1A-1B, Fig. 1A is a top view of a semiconductor device 100 of some embodiments, and Fig. 1B is a cross-sectional view taken along line 1B-1B' of Fig. 1A. In some embodiments of the present disclosure, the semiconductor device 100 can include a junction field effect transistor (JFET) or any other suitable semiconductor device.

As shown in FIGS. 1A-1B, the semiconductor device 100 includes a substrate 102. This substrate 102 can be a semiconductor substrate, such as a germanium substrate. In addition, the semiconductor substrate may also be an elemental semiconductor, including germanium; a compound semiconductor including gallium nitride (GaN), silicon carbide, gallium arsenide, gallium phosphide ( Gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide; alloy semiconductors including bismuth alloy (SiGe), phosphorus gallium arsenide (GaAsP), arsenic Aluminum indium alloy (AlInAs), arsenic aluminum gallium alloy (AlGaAs), arsenic gallium alloy (GaInAs), indium gallium alloy (GaInP) and/or phosphorus indium gallium alloy (GaInAsP) or a combination thereof. Further, the substrate 102 may be a semiconductor on insulator. In an embodiment, the substrate 102 can be a lightly doped first conductivity type substrate. For example, in some embodiments of the present disclosure, the substrate 102 can be a lightly doped P-type substrate.

In the embodiment, "lightly doped" means a doping concentration of 10 ¹² -10 ¹⁵ /cm ³ , for example, a doping concentration of 10 ¹³ /cm ³ . However, it will be appreciated by those of ordinary skill in the art that the definition of "lightly doped" can also be determined by the particular device type, technology generation, minimum component size, and the like. Thus, the definition of "lightly doped" is re-evaluated as visual technology content and is not limited by the embodiments presented herein.

Continuing to refer to FIGS. 1A-1B, semiconductor device 100 includes a second conductivity type well region 104 disposed in substrate 102. This first conductivity type is different from the second conductivity type. This second conductivity type well region 104 can be formed by an ion implantation step. For example, when the second conductivity type is N-type, phosphorus ions or arsenic ions may be implanted in a region where the second conductivity type well region 104 is to be formed to form the second conductivity type well region 104.

Continuing to refer to FIG. 1A, the semiconductor device 100 further includes a first conductive well region 106 disposed in the substrate 102 and surrounding the second conductive well region 104. This first conductivity type well region 106 can be formed by an ion implantation step. For example, when the first conductivity type is a P-type, boron ions, indium ions or boron trifluoride ions (BF ₃ ⁺ ) may be implanted in a region where the first conductivity type well region 106 is to be formed to form a first conductivity type. Well area 106.

It should be noted that in the embodiment, if it is not specifically named "lightly doped" or "heavily doped", "doping" means a doping concentration of 10 ¹⁵ -10 ¹⁷ /cm ³ , for example Doping concentration of 10 ¹⁶ /cm ³ . In other words, in some embodiments, the doping concentration of the second conductive type well region 104 and the first conductive type well region 106 may be a doping concentration of 10 ¹⁵ -10 ¹⁷ /cm ³ , for example, 10 ¹⁶ / Cm ³ . However, it will be appreciated by those of ordinary skill in the art that the definition of "doping" can also be determined by the particular device type, technical generation, minimum component size, and the like. Thus, the definition of "doping" is re-evaluated when the visual technology content is not limited by the embodiments presented herein.

Continuing to refer to FIGS. 1A-1B, the semiconductor device 100 further includes a source region 108 and a drain region 110 disposed in the substrate 102. The source region 108 and the drain region 110 is disposed in the second conductivity type well region 104. In some embodiments of the present disclosure, the source region 108 and the drain region 110 have a heavily doped second conductivity type and can be formed by the ion implantation step described above.

In the embodiment, "heavily doped" means a doping concentration exceeding 10 ¹⁹ /cm ³ , for example, a doping concentration of 10 ¹⁹ /cm ³ to 10 ²¹ /cm ³ . However, it will be appreciated by those of ordinary skill in the art that the definition of "heavily doped" can also be determined by the particular device type, technical generation, minimum component size, and the like. Thus, the definition of "heavily doped" is re-evaluated as visual technology content and is not limited by the embodiments presented herein.

Continuing to refer to FIGS. 1A-1B , the semiconductor device 100 further includes a first conductive type doped region 112 disposed in the substrate 102 and disposed between the source region 108 and the drain region 110 . In some embodiments of the present disclosure, the first conductive type doping region 112 is of a first conductivity type, and the doping concentration thereof is similar to the doping concentration of the second conductive type well region 104, and can be implanted by the above ion implantation. The steps are formed. Moreover, in some embodiments of the present disclosure, the doping concentration in the first conductivity type doping region 112 is uniform and the same.

Continuing to refer to FIG. 1A, the semiconductor device 100 further includes two gate regions 114A and 114B disposed on the substrate 102 and disposed on opposite sides of the first conductive type doping region 112. In detail, the two gate regions 114A and 114B are disposed between the source region 108 and the drain region 110 and are disposed in the first conductive well region 106 on both sides of the second conductive well region 104. In some embodiments of the present disclosure, the two gate regions 114A and 114B have a first conductivity type and may be formed by the ion implantation step described above.

Further, as shown in FIG. 1B, a depletion region 116 is formed between the first conductivity type doping region 112 and the second conductivity type well region 104. And the semiconductor device 100 is more A second conductivity type channel region (i.e., a portion of the second conductivity type well region 104 located in the vicinity of the current path I in FIG. 1B) is included in the second conductivity type well region 104 of the substrate 102. The second conductive type channel region is disposed between the source region 108 and the drain region 110 and is disposed between the second gate regions 114A and 114B. In addition, the second conductive type channel region is located under the bottom surface of the first conductive type doping region 112 and between the source region 108 and the drain region 110, and is located under the side edges 112S1 and 112S2. This second conductive type channel region has a second conductivity type.

In addition, as shown in FIG. 1B, the semiconductor device 100 further includes a protective layer 118 covering the surface of the substrate 102 and exposing only the source region 108, the drain region 110, and the gate regions 114A, 114B. The protective layer 118 can be tantalum oxide, tantalum nitride, hafnium oxynitride, borophosphoquinone glass (BPSG), phosphoric bismuth glass (PSG), spin on glass (SOG), or any other suitable dielectric material, or Combination of the above. The protective layer 118 can be formed by thermal oxidation, chemical vapor deposition (CVD) or spin coating, and a patterning step. It should be noted that in order to clearly describe the disclosed embodiment, the protective layer 118 is not shown in FIG. 1A.

Continuing to refer to FIGS. 1A-1B, there is a region 120 between the source region 108 and the drain region 110, and the region 120 between the source region 108 and the drain region 110 is equally divided into the adjacent drain region 110. The first sub-region 120A and the second sub-region 120B adjacent to the source region 108, and the first conductivity type doping region 112 in the first sub-region 120A has more first conductivity type dopants than the second sub-region 120B The number of first conductivity type dopants of the first conductivity type doping region 112.

In detail, in some embodiments of the present disclosure, as shown in FIG. 1A, the connection direction between the source region 108 and the drain region 110 is the direction A1, and between the two gate regions 114A and 114B. The direction of the connection is direction A2, and the direction A1 is large. The abutment is perpendicular to the direction A2. The edge of the parallel direction A1 of the region 120 (for example, the edge 120S1) is aligned with the edge 108S1 of the parallel direction A1 of the source region 108 and the edge 110S1 of the parallel direction A1 of the drain region 110. And one of the edges of the parallel direction A2 of the region 120 (for example, the edge 120S2) overlaps with the edge 108S2 of the parallel direction A2 of the source region 108, and the other edge of the region 120 parallel to the direction A2 (for example, the edge 120S3) is tied with the bungee The edge 110S2 of the parallel direction A2 of the region 110 overlaps.

Further, the first sub-region 120A and the second sub-region 120B are defined as a boundary line parallel to the direction A2 and located between the source region 108 and the drain region 110. In other words, the center line 120L passes through the center point of the line connecting the source region 108 to the drain region 110 and is parallel to the direction A2, and divides the region 120 into the first sub-region 120A and the second sub-region. 120B. Therefore, the areas of the first sub-region 120A and the second sub-region 120B are equal in area.

In some embodiments of the present disclosure, as shown in FIGS. 1A-1B, the distance between the first conductive type doped region 112 and the source region 108 and the drain region 110 is different, and the first conductive type doped region 112 is different. It is closer to the bungee zone 110.

In detail, the first conductive type doping region 112 has a first side 112S1 adjacent to the drain region 110 and a second side 112S2 adjacent to the source region 108, and the first side 112S1 and the second side 112S2 are opposite to each other. side. The distance between the first side 112S1 and the drain region 110 is the first distance D1, the distance between the second side 112S2 and the source region 108 is the second distance D2, and the first distance D1 is smaller than the second distance D2. .

Some embodiments of the present disclosure make the first conductive type doping region 112 disposed between the source region 108 and the drain region 110 different from the source region 108 and the drain region 110, and make the first The conductive doped region 112 is closer to the drain region 110, and can be located in the region 120 between the source region 108 and the drain region 110. The first conductive type doped region 112 in the first sub-region 120A of the near-drain region 110 has a first conductivity type dopant more than the first conductivity type dopant in the second sub-region 120B closer to the source region 108. The number of first conductivity type dopants in the impurity region 112 is such that the depletion region 116 is closer to the drain region 110, so that the width of the channel region near the gate region 110 in FIG. 1B is smaller, and thus the drain region 110 is It is easier to be pinched than the source region 108. Therefore, the absolute value of the pinch-off voltage of the semiconductor device 100 can be lowered, and the absolute value of the cut-off voltage can be increased with respect to the absolute value of the pinch-off voltage. In other words, the absolute value of the pinch-off voltage of the device is not equal to and less than the absolute value of the cut-off voltage, and the system voltage (VDD) of the semiconductor device 100 can be further increased by this. The application range and the voltage operation range of the output voltage (Vout) thereof are increased to improve the performance of the semiconductor device 100.

It should be noted that although the first conductive type doping region 112 of the first embodiment 1A-1B is simultaneously located in the first sub-region 120A and the second sub-region 120B, the first conductive type doping region 112 may also be located only. In the first sub-area 120A. At this time, the first conductivity type doping region 112 of the first conductivity type doping region 112 in the second sub-region 120B is 0, and the first conductivity type of the first conductivity type doping region 112 in the first sub-region 120A is The number of dopants is of course greater than the number of first conductivity type dopants of the first conductivity type doping region 112 in the second sub-region 120B.

It should be noted that the embodiment shown in FIG. 1A-1B is for illustrative purposes only, and the scope of the disclosure is not limited thereto. In addition to the embodiments shown in Figures 1A-1B above, the first conductivity type doped regions of the present disclosure may have other configurations, as shown in the embodiment of Figures 2A-2B. The scope of the disclosure is not limited to the embodiment shown in Figures 1A-1B. This section will be explained in detail later.

It should be noted that elements or layers that are the same or similar to those in the foregoing will be denoted by the same or similar reference numerals, and the materials, manufacturing methods and functions thereof are the same or similar to those described above, and therefore will not be described later. Narration.

2A is a top view of a semiconductor device 200 in accordance with still other embodiments. Fig. 2B is a cross-sectional view taken along line 2B-2B' of Fig. 2A. As shown in FIG. 2A-2B, the distance between the first side 112S1 of the first conductive type doped region 112 and the drain region 110 is zero. In other words, the first conductive type doped region 112 directly contacts the drain region 110.

It should be noted that the embodiment shown in FIG. 1A-2B is for illustrative purposes only, and the scope of the disclosure is not limited thereto. In addition to the embodiments shown in Figures 1A-2B above, the first conductivity type doped regions of the present disclosure may have other configurations and other doping concentration profiles, as shown in the embodiment of Figures 3A-3B. The scope of the disclosure is not limited to the embodiment shown in Figures 1A-2B. This section will be explained in detail later.

3A is a top view of a semiconductor device 300 in accordance with still other embodiments. Fig. 3B is a cross-sectional view taken along line 3B-3B' of Fig. 3A. As shown in FIGS. 3A-3B, the first conductive type doping region 112 has a gradually changing doping concentration, and the doping concentration in the first conductive type doping region 112 is from the source region 108 toward the drain region. 110 gradually increased.

In detail, in some embodiments of the present disclosure, as shown in FIGS. 3A-3B, the first conductive type doped region 112 sequentially includes a region 112A, a region 112B, and a region 112C from the drain region 110 toward the source region 108. And a region 112D, wherein the region 112A and the region 112B are located in the first sub-region 120A, and the region 112C and the region 112D are located in the second sub-region 120B. And the doping concentration of the first conductivity type dopant of the region 112A is greater than the doping concentration of the first conductivity type dopant of the region 112B, and the region The doping concentration of the first conductivity type dopant of the domain 112B is greater than the doping concentration of the first conductivity type dopant of the region 112C, and the doping concentration of the first conductivity type dopant of the region 112C is greater than the first conductivity type of the region 112D. Doping concentration of the mass.

Moreover, in some embodiments of the present disclosure, the doping concentration within region 112A can be uniform and identical. However, in other embodiments, the doping concentration within region 112A may gradually increase from source region 108 toward drain region 110. It should be noted that the doping concentration in the region 112A may be any suitable distribution as long as the first conductivity type doping region 112 in the first sub-region 120A has a larger number of first conductivity type dopants than the second sub-region 120B. The first conductivity type dopant of the first conductivity type doping region 112 may be any. In addition, the doping concentration distribution in the region 112B, the region 112C, and the region 112D may be similar or identical to the above-mentioned region 112A, and thus will not be described herein.

Some embodiments of the present disclosure can provide an area between the source region 108 and the drain region 110 by gradually increasing the doping concentration in the first conductivity type doping region 112 from the source region 108 toward the drain region 110. 120, the first conductivity type doping region 112 in the first sub-region 120A closer to the drain region 110 has a larger number of first conductivity type dopants than the second sub-region 120B closer to the source region 108. The first conductive type dopant of the conductive doping region 112 makes the depletion region 116 closer to the drain region 110, so that the current path I near the drain region 110 in FIG. 3B can be made longer, and the channel region is The width is small, and thus the drain region 110 is more easily pinched than the source region 108. Therefore, the absolute value of the pinch-off voltage of the semiconductor device 300 can be lowered, and the absolute value of the cut-off voltage can be increased with respect to the absolute value of the pinch-off voltage. In other words, the absolute value of the pinch-off voltage of the device is not equal to and less than the absolute value of the cut-off voltage, and the system voltage of the semiconductor device 300 can be further increased by this. The application range of (VDD) is increased, and the voltage operation range of the output voltage (Vout) is increased to improve the performance of the semiconductor device 300.

It should be noted that, in the embodiment of FIG. 3A-3B, the first conductive type doped region 112 includes four regions having different doping concentrations, but the scope of the disclosure is not limited thereto, and the first conductive type The doped region 112 may include more or less four regions having different doping concentrations from each other. In addition, although in the embodiment of FIG. 3A-3B, the concentration variation in the first conductivity type doping region 112 is discontinuous, in other embodiments, in the first conductivity type doping region 112 The concentration change can also be a continuous change, and the doping concentration gradually increases from the source region 108 toward the drain region 110. Accordingly, the scope of the disclosure is not limited to the embodiments of Figures 3A-3B.

In some embodiments of the present disclosure, the first conductive type doped region 112 having a doping concentration gradually increasing from the source region 108 toward the drain region 110 may be formed by a mask layer having a gradually varying opening density or a gradually changing opening. The size of the mask layer is formed in conjunction with an ion implantation step. For example, the mask layer may have a larger opening density, or a larger opening size, in areas where greater doping concentration is required (eg, region 112A), but in regions where less doping concentration is required (eg, region 112D). Having a smaller opening density, or a smaller opening size, the first conductive type doped region 112 corresponding to the portion of the mask layer having a larger opening density or a larger opening size after the ion implantation step The region (e.g., region 112A) will have a greater doping concentration, and the mask layer will have a smaller opening density or a smaller portion of the opening size corresponding to the region of the first conductivity type doping region 112 (e.g., region) 112D) will have a smaller doping concentration.

Moreover, in other embodiments, the first conductive type doping region 112 It can also be formed by using a multi-gray mask, which can include a Gray Tone Mask and a half tone mask. Alternatively, in other embodiments, the first conductive type doping region 112 may be formed by using a plurality of patterned mask layers and a plurality of ion implantation steps having different implantation energies.

Moreover, in some embodiments of the present disclosure, as shown in FIGS. 3A-3B, the distance between the first conductive type doping region 112 and the source region 108 and the drain region 110 is the same. For example, in some embodiments of the present disclosure, as shown in FIGS. 3A-3B, the distance between the first conductive type doped region 112 and the source region 108 and the drain region 110 is zero. In other words, the first conductive type doping region 112 is in direct contact with the source region 108 and the drain region 110.

It should be noted that the embodiments shown in FIG. 3A-3B are for illustrative purposes only, and the scope of the disclosure is not limited thereto. In addition to the embodiments shown in FIG. 3A-3B above, the first conductive type doped region 112 and the source region 108 and the drain region 110 of the present disclosure may have other configurations, such as the embodiment of FIG. 4A-4C. Shown. The scope of the disclosure is not limited to the embodiment shown in Figures 3A-3B. This section will be explained in detail later.

It should be noted that elements or layers that are the same or similar to those in the foregoing will be denoted by the same or similar reference numerals, and the materials, manufacturing methods and functions thereof are the same or similar to those described above, and therefore will not be described later. Narration.

4A is a top plan view of a semiconductor device 400A according to other embodiments. The difference between the embodiment shown in FIG. 4A and the embodiment of FIG. 3A-3B is that the distance between the first conductive type doping region 112 and the source region 108 and the drain region 110 is different, and the first conductivity type The distance between the doped region 112 and the drain region 110 is zero, and the distance between the first conductive type doped region 112 and the source region 108 is not zero.

FIG. 4B is a top view of the semiconductor device 400B of the other embodiments. The difference between the embodiment shown in FIG. 4B and the embodiment of FIG. 3A-3B is that the distance between the first conductive type doping region 112 and the source region 108 and the drain region 110 is not 0, and this The distance between the first conductive type doping region 112 and the source region 108 and the drain region 110 is the same. However, those of ordinary skill in the art will recognize that in other embodiments, the distance between the first conductive type doped region 112 and the source region 108 and the drain region 110 may also be different.

FIG. 4C is a top view of the semiconductor device 400C of the other embodiments. The difference between the embodiment shown in FIG. 4C and the embodiment of FIG. 3A-3B is that the distance between the first conductive type doping region 112 and the source region 108 and the drain region 110 is different, and the first conductivity type The distance between the doped region 112 and the source region 108 is zero, and the distance between the first conductive type doped region 112 and the drain region 110 is not zero.

In addition, it should be noted that although the first conductive type doping region 112 in the semiconductor device 400C is closer to the source region 108, the doping concentration of the portion of the first conductive type doping region 112 near the drain region 110 is higher. Therefore, in the semiconductor device 400C, the first conductivity type doping region 112 in the first sub-region 120A is still more than the first conductivity type doping region 112 in the second sub-region 120B. The number of first conductivity type dopants.

In summary, the disclosed embodiments are different in distance between the first conductive type doped region disposed between the source region and the drain region and the source region and the drain region, and/or by The first conductive type doped region has a gradually changing doping concentration such that the region between the source region and the drain region is closer to the portion of the drain region (ie, the first sub-region) The first conductivity type doping region has a first conductivity type dopant number more than a portion closer to the source region (ie, the second sub region) The first conductivity type dopant of a conductive type doping region is such that the absolute value of the pinch-off voltage of the device is smaller than the absolute value of the cut-off voltage, and can be further increased by this The application range of the system voltage (VDD) of the semiconductor device is increased, and the voltage operation range of the output voltage (Vout) is increased to increase the performance of the device.

In addition, it should be noted that although in the above embodiments, the first conductivity type is P type and the second conductivity type is N type, however, those skilled in the art can understand the first conductivity. The type can also be N-type, while the second conductivity type is P-type.

It should be noted that the component sizes, component parameters, and component shapes described above are not limitations of the disclosure. Those of ordinary skill in the art can adjust these settings according to different needs. Further, the semiconductor device of the present disclosure is not limited to the state illustrated in FIGS. 1A-4C. The disclosure may include only any one or more of the features of any one or a plurality of embodiments of Figures 1A-4C. In other words, not all illustrated features must be implemented in the semiconductor device of the present disclosure.

In addition, although the doping concentrations of the various doped regions in some embodiments are set forth above. However, it will be understood by those of ordinary skill in the art that the doping concentration of each doped region can be determined according to a particular device type, technology generation, minimum component size, and the like. Thus, the doping concentration of each doped region can be re-evaluated in accordance with the technical content without being limited to the embodiments presented herein.

Although the embodiments of the present disclosure and its advantages are disclosed above, it should be understood that those skilled in the art can make changes, substitutions, and refinements without departing from the spirit and scope of the disclosure. In addition, this The scope of the disclosure is not limited to the processes, machines, manufacture, compositions, devices, methods and steps in the specific embodiments described in the specification, and any one of ordinary skill in the art can understand the present disclosure. Processes, machines, manufacturing, material compositions, devices, methods, and steps that are developed in the future may be used in accordance with the present disclosure as long as they can perform substantially the same function or achieve substantially the same results in the embodiments described herein. Accordingly, the scope of protection of the present disclosure includes the above-described processes, machines, manufacturing, material compositions, devices, methods, and procedures. In addition, each patent application scope constitutes an individual embodiment, and the scope of protection of the disclosure also includes a combination of the scope of the patent application and the embodiments.

100‧‧‧Semiconductor device

102‧‧‧Substrate

104‧‧‧Second Conductive Well Area

106‧‧‧First Conductive Well Area

108‧‧‧ source area

108S1‧‧‧ edge

108S2‧‧‧ edge

110‧‧‧Bungee Area

Edge of 110S1‧‧

Edge of 110S2‧‧

112‧‧‧First Conductive Doped Area

112S1‧‧‧ first side

112S2‧‧‧ second side

114A‧‧‧Gate

114B‧‧‧The gate area

120‧‧‧Area

120A‧‧‧First subregion

120B‧‧‧Second subregion

120S1‧‧‧ edge

120S2‧‧‧ edge

120S3‧‧‧ edge

120L‧‧‧ center line

D1‧‧‧ distance

D2‧‧‧ distance

D3‧‧‧ distance

A1‧‧ Direction

A2‧‧‧ direction

1B-1B’‧‧‧ segment

Claims (10)

A semiconductor device includes: a substrate; a source region and a drain region disposed horizontally in the substrate; a first conductive type doped region disposed in the substrate and disposed in the source region Between the drain regions, wherein the first conductive type doped region has a first conductivity type, wherein a region between the source region and the drain region is first adjacent to the first one of the drain regions a sub-region and a second sub-region adjacent to the source region, wherein the first conductivity type doping region of the first sub-region has a larger number of first conductivity type dopants than the second subregion region a first conductive type doping quantity of a conductive type doped region; a second gate region disposed in the substrate and disposed on both sides of the first conductive type doped region; and a second conductive type channel region, Provided in the substrate, wherein the second conductive type channel region is disposed between the source region and the drain region, and is disposed between the two gate regions, wherein the second conductive type channel region is located A bottom surface of one of the first conductive type doping regions and the first conductive type doped region are adjacent to both sides of the source region and the drain region And the second conductivity type channel region having a second conductivity type, wherein the first conductivity type and the second conductivity type are different. The semiconductor device of claim 1, wherein a distance between the first conductive type doped region and the source region and the drain region is different, and the first conductive type doped region has a proximity a first side of the drain region and a second side adjacent to the source region, and the first side and the second side are opposite sides of each other; wherein the distance between the first side and the drain region is first a distance; wherein a distance between the second side and the source region is a second distance; Wherein the first distance is less than the second distance. The semiconductor device of claim 2, wherein the first distance is zero. The semiconductor device according to claim 2, wherein the doping concentration in the first conductivity type doping region is the same. The semiconductor device of claim 1, wherein the first conductive type doped region has a gradually changing doping concentration, and the doping concentration in the first conductive type doped region is from the source region The bungee area is gradually increasing. The semiconductor device of claim 5, wherein the first conductive type doped region has the same distance from the source region and the drain region. The semiconductor device of claim 6, wherein the distance between the first conductive type doped region and the source region and the drain region is zero. The semiconductor device of claim 1, wherein a distance between the first conductive type doped region and the source region is smaller than a distance between the first conductive type doped region and the drain region. The semiconductor device of claim 1, further comprising: a second conductivity type well region disposed in the substrate, wherein the source region, the drain region, and the first conductivity type doping region are The second conductive type channel region is disposed in the second conductive type well region. The semiconductor device according to claim 1, wherein an absolute value of a pinch off voltage of the semiconductor device is less than an absolute value of a cut off voltage.