TWI589972B - Active device array susbtrate and liquid crystal panel using the same - Google Patents

Active device array susbtrate and liquid crystal panel using the same Download PDF

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Publication number
TWI589972B
TWI589972B TW105143686A TW105143686A TWI589972B TW I589972 B TWI589972 B TW I589972B TW 105143686 A TW105143686 A TW 105143686A TW 105143686 A TW105143686 A TW 105143686A TW I589972 B TWI589972 B TW I589972B
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Taiwan
Prior art keywords
pixel
sub
electrode
data line
line
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TW105143686A
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Chinese (zh)
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TW201823829A (en
Inventor
陳宜瑢
吳尚杰
何昇儒
林文燦
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友達光電股份有限公司
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Priority to TW105143686A priority Critical patent/TWI589972B/en
Priority to CN201710092059.1A priority patent/CN106842746B/en
Application granted granted Critical
Publication of TWI589972B publication Critical patent/TWI589972B/en
Priority to US15/651,054 priority patent/US9933678B1/en
Priority to EP17200119.0A priority patent/EP3343283B1/en
Publication of TW201823829A publication Critical patent/TW201823829A/en

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134336—Matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G—PHYSICS
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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    • G—PHYSICS
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
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    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
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    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0405—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising semiconducting carbon, e.g. diamond, diamond-like carbon
    • H01L21/042—Changing their shape, e.g. forming recesses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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    • G—PHYSICS
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
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    • G02F1/136222—Colour filters incorporated in the active matrix substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Optics & Photonics (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Theoretical Computer Science (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Liquid Crystal (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Human Computer Interaction (AREA)
  • Electromagnetism (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Molecular Biology (AREA)

Description

主動元件陣列基板及應用其之液晶面板 Active device array substrate and liquid crystal panel using same

本發明是關於一種主動元件陣列基板及應用其之液晶面板。 The present invention relates to an active device array substrate and a liquid crystal panel using the same.

隨著顯示技術的發展，液晶顯示裝置已廣泛地應用於各種電子設備中。在液晶顯示裝置的製造過程中，需將上、下基板的預定位置貼合以組成各個畫素。 With the development of display technology, liquid crystal display devices have been widely used in various electronic devices. In the manufacturing process of the liquid crystal display device, predetermined positions of the upper and lower substrates are attached to form respective pixels.

然而，在部分情況下，上、下基板容易發生錯位的問題。以曲面液晶顯示裝置為例，通常是將顯示裝置先做成平面結構，再對平面結構的液晶顯示裝置進行彎曲處理，以得到曲面液晶顯示裝置。當彎曲程度較大時，由於基板之間的相對移動程度較大，造成在彎曲部位的基板的預定對應位置錯位，而在錯位部分出現液晶排列錯亂的現象，進而影響視覺效果。 However, in some cases, the upper and lower substrates are prone to misalignment. Taking a curved liquid crystal display device as an example, the display device is usually formed into a planar structure, and then the liquid crystal display device having a planar structure is subjected to bending treatment to obtain a curved liquid crystal display device. When the degree of bending is large, due to the relatively large degree of relative movement between the substrates, the predetermined corresponding position of the substrate at the bent portion is misaligned, and the liquid crystal alignment disorder occurs in the misaligned portion, thereby affecting the visual effect.

本發明之部分實施方式提供一種主動元件陣列基板及應用其之液晶面板，透過設計子畫素的長邊平行於液晶 面板的彎曲方向，縮小因上下基板錯位而液晶排列錯亂的區域。此外，本實施方式還透過同一閘極訊號與不同的資料訊號，供給第一子畫素單元、第二子畫素單元以及第三子畫素單元，使第一子畫素單元、第二子畫素單元以及第三子畫素單元有各自的操作電壓，而各自呈現預期的亮度，此作法可以提升各個子畫素單元的供電時間，確保其子畫素單元內的主動元件充電充足。 Some embodiments of the present invention provide an active device array substrate and a liquid crystal panel using the same, wherein a long side of the design sub-pixel is parallel to the liquid crystal In the bending direction of the panel, the area where the liquid crystals are disordered due to the displacement of the upper and lower substrates is reduced. In addition, the first sub-pixel unit, the second sub-pixel unit, and the third sub-pixel unit are supplied to the first sub-pixel unit and the second sub-pixel unit through the same gate signal and different data signals. The pixel unit and the third sub-pixel unit have respective operating voltages, and each exhibits a desired brightness. This method can improve the power supply time of each sub-pixel unit and ensure that the active components in the sub-pixel unit are fully charged.

根據本發明之部分實施方式，一種主動元件陣列基板包含基板、至少一第一資料線、至少一第二資料線、至少一第三資料線、多個第一掃描線、至少一第二掃描線、至少一共通電極線、至少一第一子畫素單元、至少一第二子畫素單元以及至少一第三子畫素單元。基板具有主動區與設置於主動區之至少一側的周邊線路區。第一資料線、第二資料線以及第三資料線沿第一方向延伸且設置於基板上。第一掃描線沿第二方向延伸且設置於基板上，其中第一方向不平行於第二方向，其中第一資料線以及第三資料線分別與第一掃描線之第一者與第二者交錯，以定義基板上主動區內之至少一畫素區域。第二資料線位於第一資料線以及第三資料線之間，且通過畫素區域。第二掃描線以及共通電極線沿第二方向延伸且設置於基板上，其中第一資料線與第二掃描線以及共通電極線交錯，以定義畫素區域內之第一子畫素區域、第二子畫素區域以及第三子畫素區域。第一子畫素單元設置於第一子畫素區域且電性連接第一資料線與第一掃描線之第一者。第二子畫素單元設置於第二子畫素區域且電性連接第二資料線與第二掃描線。第三子畫 素單元設置於第三子畫素區域且電性連接第三資料線與第二掃描線。 According to some embodiments of the present invention, an active device array substrate includes a substrate, at least one first data line, at least one second data line, at least one third data line, a plurality of first scan lines, and at least one second scan line. And at least one common electrode line, at least one first sub-pixel unit, at least one second sub-pixel unit, and at least one third sub-pixel unit. The substrate has an active area and a peripheral line area disposed on at least one side of the active area. The first data line, the second data line, and the third data line extend in the first direction and are disposed on the substrate. The first scan line extends in the second direction and is disposed on the substrate, wherein the first direction is not parallel to the second direction, wherein the first data line and the third data line are respectively associated with the first and second of the first scan line Interleaved to define at least one pixel region in the active region on the substrate. The second data line is located between the first data line and the third data line and passes through the pixel area. The second scan line and the common electrode line extend along the second direction and are disposed on the substrate, wherein the first data line is interlaced with the second scan line and the common electrode line to define a first sub-pixel area in the pixel area, The second sub-pixel area and the third sub-pixel area. The first sub-pixel unit is disposed in the first sub-pixel area and electrically connected to the first one of the first data line and the first scan line. The second sub-pixel unit is disposed in the second sub-pixel area and electrically connected to the second data line and the second scan line. Third sub painting The element unit is disposed in the third sub-pixel area and electrically connected to the third data line and the second scan line.

於本發明之部分實施方式中，每一第一子畫素區域、第二子畫素區域以及第三子畫素區域於第一方向具有第一長度且於第二方向具有一第二長度，其中第一長度小於第二長度。 In some embodiments of the present invention, each of the first sub-pixel region, the second sub-pixel region, and the third sub-pixel region have a first length in the first direction and a second length in the second direction. Wherein the first length is less than the second length.

於本發明之部分實施方式中，第一掃描線與第二掃描線延伸至周邊線路區，第一掃描線之第一者與第二掃描線電性連接。 In some embodiments of the present invention, the first scan line and the second scan line extend to the peripheral line region, and the first one of the first scan lines is electrically connected to the second scan line.

於本發明之部分實施方式中，主動元件陣列基板更包含閘極驅動器，位於基板之周邊線路區，其中閘極驅動器包含至少一腳位，其中第一掃描線之第一者與第二掃描線電性連接至同一腳位。 In some embodiments of the present invention, the active device array substrate further includes a gate driver located in a peripheral line region of the substrate, wherein the gate driver includes at least one pin, wherein the first and second scan lines of the first scan line Electrically connected to the same foot.

於本發明之部分實施方式中，每一第一子畫素單元、第二子畫素單元以及第三子畫素單元包含主動元件以及至少一畫素電極，其中畫素電極電性連接主動元件，其中畫素電極包含第一主幹電極以及多個分支電極。第一主幹電極沿第二方向延伸。分支電極電性連接第一主幹電極且往多個不同延伸方向延伸，其中延伸方向不平行於第一方向與第二方向。 In some embodiments of the present invention, each of the first sub-pixel unit, the second sub-pixel unit, and the third sub-pixel unit includes an active component and at least one pixel electrode, wherein the pixel electrode is electrically connected to the active component Wherein the pixel electrode comprises a first trunk electrode and a plurality of branch electrodes. The first trunk electrode extends in the second direction. The branch electrode is electrically connected to the first trunk electrode and extends in a plurality of different extending directions, wherein the extending direction is not parallel to the first direction and the second direction.

於本發明之部分實施方式中，畫素電極更包含第二主幹電極，沿第一方向延伸，且與第一主幹電極交錯。 In some embodiments of the present invention, the pixel electrode further includes a second stem electrode extending in the first direction and interlaced with the first stem electrode.

於本發明之部分實施方式中，第二資料線與第一掃描線之第一者交錯，以定義每一第一子畫素區域、第二子畫素區域以及第三子畫素區域之第一分割區域與第二分割區 域，其中每一第一子畫素單元、第二子畫素單元以及第三子畫素單元之畫素電極的數量為二，畫素電極分別位於第一分割區域與第二分割區域，每一第一子畫素單元、第二子畫素單元以及第三子畫素單元包含一連接電極，以電性連接分別位於第一分割區與第二分割區域的畫素電極。 In some embodiments of the present invention, the second data line is interleaved with the first one of the first scan lines to define a first sub-pixel region, a second sub-pixel region, and a third sub-pixel region. a divided area and a second divided area a field, wherein the number of pixel electrodes of each of the first sub-pixel unit, the second sub-pixel unit, and the third sub-pixel unit is two, and the pixel electrodes are respectively located in the first divided area and the second divided area, and each A first sub-pixel unit, a second sub-pixel unit, and a third sub-pixel unit comprise a connection electrode electrically connected to the pixel electrodes respectively located in the first division area and the second division area.

於本發明之部分實施方式中，每一畫素電極之分支電極具有二個延伸方向。 In some embodiments of the invention, the branch electrodes of each pixel electrode have two extension directions.

於本發明之部分實施方式中，每一畫素電極之分支電極具有四個延伸方向。 In some embodiments of the invention, the branch electrodes of each pixel electrode have four directions of extension.

於本發明之部分實施方式中，每一該第一子畫素單元、該第二子畫素單元以及該第三子畫素單元包含一主動元件以及一畫素電極，其中該畫素電極電性連接該主動元件，其中該主動元件陣列基板更包含彩色濾光片以及遮光層。彩色濾光片包含紅色色阻、藍色色阻以及綠色色阻。紅色色阻對應第一子畫素區域之畫素電極設置。藍色色阻對應第二子畫素區域之畫素電極設置。綠色色阻對應第三子畫素區域之畫素電極設置。遮光層覆蓋主動元件。 In some embodiments of the present invention, each of the first sub-pixel unit, the second sub-pixel unit, and the third sub-pixel unit comprise an active component and a pixel electrode, wherein the pixel electrode is electrically The active component is connected to the active device, wherein the active device array substrate further comprises a color filter and a light shielding layer. The color filter includes red color resistance, blue color resistance, and green color resistance. The red color resistance corresponds to the pixel setting of the first sub-pixel area. The blue color resistance corresponds to the pixel electrode setting of the second sub-pixel area. The green color resistance corresponds to the pixel setting of the third sub-pixel area. The light shielding layer covers the active components.

根據本發明之部分實施方式，液晶面板包含前述之主動元件陣列基板、對向基板、液晶層以及二垂直配向層。液晶層設置於主動元件陣列基板與對向基板之間。垂直配向層分別設置於液晶層與主動元件陣列基板之間以及液晶層與對向基板之間。 According to some embodiments of the present invention, the liquid crystal panel includes the active device array substrate, the opposite substrate, the liquid crystal layer, and the two vertical alignment layers. The liquid crystal layer is disposed between the active device array substrate and the opposite substrate. The vertical alignment layers are respectively disposed between the liquid crystal layer and the active device array substrate and between the liquid crystal layer and the opposite substrate.

於本發明之部分實施方式中，垂直配向層由聚合物穩定材料所形成。 In some embodiments of the invention, the vertical alignment layer is formed from a polymeric stabilizing material.

於本發明之部分實施方式中，每一第一子畫素單元、第二子畫素單元以及第三子畫素單元包含主動元件以及畫素電極，其中畫素電極電性連接主動元件，其中該主動元件陣列基板更包含彩色濾光片、遮光層以及至少一間隙物。彩色濾光片對應畫素電極設置。遮光層對應主動元件設置。間隙物設置於彩色濾光片上，其中間隙物之頂端連接對向基板。 In some embodiments of the present invention, each of the first sub-pixel unit, the second sub-pixel unit, and the third sub-pixel unit includes an active element and a pixel electrode, wherein the pixel electrode is electrically connected to the active element, wherein The active device array substrate further includes a color filter, a light shielding layer, and at least one spacer. The color filter corresponds to the pixel electrode setting. The light shielding layer corresponds to the active component setting. The spacer is disposed on the color filter, wherein the top end of the spacer is connected to the opposite substrate.

於本發明之部分實施方式中，主動元件陣列基板之基板與對向基板沿第二方向彎曲。 In some embodiments of the present invention, the substrate of the active device array substrate and the opposite substrate are bent in the second direction.

於本發明之部分實施方式中，每一第一子畫素區域、第二子畫素區域以及第三子畫素區域於第一方向具有第一長度且於第二方向具有第二長度，其中第一長度小於第二長度。 In some embodiments of the present invention, each of the first sub-pixel region, the second sub-pixel region, and the third sub-pixel region have a first length in the first direction and a second length in the second direction, wherein The first length is less than the second length.

100‧‧‧液晶面板 100‧‧‧LCD panel

200‧‧‧主動元件陣列基板 200‧‧‧Active component array substrate

210‧‧‧基板 210‧‧‧Substrate

220‧‧‧第一子畫素單元 220‧‧‧ first sub-pixel unit

222‧‧‧主動元件 222‧‧‧Active components

224‧‧‧畫素電極 224‧‧‧ pixel electrodes

224a‧‧‧第一主幹電極 224a‧‧‧first main electrode

224b‧‧‧第二主幹電極 224b‧‧‧second trunk electrode

224c‧‧‧分支電極 224c‧‧‧ branch electrode

226‧‧‧連接電極 226‧‧‧Connected electrode

230‧‧‧第二子畫素單元 230‧‧‧ second sub-pixel unit

232‧‧‧主動元件 232‧‧‧Active components

234‧‧‧畫素電極 234‧‧‧ pixel electrodes

234a‧‧‧第一主幹電極 234a‧‧‧first main electrode

234b‧‧‧第二主幹電極 234b‧‧‧second trunk electrode

234c‧‧‧分支電極 234c‧‧‧ branch electrode

236‧‧‧連接電極 236‧‧‧Connecting electrode

282‧‧‧頂端 282‧‧‧Top

290‧‧‧遮蔽電極 290‧‧‧shading electrode

300‧‧‧對向基板 300‧‧‧ opposite substrate

400‧‧‧液晶層 400‧‧‧Liquid layer

500‧‧‧垂直配向層 500‧‧‧Vertical alignment layer

D1‧‧‧第一方向 D1‧‧‧ first direction

D2‧‧‧第二方向 D2‧‧‧ second direction

L1‧‧‧第一長度 L1‧‧‧ first length

L2‧‧‧第二長度 L2‧‧‧ second length

DL1‧‧‧第一資料線 DL1‧‧‧ first data line

DL2‧‧‧第二資料線 DL2‧‧‧ second data line

DL3‧‧‧第三資料線 DL3‧‧‧ third data line

SL1‧‧‧第一掃描線 SL1‧‧‧ first scan line

SL2‧‧‧第二掃描線 SL2‧‧‧Second scan line

SP1‧‧‧第一子畫素區域 SP1‧‧‧ first sub-pixel area

SP2‧‧‧第二子畫素區域 SP2‧‧‧Second sub-pixel area

SP3‧‧‧第三子畫素區域 SP3‧‧‧ Third sub-pixel area

240‧‧‧第三子畫素單元 240‧‧‧ third sub-pixel unit

242‧‧‧主動元件 242‧‧‧Active components

244‧‧‧畫素電極 244‧‧‧pixel electrodes

244a‧‧‧第一主幹電極 244a‧‧‧first main electrode

244b‧‧‧第二主幹電極 244b‧‧‧second trunk electrode

244c‧‧‧分支電極 244c‧‧‧ branch electrode

246‧‧‧連接電極 246‧‧‧Connecting electrode

250‧‧‧閘極驅動器 250‧‧‧gate driver

260‧‧‧彩色濾光片 260‧‧‧Color filters

262‧‧‧紅色色阻 262‧‧‧Red color resistance

264‧‧‧綠色色阻 264‧‧‧Green color resistance

266‧‧‧藍色色阻 266‧‧‧Blue color resistance

270‧‧‧遮光層 270‧‧‧ shading layer

280‧‧‧間隙物 280‧‧ ‧ spacers

AA‧‧‧主動區 AA‧‧‧Active Area

NA‧‧‧周邊線路區 NA‧‧‧ surrounding area

CL‧‧‧共通電極線 CL‧‧‧Common electrode line

PR‧‧‧畫素區域 PR‧‧‧ pixel area

PA‧‧‧第一分割區域 PA‧‧‧ first segmentation area

PB‧‧‧第二分割區域 PB‧‧‧Second segmentation area

PL‧‧‧絕緣層 PL‧‧‧Insulation

GI‧‧‧閘極介電層 GI‧‧‧ gate dielectric layer

SE‧‧‧源極 SE‧‧‧ source

DE‧‧‧汲極 DE‧‧‧汲

AS‧‧‧半導體層 AS‧‧‧Semiconductor layer

O1‧‧‧開口 O1‧‧‧ openings

1D-1D‧‧‧線 1D-1D‧‧‧ line

1E-1E‧‧‧線 Line 1E-1E‧‧

第1A圖為根據本發明之一實施方式之主動元件陣列基板之上視示意圖。 1A is a top plan view of an active device array substrate according to an embodiment of the present invention.

第1B圖為第1A圖之單個畫素區域之上視示意圖。 Figure 1B is a top plan view of a single pixel region of Figure 1A.

第1C圖為本發明之部分實施方式中彩色濾光片與遮光層的上視示意圖。 FIG. 1C is a top view showing a color filter and a light shielding layer in a part of the embodiment of the present invention.

第1D圖為沿第1A圖之線1D-1D之剖面示意圖。 Fig. 1D is a schematic cross-sectional view taken along line 1D-1D of Fig. 1A.

第1E圖為沿第1A圖之線1E-1E之剖面示意圖。 Fig. 1E is a schematic cross-sectional view taken along line 1E-1E of Fig. 1A.

第2圖為根據本發明之另一實施方式之單個畫素區域之上視示意圖。 2 is a top plan view of a single pixel region in accordance with another embodiment of the present invention.

以下將以圖式揭露本發明之多個實施方式，為明確說明起見，許多實務上的細節將在以下敘述中一併說明。然而，應瞭解到，這些實務上的細節不應用以限制本發明。也就是說，在本發明部分實施方式中，這些實務上的細節是非必要的。此外，為簡化圖式起見，一些習知慣用的結構與元件在圖式中將以簡單示意的方式為之。 The various embodiments of the present invention are disclosed in the drawings, and in the claims However, it should be understood that these practical details are not intended to limit the invention. That is, in some embodiments of the invention, these practical details are not necessary. In addition, some of the conventional structures and elements are shown in the drawings in a simplified manner.

第1A圖為根據本發明之一實施方式之主動元件陣列基板200之上視示意圖。主動元件陣列基板200包含基板210，基板210具有主動區AA與設置於主動區AA之至少一側的周邊線路區NA。主動元件陣列基板200包含設置於基板210上的至少一第一資料線DL1、至少一第二資料線DL2、至少一第三資料線DL3、多個第一掃描線SL1、至少一第二掃描線SL2、至少一共通電極線CL、至少一第一子畫素單元220、至少一第二子畫素單元230以及至少一第三子畫素單元240。 FIG. 1A is a top plan view of an active device array substrate 200 according to an embodiment of the present invention. The active device array substrate 200 includes a substrate 210 having an active area AA and a peripheral line area NA disposed on at least one side of the active area AA. The active device array substrate 200 includes at least one first data line DL1, at least one second data line DL2, at least one third data line DL3, a plurality of first scan lines SL1, and at least one second scan line disposed on the substrate 210. SL2, at least one common electrode line CL, at least one first sub-pixel unit 220, at least one second sub-pixel unit 230, and at least one third sub-pixel unit 240.

於本發明之部分實施方式中，第一資料線DL1、第二資料線DL2以及第三資料線DL3沿第一方向D1延伸且依序排列，使得第二資料線DL2設置於第一資料線DL1以及第三資料線DL3之間。第一掃描線SL1、共通電極線CL以及第二掃描線SL2沿第二方向D2延伸且依序排列，使得共通電極線CL設置於第一掃描線SL1以及第二掃描線SL2之間。第一方向D1不平行於第二方向D2。於部分實施方式中，每兩相鄰的第一掃描線SL1分別與第一資料線DL1以及第三資料線DL3交 錯，以定義基板210上主動區AA內之畫素區域PR。第二資料線DL2通過此畫素區域PR。於此，基板210上設置有多個以陣列排列的畫素區域PR。 In some embodiments of the present invention, the first data line DL1, the second data line DL2, and the third data line DL3 extend along the first direction D1 and are sequentially arranged such that the second data line DL2 is disposed on the first data line DL1. And between the third data line DL3. The first scan line SL1, the common electrode line CL, and the second scan line SL2 extend in the second direction D2 and are sequentially arranged such that the common electrode line CL is disposed between the first scan line SL1 and the second scan line SL2. The first direction D1 is not parallel to the second direction D2. In some embodiments, each two adjacent first scan lines SL1 are respectively intersected with the first data line DL1 and the third data line DL3. Wrong, to define the pixel area PR in the active area AA on the substrate 210. The second data line DL2 passes through this pixel area PR. Here, the substrate 210 is provided with a plurality of pixel regions PR arranged in an array.

換言之，於本發明上述之實施方式中，畫素區域PR係由二個相鄰之第一掃描線SL1、一個第一資料線DL1以及一個第三資料線DL3共同交錯構成，此外，上述的共通電極線CL係與第一資料線DL1以及第三資料線DL3交錯，而以畫素區域PR中的一個第一掃描線SL1、第一資料線DL1、第三資料線DL3以及共通電極線CL定義出畫素區域PR內之第一子畫素區域SP1。而第二掃描線SL2係與第一資料線DL1以及第三資料線DL3交錯，並以第一資料線DL1、第三資料線DL3、共通電極線CL以及第二掃描線SL2定義畫素區域PR內之第二子畫素區域SP2。再以畫素區域PR中的另一個第一掃描線SL1、第一資料線DL1、第三資料線DL3以及第二掃描線SL2定義畫素區域PR內之第三子畫素區域SP3。 In other words, in the above embodiment of the present invention, the pixel region PR is formed by interlacing two adjacent first scan lines SL1, one first data line DL1, and one third data line DL3, and the above common The electrode line CL is interleaved with the first data line DL1 and the third data line DL3, and is defined by a first scan line SL1, a first data line DL1, a third data line DL3, and a common electrode line CL in the pixel region PR. The first sub-pixel area SP1 in the pixel region PR. The second scan line SL2 is interleaved with the first data line DL1 and the third data line DL3, and the pixel area PR is defined by the first data line DL1, the third data line DL3, the common electrode line CL, and the second scan line SL2. The second sub-pixel area SP2. The third sub-pixel region SP3 in the pixel region PR is defined by the other first scan line SL1, the first data line DL1, the third data line DL3, and the second scan line SL2 in the pixel region PR.

第一子畫素單元220設置於第一子畫素區域SP1且電性連接第一資料線DL1與一個第一掃描線SL1。第二子畫素單元230設置於第二子畫素區域SP2且電性連接第二資料線DL2與第二掃描線SL2。第三子畫素單元240設置於第三子畫素區域SP3且電性連接第三資料線DL3與第二掃描線SL2。 The first sub-pixel unit 220 is disposed in the first sub-pixel area SP1 and electrically connected to the first data line DL1 and one first scan line SL1. The second sub-pixel unit 230 is disposed in the second sub-pixel area SP2 and electrically connected to the second data line DL2 and the second scan line SL2. The third sub-pixel unit 240 is disposed in the third sub-pixel area SP3 and electrically connected to the third data line DL3 and the second scan line SL2.

於本發明之部分實施方式中，第一掃描線SL1與第二掃描線SL2延伸至周邊線路區NA，同一畫素區域PR中，電性連接第一子畫素單元220之第一掃描線SL1與電性連接第二子畫素單元230與第三子畫素單元240的第二掃描線SL2電 性連接。具體而言，主動元件陣列基板200更包含閘極驅動器250，位於基板210之周邊線路區NA。舉例而言，閘極驅動器250可以是驅動晶片。或者，閘極驅動器250也可以是適當的驅動電路。閘極驅動器250包含至少一腳位，其中同一畫素區域PR之第一掃描線SL1與第二掃描線SL2電性連接至同一腳位。藉此，透過同一閘極訊號與不同的資料訊號(第一資料線DL1、第二資料線DL2以及第三資料線DL3)，可以同時供給第一子畫素單元220、第二子畫素單元230以及第三子畫素單元240有各自的操作電壓，而呈現預期的亮度。本實施方式中，由於不用透過時間分割對同一畫素區域PR提供多種閘極訊號，有鑑於此，可以提升各個子畫素單元的供電時間，確保其子畫素單元內的主動元件充電充足。且相較於以多個閘極線搭配一個資料線控制同一畫素單元內各個子畫素單元運作的操作方式，本實施方式以一個閘極線搭配多個資料線控制同一畫素單元內各個子畫素單元運作，因此可進一步降低閘極驅動器250所需的腳位數量，並且由於腳位數量下降，可以延長閘極的充電時間，改善在人眼所能接收動態顯示的效果。 In some embodiments of the present invention, the first scan line SL1 and the second scan line SL2 extend to the peripheral line area NA, and the first pixel line PR of the first sub-pixel unit 220 is electrically connected to the first scan line SL1. Electrically connecting the second sub-pixel unit 230 and the second scan line SL2 of the third sub-pixel unit 240 Sexual connection. Specifically, the active device array substrate 200 further includes a gate driver 250 located at a peripheral line region NA of the substrate 210. For example, the gate driver 250 can be a drive wafer. Alternatively, the gate driver 250 can also be a suitable driver circuit. The gate driver 250 includes at least one pin, wherein the first scan line SL1 and the second scan line SL2 of the same pixel region PR are electrically connected to the same pin. Thereby, the first sub-pixel unit 220 and the second sub-pixel unit can be simultaneously supplied through the same gate signal and different data signals (the first data line DL1, the second data line DL2, and the third data line DL3). 230 and the third sub-pixel unit 240 have respective operating voltages that exhibit the desired brightness. In the present embodiment, since a plurality of gate signals are provided for the same pixel region PR without time division, in view of this, the power supply time of each sub-pixel unit can be improved, and the active components in the sub-pixel unit can be sufficiently charged. Compared with the operation mode of controlling the operation of each sub-pixel unit in the same pixel unit by using one data line with multiple gate lines, the present embodiment controls each of the same pixel units with one gate line and multiple data lines. The sub-pixel unit operates, so that the number of pins required for the gate driver 250 can be further reduced, and since the number of pins is reduced, the charging time of the gate can be extended, and the effect of receiving dynamic display in the human eye can be improved.

雖然在此並未詳細繪示，於部分實施方式中，基板210可沿第二方向D2彎曲(即以第一方向D1為軸心線方向)。更甚者，為了與人體視覺搭配，基板210彎曲的第二方向D2即使用者眼睛所能觀察的左右兩側的方向。於此，雖然並未繪示完整的基板210，基板210於第一方向D1的長度可以設計小於基板210於第二方向D2的長度，而讓使用者可以在左右兩側(即第二方向D2上)感受到較明顯的曲面顯示效果。 Although not shown in detail herein, in some embodiments, the substrate 210 may be curved in the second direction D2 (ie, in the first direction D1 as the axis direction). Moreover, in order to match the human visual, the second direction D2 of the bending of the substrate 210 is the direction of the left and right sides that the user's eyes can observe. Here, although the complete substrate 210 is not shown, the length of the substrate 210 in the first direction D1 can be designed to be smaller than the length of the substrate 210 in the second direction D2, so that the user can be on the left and right sides (ie, the second direction D2) Upper) Feel the obvious surface display effect.

第1B圖為第1A圖之單個畫素區域PR之上視示意圖。同時參照第1B圖與第1A圖。於本發明之部分實施方式中，第一子畫素單元220包含主動元件222以及至少一畫素電極224，其中畫素電極224電性連接主動元件222。畫素電極224可選擇性的包含第一主幹電極224a、第二主幹電極224b以及多個分支電極224c。第一主幹電極224a沿第一方向D1延伸。第二主幹電極224b沿第二方向D2延伸且與第一主幹電極224a交錯。分支電極224c電性連接第一主幹電極224a或第二主幹電極224b且往多個不同延伸方向延伸，其中分支電極224c的延伸方向不平行於第一方向D1與第二方向D2。 Figure 1B is a top plan view of a single pixel region PR of Figure 1A. Refer to both Figure 1B and Figure 1A. In some embodiments of the present invention, the first sub-pixel unit 220 includes an active element 222 and at least one pixel electrode 224, wherein the pixel electrode 224 is electrically connected to the active element 222. The pixel electrode 224 can selectively include a first stem electrode 224a, a second stem electrode 224b, and a plurality of branch electrodes 224c. The first trunk electrode 224a extends in the first direction D1. The second stem electrode 224b extends in the second direction D2 and is interleaved with the first stem electrode 224a. The branch electrode 224c is electrically connected to the first main electrode 224a or the second main electrode 224b and extends in a plurality of different extending directions, wherein the extending direction of the branch electrode 224c is not parallel to the first direction D1 and the second direction D2.

同樣地，第二子畫素單元230包含主動元件232以及至少一畫素電極234，其中畫素電極234電性連接主動元件232。畫素電極234可選擇性的包含第一主幹電極234a、第二主幹電極234b以及多個分支電極234c。第一主幹電極234a沿第一方向D1延伸。第二主幹電極234b沿第二方向D2延伸且與第一主幹電極234a交錯。分支電極234c電性連接第一主幹電極234a或第二主幹電極234b且往多個不同延伸方向延伸，其中分支電極234c的延伸方向不平行於第一方向D1與第二方向D2。 Similarly, the second sub-pixel unit 230 includes an active component 232 and at least one pixel electrode 234, wherein the pixel electrode 234 is electrically connected to the active component 232. The pixel electrode 234 can selectively include a first trunk electrode 234a, a second trunk electrode 234b, and a plurality of branch electrodes 234c. The first trunk electrode 234a extends in the first direction D1. The second stem electrode 234b extends in the second direction D2 and is interleaved with the first stem electrode 234a. The branch electrode 234c is electrically connected to the first main electrode 234a or the second main electrode 234b and extends in a plurality of different extending directions, wherein the extending direction of the branch electrode 234c is not parallel to the first direction D1 and the second direction D2.

同樣地，第三子畫素單元240分別包含主動元件242以及至少一畫素電極244。畫素電極244電性連接主動元件242，其中畫素電極244可選擇性的包含第一主幹電極244a、第二主幹電極244b以及多個分支電極244c。第一主幹電極244a沿第一方向D1延伸。第二主幹電極244b沿第二方向D2 延伸且與第一主幹電極244a交錯。分支電極244c電性連接第一主幹電極244a或第二主幹電極244b且往多個不同延伸方向延伸，其中分支電極244c的延伸方向不平行於第一方向D1與第二方向D2。 Similarly, the third sub-pixel unit 240 includes an active element 242 and at least one pixel electrode 244, respectively. The pixel electrode 244 is electrically connected to the active component 242, wherein the pixel electrode 244 can selectively include a first stem electrode 244a, a second stem electrode 244b, and a plurality of branch electrodes 244c. The first trunk electrode 244a extends in the first direction D1. The second trunk electrode 244b is along the second direction D2 It extends and is interleaved with the first stem electrode 244a. The branch electrode 244c is electrically connected to the first main electrode 244a or the second main electrode 244b and extends in a plurality of different extending directions, wherein the extending direction of the branch electrode 244c is not parallel to the first direction D1 and the second direction D2.

於此，每個第一主幹電極224a、234a、244a沿第二方向D2的兩側均設有與其連接的分支電極224c、234c、244c，第二主幹電極224b、234b、244b沿第一方向D1的兩側均設有與其連接的分支電極224c、234c、244c。於本實施方式中，每一畫素電極224、234、244之分支電極224c、234c、244c具有四個延伸方向，藉以有效地將液晶排列分為多域。 Here, each of the first trunk electrodes 224a, 234a, 244a is provided with branch electrodes 224c, 234c, 244c connected thereto along the second direction D2, and the second trunk electrodes 224b, 234b, 244b are along the first direction D1. Both sides are provided with branch electrodes 224c, 234c, 244c connected thereto. In the present embodiment, the branch electrodes 224c, 234c, and 244c of each of the pixel electrodes 224, 234, and 244 have four extending directions, thereby effectively dividing the liquid crystal alignment into a plurality of domains.

於本發明之部分實施方式中，第一子畫素單元220之畫素電極224的數量為二，第一子畫素單元220包含連接電極226以電性連接二個畫素電極224。於此，第二資料線DL2與第一掃描線SL1交錯，且第二資料線DL2與共通電極線CL交錯，以將第一子畫素區域SP1分割成第一分割區域PA與第二分割區域PB。二個畫素電極224分別位於第一分割區域PA與第二分割區域PB中。 In some embodiments of the present invention, the number of pixel electrodes 224 of the first sub-pixel unit 220 is two, and the first sub-pixel unit 220 includes a connection electrode 226 for electrically connecting the two pixel electrodes 224. Here, the second data line DL2 is interleaved with the first scan line SL1, and the second data line DL2 is interleaved with the common electrode line CL to divide the first sub-pixel area SP1 into the first divided area PA and the second divided area. PB. The two pixel electrodes 224 are respectively located in the first divided area PA and the second divided area PB.

同樣地，第二子畫素單元230之畫素電極234的數量為二，第二子畫素單元230包含連接電極236，以電性連接二個畫素電極234。於此，第二資料線DL2與共通電極線CL交錯，且第二資料線DL2與第二掃描線SL2交錯，以將第二子畫素區域SP2分割成第一分割區域PA與第二分割區域PB。二個畫素電極234分別位於第一分割區域PA與第二分割區域PB中。 Similarly, the number of the pixel electrodes 234 of the second sub-pixel unit 230 is two, and the second sub-pixel unit 230 includes the connection electrode 236 to electrically connect the two pixel electrodes 234. Here, the second data line DL2 is interleaved with the common electrode line CL, and the second data line DL2 is interleaved with the second scan line SL2 to divide the second sub-pixel area SP2 into the first divided area PA and the second divided area. PB. The two pixel electrodes 234 are respectively located in the first divided area PA and the second divided area PB.

同樣地，第三子畫素單元240之畫素電極244的數量為二，第三子畫素單元240包含連接電極246以電性連接二個畫素電極244。於此，第二資料線DL2與第二掃描線SL2交錯，且第二資料線DL2與下一個第一掃描線SL1交錯，以將第三子畫素區域SP3分割成第一分割區域PA與第二分割區域PB。二個畫素電極244分別位於第一分割區域PA與第二分割區域PB中。於本發明之部分實施方式中，每一畫素電極224、234、244之第一主幹電極224a、234a、244a大致位於其第一分割區域PA與第二分割區域PB的中央。 Similarly, the number of the pixel electrodes 244 of the third sub-pixel unit 240 is two, and the third sub-pixel unit 240 includes the connection electrode 246 to electrically connect the two pixel electrodes 244. Here, the second data line DL2 is interleaved with the second scan line SL2, and the second data line DL2 is interleaved with the next first scan line SL1 to divide the third sub-pixel area SP3 into the first divided area PA and the first Two divided areas PB. The two pixel electrodes 244 are respectively located in the first divided area PA and the second divided area PB. In some embodiments of the present invention, the first main electrodes 224a, 234a, 244a of each of the pixel electrodes 224, 234, 244 are located substantially at the center of the first divided area PA and the second divided area PB.

當主動元件陣列基板200應用於曲面型顯示面板時，顯示面板的上下基板的配向層提供多個定義域，由於各個定義域配向方向不同，當上下基板因彎曲而錯位時，而容易在定義域邊緣產生錯位區，而有黑羽毛現象。舉例而言，可能在第一主幹電極224a、234a、244a的一側或在第一分割區域PA與第二分割區域PB的一邊，產生黑羽毛現象。 When the active device array substrate 200 is applied to a curved display panel, the alignment layer of the upper and lower substrates of the display panel provides a plurality of definition domains. Since the alignment directions of the respective domains are different, when the upper and lower substrates are misaligned due to bending, the domain is easily defined. The edge produces a misaligned area with black feathers. For example, a black feather phenomenon may occur on one side of the first trunk electrode 224a, 234a, 244a or on one side of the first divided area PA and the second divided area PB.

於本發明之部分實施方式中，每一第一子畫素區域SP1、第二子畫素區域SP2以及第三子畫素區域SP3於第一方向D1具有第一長度L1且於第二方向D2具有第二長度L2，其中第一長度L1小於第二長度L2。亦即，各個第一子畫素區域SP1、第二子畫素區域SP2以及第三子畫素區域SP3沿著第二方向D2延伸。藉此，可以降低錯位區域的面積，改善黑羽毛現象。 In some embodiments of the present invention, each of the first sub-pixel area SP1, the second sub-pixel area SP2, and the third sub-pixel area SP3 has a first length L1 and a second direction D2 in the first direction D1. There is a second length L2, wherein the first length L1 is smaller than the second length L2. That is, each of the first sub-pixel area SP1, the second sub-pixel area SP2, and the third sub-pixel area SP3 extends along the second direction D2. Thereby, the area of the misaligned area can be reduced, and the black feather phenomenon can be improved.

舉例而言，於本實施方式中，各個畫素電極224、234、244的數量為二個，此時，可以設計二個畫素電極224 的二個第二主幹電極224b的長度之和大於二個畫素電極224的二個第一主幹電極224a的長度之和；二個畫素電極234的二個第二主幹電極234b的長度之和大於二個畫素電極234的二個第一主幹電極234a的長度之和；二個畫素電極244的二個第二主幹電極244b的長度之和大於二個畫素電極244的二個第一主幹電極244a的長度之和。如此一來，即使當基板210沿著第二方向D2彎曲而可能在第一主幹電極224a、234a、244a周邊因錯位而有黑羽毛現象，有鑑於第一主幹電極224a、234a、244a之和的長度小於第二主幹電極224b、234b、244b之和的長度，相較於縱向延伸的畫素電極配置，本實施方式的配置可以縮小錯位區域的面積，以減少黑羽毛現象對視覺效果的影響。於其他實施方式中，可以選擇性地設置各個畫素電極224、234、244的數量，並不以圖中所示為限。 For example, in the embodiment, the number of the pixel electrodes 224, 234, and 244 is two. In this case, the two pixel electrodes 224 can be designed. The sum of the lengths of the two second main electrodes 224b is greater than the sum of the lengths of the two first main electrodes 224a of the two pixel electrodes 224; the sum of the lengths of the two second main electrodes 234b of the two pixel electrodes 234 The sum of the lengths of the two first main electrodes 234a of the two pixel electrodes 234; the sum of the lengths of the two second main electrodes 244b of the two pixel electrodes 244 is greater than the two first of the two pixel electrodes 244 The sum of the lengths of the main electrodes 244a. As a result, even when the substrate 210 is bent along the second direction D2, there may be a black feather phenomenon due to the misalignment around the first trunk electrodes 224a, 234a, 244a, in view of the sum of the first stem electrodes 224a, 234a, 244a. The length is smaller than the length of the sum of the second main electrodes 224b, 234b, 244b. Compared to the longitudinally extending pixel electrode configuration, the configuration of the present embodiment can reduce the area of the misalignment area to reduce the influence of the black feather phenomenon on the visual effect. In other embodiments, the number of individual pixel electrodes 224, 234, 244 can be selectively set, and is not limited to the one shown in the figure.

於其他實施方式中，可以設置各個畫素電極224、234、244的數量為一個，每個畫素電極224、234、244的第二主幹電極224b、234b、244b的長度大於第一主幹電極224a、234a、244a的長度。 In other embodiments, the number of the respective pixel electrodes 224, 234, 244 may be set to one, and the length of the second trunk electrodes 224b, 234b, 244b of each of the pixel electrodes 224, 234, 244 is greater than the first trunk electrode 224a. , the length of 234a, 244a.

另一方面，於本發明之部分實施方式中，第一子畫素單元220、第二子畫素單元230、第三子畫素單元240可以包含遮蔽電極290，設計遮蔽電極290遮擋在第一分割區域PA與第二分割區域PB的一邊的錯位區域，以降低黑羽毛現象以免影響視覺效果。此外，遮蔽電極290還可設置於第二主幹電極224b、234b以及244b的下方，以在不影響視覺效果的情況下連接遮蔽電極片段(未標示)。遮蔽電極290的配置有許多種 可能，不應以圖中所繪而限制本發明之範圍。為方便繪示起見，第1A圖中並未繪示遮蔽電極290。 On the other hand, in some embodiments of the present invention, the first sub-pixel unit 220, the second sub-pixel unit 230, and the third sub-pixel unit 240 may include a shielding electrode 290, and the shielding electrode 290 is designed to be shielded at the first The misalignment area of one side of the area PA and the second division area PB is divided to reduce the black feather phenomenon so as not to affect the visual effect. In addition, the shielding electrode 290 may also be disposed under the second trunk electrodes 224b, 234b, and 244b to connect the shielding electrode segments (not labeled) without affecting the visual effect. There are many types of shielding electrodes 290 The scope of the invention should not be limited by the drawings. For convenience of illustration, the shielding electrode 290 is not shown in FIG. 1A.

於此，第一掃描線SL1、第二掃描線SL2以及共通電極線CL的間距大致相同，以使第一子畫素區域SP1、第二子畫素區域SP2以及第三子畫素區域SP3的寬度大致相同，但不應以此限制本發明之範圍。於部分實施方式中，第一掃描線SL1、第二掃描線SL2以及共通電極線CL的間距可以不同，以配合各種畫素結構設計。 Here, the pitches of the first scan line SL1, the second scan line SL2, and the common electrode line CL are substantially the same, such that the first sub-pixel area SP1, the second sub-pixel area SP2, and the third sub-pixel area SP3 The widths are substantially the same, but should not limit the scope of the invention. In some embodiments, the pitches of the first scan line SL1, the second scan line SL2, and the common electrode line CL may be different to match various pixel structure designs.

第1C圖為本發明之部分實施方式中彩色濾光片260與遮光層270的上視示意圖。同時參照第1A圖與第1C圖。於本發明之部分實施方式中，主動元件陣列基板200可包含彩色濾光片260以及遮光層270。彩色濾光片260對應畫素電極224、234、244設置。遮光層270定義前述之主動區AA與周邊線路區NA。遮光層270可為單層或多層結構，且其材料可以是黑色矩陣、至少二個不同色的彩色色阻堆疊而成或其它合適的材料，其可以藉由油墨印刷或曝光顯影而形成。 1C is a top plan view of the color filter 260 and the light shielding layer 270 in some embodiments of the present invention. Refer to both Figure 1A and Figure 1C. In some embodiments of the present invention, the active device array substrate 200 may include a color filter 260 and a light shielding layer 270. The color filter 260 is provided corresponding to the pixel electrodes 224, 234, and 244. The light shielding layer 270 defines the aforementioned active area AA and the peripheral line area NA. The light shielding layer 270 may be a single layer or a multilayer structure, and the material thereof may be a black matrix, a stack of at least two different color color resists or other suitable materials, which may be formed by ink printing or exposure development.

於本發明之部分實施方式中，彩色濾光片260包含紅色色阻262、綠色色阻264以及藍色色阻266。紅色色阻262對應第一子畫素區域SP1設置。綠色色阻264對應第二子畫素區域SP2設置。藍色色阻266對應第三子畫素區域SP3設置。藉此，可以操控穿過畫素區域PR的光的顏色。當然不應以此顏色順序分佈限制本發明之範圍，於其他實施方式中，可以設置藍色色阻對應第一子畫素區域SP1，綠色色阻對應第二子畫素區域SP2，紅色色阻對應第三子畫素區域SP3。於此， 遮光層270可覆蓋主動元件222、232、242、第一資料線DL1、第二資料線DL2、第三資料線DL3以及連接各個主動元件的電容(未標示)。於部份實施例中，遮光層270可選擇性的覆蓋共通電極線CL。 In some embodiments of the present invention, the color filter 260 includes a red color resist 262, a green color resist 264, and a blue color resist 266. The red color resist 262 is set corresponding to the first sub-pixel area SP1. The green color resist 264 is set corresponding to the second sub-pixel area SP2. The blue color resist 266 is set corresponding to the third sub-pixel area SP3. Thereby, the color of the light passing through the pixel area PR can be manipulated. Certainly, the range of the present invention should not be limited by the color sequence. In other embodiments, the blue color resistance may be set to correspond to the first sub-pixel area SP1, the green color resistance corresponds to the second sub-pixel area SP2, and the red color resistance corresponds to The third sub-pixel area SP3. herein, The light shielding layer 270 may cover the active elements 222, 232, 242, the first data line DL1, the second data line DL2, the third data line DL3, and a capacitor (not labeled) that connects the respective active components. In some embodiments, the light shielding layer 270 can selectively cover the common electrode line CL.

於此，採用彩色濾光層於陣列基板上(Color Filter on Array；COA)技術，即將彩色濾光層260與遮光層270設置於主動元件陣列基板200中，藉以改善傳統彩色濾光片基板與主動元件陣列基板對準不易的問題。當然不應以此為限，於本發明之其他實施方式中，仍可以將彩色濾光層260與遮光層270設置於對向基板300(請先行參閱第1D圖)。換句話說，主動元件陣列基板200上可不設有彩色濾光層260與遮光層270。 In this case, a color filter on Array (COA) technology is adopted, that is, the color filter layer 260 and the light shielding layer 270 are disposed in the active device array substrate 200, thereby improving the conventional color filter substrate and Active element array substrate alignment is not a problem. Of course, in this embodiment, the color filter layer 260 and the light shielding layer 270 may be disposed on the opposite substrate 300 (please refer to FIG. 1D first). In other words, the color filter layer 260 and the light shielding layer 270 may not be disposed on the active device array substrate 200.

第1D圖為沿第1A圖與第1C圖之線1D-1D之剖面示意圖。同時參照第1A圖、第1C圖與第1D圖。主動元件陣列基板200可以應用於液晶面板100中。具體而言，液晶面板100包含主動元件陣列基板200、對向基板300、液晶層400以及配向層(例如：垂直配向層，未繪示)。液晶層400設置於主動元件陣列基板200與對向基板300之間。配向層(例如：垂直配向層，未繪示)分別設置於液晶層400與主動元件陣列基板200之間以及液晶層400與對向基板300之間。於本實施方式中，主動元件陣列基板200更包含至少一間隙物280，間隙物280設置於彩色濾光片260上，其中間隙物280之頂端282連接對向基板300，用以支撐/維持液晶層400高度。 Fig. 1D is a schematic cross-sectional view taken along line 1D-1D of Fig. 1A and Fig. 1C. Reference is also made to FIG. 1A, FIG. 1C and FIG. 1D. The active device array substrate 200 can be applied to the liquid crystal panel 100. Specifically, the liquid crystal panel 100 includes an active device array substrate 200, a counter substrate 300, a liquid crystal layer 400, and an alignment layer (for example, a vertical alignment layer, not shown). The liquid crystal layer 400 is disposed between the active device array substrate 200 and the opposite substrate 300. An alignment layer (for example, a vertical alignment layer, not shown) is disposed between the liquid crystal layer 400 and the active device array substrate 200 and between the liquid crystal layer 400 and the opposite substrate 300, respectively. In the embodiment, the active device array substrate 200 further includes at least one spacer 280. The spacer 280 is disposed on the color filter 260. The top end 282 of the spacer 280 is connected to the opposite substrate 300 for supporting/maintaining the liquid crystal. Layer 400 height.

主動元件232包含半導體層AS、閘極(即圖中所 標的第二掃描線SL2)、閘極介電層GI以及連接半導體層AS兩端的汲極DE與源極SE。閘極介電層GI設置於主動元件232之閘極以及半導體層AS之間。主動元件232之閘極電性連接掃描線。主動元件232之源極SE電性連接第二資料線DL2。主動元件232之汲極DE透過絕緣層PL之開口O1電性連接連接電極236以及畫素電極234(參考第1A圖與第1B圖)。遮光層270可以填入絕緣層PL之開口O1中，以遮蔽不理想的光線。 The active device 232 includes a semiconductor layer AS and a gate (ie, in the figure) The target second scan line SL2), the gate dielectric layer GI, and the drain electrode DE and the source SE connected to both ends of the semiconductor layer AS. The gate dielectric layer GI is disposed between the gate of the active device 232 and the semiconductor layer AS. The gate of the active component 232 is electrically connected to the scan line. The source SE of the active component 232 is electrically connected to the second data line DL2. The drain electrode DE of the active device 232 is electrically connected to the connection electrode 236 and the pixel electrode 234 through the opening O1 of the insulating layer PL (refer to FIGS. 1A and 1B). The light shielding layer 270 may be filled in the opening O1 of the insulating layer PL to shield undesired light.

於本發明之部分實施方式中，主動元件232之汲極DE與共通電極線CL至少部分重疊，藉以產生電容以維持汲極DE之電位。汲極DE與共通電極線CL之重疊部分可與間隙物280重疊，藉以縮減不透光的範圍，以提升開口率。進一說明的是在本發明實施例中的重疊，例如指重直投影方向上的重疊。此外，雖然並未詳細說明，主動元件222、242的配置實質上大致如同主動元件232的配置，在此不再贅述。 In some embodiments of the present invention, the drain DE of the active device 232 at least partially overlaps the common electrode line CL, thereby generating a capacitance to maintain the potential of the drain DE. The overlapping portion of the drain electrode DE and the common electrode line CL may overlap with the spacer 280, thereby reducing the range of opacity to increase the aperture ratio. Further illustrated is the overlap in the embodiment of the invention, for example the overlap in the direction of the direct projection. Moreover, although not illustrated in detail, the configuration of the active elements 222, 242 is substantially similar to the configuration of the active elements 232 and will not be described herein.

於本發明之部分實施方式中，主動元件222、232、242可以是各種半導體元件，例如電晶體、二極體或其它合適的元件，且半導體元件的材料包含多晶矽、單晶矽、微晶矽、非晶矽、奈米碳管/桿、有機半導體材料、金屬氧化物半導體材料、或其它合適的材料、或前述至少二種的組合。本發明之主動元件222、232、242若為電晶體，其可為底閘型電晶體(例如：閘極位於半導體層AS之下方)、頂閘型電晶體(例如：閘極位於半導體層AS之上方)、多維通道型電晶體(例如：半導體層AS之載子流動路徑包含二個方向(例如：水平向與非水平向))、立體型電晶體(例如：閘極、源極SE與汲極DE其中 至少二者分別位於不同的水平面上)、或其它合適的電晶體。 In some embodiments of the present invention, the active components 222, 232, 242 may be various semiconductor components, such as transistors, diodes, or other suitable components, and the material of the semiconductor component includes polycrystalline germanium, single crystal germanium, and microcrystalline germanium. An amorphous germanium, a carbon nanotube/rod, an organic semiconductor material, a metal oxide semiconductor material, or other suitable material, or a combination of at least two of the foregoing. The active device 222, 232, 242 of the present invention is a transistor, which may be a bottom gate type transistor (for example, the gate is located below the semiconductor layer AS), and a top gate type transistor (for example, the gate is located at the semiconductor layer AS) Above), multi-dimensional channel type transistor (for example, the carrier flow path of the semiconductor layer AS includes two directions (for example, horizontal direction and non-horizontal direction)), and a stereo type transistor (for example: gate, source SE and Bungee DE At least two are located at different levels, respectively, or other suitable transistors.

於此，液晶面板100可以採用多域分割垂直配向技術(multi-domain vertical alignment，MVA)。具體而言，液晶層400的上下設置有配向層(例如：垂直配向膜，未標示)，配向層(例如：垂直配向膜，未標示)可以針對液晶分子提供配向力(例如：垂直配向力)，又可搭配電極提供多個定義域不同的預傾角，而使液晶層400內可包含多個定義域(domain)，以達到多域分割垂直配向技術。舉例而言，垂直配向層可由聚合物穩定材料形成。理想上，液晶層400之任意區域的上下二個垂直配向層具有相同的配向方向。然而實際上，液晶層400之某些區域的上下二個垂直配向層具有不同的配向方向，即文中所指的錯位區域。當然不應以此多域分割垂直配向技術限制本發明之範圍，於其他實施方式中，亦可採用他種液晶面板100。 Here, the liquid crystal panel 100 may employ a multi-domain vertical alignment (MVA). Specifically, the liquid crystal layer 400 is provided with an alignment layer (for example, a vertical alignment film, not shown), and an alignment layer (for example, a vertical alignment film, not shown) can provide an alignment force (for example, a vertical alignment force) for the liquid crystal molecules. In addition, the electrode can be provided with different pre-tilt angles of multiple domains, and the liquid crystal layer 400 can include multiple domains to achieve multi-domain segmentation vertical alignment technology. For example, the vertical alignment layer can be formed from a polymer stabilizing material. Ideally, the upper and lower vertical alignment layers of any region of the liquid crystal layer 400 have the same alignment direction. In practice, however, the upper and lower vertical alignment layers of certain regions of the liquid crystal layer 400 have different alignment directions, i.e., the misalignment regions referred to herein. Of course, this multi-domain split vertical alignment technique should not be used to limit the scope of the present invention. In other embodiments, other types of liquid crystal panel 100 may also be used.

於本發明之部分實施方式中，液晶面板100可以是曲面型顯示面板，例如對向基板300與主動元件陣列基板200皆朝某一方向彎曲。或者，於其他實施方式中，液晶面板100可以是平面顯示面板。 In some embodiments of the present invention, the liquid crystal panel 100 may be a curved display panel, for example, the opposite substrate 300 and the active device array substrate 200 are bent in a certain direction. Alternatively, in other embodiments, the liquid crystal panel 100 may be a flat display panel.

於本發明之部分實施方式中，主動元件陣列基板200之基板210與對向基板300其中一者的材料可包含玻璃、石英、聚合物材料(例如：聚亞醯胺(PI)、苯並環丁烯(benzocyclobutene；BCB)、聚碳酸酯(PC)、或其它合適的材料)、或其它合適的材料、或前述至少二種之組合。顯示介質層的材料包含自發光材料(例如：有機發光材料、無機發光材料、或其它合適的材料、或前述之組合)或非自發光材料(例 如：液晶、電泳、電濕潤、或其它合適的材料、或前述之組合)。 In some embodiments of the present invention, the material of one of the substrate 210 and the opposite substrate 300 of the active device array substrate 200 may include glass, quartz, and a polymer material (eg, polyamidamine (PI), benzo ring). Benzocyclobutene (BCB), polycarbonate (PC), or other suitable material), or other suitable material, or a combination of at least two of the foregoing. The material of the display dielectric layer comprises a self-luminous material (for example: an organic light-emitting material, a phosphor, or other suitable material, or a combination thereof) or a non-self-luminous material (for example) Such as: liquid crystal, electrophoresis, electrowetting, or other suitable materials, or a combination of the foregoing.

絕緣層PL與閘極介電層GI可為單層或多層結構，且其材料包含(例如：氧化矽、氮化矽、氮氧化矽、或其它合適的材料)、有機材料(例如：光阻、聚亞醯胺(polyimide；PI)、苯並環丁烯(benzocyclobutene；BCB)、或其它合適的材料)、或其它合適的材料。 The insulating layer PL and the gate dielectric layer GI may be a single layer or a multilayer structure, and the material thereof includes (for example, hafnium oxide, tantalum nitride, hafnium oxynitride, or other suitable materials), and an organic material (for example, photoresist). , polyimide (PI), benzocyclobutene (BCB), or other suitable materials), or other suitable materials.

於本發明之部分實施方式中，各個資料線DL1~DL3、掃描線SL1~SL2以及共通電極線CL可以是各種導電性良好的材料，例如金屬、合金、導電膠或其它合適的材料，或前述至少二種之組合。畫素電極224~244以及連接電極226~246可由同一材料層經圖案化而形成，其中該材料層可以由各種導電性與透明性良好的材料所組成，例如氧化銦錫。於其它實施例中，畫素電極224~244以及連接電極226~246可由不同材料層經圖案化而成。 In some embodiments of the present invention, each of the data lines DL1 to DL3, the scan lines SL1 to SL2, and the common electrode line CL may be various materials having good electrical conductivity, such as metals, alloys, conductive pastes, or other suitable materials, or the foregoing. A combination of at least two. The pixel electrodes 224-244 and the connection electrodes 226-246 may be formed by patterning the same material layer, wherein the material layer may be composed of various materials having good conductivity and transparency, such as indium tin oxide. In other embodiments, the pixel electrodes 224-244 and the connection electrodes 226-246 may be patterned by different material layers.

第1E圖為沿第1A圖與第1C圖之線1E-1E之剖面示意圖。同時參照第1A圖、第1C圖與第1E圖。遮光層270設置於相鄰兩個畫素區域PR之間，覆蓋第一資料線DL1與第三資料線DL3以及兩者之間的間隙，以較佳地區別兩個畫素區域PR。於此，遮蔽電極290於基板210的投影至少部份位於遮光層270於基板210的投影之外，藉以增加遮蔽的區域，並確保第一資料線DL1與第三資料線DL3的電場不會竄出影響液晶排列。 Fig. 1E is a schematic cross-sectional view taken along line 1E-1E of Fig. 1A and Fig. 1C. Reference is also made to FIGS. 1A, 1C, and 1E. The light shielding layer 270 is disposed between the adjacent two pixel regions PR, covering the gap between the first data line DL1 and the third data line DL3 and the two to better distinguish the two pixel regions PR. Herein, the projection of the shielding electrode 290 on the substrate 210 is at least partially located outside the projection of the light shielding layer 270 on the substrate 210, thereby increasing the area of the shielding and ensuring that the electric fields of the first data line DL1 and the third data line DL3 are not collapsed. Affect the liquid crystal alignment.

第2圖為根據本發明之另一實施方式之單個畫素區域PR之上視示意圖。於本實施方式與第1B圖的實施方式相 似，差別在於：於本實施方式中，每一畫素電極224、234、244並不包含第一主幹電極224a、234a、244a(參照第1B圖)，且每一畫素電極224、234、244之分支電極224c、234c、244c具有二個延伸方向。 2 is a top plan view of a single pixel region PR in accordance with another embodiment of the present invention. In this embodiment, the embodiment of FIG. 1B is The difference is that in the present embodiment, each of the pixel electrodes 224, 234, and 244 does not include the first trunk electrodes 224a, 234a, and 244a (refer to FIG. 1B), and each of the pixel electrodes 224, 234, The branch electrodes 224c, 234c, 244c of 244 have two extending directions.

於部分實施方式中，為了以多域方式有效地控制液晶，畫素電極224、234、244的數量可能是複數個，分布在第一子畫素區域SP1、第二子畫素區域SP2以及第三子畫素區域SP3的不同區域，此時，可以設計畫素電極224、234、244不包含第一主幹電極224a、234a、244a(參照第1B圖)。如此一來，即使當基板210沿著第二方向D2彎曲而可能因錯位而有黑羽毛現象，有鑑於畫素電極224、234、244不包含第一主幹電極224a、234a、244a，且已設計遮蔽電極290遮擋在第一分割區域PA與第二分割區域PB的一邊的錯位區域，因此可以縮小錯位區域的面積，以減少黑羽毛現象對視覺效果的影響。 In some embodiments, in order to effectively control the liquid crystal in a multi-domain manner, the number of pixel electrodes 224, 234, 244 may be plural, distributed in the first sub-pixel region SP1, the second sub-pixel region SP2, and the first In the different regions of the three sub-pixel regions SP3, at this time, the pixel electrodes 224, 234, and 244 can be designed not to include the first main electrodes 224a, 234a, and 244a (see FIG. 1B). As a result, even when the substrate 210 is bent along the second direction D2, there may be a black feather phenomenon due to the misalignment, in view of the fact that the pixel electrodes 224, 234, 244 do not include the first stem electrodes 224a, 234a, 244a, and have been designed. The shielding electrode 290 blocks the misalignment region on one side of the first divided region PA and the second divided region PB, so that the area of the misaligned region can be reduced to reduce the influence of the black feather phenomenon on the visual effect.

本實施方式的其他細節大致上如前所述，在此不在贅述。 Other details of the present embodiment are substantially as described above, and are not described herein.

本發明之部分實施方式提供一種主動元件陣列基板及應用其之液晶面板，透過設計子畫素的長邊平行於液晶面板的長邊，縮小因上下基板錯位而液晶排列錯亂的區域。此外，本實施方式還透過同一閘極訊號與不同的資料訊號，供給第一子畫素單元220、第二子畫素單元230以及第三子畫素單元240有各自的操作電壓，而呈現預期的亮度，此作法可以提升各個子畫素單元的供電時間，確保其子畫素單元內的主動元件充電充足。 Some embodiments of the present invention provide an active device array substrate and a liquid crystal panel using the same, wherein the long side of the sub-pixel is parallel to the long side of the liquid crystal panel, and the area where the liquid crystal is disordered due to the displacement of the upper and lower substrates is reduced. In addition, the present embodiment also provides the first sub-pixel unit 220, the second sub-pixel unit 230, and the third sub-pixel unit 240 with respective operating voltages through the same gate signal and different data signals, and presents an expected The brightness, this method can improve the power supply time of each sub-pixel unit, to ensure that the active components in its sub-pixel unit are fully charged.

雖然本發明已以多種實施方式揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 While the invention has been described above in terms of various embodiments, it is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application attached.

200‧‧‧主動元件陣列基板 200‧‧‧Active component array substrate

210‧‧‧基板 210‧‧‧Substrate

220‧‧‧第一子畫素單元 220‧‧‧ first sub-pixel unit

230‧‧‧第二子畫素單元 230‧‧‧ second sub-pixel unit

240‧‧‧第三子畫素單元 240‧‧‧ third sub-pixel unit

250‧‧‧閘極驅動器 250‧‧‧gate driver

280‧‧‧間隙物 280‧‧ ‧ spacers

D1‧‧‧第一方向 D1‧‧‧ first direction

D2‧‧‧第二方向 D2‧‧‧ second direction

L1‧‧‧第一長度 L1‧‧‧ first length

DL3‧‧‧第三資料線 DL3‧‧‧ third data line

SL1‧‧‧第一掃描線 SL1‧‧‧ first scan line

SL2‧‧‧第二掃描線 SL2‧‧‧Second scan line

SP1‧‧‧第一子畫素區域 SP1‧‧‧ first sub-pixel area

SP2‧‧‧第二子畫素區域 SP2‧‧‧Second sub-pixel area

SP3‧‧‧第三子畫素區域 SP3‧‧‧ Third sub-pixel area

AA‧‧‧主動區 AA‧‧‧Active Area

NA‧‧‧周邊線路區 NA‧‧‧ surrounding area

CL‧‧‧共通電極線 CL‧‧‧Common electrode line

PR‧‧‧畫素區域 PR‧‧‧ pixel area

L2‧‧‧第二長度 L2‧‧‧ second length

DL1‧‧‧第一資料線 DL1‧‧‧ first data line

DL2‧‧‧第二資料線 DL2‧‧‧ second data line

1D-1D‧‧‧線 1D-1D‧‧‧ line

1E-1E‧‧‧線 Line 1E-1E‧‧

Claims (15)

一種主動元件陣列基板，包含：一基板，具有一主動區與設置於該主動區之至少一側的一周邊線路區；至少一第一資料線、至少一第二資料線以及至少一第三資料線，沿一第一方向延伸且設置於該基板上；複數個第一掃描線，沿一第二方向延伸且設置於該基板上，其中該第一方向不平行於該第二方向，其中該第一資料線與該些第一掃描線之相鄰之一第一者與一第二者交錯，且該第三資料線與該些第一掃描線之相鄰之該第一者與該第二者交錯，以定義該基板上該主動區內之至少一畫素區域，其中該第二資料線位於該第一資料線與該第三資料線之間，且通過該畫素區域；至少一第二掃描線以及至少一共通電極線，沿該第二方向延伸且設置於該基板上，其中該第一資料線與該第二掃描線以及該共通電極線交錯，且該第三資料線與該第二掃描線以及該共通電極線交錯，以定義該畫素區域內之一第一子畫素區域、一第二子畫素區域以及一第三子畫素區域；至少一第一子畫素單元，設置於該第一子畫素區域且電性連接該第一資料線與該些第一掃描線之該第一者；至少一第二子畫素單元，設置於該第二子畫素區域且電性連接該第二資料線與該第二掃描線；以及至少一第三子畫素單元，設置於該第三子畫素區域且電性連接該第三資料線與該第二掃描線。 An active device array substrate includes: a substrate having an active area and a peripheral line area disposed on at least one side of the active area; at least one first data line, at least one second data line, and at least one third data a line extending along a first direction and disposed on the substrate; a plurality of first scan lines extending along a second direction and disposed on the substrate, wherein the first direction is not parallel to the second direction, wherein the line The first data line and the first one of the first scan lines are interlaced with a second one, and the first data line and the first data line are adjacent to the first one of the first scan lines Interlaced to define at least one pixel region in the active region on the substrate, wherein the second data line is located between the first data line and the third data line, and passes through the pixel region; at least one a second scan line and at least one common electrode line extending along the second direction and disposed on the substrate, wherein the first data line is interlaced with the second scan line and the common electrode line, and the third data line is The second scan line and the common The polar lines are interlaced to define a first sub-pixel region, a second sub-pixel region, and a third sub-pixel region in the pixel region; at least one first sub-pixel unit is disposed at the first a sub-pixel region electrically connected to the first data line and the first one of the first scan lines; at least one second sub-pixel unit disposed in the second sub-pixel region and electrically connected to the first The second data line and the second scan line; and the at least one third sub-pixel unit are disposed in the third sub-pixel area and electrically connected to the third data line and the second scan line. 如請求項1所述之主動元件陣列基板，其中每一該第一子畫素區域、該第二子畫素區域以及該第三子畫素區域於該第一方向具有一第一長度且於該第二方向具有一第二長度，其中該第一長度小於該第二長度。 The active device array substrate of claim 1, wherein each of the first sub-pixel region, the second sub-pixel region, and the third sub-pixel region have a first length in the first direction and The second direction has a second length, wherein the first length is less than the second length. 如請求項1所述之主動元件陣列基板，其中該些第一掃描線與該第二掃描線延伸至該周邊線路區，該些第一掃描線之該第一者與該第二掃描線電性連接。 The active device array substrate of claim 1, wherein the first scan lines and the second scan lines extend to the peripheral line region, the first one of the first scan lines and the second scan line Sexual connection. 如請求項3所述之主動元件陣列基板，更包含一閘極驅動器，位於該基板之該周邊線路區，其中該閘極驅動器包含至少一腳位，其中該些第一掃描線之該第一者與該第二掃描線電性連接至同一該腳位。 The active device array substrate of claim 3, further comprising a gate driver located in the peripheral circuit region of the substrate, wherein the gate driver includes at least one pin, wherein the first of the first scan lines The second scan line is electrically connected to the same pin. 如請求項1所述之主動元件陣列基板，其中每一該第一子畫素單元、該第二子畫素單元以及該第三子畫素單元包含一主動元件以及至少一畫素電極，其中該畫素電極電性連接該主動元件，其中該畫素電極包含：一第一主幹電極，沿該第二方向延伸；以及複數個分支電極，電性連接該第一主幹電極且往複數個不同延伸方向延伸，其中該些延伸方向不平行於該第一方向與該第二方向。 The active device array substrate according to claim 1, wherein each of the first sub-pixel unit, the second sub-pixel unit, and the third sub-pixel unit comprises an active component and at least one pixel electrode, wherein The pixel electrode is electrically connected to the active device, wherein the pixel electrode comprises: a first main electrode extending along the second direction; and a plurality of branch electrodes electrically connected to the first main electrode and reciprocating a plurality of different The extending direction extends, wherein the extending directions are not parallel to the first direction and the second direction. 如請求項5所述之主動元件陣列基板，其中該畫素電極更包含：一第二主幹電極，沿該第一方向延伸，且與該第一主幹電極交錯。 The active device array substrate of claim 5, wherein the pixel electrode further comprises: a second main electrode extending in the first direction and interlaced with the first main electrode. 如請求項5所述之主動元件陣列基板，其中該第二資料線與該些第一掃描線之該第一者與該第二者交錯，以定義每一該第一子畫素區域、該第二子畫素區域以及該第三子畫素區域之一第一分割區域與一第二分割區域，其中每一該第一子畫素單元、該第二子畫素單元以及該第三子畫素單元之該畫素電極的數量為二，該些畫素電極分別位於該第一分割區域與該第二分割區域，每一該第一子畫素單元、該第二子畫素單元以及該第三子畫素單元包含一連接電極，以電性連接分別位於該第一分割區與該第二分割區域的該些畫素電極。 The active device array substrate of claim 5, wherein the first data line and the first one of the first scan lines are interlaced with the second one to define each of the first sub-pixel regions, a second sub-pixel region and a first segment region of the third sub-pixel region and a second segment region, wherein each of the first sub-pixel unit, the second sub-pixel unit, and the third sub- The number of the pixel electrodes of the pixel unit is two, and the pixel electrodes are respectively located in the first divided area and the second divided area, each of the first sub-pixel unit, the second sub-pixel unit, and The third sub-pixel unit includes a connection electrode electrically connected to the pixel electrodes respectively located in the first division area and the second division area. 如請求項7所述之主動元件陣列基板，其中每一該些畫素電極之該些分支電極具有二個該些延伸方向。 The active device array substrate according to claim 7, wherein the branch electrodes of each of the pixel electrodes have two extending directions. 如請求項7所述之主動元件陣列基板，其中每一該些畫素電極之該些分支電極具有四個該些延伸方向。 The active device array substrate of claim 7, wherein the branch electrodes of each of the pixel electrodes have four of the extending directions. 如請求項1所述之主動元件陣列基板，其中每一該第一子畫素單元、該第二子畫素單元以及該第三子畫 素單元包含一主動元件以及一畫素電極，其中該畫素電極電性連接該主動元件，其中該主動元件陣列基板更包含：一彩色濾光片，包含：一紅色色阻，對應該第一子畫素區域之該畫素電極設置；一綠色色阻，對應該第二子畫素區域之該畫素電極設置；以及一藍色色阻，對應該第三子畫素區域之該畫素電極設置；以及一遮光層，覆蓋該主動元件。 The active device array substrate according to claim 1, wherein each of the first sub-pixel unit, the second sub-pixel unit, and the third sub-picture The element unit includes an active component and a pixel electrode, wherein the pixel electrode is electrically connected to the active component, wherein the active component array substrate further comprises: a color filter, comprising: a red color resist, corresponding to the first a pixel electrode of the subpixel region; a green color resist corresponding to the pixel electrode of the second subpixel region; and a blue color resist corresponding to the pixel electrode of the third subpixel region a setting; and a light shielding layer covering the active component. 一種液晶面板，包含：如請求項1所述之主動元件陣列基板；一對向基板；一液晶層，設置於該主動元件陣列基板與該對向基板之間；以及二垂直配向層，分別設置於該液晶層與該主動元件陣列基板之間以及該液晶層與該對向基板之間。 A liquid crystal panel comprising: the active device array substrate according to claim 1; a pair of substrates; a liquid crystal layer disposed between the active device array substrate and the opposite substrate; and two vertical alignment layers respectively disposed Between the liquid crystal layer and the active device array substrate and between the liquid crystal layer and the opposite substrate. 如請求項11所述之液晶面板，其中該垂直配向層由聚合物穩定材料所形成。 The liquid crystal panel of claim 11, wherein the vertical alignment layer is formed of a polymer stabilizing material. 如請求項11所述之液晶面板，其中每一該第一子畫素單元、該第二子畫素單元以及該第三子畫素單元 包含一主動元件以及一畫素電極，其中該畫素電極電性連接該主動元件，其中該主動元件陣列基板更包含：一彩色濾光片，對應該畫素電極設置；一遮光層，對應該主動元件設置；以及至少一間隙物，設置於該彩色濾光片上，其中該間隙物之頂端連接該對向基板。 The liquid crystal panel of claim 11, wherein each of the first sub-pixel unit, the second sub-pixel unit, and the third sub-pixel unit An active component and a pixel electrode, wherein the pixel electrode is electrically connected to the active component, wherein the active component array substrate further comprises: a color filter disposed corresponding to the pixel electrode; a light shielding layer corresponding to The active component is disposed; and at least one spacer is disposed on the color filter, wherein a top end of the spacer is connected to the opposite substrate. 如請求項11所述之液晶面板，其中該主動元件陣列基板之該基板與該對向基板沿該第二方向彎曲。 The liquid crystal panel of claim 11, wherein the substrate of the active device array substrate and the opposite substrate are bent in the second direction. 如請求項11所述之液晶面板，其中每一該第一子畫素區域、該第二子畫素區域以及該第三子畫素區域於該第一方向具有一第一長度且於該第二方向具有一第二長度，其中該第一長度小於該第二長度。 The liquid crystal panel of claim 11, wherein each of the first sub-pixel area, the second sub-pixel area, and the third sub-pixel area have a first length in the first direction and The two directions have a second length, wherein the first length is less than the second length.
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