TWI589116B - A system and method of driving a power transistor - Google Patents

Description

System and method for driving power transistor

The present invention relates to the field of circuits, and more particularly to systems and methods for driving power transistors.

In recent years, with the rapid development of the electronics industry and integrated circuits, countries are increasingly demanding energy consumption for electronic products. In the field of low-power power converters, Bipolar Power Transistor (referred to as power transistor) is widely used with good switching characteristics and low price. In order to meet the energy consumption standard, it is desirable to reduce the loss of the driving circuit for the power transistor and improve the efficiency of the driving circuit.

In the existing driving circuit for a power transistor, a fixed driving current is used to drive the power transistor regardless of the input voltage level. In this way, it is easy to occur that when the input voltage is low, the input electric charge of the power transistor is excessive due to the long conduction time, and the power transistor can easily enter the deep saturated working state, thereby causing the power transistor to turn off slowly. The turn-off loss rises; when the input voltage is high, the input capacitance of the power transistor is insufficient due to the short on-time, and the power transistor does not enter a saturated operating state, thereby causing the conduction loss of the power transistor to rise. In both cases, the power consumption of the drive circuit for the power transistor is relatively high.

In view of the problems described above, the present invention provides a novel system and method for driving a power transistor.

According to an aspect of the present disclosure, a system for driving a power transistor is provided, comprising: a ratio conversion circuit configured to characterize a flow through a power transistor using a first conversion ratio or a second conversion ratio pair based on a first control signal The first characterization signal of the current is turned And generating a second characterization signal; and a switch driving circuit configured to generate a driving signal for controlling conduction and deactivation of the power transistor based on the second control signal, the third control signal, and the second characterization signal, wherein the proportional conversion circuit Converting the first characterization signal with the first conversion ratio when the first control signal is at a high level, and converting the first characterization signal with the second conversion ratio when the first control signal is at a low level, the switch driving circuit is in the second control The first predetermined signal is used as the driving signal in the first period in which the signal is at the high level and the third control signal is in the low level, and the second is in the second period in which the second control signal is at the high level and the third control signal is in the low level The characterization signal is used as a drive signal, and the second predetermined signal is used as a drive signal when both the second control signal and the third control signal are at a high level.

In accordance with another aspect of the present disclosure, a method of driving a power transistor is provided, comprising: utilizing a first conversion ratio or a second conversion ratio pair to characterize a first characterization signal of a current flowing through a power transistor based on a first control signal Performing a conversion to generate a second characterization signal; and generating a driving signal for controlling the on and off of the power transistor based on the second control signal, the third control signal, and the second characterization signal, wherein the first control signal is utilized when the first control signal is at a high level The first conversion ratio converts the first characterization signal, and converts the first characterization signal with the second conversion ratio when the first control signal is at a low level, the second control signal is at a high level and the third control signal is at a low level The first predetermined signal is used as the driving signal in the first period, the second characterization signal is used as the driving signal in the second period in which the second control signal is at the high level, and the second control signal is in the low level, and in the second control signal The second predetermined signal is used as the driving signal when both the third control signal and the third control signal are at a high level.

A system and method for controlling a power transistor based on on-time control in accordance with embodiments of the present application provides a way to drive a power transistor at a lower power loss. One or more benefits may also be obtained depending on the embodiment. These and other additional objects, features and advantages of the present invention will be fully understood from the description and appended claims.

100‧‧‧ system

101‧‧‧ Pulse wave generation circuit

102‧‧‧Switch drive circuit

103‧‧‧ Bias current circuit

104‧‧‧K1/K2 ratio conversion circuit

105‧‧‧Fixed on-time generation circuit

106‧‧‧One winding inductance

107‧‧‧Power transistor

108‧‧‧Sampling resistor

200‧‧‧flow chart

300, 400‧‧‧ Timing Chart

201, 202, 203‧ ‧ steps

t ₀ , t ₁ , t ₂ , t ₃ , t ₄ ‧‧‧ time

301, 302, 303, 304, 401, 402, 403, 404‧‧‧ waveforms

PWM‧‧‧ Pulse Switch Signal

PWM_PRE‧‧‧ pre-shutdown signal

PWM_ON‧‧‧PWM on time

T _{ON_TH ‧‧‧Fixed} on time

Re‧‧‧ bias resistor

V _IN ‧‧‧ input voltage

V _CS ‧‧‧ voltage signal

I _B ‧‧‧bias current signal

I _CS ‧‧‧current signal

I _{pusle ‧‧‧pulse} drive current

I _BASE ‧‧‧base drive current signal

In the following, features, advantages and techniques of an exemplary embodiment of the present invention will be described with reference to the drawings. The effect is described in the drawings, like reference numerals designate like elements, in which: FIG. 1 is a block diagram showing a system for controlling a power transistor based on on-time control, in accordance with an embodiment of the present disclosure.

2 is a flow chart showing a method of controlling a driving power transistor based on an on-time according to an embodiment of the present disclosure.

3 is a simplified timing diagram showing a timing relationship of respective signals and a base current of a power transistor in a method of controlling a driving power transistor based on an on-time according to an embodiment of the present disclosure.

4 is a simplified timing diagram showing another timing relationship of respective signals with a base current of a power transistor in a method of controlling a driving power transistor based on an on-time according to an embodiment of the present disclosure.

Features and exemplary embodiments of various aspects of the invention are described in detail below. In the following detailed description, numerous specific details are set forth However, it will be apparent to those skilled in the art that the present invention may be practiced without some of the details. The following description of the embodiments is merely provided to provide a better understanding of the invention. The present invention is in no way limited to any specific configurations and algorithms presented below, but without departing from the spirit and scope of the invention. In the drawings and the following description, well-known structures and techniques are not shown in order to avoid unnecessary obscuring the invention.

FIG. 1 is a block diagram showing a system for driving a power transistor according to an embodiment of the present invention. As shown in FIG. 1, the system 100 for driving a power transistor includes a switch driving circuit 102, a sampling voltage K1/K2 ratio conversion circuit 104, and optionally includes a pulse wave generating circuit 101, a bias current circuit 103, and a fixed conduction. Time generation circuit 105. In addition, the system can also include a primary winding inductance 106 of the transformer, a power transistor 107, and a sampling resistor 108.

In one example, power transistor 107 is a bipolar junction transistor. in In another example, the power transistor 107 is a field effect transistor (eg, a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET)). In yet another example, the power transistor 107 is an insulated gate bipolar transistor (IGBT). In various examples, the biasing circuit tends to have several components, wherein the resistance value of the biasing resistor Re can be set as desired by those skilled in the art.

As shown in Fig. 1, the pulse wave generating circuit 101 is coupled to the switch drive circuit 102, the bias current circuit 103, the K1/K2 ratio conversion circuit 104, and the base of the power transistor 107. The switch drive circuit 102 is coupled to the pulse wave generating circuit 101, the bias current circuit 103, and the K1/K2 ratio conversion circuit 104. The bias current circuit 103 is coupled to the pulse wave generating circuit 101 and the switch driving circuit 102. The K1/K2 ratio conversion circuit 104 is coupled to the pulse wave generation circuit 101, the switch drive circuit 102, the fixed on-time generation circuit 105, and the sampling resistor 108. One end of the primary winding inductor 106 is coupled to the collector of the power transistor 107, and the other end is coupled to the input voltage V _{IN of the} switching power supply. The base of the power transistor 107 is coupled to the pulse wave generating circuit 101, the collector is coupled to one end of the primary winding inductor 106, and the emitter is coupled to one end of the sampling resistor 108. One end of the sampling resistor 108 is coupled to the emitter of the power transistor 107, and the other end is grounded.

According to some embodiments, the switch drive circuit 102 receives a Pulse Width Modulation (PWM) signal/pre-shutdown signal (PWM_PRE) from the pulse wave generation circuit 101, and a bias current signal I from the bias current circuit 103. _B , and the current signal I _CS from the K1/K2 ratio conversion circuit 104. The switch drive circuit 102 can generate a base drive current signal I _BASE based on the received pulse switching signal PWM/PWM_PRE, the bias current signal I _{B ,} and the ramp current signal I _CS to control the turn-on and turn-off of the power transistor 107.

The switching power supply is sampled on the sampling resistor 106, and the resulting voltage signal V _CS is input to the K1/K2 ratio conversion circuit 104. The K1/K2 ratio conversion circuit 104 then converts the voltage signal V _CS into a ramp current signal I _{CS at a} different K1/K2 ratio. Specifically, if the on-time PWM_ON of the pulse wave switching signal PWM is less than the fixed on-time T _{ON_TH} (eg, the on-time threshold), the K1/K2 ratio conversion circuit 104 converts V _CS into I _CS in a K1 ratio, and if the pulse wave The on-time PWM_ON of the switching signal PWM is greater than the fixed on-time T _{ON_TH} , and the K1/K2 ratio conversion circuit 104 first converts V _CS by a larger K1 ratio, and then further converts to I _CS with a smaller K2 ratio, where K1 The ratio is larger in magnitude than the K2 ratio; and wherein the fixed on-time T _{ON_TH} is a threshold time that can be predefined according to actual conditions.

Therefore, when the system input voltage V _{IN is} high, since the PWM on-time PWM_ON is shorter than the fixed on-time T _{ON_TH} , V _CS can be converted to I _CS by using a large K1 ratio, and the larger I _CS can ensure that the base input charge is sufficient. Power transistor 107 enters a saturated operating state, reducing power transistor conduction losses. When the system input voltage V _{IN is} low, since the PWM on-time PWM_ON is much longer than the fixed on-time T _{ON_TH} , V _{CS is} first converted with a larger K1 ratio, and then further converted to I _CS with a smaller K2 ratio. The smaller I _CS produced by this conversion ensures that the base input charge is not left, reducing the drive loss of the power transistor 107.

2 is a flow chart showing a method of controlling a driving power transistor based on an on-time according to an embodiment of the present disclosure. This figure is only an example and should not unduly limit the scope of patent application. Many variations, alternatives, and modifications will be apparent to those of ordinary skill in the art.

The method begins in step 201 by receiving a pulse width modulated PWM signal and a sampled voltage signal V _CS from the emitter of the power transistor; and then at step 202, converting the voltage signal V _CS to a current signal I _CS . Wherein if the PWM on-time PWM_ON less than the on-time threshold, the voltage signal V _CS conversion press K1 proportional to current signal I _CS, and if PWM_ON than the turn on time threshold value, the first voltage signal V _CS press K1 scale conversion, followed by Further converted to a current signal I _CS in a K2 ratio, wherein the K1 ratio is larger in magnitude than the K2 ratio.

The method then proceeds to step 203 to receive the PWM signal, the bias current signal I _B , and the current signal I _CS , and generate a base drive current signal I _BASE based at least in part on the current signal I _CS to drive the power transistor.

3 is a simplified timing diagram 300 showing a timing relationship of respective signals to a base current of a power transistor in a method of driving a power transistor based on on-time control, in accordance with an embodiment of the present disclosure. This figure is only an example and should not unduly limit the scope of patent application. Many variations, alternatives, and modifications will be apparent to those of ordinary skill in the art. As shown in FIG. 3, waveform 301 represents a fixed on-time T _{ON_TH} , waveform 302 represents a PWM signal that changes with time, waveform 303 represents a PWM_PRE signal that changes with time, and waveform 304 represents a base drive current signal I that changes with time. _BASE .

Figure 3 shows the signal timing when the system input voltage V _{IN is} high. Wherein for the on-time period and the off-time period associated with the PWM signal, the on-time period PWN_ON starts at time t ₀ and ends at time t ₃ . For example, t ₀ t ₁ t ₂ t ₃ t ₄ . Wherein, according to the relationship between the base current and the emitter current of the power diode, the relationship between the voltage V _CS sampled by the sampling resistor (for example, the sampling resistor 108) and the base driving current signal I _BASE can be expressed as follows: V _CS = (1 + β) × I _BASE × R (Equation 1)

Where β represents the quiescent current amplification factor of the power transistor (eg, power transistor 107) and R represents the resistance value of the sense resistor.

According to one embodiment, at t ₀ , the PWM signal changes from a logic low level to a logic high level, and in response, the base drive current signal I _{BASE is} abruptly changed to a fixed time width pulse drive current I _pusle , eg, I _pusle The high level duration can be t ₀ ~ t ₁ . Since the PWM on-time PWN_ON (for example, during t ₀ to t ₃ ) is shorter than the fixed on-time T _{ON — TH} (for example, during t ₀ to t ₄ ), V _CS is converted to I _CS in a K1 ratio. For example, the current signal I _CS is configured to be determined as follows: I _CS =V _CS ×K1 (Equation 2)

Wherein, V _CS represents a sampling voltage obtained by sampling a sampling resistor (for example, sampling resistor 108) for sampling the switching power supply system, and K1 is a conversion ratio of V _CS to I _CS when PWN_ON is shorter than T _{ON_TH} , and K1 is relatively large. The ratio is to ensure sufficient I _CS to bring the power transistor into saturation, thereby reducing conduction losses. As shown in FIG. 3, according to Equation 1 - Equation 2, the base drive current signal I _{BASE is} at least partially linearly increased based on the current signal I _CS during the period t ₁ ~ t ₂ .

In one embodiment, when the pre-turn-off signal PWM_PRE (e.g., at t ₂₎ changes from a logic low level to a logic high level, to first reduce the base drive current signal I _BASE (e.g., such as t ₂ ~ t ₃ period Shown), then when the PWM signal changes from the logic low level to the logic high level simultaneously with the pre-shutdown signal PWM_PRE (eg, at t ₃ ), the base drive current signal I _{BASE is} lowered to turn off the power transistor, which A step-down of the base drive current signal I _BASE is beneficial to reduce turn-off losses.

4 is a simplified timing diagram showing another timing relationship of respective signals with a base current of a power transistor in a method of controlling a driving power transistor based on an on-time according to an embodiment of the present disclosure. This figure is only an example and should not unduly limit the scope of patent application. Many variations, alternatives, and modifications will be apparent to those of ordinary skill in the art. As shown in FIG. 4, waveform 401 represents a fixed on-time T _{ON_TH} , waveform 402 represents a PWM signal that changes with time, waveform 403 represents a PWM_PRE signal that changes with time, and waveform 404 represents a base drive current signal I that changes with time. _BASE .

Figure 4 shows the signal timing when the system input voltage V _{IN is} low. Wherein for the on-time period and the off-time period associated with the PWM signal, the on-time period PWN_ON starts at time t ₀ and ends at time t ₄ . For example, t ₀ t ₁ t ₂ t ₃ t ₄ . Similar to FIG. 3, the relationship between the voltage V _CS sampled by the sampling resistor (for example, the sampling resistor 108) and the base drive current signal I _BASE is as shown in Equation 1.

According to one embodiment, at t ₀ , the PWM signal changes from a logic low level to a logic high level, and in response, the base drive current signal I _{BASE is} abruptly changed to a fixed time width pulse drive current I _pusle , eg, I _pusle The high level duration can be t ₀ ~ t ₁ . Since the PWM on-time PWN_ON (for example, during t ₀ to t ₄ ) is much longer than the fixed on-time T _{ON — TH} (for example, during t ₀ to t ₂ ), V _{CS is} first converted with a larger K1 ratio, and then further The small K2 ratio is converted to I _CS , so that the smaller I _CS generated by the conversion can ensure that the base input charge is not left, reducing the driving loss of the power transistor. The current signal I _CS is configured to be determined as follows: I _CS '=V _CS ×K1 I _CS =I _CS '×K2 (Equation 3)

Wherein, V _CS represents a sampling voltage obtained by sampling a sampling resistor (for example, sampling resistor 108) for sampling the switching power supply system, K1 is a conversion ratio of V _CS to I _CS when PWN_ON is shorter than T _{ON_TH} , and K2 is PWN_ON longer than T _{ON_TH} The ratio of V _CS to I _CS , where K2 is a relatively small ratio. According to Equation 1 - Equation 2, during the period t ₁ ~ t ₂ , the base drive current signal I _{BASE is} at least partially linearly increased based on the current signal I _CS . Then at t ₂ (where the threshold signal T _{ON_TH} changes from a logic high level to a logic low level), the intermediate signal I _CS 'bumps down by a predetermined magnitude and then linearly grows at a smaller rate based on K2, as in Equation 3. Show.

In one embodiment, when the pre-turn-off signal PWM_PRE (e.g., at t ₃₎ changes from a logic low level to a logic high level, to first reduce the base drive current signal I _BASE (e.g., such as t ₃ ~ t ₄ time period Shown). Then, when the PWM signal and the pre-shutdown signal PWM_PRE are simultaneously changed (for example, at t ₄ ) from the logic low level to the logic high level, the base driving current signal I _{BASE is} lowered to the off power transistor, the pair of bases The step-down of the drive current signal I _BASE is beneficial to reduce the turn-off loss.

The invention may be embodied in other specific forms without departing from the spirit and essential characteristics. For example, the algorithms described in the specific embodiments can be modified, and the system architecture does not depart from the basic spirit of the invention. The present embodiments are to be considered in all respects as illustrative and not limiting, and the scope of the invention All changes in the scope of the invention are thus included in the scope of the invention.

Some or all of the elements of various embodiments of the invention, alone and/or in combination with at least one other element, utilize one or more of the software elements, one or more hardware elements, and/or one of the soft and hard elements. Or a variety of combinations to achieve. In another example, each of the inventions Some or all of the elements in one embodiment are implemented in one or more circuits, alone or in combination with at least one other element, such as in one or more analog circuits and/or one or more digital circuits. . In yet another example, various embodiments and/or examples of the invention may be combined.

Although specific embodiments of the invention have been described, it will be apparent to those skilled in the art Therefore, it is to be understood that the invention is not limited by

100‧‧‧ system

101‧‧‧ Pulse wave generation circuit

102‧‧‧Switch drive circuit

103‧‧‧ Bias current circuit

104‧‧‧K1/K2 ratio conversion circuit

105‧‧‧Fixed on-time generation circuit

106‧‧‧One winding inductance

107‧‧‧Power transistor

108‧‧‧Sampling resistor

PWM‧‧‧ Pulse Switch Signal

PWM_PRE‧‧‧ pre-shutdown signal

T _{ON_TH ‧‧‧Fixed} on time

V _IN ‧‧‧ input voltage

V _CS ‧‧‧ voltage signal

I _B ‧‧‧bias current signal

I _CS ‧‧‧current signal

I _BASE ‧‧‧base drive current signal

Claims (3)

A system for driving a power transistor, comprising: a ratio conversion circuit configured to convert a first characterization signal characterizing a current flowing through a power transistor using a first conversion ratio or a second conversion ratio based on a first control signal, Generating a second characterization signal; and a switch drive circuit configured to generate a drive signal that controls conduction and deactivation of the power transistor based on the second control signal, the third control signal, and the second characterization signal, wherein The ratio conversion circuit converts the first characterization signal with the first conversion ratio when the first control signal is at a high level, and utilizes the second conversion ratio pair when the first control signal is at a low level Converting the first characterization signal, the switch driving circuit using the first predetermined signal as the driving signal in a first period in which the second control signal is at a high level and the third control signal is at a low level The second time period in which the second control signal is at a high level and the third control signal is at a low level Determining a signal as the driving signal, and using a second predetermined signal as the driving signal when both the second control signal and the third control signal are at a high level; the first characterization signal is flowing through the pair A sampled voltage signal generated by sampling a current of an emitter of the power transistor; the second characterization signal being a sampled current signal generated by converting the first characterization signal. The system for driving a power transistor according to claim 1, wherein the driving signal is supplied as a base output current signal to a base of the power transistor, and the collector of the power transistor is via The primary winding of the transformer is connected to the input voltage and is connected to ground via a sampling resistor. A method of driving a power transistor, comprising: converting, based on a first control signal, a first characterization signal characterizing a current flowing through a power transistor with a first conversion ratio or a second conversion ratio to generate a second characterization signal; Generating a driving signal for controlling conduction and deactivation of the power transistor based on the second control signal, the third control signal, and the second characterization signal, wherein the first signal is utilized when the first control signal is at a high level Converting the first characterization signal, and converting the first characterization signal with the second conversion ratio when the first control signal is at a low level, wherein the second control signal is at a high level And the first predetermined signal is used as the driving signal in the first period in which the third control signal is in the low level, in the second period in which the second control signal is in the high level and the third control signal is in the low level The second characterization signal is internally used as the driving signal, and the second predetermined signal is used as the driving signal when the second control signal and the third control signal are both at a high level; the first characterization signal a sampled voltage signal generated by sampling a current flowing through an emitter of the power transistor; the second characterization signal is passed Sampling a signal indicative of a current signal generated by the conversion.