TWI587485B - Semiconductor device - Google Patents

Description

Semiconductor device

The present invention relates to semiconductor devices, and more particularly to techniques for effectively applying to semiconductor devices having SRAMs.

SRAM (Static Random Access Memory) is a type of semiconductor memory that uses a flip-flop to store data. That is, in the SRAM, data ("1" or "0") is stored in two cross-connected inverters composed of four transistors. Further, since two transistors are required for reading and writing access, a typical SRAM is a transistor having six memory cells.

For example, Patent Document 1 (JP-A-2001-28401) discloses a semiconductor memory device (FIG. 1) having a memory cell of a static RAM composed of six transistors.

In the following Patent Document 2 (JP-A-2002-237539), it is disclosed that an NMOS transistor (N1, N4) is formed in one P well region (PW0), and an NMOS transistor (N2, N3) is used. shape The SRAM memory cell (see FIG. 32) in the other P well region (PW1) of the N well region (NW) is formed to improve the soft error resistance.

In the following Patent Document 3 (Japanese Laid-Open Patent Publication No. Hei 7-7089), it is disclosed that two divided driver NMOSs (regions N1', N1', N2', and N2" of the transistor) are disposed in each P. The SRAM memory cell on the well (see Fig. 5) is used to perform soft error countermeasures. Moreover, in this SRAM cell, the gate direction of the word line access ‧ transistors (NA1) and (NB1) becomes the driver NMOS (regions N1', N1', N2', and N2" of the transistor) The direction of the gate is orthogonal to the direction.

In the following Patent Document 4 (JP-A-2002-43441), a SRAM memory cell is disclosed which is formed in a first P-well region (PW1) and has a main axis of a polysilicon wiring layer (PL11) as a gate. An N-channel MOS transistor (N1) of a pole electrode, and an N-channel MOS transistor (N1') in which a turn-back axis of the polysilicon wiring layer (PL11) is a gate electrode (refer to FIG. 1, FIG. 2, [0062] ]paragraph).

Further, in the following Patent Document 5 (Japanese Laid-Open Patent Publication No. 2000-36543), a SRAM memory cell is described, which is in the layout of the SRAM memory cell, and two word lines (21a, 21b) are respectively activated in the p-type. The ends of the region (13) are orthogonal to each other and are parallel to each other, and the length thereof is formed to be 1/2 bit short, and the common gate lines (22a, 22b) are between the word lines (21a, 21b). The p-type active region (13) and the n-type active region (14) are orthogonal to each other, and are lined up in parallel with the word lines (21a, 21b) so as to be equally spaced (see FIG. 4). In addition, brackets The symbols are shown in the respective documents, the figure numbers, and the like.

[prior technical literature] [Patent Document]

[Patent Document 1]

Japanese Special Report 2001-28401

[Patent Document 2]

Japanese Patent Laid-Open Publication No. 2002-237539

[Patent Document 3]

Japanese Special Report No. 7-7089

[Patent Document 4]

Japanese Patent Laid-Open Publication No. 2002-43441

[Patent Document 5]

Japanese Special Publication No. 2000-36543

For example, as described in the above-mentioned Patent Document 1 (FIG. 1 and the like), the SRAM memory cell has a complicated pattern structure, and as the semiconductor device is miniaturized in recent years, for example, variation in variation in device characteristics such as variation in gate width occurs. Or problems such as difficulty in simulating memory characteristics.

As will be described later in detail, the variation in the above-described element characteristics is caused by the shape of the active region, the shape of the gate electrode, and the like.

Therefore, it is preferable to optimize the shape of the active region or the shape of the gate electrode. In order to improve the controllability of the component characteristics or the ease of simulation.

It is an object of the invention to provide a semiconductor device having good characteristics. In particular, a semiconductor device having an SRAM memory cell provides a cell layout in which the characteristics can be improved.

The above and other objects and novel features of the present invention will become apparent from the description and appended claims.

In the invention disclosed in the present invention, the semiconductor device shown in the representative embodiment has a memory cell having the following (a1) to (a8).

(a1) is a first conductivity type first MIS transistor that is connected between the first potential and the first node.

(a2) is a second conductivity type first MIS transistor that is connected between the first node and the second potential different from the first potential.

(a3) is a second conductivity type second MIS transistor in parallel with the second conductivity type first MIS transistor between the first node and the second potential.

(a4) is a first conductivity type second MIS transistor that is connected between the first potential and the second node.

(a5) is a second conductivity type third MIS transistor that is connected between the second node and the second potential.

(a6) is a second conductivity type fourth MIS transistor in parallel with the second conductivity type third MIS transistor between the second node and the second potential.

(a7) is the number that is connected between the first node and the first bit line 2 Conductive type 5 MIS transistor.

(a8) is a second conductivity type sixth MIS transistor that is connected between the second node and the second bit line.

Further, it has the following active regions (b1) to (b4).

(b1) is a first active region in which one of the second conductivity type first MIS transistor and the second conductivity type fifth MIS transistor is disposed.

(b2) is a pattern in which the pattern of the first active region and the active region is separated, and the second active region of the second conductivity type second MIS transistor is disposed.

(b3) is a third active region in which one of the second conductivity type third MIS transistor and the second conductivity type sixth MIS transistor is disposed.

(b4) The pattern of the third active region and the active region is separated, and the fourth active region of the second conductivity type fourth transistor is disposed.

Further, the first to fourth active regions are arranged to be arranged apart from each other in the first direction.

In the first active region, the first gate wiring is arranged to extend in the first direction.

In the first active region and the second active region, the second gate wiring is arranged to extend in the first direction.

In the third active region, the third gate wiring is arranged to extend in the first direction.

In the third active region and the fourth active region, the fourth gate wiring is arranged to extend in the first direction.

In the invention disclosed in the present invention, the semiconductor device shown in another representative embodiment has the above (a1) to (a8). And, on The semiconductor device is an active region having (b1) and (b2). (b1) is a first active region in which the first transistor, the fourth transistor, and the fifth transistor are disposed. (b2) is a second active region in which the third transistor, the second transistor, and the sixth transistor are disposed. The active region is (c) the first and second active regions are arranged to be arranged in the first direction. Further, (d1), in the first active region, the first gate wiring is arranged to extend in the first direction, and (d2) is in the first active region and the second active region, and the second gate The pole wiring is arranged to extend in the first direction described above. Further, (d3) in the first active region and the second active region, the third gate wiring is arranged to extend in the first direction, and (d4) the fourth gate is in the second active region. The wiring is arranged to extend in the first direction described above.

In the invention disclosed in the present invention, the semiconductor device shown in another representative embodiment has the above (a1) to (a8). Further, the above semiconductor device is an active region having (b1) and (b2). (b1) is a first active region in which the first transistor, the fourth transistor, and the fifth transistor are disposed. (b2) is a second active region in which the third transistor, the second transistor, and the sixth transistor are disposed. The active region is (c) the first active region and the second active region are arranged in the first direction. Further, (d1) in the first active region, the first gate wiring is arranged to extend in the first direction, and (d2) is in the first active region and the second active region, and the second gate The wiring is arranged to extend in the first direction described above. Further, (d3) in the first active region and the second active region, the third gate wiring is arranged to extend in the first direction, and (d4) the fourth gate is on the first active region. The wiring is arranged to extend in the first direction described above.

In the invention disclosed in the present invention, the characteristics can be improved by the semiconductor device shown in the representative embodiment described below.

1‧‧‧Semiconductor substrate

Ac‧‧‧active area

AcN1‧‧‧active area

AcN2‧‧‧active area

AcN3‧‧‧active area

AcN4‧‧‧active area

AcP1‧‧‧active area

AcP2‧‧‧active area

AcP3‧‧‧active area

AcP4‧‧‧active area

AN‧‧‧active area

AP1, AP2‧‧‧active area

A, B‧‧‧ accumulation node

AcS‧‧ active area

BL, /BL‧‧‧ bit line

BLA, /BLA‧‧‧ bit line

BLB, /BLB‧‧‧ bit line

DG‧‧‧Virtual Gate Electrode

EX1‧‧‧ low concentration impurity area

EX2‧‧‧High concentration impurity area

F‧‧‧ memory

F’‧‧‧ Connection unit

G (G1~G4, G2a, G2b, G4a, G4b) ‧‧ ‧ gate electrode

GO‧‧‧gate insulating film

IL1‧‧‧ interlayer insulating film

IL2‧‧‧ interlayer insulating film

IL3‧‧‧ interlayer insulating film

M1 (M1S, M1D, M1W, M1BL) ‧‧‧1st wiring

M2‧‧‧2nd layer wiring

M2W‧‧‧2nd layer wiring

M3‧‧‧3rd layer wiring

N-well‧‧n-type trap

P1 (P1a~P1o, P1A~P1Z) ‧‧‧1st plug

P2‧‧‧2nd plug

P3‧‧‧3rd plug

P-well‧‧‧p-type well

SP1‧‧‧Shared 1st plug

STI‧‧‧ component separation area

SW‧‧‧ side wall

Sp‧‧‧Separation Department

TNA1‧‧‧ access transistor (transistor)

TNA2‧‧‧ access transistor (transistor)

TNA3‧‧‧ access transistor (transistor)

TNA4‧‧‧ access transistor (transistor)

TND1‧‧‧ drive transistor (transistor)

TND2‧‧‧ drive transistor (transistor)

TND3‧‧‧Driver Transistor (Crystal)

TND4‧‧‧Driver Transistor (Crystal)

TP1‧‧‧ loaded into the transistor (transistor)

TP2‧‧‧ loaded into the transistor (transistor)

VDD‧‧‧ power supply potential

LVDD‧‧‧Power potential line

VSS‧‧‧ Ground potential

LVSS‧‧‧Ground potential line

LVSSB‧‧‧2nd ground potential line

WL‧‧‧ character line

WLA‧‧ character line

WLB‧‧‧ character line

Fig. 1 is an equivalent circuit diagram showing a memory cell of the SRAM of the first embodiment.

Fig. 2 is a plan view showing a configuration of a memory cell of the SRAM of the first embodiment.

Fig. 3 is a plan view showing a configuration of a memory cell of the SRAM of the first embodiment.

Fig. 4 is a plan view showing a configuration of a memory cell of the SRAM of the first embodiment.

Fig. 5 is a circuit diagram showing a configuration of a transistor corresponding to the layout of the memory cell of the SRAM of the first embodiment.

Fig. 6 is a cross-sectional view showing the configuration of a memory cell of the SRAM of the first embodiment.

Fig. 7 is a cross-sectional view showing the configuration of a memory cell of the SRAM of the first embodiment.

Fig. 8 is a cross-sectional view showing the configuration of a memory cell of the SRAM of the first embodiment.

Fig. 9 is a cross-sectional view showing the configuration of a memory cell of the SRAM of the first embodiment.

Fig. 10 is a cross-sectional view showing the configuration of a memory cell of the SRAM of the first embodiment.

Fig. 11 is a cross-sectional view showing the configuration of a memory cell of the SRAM of the first embodiment.

Fig. 12 is a plan view showing the concept of a memory cell array of the SRAM of the first embodiment.

Fig. 13 is a plan view showing the configuration of a memory cell array of the SRAM of the first embodiment.

Fig. 14 is a plan view showing the configuration of a memory cell array of the SRAM of the first embodiment.

Fig. 15 is a plan view conceptually showing the position of a connection unit region in the memory cell array of the SRAM of the first embodiment.

Fig. 16 is a plan view showing the configuration of a connection unit (F') of the SRAM of the first embodiment.

Fig. 17 is a plan view showing the configuration of a connection unit (F') of the SRAM of the first embodiment.

Fig. 18 is a plan view showing the concept of a memory cell and a connection unit forming region of the SRAM of the first embodiment.

Fig. 19 is a plan view showing a configuration of a memory cell and a connection unit forming region of the SRAM of the first embodiment.

Fig. 20 is a plan view showing the configuration of a memory cell and a connection unit forming region of the SRAM of the first embodiment.

Fig. 21 is a plan view showing the configuration of a memory cell of the SRAM of the second embodiment.

Fig. 22 is a plan view showing the configuration of a memory cell of the SRAM of the second embodiment.

Fig. 23 is a plan view showing the configuration of a connection unit of the SRAM of the third embodiment.

Fig. 24 is a plan view showing the configuration of a connection unit of the SRAM of the third embodiment.

Fig. 25 is a circuit diagram showing a memory cell of the SRAM of the third embodiment.

Fig. 26 is a plan view showing the configuration of a memory cell of the SRAM of the fourth embodiment.

Fig. 27 is a plan view showing the configuration of a memory cell of the SRAM of the fourth embodiment.

Fig. 28 is a plan view showing the configuration of a memory cell of the SRAM of the fourth embodiment.

Fig. 29 is a circuit diagram showing a configuration of a transistor in accordance with the layout of the memory cell of the SRAM of the fourth embodiment.

Fig. 30 is a plan view showing the configuration of a memory cell of the SRAM of the fifth embodiment.

Fig. 31 is a plan view showing the configuration of a memory cell of the SRAM of the fifth embodiment.

Fig. 32 is a plan view showing the configuration of a memory cell of the SRAM of the fifth embodiment.

Fig. 33 is a circuit diagram showing a configuration of a transistor in accordance with the layout of the memory cell of the SRAM of the fifth embodiment.

Fig. 34 is a plan view showing the configuration of a memory cell of the SRAM of the sixth embodiment.

Fig. 35 is a plan view showing the configuration of a memory cell of the SRAM of the sixth embodiment.

Fig. 36 is a plan view showing the configuration of a memory cell of the SRAM of the sixth embodiment.

Fig. 37 is a circuit diagram showing a configuration of a transistor in accordance with the layout of the memory cell of the SRAM of the sixth embodiment.

Fig. 38 is a plan view showing the configuration of a memory cell of the SRAM of the seventh embodiment.

Fig. 39 is a plan view showing the configuration of a memory cell of the SRAM of the seventh embodiment.

Fig. 40 is a plan view showing the configuration of a memory cell of the SRAM of the seventh embodiment.

Fig. 41 is a circuit diagram showing a configuration of a transistor in accordance with the layout of the memory cell of the SRAM of the seventh embodiment.

Fig. 42 is a plan view showing the configuration of a connection unit (F') of the SRAM of the seventh embodiment.

Fig. 43 is a plan view showing the configuration of a connection unit (F') of the SRAM of the seventh embodiment.

Fig. 44 is a plan view showing the configuration of a memory cell of the SRAM of the eighth embodiment.

Fig. 45 is a plan view showing the configuration of a memory cell of the SRAM of the eighth embodiment.

Fig. 46 is a plan view showing the configuration of a memory cell of the SRAM of the eighth embodiment.

Fig. 47 is a circuit diagram showing a configuration of a transistor in accordance with the layout of the memory cell of the SRAM of the eighth embodiment.

Fig. 48 is an equivalent circuit diagram showing a memory cell of the SRAM of the ninth embodiment.

Fig. 49 is a plan view showing the configuration of a memory cell of the SRAM of the ninth embodiment.

Fig. 50 is a plan view showing the configuration of a memory cell of the SRAM of the ninth embodiment.

Fig. 51 is a plan view showing the configuration of a memory cell of the SRAM of the ninth embodiment.

Fig. 52 is a circuit diagram showing a configuration of a transistor in accordance with the layout of the memory cell of the SRAM of the ninth embodiment.

Figure 53 is a plan view showing the configuration of a memory cell of the SRAM of the tenth embodiment.

Fig. 54 is a plan view showing the configuration of a memory cell of the SRAM of the tenth embodiment.

Fig. 55 is a plan view showing the configuration of a memory cell of the SRAM of the tenth embodiment.

Fig. 56 is a circuit diagram showing a configuration of a transistor in accordance with the layout of the memory cell of the SRAM of the tenth embodiment.

57 is an equivalent circuit diagram showing a memory cell of the SRAM of the eleventh embodiment.

Figure 58 is a plan view showing the configuration of a memory cell of the SRAM of the eleventh embodiment.

Figure 59 is a plan view showing the configuration of a memory cell of the SRAM of the eleventh embodiment.

Fig. 60 is a plan view showing the configuration of a memory cell of the SRAM of the eleventh embodiment.

Fig. 61 is a circuit diagram showing a configuration of a transistor in accordance with the layout of the memory cell of the SRAM of the eleventh embodiment.

Figure 62 is a diagram showing the layout of a semiconductor wafer in a twelfth embodiment.

63 is a plan view showing a configuration example of a part of a memory cell of the SRAM of the first embodiment.

Fig. 64 is a plan view showing the memory cell of the SRAM of the comparative example.

Fig. 65 is a plan view showing a part of a memory cell of an SRAM of a comparative example.

In the following embodiments, the description will be made by dividing into plural parts or embodiments for the sake of convenience. However, unless otherwise specified, the ones are not related to each other, and one of them is a part or all of the other. Modifications, application examples, detailed descriptions, and supplementary explanations. In addition, in the following embodiments, the number of elements (including the number, the numerical value, the quantity, the range, and the like) is not limited to the specific number and the like when it is specifically limited and the principle is obviously limited to a specific number. It is limited to the specific quantity, and may be more than a certain amount or less.

Further, in the following embodiments, the constituent elements (including the element steps and the like) are not necessarily essential unless otherwise specified and essential in principle. Similarly, in the following embodiments, when the shape, the positional relationship, and the like of the constituent elements and the like are mentioned, the substantially similar or similar shapes and the like are included, unless otherwise specified. This is also true for the above-mentioned quantities (including numbers, values, quantities, ranges, etc.).

Hereinafter, embodiments of the present invention will be described in detail based on the drawings. In the entire drawings for explaining the embodiments, the same or related symbols are attached to members having the same function, and the repeated description thereof is omitted. Further, when there are a plurality of similar members (parts), an individual or a specific portion may be added to the generalized symbol. Further, in the following embodiments, the description of the same or similar parts will not be repeated in principle unless otherwise specified.

Further, in the drawings used in the embodiment, the hatching may be omitted in order to facilitate the drawing even in the cross-sectional view. Moreover, even if it is a plan view, a hatching may be attached in order to view a figure.

(Embodiment 1)

[circuit composition]

The semiconductor device (semiconductor memory device, semiconductor integrated circuit device) of the present embodiment is a memory cell having an SRAM. Fig. 1 is an equivalent circuit diagram showing a memory cell of the SRAM of the embodiment. As shown, the memory cell is an intersection of a bit line (bit line BL, bit line / (bar) BL) and a word line WL arranged in a pair. This memory cell has a pair of load transistors (load MOS, load transistor, load MISFET) TP1, TP2, a pair of access transistors (access MOS, access transistor, save Take MISFET, transfer transistor) TNA1, TNA2 and a pair of driver transistors (driver MOS, drive transistor, drive MISFET) TND2, TND4.

Here, the present embodiment is a driver transistor TND1 having a parallel connection with the driver transistor TND2. Moreover, there is a driver transistor TND3 in parallel with the driver transistor TND4. Among the above eight transistors constituting the above memory cell, the transistor (TP1, TP2) is a p-type (p channel type) transistor of the first conductivity type, access transistor (TNA1, TNA2) and driver. The transistor (TND1, TND2, TND3, TND4) is a second conductivity type n-type (n-channel type) transistor.

In addition, MOS is an abbreviation for Metal Oxide Semiconductor, and MISFET is an abbreviation for Metal Insulator Semiconductor Field Effect Transistor. Further, in the following, the above-described load transistor, the access transistor and the driver transistor are simply referred to as "transistors". Further, each transistor may be represented by only the sign of each transistor.

Among the above eight transistors constituting the above memory cell, TND2 and TP1 constitutes a CMOS (Complementary MOS) inverter (which can also be a CMIS inverter), and TND4 and TP2 constitute other CMOS inverters. The input/output terminals (accumulation nodes A, B) of the pair of CMOS inverters are cross-coupled to form a flip-flop circuit as an information storage unit that stores information of one bit.

Here, in the memory cell of the SRAM of the present embodiment, TND1 is provided in parallel with TND2, and TND3 is provided in parallel with TND4. Therefore, CMOS inverters can be formed by TND1, TND2, and TP1, and TND3, TND4, and TP2 are formed. To form other CMOS inverters.

Therefore, when the connection relationship of the eight transistors constituting the SRAM memory cell of the present embodiment is described in detail, the following will be obtained.

TP1 is connected between the power supply potential (VDD, the first power supply potential) and the accumulation node A, and the storage node A and the ground potential (VSS, GND, reference potential, the second power supply potential lower than the first power supply potential, and TND1 and TND2 are connected in parallel between the second power supply potentials having different first power supply potentials, and the gate electrodes of TP1, TND1 and TND2 are connected to the accumulation node B.

TP2 is connected between the power supply potential and the accumulation node B, TND3 and TND4 are connected in parallel between the accumulation node B and the ground potential, and the gate electrodes of TP2, TND3 and TND4 are connected to the accumulation node A.

TNA1 is connected between the bit line BL and the accumulation node A, TNA2 is connected between the bit line /BL and the accumulation node B, and the gate electrodes of TNA1 and TNA2 are connected to the word line WL (becomes a word) Yuan line).

As described above, in the SRAM memory cell of the present embodiment, the driver transistors (TND1 and TND2, TND3, and TND4) are divided.

Further, in the explanation, the gate electrodes of TND1 and TND2 are common, and therefore, they can be regarded as one transistor, but here, they are described as two transistors. The same applies to TND3 and TND4.

[circuit action]

The circuit operation of the memory cell of the above SRAM will be described. When the accumulation node A of the CMOS inverter is at a high potential (H), since TND3 and TND4 are turned "ON", the accumulation node B of the other CMOS inverters forms a low potential (L). Therefore, TND1 and TND2 are in an OFF state, and the high potential (H) of the accumulation node A is maintained. That is, the state of the mutual accumulation nodes A, B is maintained by the latch circuit that cross-couples the pair of CMOS inverters, and the information is held while the power supply voltage is being applied.

On the other hand, at TNA1, each gate electrode of TNA2 is connected with a word line WL. That is, when the word line WL is at a high potential (H), TNA1, TNA2 will be turned on, and the flip-flop circuit and the bit line (BL, /BL) will be electrically connected, thus accumulating nodes A, B The potential state (H or L) appears on the bit line BL, /BL, and is read as information of the memory cell.

Moreover, in order to write information in the memory cell, the word line WL is set to a high potential (H), and TNA1 and TNA2 are set to an on state, thereby causing the flip-flop circuit and the bit line (BL, /BL). ) electrical connection, bit line The information of BL, /BL (the combination of H and L or the combination of L and H) is transmitted to the accumulation nodes A, B, and the information is saved as described above.

[Structure of SRAM]

[Composition of memory]

2 to 4 are plan views showing the configuration of a memory cell of the SRAM of the embodiment. FIG. 2 shows the arrangement of the active region Ac, the gate electrode G, and the first plug P1. FIG. 3 shows the arrangement of the first plug P1, the first layer wiring M1, and the second plug P2. 4 is a view showing the arrangement of the second plug P2, the second layer wiring M2, the third plug P3, and the third layer wiring M3. Therefore, in FIGS. 2 and 3, the plan view is superimposed on the basis of the first plug P1, whereby the positional relationship of the patterns displayed in the respective drawings is clear. Further, in FIGS. 3 and 4, the plan view is superimposed on the basis of the second plug P2, whereby the positional relationship of the patterns displayed in the respective drawings is clear. Further, a rectangular area surrounded by a dotted line in the figure is a memory cell area indicating 1 (1 bit).

6 to 11 are cross-sectional views showing the configuration of a memory cell of the SRAM of the embodiment. Fig. 6 is a cross-sectional view taken along line A-A' of Fig. 2, Fig. 7 is a cross-sectional portion corresponding to B-B' of Fig. 2, and Fig. 8 is a cross-sectional portion corresponding to C-C' of Fig. 2. Fig. 9 is a cross-sectional view taken along line A-A' of Fig. 2, Fig. 10 is a cross-sectional portion corresponding to B-B' of Fig. 2, and Fig. 11 is a cross-sectional portion corresponding to C-C' of Fig. 2. 9 to 11 also show a pattern of the upper layer than the first plug P1 shown in FIG. 2, and FIGS. 9 to 11 correspond to the above-mentioned A when the plan views shown in FIGS. 2 to 4 are superimposed. -A' section, B-B' section and C-C' section unit.

[Memory grid layout]

[Ac, G, P1]

As shown in FIG. 2, in the semiconductor substrate, a p-type well (P-well, first region, first conductivity type first well), n-type well (N-well, second region, second conductivity type, second The well and the p-well (P-well, third region, first conductivity type third well) are arranged in the X direction (first direction). In FIG. 2, only one (1 bit) memory cell area is displayed. However, as will be described later, the memory cell is repeatedly arranged in the X direction (first direction) and the Y direction (the first intersecting with the first direction) In the 2 direction) (refer to FIG. 12), the wells (P-well, N-well, P-well) are formed to extend in the Y direction. Further, the exposed regions of the wells become active regions (active regions, transistor formation regions, Ac).

Further, in the semiconductor substrate, six active regions (AcP2, AcP1, AcN1, AcN2, AcP3, AcP4) are arranged in the X direction. Between these active regions (Ac) is a component separation region (STI). In other words, in the element separation region (STI), the active region (Ac) is patterned or the pattern of the active region is separated. Further, each of the above wells (P-well, N-well, P-well) is connected at a lower portion of the element isolation region STI (see FIG. 6).

Further, in other words, AcP2 and AcP1 are arranged to be arranged apart from each other in the X direction (first direction).

Similarly, AcN1 and AcN2, AcP3 and AcP4 are also in X respectively. The directions (the first direction) are arranged to be arranged separately from each other.

Further, in other words, AcP2 and AcP1 are arranged to be separated by an element in the X direction (first direction).

Similarly, AcN2 and AcN1 are arranged in the X direction (first direction) so as to be separated by elements.

Further, AcP4 and AcP3 are arranged to be separated by an element in the X direction (first direction).

When the active regions are described again, the active region AcP2 is an exposed region of a p-well and has a substantially rectangular shape having a long side in the Y direction. The active region AcP1 is disposed adjacent to the active region AcP2 and is an exposed region of a p-well (P-well) having a substantially rectangular shape having a long side in the Y direction. In addition, in FIG. 2, only one (1 bit) memory cell area is displayed for convenience, but as will be described later, the memory cell is repeatedly arranged in the X direction and the Y direction (refer to FIG. 12, FIG. 13). Therefore, in the memory cell array, the active region AcP1 extends linearly in the Y direction (refer to FIG. 13). In addition, the "line shape" can also be imagined as "a roughly rectangular shape having a long side in the Y direction".

The active region AcN1 is an exposed region of an n-well and has a substantially rectangular shape having a long side in the Y direction. The active region AcN2 is an exposed region of an n-well and has a substantially rectangular shape having a long side in the Y direction.

The active region AcP3 is an exposed region of a p-well (P-well) located on the right side of the n-type well, and has a substantially rectangular shape having a long side in the Y direction. The active region AcP4 is located beside the active region AcP3, The exposed region of the p-well has a substantially rectangular shape having a long side in the Y direction. Further, in the memory cell array, the active region AcP3 extends linearly in the Y direction as in AcP1 (see FIG. 13).

On the above six active regions (AcP2, AcP1, AcN1, AcN2, AcP3, AcP4), the gate electrode (gate wiring, linear gate) G is separated by a gate insulating film (GO, see FIG. 7, etc.) The eight transistors described in the column of the above-mentioned "circuit configuration" are formed so as to extend through the respective active regions in the X direction. Further, the active region (Ac) on both sides of the gate electrode G serves as a source ‧ a drain region of the transistor (see FIG. 7 and the like).

Hereinafter, the gate electrode G will be described in detail. In addition, the gate electrode is collectively referred to by the symbol "G". However, in the following description, when the individual gate electrode is shown, the symbol (G) is added with a symbol (1 to 4, etc.). Further, in the corresponding drawing, the general symbol (G) and the symbol (G) additional symbol (1 to 4, etc.) are also used. In addition, in this specification, in addition to G (gate electrode), P1 (first plug), M1 (first layer wiring) and M2 (second layer wiring) are also marked with symbols (digital or English). The letter) is used to indicate the situation.

Specifically, a common gate electrode G1 is disposed so as to pass through the active regions AcP2, AcP1, and AcN1. Thereby, TND2 is disposed on the active region AcP2, TND1 is disposed on the active region AcP1, and TP1 is disposed on the active region AcN1 to connect the gate electrodes (G). In the active area AcN1 is configured with TP1, in the gate The P-type source ‧ drain region of TP1 is provided on both sides of the pole electrode G.

In the active region AcP1, another gate electrode G2 is disposed in parallel with the above-described common gate electrode G1. Thereby, TNA1 is disposed on the active region AcP1, and the N-type source ‧thole region of TNA1 and the N-type source ‧thole region of TND1 are connected (commonized).

Further, a common gate electrode G3 is disposed so as to pass through the active regions AcP4, AcP3, and AcN2. Thereby, TND4 is disposed on the active region AcP4, TND3 is disposed on the active region AcP3, and TP2 is disposed on the active region AcN2, and the gate electrode (G) is connected to the active region AcN2. TP2 is disposed in the active region AcN2, and a P-type source ‧thole region of TP2 is provided on both sides of the gate electrode G.

On the active region AcP3, another gate electrode G4 is disposed in parallel with the above-described common gate electrode G3. Thereby, TNA2 is disposed on the active region AcP3, and the N-type source ‧thole region of the TNA 2 and the N-type source ‧thole region of the TND 3 are connected (combined).

Further, the four gate electrodes G (G1 to G4) are arranged on the same line (straight line shape). Specifically, the common gate electrode G1 passing through the active region AcP2, AcP1 and AcN1 and the gate electrode G4 on the active region AcP3 are arranged on the same line extending in the X direction. The common gate electrode G3 passing through the active region AcP4, AcP3 and AcN2 and the gate electrode G2 on the active region AcP1 are arranged on the same line extending in the X direction.

As described above, in the present embodiment, the driver transistor is divided (TND1, TND2, TND3, and TND4) and arranged in different activities. Areas (AcP2 and AcP1, AcP4 and AcP3). Further, by extending the active regions (AcP2 and AcP1, AcP4, and AcP3) in the Y direction, the layout is simplified and the processing accuracy is improved.

Fig. 64 is a plan view showing the memory cell of the SRAM of the comparative example of the embodiment. The equivalent circuit of this memory cell is TND2 and TND4 which omits the circuit diagram shown in FIG. In this case, in order to increase the driving ability of the driver transistors TND1, TND3, it is necessary to increase the width of the active region (gate width, channel width) or to enlarge the gate length.

The drive capability of the driver transistor (TND1, TND3) is much better than that of the access transistor (TNA1, TNA2). For example, it is desirable to set the gate width of the access transistor to the gate width of the driver transistor to be 1:2. Further, the ratio indicating the driving ability in terms of the ratio of the gate width is referred to as "β ratio". The "β ratio" will be described in detail later.

Therefore, in this case, as shown in FIG. 64, a corner portion (curved portion, step portion) is generated in the shape of the active region (Ac). However, in reality, it is difficult to pattern (process) according to the desired shape (intermediate mask pattern). For example, as shown in FIG. 65, the corner portion is not formed with high precision, and the width of the active region is gradually increased. Smooth shapes like that. Fig. 65 is a plan view showing a part of a memory cell of the SRAM of the comparative example of the embodiment. In such a case, in TNA1, the gate width varies depending on the place, and the transistor characteristics of TNA1 deteriorate. Moreover, in the memory cell array, there are many cases where the processing precision differs for each memory cell, and manufacturing variations occur. In such a case, the variation in the characteristics of each memory cell becomes large, which is a cause of product defects. Moreover, such problems are particularly noticeable as the memory cells are miniaturized. With.

On the other hand, in the present embodiment, as described above, the driver transistors (TND1, TND2, TND3, and TND4) are divided and disposed in different active regions (AcP2, AcP1, AcP4, and AcP3). Therefore, the driving ability of the driver transistor (TND1, TND3) can be made larger than that of the access transistor (TNA1, TNA2). For example, by setting the width (length in the X direction) of the active regions (AcP2 and AcP1, AcP4 and AcP3) to 1:1, it is easy to widen the gate width of the access transistor and the gate width of the driver transistor. Set to 1:2.

Further, by dividing the active regions (TND1 and TND2, TND3 and TND4), each active region can be formed into a substantially rectangular shape. In other words, it can be set to a shape that does not have the above-described corners. Therefore, the processing accuracy is improved, and the characteristics of the respective transistors formed on the active region (Ac) can be improved. Moreover, manufacturing variations can be reduced, and the operational characteristics of the memory cell array of the SRAM can be improved. Moreover, the manufacturing yield can be improved.

Further, one of the divided active regions (TND1 and TND2, TND3, and TND4) (AcP1 or AcP3 in FIG. 2) is provided with an access transistor (TNA1, TNA2) in addition to the driver transistor (TND1, TND3). ), thus reducing the number of active areas. Thereby, a simple layout can be realized, and the memory cell area can be reduced.

Further, by extending the active region (Ac) in the Y direction, the gate electrode (G) can be extended in the X direction, and not only the processing accuracy of the active region (Ac) but also the processing accuracy of the gate electrode (G) can be achieved. Upgrade. In particular, in fine pattern processing, multiple exposure techniques are sometimes used. For example, in After the X-direction exposure is performed linearly, exposure in the Y direction is performed, that is, exposure in the region to be separated is performed. By using such a double exposure technique, the processing precision of the photoresist film can be improved, and the processing precision of the underlying etching film can be improved. When such a multiple exposure technique is used, it is desirable that the pattern shape is a line shape. Therefore, as described above, by arranging the active region (Ac) or the gate electrode (G) linearly, the use of the multiple exposure technique is easy, and the processing accuracy can be improved. Moreover, the simulation mode is easy to make, and the inspection accuracy can be improved.

[P1, M1, P2]

As shown in FIG. 3, the first plug is disposed on the source ‧th pole region of the eight transistors (TND2, TNA1, TND1, TP1, TP2, TND3, TNA2, TND4) described with reference to FIG. P1. Further, the first plug P1 is also disposed on the four gate electrodes described with reference to FIG. 2 described above.

The first layer wiring M1 is disposed on the first plug P1, and the electrical connection between the first plugs P1 is achieved.

Specifically, the first plug P1a on one of the source ‧th pole regions of TND2, and the first plug P1b on the common source ‧thole region of TND1 and TNA1, and one source of TP1 The first plug P1c on the drain region and the first plug P1d on the common gate electrode G3 of TP2, TND3, and TND4 are connected by the first layer wiring (first node wiring) M1A. The first layer wiring M1A (first node wiring) can correspond to the accumulation node A of FIG. 1 . The above "one side" means the upper side in Fig. 2 Source ‧ bungee area.

The first plug P1e on one source ‧th pole region of TND4, and the first plug P1f on the common source ‧thole region of TND3 and TNA2, and one source ‧dole region of TP2 The first plug P1g on the upper side and the first plug P1h on the common gate electrode G1 of TP1, TND1, and TND2 are connected by the first layer wiring (second node wiring) M1B. The first layer wiring M1B (second node wiring) can correspond to the accumulation node B of FIG. 1 . The first layer wiring M1 (M1A, M1B) corresponding to the above-described accumulation node (A or B) is mainly arranged to extend in the X direction. Here, "one side" means a source ‧ a drain region on the lower side in FIG. 2 .

Further, the first plug P1i on the other source ‧ drain region of the TND 2 and the first plug P1 j on the other source ‧ drain region of the TND 1 are connected by the first layer wiring M1S. The first layer wiring M1 can correspond to the ground potential (VSS) of FIG. 1, and is connected to the ground potential line (LVSS) as will be described later.

The first plug P1k on the other source ‧ drain region of the TND 4 and the first plug P1 m on the other source ‧ drain region of the TND 3 are connected by the first layer wiring M1S. The first layer wiring M1S can correspond to the ground potential (VSS) of FIG. 1, and is connected to the ground potential line (LVSS) as will be described later.

Further, the first layer P1n on the other source ‧th pole region of the TNA1 and the first plug P1o on the other source ‧thole region of the TP1 are respectively arranged with the first layer wiring M1 (M1BL, M1D). Moreover, the first plug on the source ‧ bungee region of the other side of the TNA 2 The first layer wiring M1 (M1BL, M1D) is disposed on the first plug P1q on the other source ‧ drain region of P1p and TP2, respectively.

Further, the first layer wiring M1W is disposed on the first plug P1r on the gate electrode G2 of the TNA1 and the first plug P1s on the gate electrode G4 of the TNA2. The first layer wiring M1W connected to the gate electrodes G (G2, G4) is disposed at the end portion in the X direction of the memory cell region and extends in the Y direction, but the other first layer wiring M1 (M1S, Similarly to the first layer wiring M1 (M1A, M1B) corresponding to the above-described accumulation node (A or B), M1D, M1BL) is mainly arranged to extend in the X direction.

The connection state of the first layer wiring M1 between the plurality of first plugs P1 can be variously deformed as long as it conforms to the state of the wiring of the circuit diagram shown in Fig. 1. As described above, the end portion of the memory cell region is made The first layer wiring M1 extends in the Y direction, and the first layer wiring M1 is extended in the X direction inside the memory cell region, whereby a simple layout can be realized.

[P2, M2, P3, M3]

As shown in FIG. 4, the first layer wiring M1 described above with reference to FIG. 3 is the first layer other than the first layer wiring M1 (M1A, M1B) corresponding to the storage node (A or B). The second plug P2 is disposed on the layer wiring M1 (M1S, M1D, M1BL, M1W), and the second layer wiring M2 is disposed on the upper portion thereof.

Specifically, the first layer wiring M1W connected to the gate electrode G (G2) of the TNA 1 is connected to the second layer wiring M2W via the second plug P2. Pick up. Further, the first layer wiring M1W connected to the gate electrode G (G4) of the TNA 2 is connected to the second layer wiring M2W via the second plug P2. The two second layer wirings M2W are disposed at both end portions in the X direction of the memory cell region, and are arranged to extend in the Y direction. In addition, the third plug P3 is disposed on the two second layer wirings M2W, and the third layer wiring M3 (WL) is disposed in the X direction so that the two third plugs P3 can be connected. This third layer wiring M3 (WL) is a word line. Therefore, the second layer wiring M2W may be displayed as "second layer wiring connected to the word line".

Further, the first layer wiring M1S connected to the other source ‧ the drain region of the TND 2 and the other source ‧ the drain region of the TND 1 is connected to the second layer wiring M2 (LVSS) via the second plug P2 connection. The second layer wiring M2 (LVSS) is a ground potential line (a second power source potential line to which a second power source potential is supplied). The first layer wiring M1S connected to the other source ‧ the drain region of the TND 4 and the other source ‧ the drain region of the TND 3 is connected to the second layer wiring M2 (LVSS) via the second plug P2 . This second layer wiring M2 (LVSS) is a ground potential line. The two ground potential lines are inside the two second layer wirings M2 (M2W) disposed at both end portions of the memory cell region, and are arranged to extend in the Y direction.

Further, the first layer wiring M1BL connected to the other source ‧ drain region of the TNA 1 is connected to the second layer wiring M2 (BL, first bit line) via the second plug P2. This second layer wiring M2 (BL) is one of the bit lines of the bit line pair. The source of the other side of TNA2 The first layer wiring M1BL connected in the area is connected to the second layer wiring M2 (/BL) via the second plug P2. This second layer wiring M2 (/BL, second bit line) is another bit line. The two bit lines (BL, /BL, bit line pair) are arranged inside the two ground potential lines (LVSS) so as to extend in the Y direction.

Further, the second plug P2 on the first layer wiring M1D connected to the other source ‧ the drain region of the TP1 and the first source connected to the other source ‧ the drain region of the TP 2 can be connected The second layer wiring M2 (LVDD) is disposed so as to be the second plug P2 on the layer wiring M1D. The second layer wiring M2 (LVDD) is a power supply potential line (a first power supply potential line to which a first power supply potential is supplied). The power supply potential line is between the two bit lines (BL, /BL), mainly extending in the Y direction, having a line extending in the Y direction, and thereby covering the second plug P2 with the line portion Protrusion.

The connection state of the second plug P2, the second layer wiring M2, the third plug P3, and the third layer wiring M3 is variously deformed as long as it conforms to the state of the wiring of the circuit diagram shown in FIG. In general, the second layer wiring M2 is mainly extended in the Y direction, and the third layer wiring M3 is mainly extended in the X direction, thereby achieving a simple layout. In addition, in FIG. 2 to FIG. 4, only one (1 bit) memory cell area is displayed for convenience. However, as will be described later, the memory cell is repeatedly arranged in the X direction and the Y direction, and thus is memorized. In the grid array, the ground potential line (LVSS), the bit line (BL, /BL), the power supply potential line (LVDD) are configured to extend in the Y direction, and the word line (WL) is configured to be extended. Extend in the X direction (see Figure 14).

Further, in the present embodiment, since the active region is divided and disposed (AcP2, AcP1, AcP4, and AcP3), only the device isolation region (STI) portion between the active regions and the driver transistor (TND1 and TND2, TND3, and TND4) are provided. The formation region of the second layer is increased, but the ground potential can be disposed between the second layer wiring M2W (the second layer wiring connected to the word line) and the bit line (BL, /BL) as described above. Line (LVSS). Thereby, the shielding effect of the ground potential line (LVSS) is generated, and the interaction between the second layer wiring M2W (the second layer wiring connected to the word line) and the bit line (BL, /BL) can be reduced (crosstalk hybrid) News).

Further, the interval (d1) between the ground potential line (LVSS) and the bit line (BL, /BL) can be increased, and the wiring capacitance between the wirings can be reduced. Further, the interval (d2) between the power supply potential line (LVDD) and the bit line (BL, /BL) can be increased, and the wiring capacitance between the wirings can be reduced. In particular, the bit line (BL, /BL) is used to read and write data, so that the wiring of important tasks is realized. Therefore, the change in potential caused by noise or the like affects the memory operation. Therefore, by increasing the interval (d1) between the ground potential line (LVSS) and the bit line (BL, /BL) or the power supply potential line (LVDD) and the bit line (BL, /BL) (d2), Seek to improve the operational characteristics of the memory. For example, when the interval between the second layer wiring M2W (the second layer wiring connected to the word line) and the bit line (BL, /BL) is d3, d3<d1, d3<d2 can be obtained. Seek to improve the operational characteristics of the memory.

In addition, each of the patterns described with reference to FIGS. 2 to 4 is a pair of notes. The center point of the retentive region is configured to be point symmetrical.

Further, for reference, eight transistors (TND2, TNA1, TND1, TP1, TP2, TND3, TNA2, TND4) are arranged corresponding to the above-mentioned "pattern layout of the memory cell", and a circuit diagram showing the connection states is shown. In Figure 5.

[Profile structure of memory]

Next, the cross-sectional structure of the above-described layout will be described with reference to the cross-sectional views of FIGS. 6 to 11, and the configuration of the memory cell of the SRAM of the present embodiment will be further clarified.

As shown in FIGS. 6 to 8, the element isolation region STI is formed in the semiconductor substrate 1. The active region (Ac) is distinguished by the element isolation region STI. That is, the region surrounded by the element isolation region STI becomes the active region (Ac). As described above, the six active regions (AcP2, AcP1, AcN1, AcN2, AcP3, AcP4) are arranged in the X direction, and the state thereof is also known from the cross-sectional view shown in Fig. 6 and the like.

This element isolation region STI can be formed by an STI (shallow trench isolation) method. That is, the element separation trench is formed on the semiconductor substrate 1 by using the photolithography technique and the etching technique. Further, a ruthenium oxide film is formed on the semiconductor substrate so as to be able to be buried in the element isolation trench, and then an unnecessary ruthenium oxide film formed on the semiconductor substrate is removed by chemical mechanical polishing (CMP) . Thereby, the element isolation region STI in which the hafnium oxide film is buried only in the element isolation trench can be formed. In addition, you can also use LOCOS (local Oxidation The silicon separation method STI is formed by the silicon method.

Further, a p-type well (P-well) containing a p-type impurity (for example, boron or the like) and an n-type well (N-well) containing an n-type impurity (for example, phosphorus or arsenic) are formed in the semiconductor substrate 1. The p-well is formed, for example, by ion implantation to introduce a p-type impurity into an active region (Ac), and the n-well is, for example, an ion implantation method for an active region (Ac). ) is formed by introducing an n-type impurity. As described above, the wells are associated with the lower portion of the element isolation region STI and extend in the Y direction with a predetermined width (refer to FIG. 6, FIG. 12, etc.). Also, three wells (P-well, N-well, P-well) are arranged in the X direction. In other words, a p-well is disposed on both sides of the n-well. Further, a semiconductor region (not shown) for forming a channel may be formed on the surface of each well. The semiconductor region for forming the channel is formed to adjust the threshold voltage of the formed channel.

Further, a gate insulating film GO is formed on the main surface of the active region (Ac). For example, a ruthenium oxide film or the like can be used as the gate insulating film GO. This gate insulating film GO can be formed, for example, by a thermal oxidation method, a CVD method, or the like.

Further, a gate electrode G is formed on the gate insulating film GO (Fig. 7, Fig. 8). For example, a polycrystalline germanium film can be used as the gate electrode G. For example, on the semiconductor substrate 1 including the gate insulating film GO, a polycrystalline germanium film is deposited by a CVD method or the like, and patterned, whereby the gate electrode G can be formed. Further, the gate electrode G may be formed by multi-crystallizing a laminated film of a ruthenium film and a metal film.

Further, the gate insulating film may be changed to a high-K film, and the gate electrode may be a metal gate structure.

Here, the term "patterning" means a process in which a photoresist film on a target film to be processed is exposed to a desired shape, and then a photoresist film is used as a mask to etch a target film. When the gate electrode (G) is patterned, as described above, the gate electrode (G) arranged with a fine line width and a wide space can be formed with high precision by using a double exposure technique or the like. The layout of the present embodiment (see Fig. 2 and the like) is also suitable when the double exposure technique is applied.

Further, an n-type low-concentration impurity region EX1 is formed in the p-well (P-well) on both sides of the gate electrode G (FIG. 7, FIG. 8). The n-type low-concentration impurity region EX1 is formed by using the gate electrode G as a mask and introducing an n-type impurity into the active region (AcP) by an ion implantation method. A p-type low-concentration impurity region EX1 is formed in an n-type well (N-well) on both sides of the gate electrode G (FIG. 7, FIG. 8). The p-type low-concentration impurity region EX1 is formed by using a gate electrode G as a mask and introducing a p-type impurity into an active region (AcN) by an ion implantation method.

Further, side walls SW are formed on the side walls of both sides of the gate electrode G (FIG. 7, FIG. 8). This side wall SW is composed of, for example, a tantalum nitride film. For example, after an insulating film such as a tantalum nitride film is deposited on the semiconductor substrate 1 including the gate electrode G by the CVD method, by performing an anisotropic etching, the insulating film can be left as a sidewall SW to the gate electrode. The side wall of G.

Further, an n-type high-concentration impurity region EX2 is formed in a p-type well (P-well) on both sides of the composite body of the gate electrode G and the side wall SW (Fig. 7, Figure 8). The n-type high-concentration impurity region EX2 is formed by using the above-described composite as a photomask and introducing an n-type impurity by an ion implantation method. Further, a p-type high-concentration impurity region EX2 is formed in the n-type well (N-well) on both sides of the above-described composite (FIG. 7, FIG. 8). The p-type high-concentration impurity region EX2 is formed by using the above-described composite as a photomask and introducing a p-type impurity by an ion implantation method. The high-concentration impurity region EX2 has a higher impurity concentration than the low-concentration impurity region EX1 and is formed deep. The source ‧ drain region of the LDD (Lightly Doped Drain) structure is formed by the low-concentration impurity region EX1 and the high-concentration impurity region EX2. In addition, the source ‧ bungee region means a region that becomes a source or a drain. Further, the source ‧ bungee region is sometimes expressed as "one end" or "other end" of the transistor.

As described above, in the present embodiment, the driver transistor division (TND1, TND2, TND3, and TND4) is disposed in the different active regions (AcP2, AcP1, AcP4, and AcP3). This configuration is also apparent from the cross section shown in Fig. 7 and the like. Further, in the present embodiment, access transistors (TNA1, TNA2) are also disposed in the divided active regions (TND1, TND2, TND3, and TND4). This configuration is also apparent from the cross section shown in Fig. 7 and the like.

Further, as a method of forming the transistor, a so-called Gate Last which forms a metal gate may be used after the trench of the gate pattern is formed by the dummy gate.

As shown in Fig. 9 to Fig. 11, the high-concentration impurity region EX2 (source ‧ bungee region) of each transistor (TNA1, TND1, TND2, TP1, etc.) The plug P1 is configured on the domain). Further, although the cross-sectional views of FIGS. 9 to 11 are not present, a plug P1 (see FIG. 2) is actually formed also on the gate electrode G. The plug P1 can be formed, for example, by a second engineering. A laminated film of a tantalum nitride film and a hafnium oxide film is formed on the semiconductor substrate 1 including each of the transistors (TNA1, TND1, TND2, TP1, etc.) as the interlayer insulating film IL1. Next, a contact hole is formed in the interlayer insulating film IL1, and a conductive film is deposited on the interlayer insulating film IL1 including the inside of the contact hole. As the conductive film, a laminated film of a barrier film and a metal film can be used. As the barrier film, for example, a Ti (titanium) film or a TiN (titanium nitride) film or a laminated film of these can be used. Further, as the metal film, for example, a W (tungsten) film or the like can be used. The conductive film other than the contact hole is removed from the deposited conductive film by the CMP method or the like, whereby the conductive film can be buried in the contact hole.

Further, the first layer wiring M1 is disposed on the plug P1. This first layer wiring M1 can be formed by patterning a conductive film. Further, the first layer wiring M1 may be a buried wiring (inlaid wiring).

Further, on the first layer wiring M1, the second layer wiring M2 (LVSS, BL, /BL, LVDD, etc.) is placed via the second plug P2. In other words, the wirings will be placed in the same layer. The second plug P2 can be formed in the same manner as the first plug P1 in the interlayer insulating film IL2. The second layer wiring M2 can be formed in the same manner as the first layer wiring M1. The second layer wiring M2 can also be used as the buried wiring. In this case, a so-called dual damascene method in which the conductive film is buried in the contact hole and the inside of the wiring trench, and the second plug P2 and the second layer wiring M2 are formed.

Further, the second layer wiring M2 is disposed via the third plug P3. There is a third layer wiring M3 (WL). The third plug P3 can be formed in the same manner as the first plug P1 in the interlayer insulating film IL3. The third layer wiring M3 can be formed in the same manner as the first layer wiring M1. This third layer wiring M3 can also be used as a buried wiring. In this case, a so-called dual damascene method may be used in which a conductive film is buried in the contact hole and the inside of the wiring trench, and the third plug P3 and the third layer wiring M3 are formed.

Further, the formation process of each of the patterns constituting the cross-sectional structure is not limited, but may be formed, for example, in the next order. First, after the element isolation region STI is formed in the semiconductor substrate 1, a well (P-well, N-well, P-well) is formed. Then, the gate insulating film GO and the gate electrode G are formed to form the low-concentration impurity region EX1, and the sidewall SW is formed to form the high-concentration impurity region EX2, thereby forming each transistor (TNA1, TND1, TND2, TP1, etc.) ( Refer to Figure 7, etc.). Then, the interlayer insulating film, the plug and the wiring are formed, whereby the first to third layer wirings (M1 to M3) and the like are formed. Then, a plurality of layers of wiring can be formed. Further, each pattern constituting the connection unit (power supply unit) to be described later may be formed at the same time, and a peripheral circuit or the like for driving a decoder of the SRAM or the like may be simultaneously formed.

In the following embodiments, the cross-sectional view and the description of the forming process are omitted. However, the cross-section of the transistor portion is similar to the cross-sectional structure of the present embodiment, and of course, it can be formed by the same process.

[Composition of memory array]

Fig. 12 is a view showing the memory cell array of the SRAM of the embodiment; The floor plan of the reading. 13 and 14 are plan views showing the configuration of a memory cell array of the SRAM of the embodiment. FIG. 13 is a layout showing a pattern from the lower layer to the second plug P2, and FIG. 14 is a layout of a pattern above the second plug P2. The area shown in Fig. 13 and Fig. 14 corresponds to a 2 × 2 unit area from the lower side to the second stage of Fig. 12 from the left to the second column.

As shown in FIG. 12, when the memory cell area described with reference to FIGS. 2 to 4 is indicated by "F", the memory cell array is in the vertical direction (Y direction) in the drawing, and the pair extends in X. The line (X-axis) line of the direction repeats the memory cell area (X-axis inversion) symmetrically, and repeats the line symmetrically with respect to the line extending in the Y direction (Y-axis) in the left-right direction (X direction) in the figure. Configure the memory area (Y-axis inversion).

The layout and cross-sectional structure of the memory cell region (the rectangular region surrounded by a dotted line) indicated by "F" are as described in detail with reference to the plan views of FIGS. 2 to 4 and the cross-sectional views of FIGS. 6 to 11. . Further, in the memory cell region other than the memory cell region indicated by "F", the shape of each pattern is line-symmetric with respect to a line extending in the X direction or the Y direction (see FIG. 13, FIG. 14).

Here, as described above, each well (P-well, N-well, P-well) in the memory cell region extends in the Y direction (FIG. 13). Moreover, the P-well on the outer side of the memory cell region is connected to the P-well of the memory cell region adjacent thereto, so if viewed as a whole of the memory cell array, the p-well and the n-well (N- Well) will be alternately configured in the X direction.

[Description of Connection Unit Area]

As described with reference to FIG. 12, a plurality of unit regions (for example, m×n) are arranged in the memory cell array, but a connection cell region (power supply region) is provided in the memory cell array. Each well is supplied with a predetermined potential (for example, a ground potential VSS or a power supply potential VDD) via the connection unit region.

The position of the connection unit region in the memory cell array of the SRAM of the present embodiment is conceptually shown in FIG. As shown in the figure, the connection unit (power supply unit) is arranged in each of the n memory cell regions arranged in the Y direction, and is arranged in line in the X direction symmetrically with respect to the line extending in the Y direction. In other words, a connection unit area is disposed every m×n array area portions, and this connection unit area is a plurality of connection units that are arranged in the X direction. One of the plurality of connection units arranged in the X direction is indicated by "F'".

Figs. 16 and 17 are plan views showing the configuration of the connection unit (F') of the SRAM of the embodiment. FIG. 16 shows an arrangement of an active region (power supply portion, potential application portion) AcS, a virtual gate electrode DG, a first plug P1, a first layer wiring M1, and a second plug P2. FIG. 17 shows the arrangement of the second plug P2, the second layer wiring M2, the third plug P3, and the third layer wiring M3. Therefore, in FIGS. 16 and 17, the plan view is superimposed on the basis of the second plug P2, whereby the positional relationship of the patterns displayed in the respective drawings is clear. In addition, the area of the rectangle surrounded by a dotted line in the figure indicates a 1-connected unit area, and is set to be the same size as the memory area, for example.

In the memory cell region, each well extending in the Y direction (P-well, N- Well, P-well) also extends in the Y direction in the connection unit shown in FIG. 16, and the p-well, the n-well, and the p-well Arrange in the X direction.

Further, the active region AcS for power supply is provided in the connection unit region, and the three active regions AcS are arranged in the X direction. Between these active regions (AcS) is a component separation region (STI).

Specifically, each active region AcS is an exposed region of each well (P-well, N-well, P-well), and is formed in a substantially rectangular shape having a long side in the X direction. Further, the three active regions AcS are arranged on the same line extending in the X direction.

The first plug P1 is disposed on the active region AcS on the p-well on the left side in FIG. 16, and the first layer wiring M1 is disposed on the first plug P1. Further, the second plug P2 is disposed on the first layer wiring M1. The second layer wiring M2 (LVSS) is disposed on the second plug P2 (FIG. 17). The second layer wiring M2 (LVSS) is a ground potential line described in the column of "pattern layout of the memory cell". Further, in the connection unit region, the third plug P3 is disposed on the second layer wiring M2 (LVSS), and the third layer wiring M3 (CVSS) is disposed on the upper portion thereof. The third layer wiring M3 (CVSS) is a common ground potential line that is connected to each ground potential line of the connection unit arranged in the X direction (FIG. 17).

The first plug P1 is disposed on the active region AcS on the n-well, and the first layer M1 is disposed on the first plug P1. Further, the second plug P2 is disposed on the first layer wiring M1. The second layer wiring M2 (LVDD) is disposed on the second plug P2 (FIG. 17). This first The two-layer wiring M2 (LVDD) is a power supply potential line described in the column of "pattern layout of the memory cell". Further, in the connection unit region, the third plug P3 is disposed on the second layer wiring M2 (LVDD), and the third layer wiring M3 (CVDD) is disposed on the upper portion thereof. The third layer wiring M3 (CVDD) is a common power supply potential line that is connected to each ground potential line of the connection unit arranged in the X direction (FIG. 17).

The first plug P1 is disposed on the active region AcS on the right side p-well (P-well) in FIG. 16, and the first layer wiring M1 is disposed on the first plug P1. Further, the second plug P2 is disposed on the first layer wiring M1. The second layer wiring M2 (LVSS) is disposed on the second plug P2 (FIG. 17). The second layer wiring M2 (LVSS) is a ground potential line described in the column of "pattern layout of the memory cell". Further, in the connection unit region, the third plug P3 is disposed on the second layer wiring M2 (LVSS), and the third layer wiring M3 (CVSS) is disposed on the upper portion thereof. The third layer wiring M3 (CVSS) is the common ground potential line that is connected to each ground potential line of the connection unit arranged in the X direction (FIG. 17).

In addition, in the connection unit area, the bit line (the second layer wiring M2 (BL), the second layer wiring M2 (/BL)) described in the column of the "pattern layout of the memory cell" is extended (FIG. 17). .

Further, as shown in FIG. 16, in the connection unit region, a dummy gate electrode (virtual gate wiring, dummy gate) DG extending in the X direction is disposed in the element isolation region STI. The virtual gate electrode is a conductive film that is provided in the element isolation region (STI) and cannot operate the transistor. The conductive film is the same material as the gate electrode G, and has the same engineering shape. to make.

By thus setting the dummy gate electrode DG, the unevenness caused by the gate electrode is regularly repeated, and the regularity of the layout is improved. As a result, manufacturing variations and the like can be reduced, and the device characteristics can be improved. The dummy gate electrode DG is arranged in a line extending in the X direction. However, the separation portion Sp is appropriately provided here, and the division is arranged (see FIG. 16).

Fig. 18 is a plan view showing the concept of a memory cell and a connection unit forming region of the SRAM of the embodiment. 19 and 20 are plan views showing the configuration of the memory cell and the connection unit forming region of the SRAM of the present embodiment. 19 is a layout showing a pattern from the lower layer to the second plug P2, and FIG. 20 is a layout showing a pattern above the second plug P2. The area shown in Figs. 18 to 20 is a unit area of 2 × 3, and the connection unit area is arranged in the second stage from the lower side.

As shown in Figs. 18 to 20, the dummy gate electrode DG of the connection unit (F') is disposed at both ends in the Y direction of the connection unit so as to sandwich the active region (AcS). In this case, the dummy gate electrode DG may be arranged to extend in an uninterrupted line shape in the X direction. However, the virtual gate electrode may be appropriately cut so as to correspond to the gate electrode G of the adjacent memory cell. Electrode DG. In other words, a separation portion (Sp) is provided. By configuring the dummy gate electrode DG in this way, the regularity of the gate electrode G and the dummy gate electrode DG is further improved, and the device characteristics can be improved.

Further, each of the patterns (AcS, DG, P1 to P3, M1 to M3, and the like) constituting the connection unit can be formed in the same manner as each of the patterns constituting the memory cell.

(Embodiment 2)

In the first embodiment, among the six active regions (AcP2, AcP1, AcN1, AcN2, AcP3, AcP4) arranged in the X direction, AcP2 and AcP1 of the divided driver transistors (TND1 and TND2) are disposed. The length in the X direction (width in the X direction) is equal. Further, the lengths of the AcP4 in which the driver transistors (TND3 and TND4) are arranged and the AcP3 in the X direction (the width in the X direction) are made equal. These can also be set to different lengths (widths). The width of the active region (Ac) in the X direction corresponds to the gate width of each transistor. Therefore, in other words, in the first embodiment, the gate width of the driver transistor (TND1) is made equal to the gate width of the driver transistor (TND2), and the gate width of the driver transistor (TND3) is made to the driver transistor. The gate width of (TND4) is equal.

In contrast, in the present embodiment, the gate width of the driver transistor (TND1) is different from the gate width of the driver transistor (TND2), and the gate width of the driver transistor (TND3) and the driver transistor are made. The gate width of (TND4) is different.

21 and 22 are plan views showing the configuration of the memory cell of the SRAM of the embodiment. 21 is a view showing the arrangement of the active region Ac, the gate electrode G, and the first plug P1. FIG. 22 shows the arrangement of the first plug P1, the first layer wiring M1, and the second plug P2. Therefore, in FIGS. 21 and 22, the plan view is superimposed on the basis of the first plug P1, whereby the positional relationship of the patterns displayed in the respective drawings is clear. In addition, the configuration of the second plug line M2, the third plug line M3, and the third layer line M3 are arranged in comparison with the above-described second plug P2. The same as when the form 1 is applied. Further, a rectangular area surrounded by a dotted line in the figure is a memory cell area indicating 1 (1 bit).

The configuration of the memory cell is the same as the length of the AcP2 and the AcP1 in the X direction (the width in the X direction) and the length of the AcP4 and the AcP3 in the X direction (the width in the X direction), and is the same as that in the first embodiment, and thus the detailed description thereof is omitted. instruction of.

As shown in FIG. 21, for example, when the widths of the active region AcP2 and the active region AcP1 are respectively WAcP2 and WAcP1, WAcP2<WAcP1 may be used. Further, when the widths of the active region AcP3 and the active region AcP4 are respectively WAcP3 and WAcP4, WAcP4<WAcP3 may be used.

As described above, in the present embodiment, the ratio of the driving ability of the driver transistors (TND1 and TND2, TND3 and TND4) to the driving ability of the access transistors (TNA1, TNA2) can be easily adjusted. That is, the β ratio can be simply adjusted by merely changing the width of the active regions (AcP2 and AcP1, AcP4 and AcP3).

In the first embodiment, the gate width of the access transistor (TNA1, TNA2) and the gate width of the driver transistor (the sum of the gate widths of TND1 and TND2, and the sum of the gate widths of TND3 and TND4) are set. It is 1:2, but this ratio is adjusted according to the characteristics of SRAM. That is, depending on the device, there is a case where it is desired to change the capability ratio of the access transistor to the driver transistor in accordance with the intended use, for example, to make the readout characteristics better than the write characteristics. Here, the gate width of the access transistor (TNA1, TNA2) is set to "a", and the gate width of the driver transistor is wide (the gate width of TND1 and TND2 is wide). And, the sum of the gate widths of TND3 and TND4 is set to "b". For this ratio a:b, the value of b when a is set to 1 (i.e., b/a, sometimes called "β ratio"). The range of adjustment is, for example, that it is desirable to adjust b/a in a range of 1.1 or more and 3 or less. More preferably, b/a is adjusted in a range of 1.5 or more and 2.5 or less.

This is because, for example, if b/a=1.1, the gate width of the driver transistor TND1 and the access transistor TNA1 are made equal, and when it is 1, the gate width of the driver transistor TND2 is 0.1, which is equivalent. The narrow gate is very wide, so the pattern will not settle.

Therefore, the gate widths of the driver transistors TND1 and TND2 are formed to be 0.75 front and rear.

In contrast, if b/a=1.5, the gate width of the driver transistor TND2 is 0.5, a general pattern is formed, or the gate width of the driver transistor TND1 and the access transistor TNA1 may be nearly equal. .

Further, if b/a = 3, for example, the gate width of the access transistor TNA1 is 1, and the gate width of the driver transistors TND1 and TND2 is 1.5.

In contrast, the gate width of the access transistor TNA1 is set to 1, and the gate widths of the driver transistors TND1 and TND2 are set to 1.25, and the gates of the access transistor TNA1 and the driver transistor TND1 are wide. The difference may be smaller than the case of the above "b/a=3", which is preferable.

Further, although the width of the other active regions (AcN1, AcN2) is not limited, it is set to be the same as the width of the active region AcP2 and the active region AcP4.

Also, the above relationship can be set to the opposite (WAcP2>WAcP1, WAcP4>WAcP3) adjusts the β ratio, but it is conceivable that the width of the active region (AcP1, AcP3) in which two transistors are arranged is increased, the manufacturing variation is small, and the controllability of characteristics is also high.

Further, since the arrangement of the gate electrode G and the first plug P1 is the same as that of the first embodiment (FIG. 2), the description thereof will be omitted. In the first plug P1 shown in FIG. 22, the arrangement of the first layer wiring M1 and the second plug P2 is also the same as that of the first embodiment (FIG. 3), and thus the description thereof will be omitted.

As described above, in the present embodiment, in addition to the effects described in detail in the first embodiment, the above effects can be achieved.

(Embodiment 3)

In the connection unit described in the first embodiment, the active region AcS on the p-well (P-well) is connected to the second layer wiring M2 (LVSS), and the active region AcS on the n-well (N-well) is connected. Connected to the second layer wiring M2 (LVDD). The second layer wiring M2 (LVSS) is a ground potential line described in the column of "pattern layout of the memory cell", and the second layer wiring M2 (LVDD) is a power source described in the column of "pattern layout of the memory cell". Potential line. That is, the trap power is supplied via the ground potential line or the power source potential line connected to the memory cell, but the well power supply may be performed by a wiring (third potential wiring) other than the ground potential line or the power source potential line. In the present embodiment, the second ground potential line (LVSSB) is used as the wiring for power supply of the p-well.

[Description of Connection Unit Area]

23 and 24 are plan views showing the configuration of a connection unit of the SRAM of the embodiment. FIG. 23 shows an arrangement of the active region AcS, the dummy gate electrode DG, the first plug P1, the first layer wiring M1, and the second plug P2. FIG. 24 shows the arrangement of the second plug P2, the second layer wiring M2, the third plug P3, and the third layer wiring M3. Therefore, in FIGS. 23 and 24, the plan view is superimposed on the basis of the second plug P2, whereby the positional relationship of the patterns displayed in the respective drawings is clear. Further, a rectangular area surrounded by a one-dotted line in the figure is a unit indicating a 1-connected unit area (for example, an area corresponding to F' in Fig. 18), and is set to have the same size as the memory area, for example.

In the memory cell region, each well (P-well, N-well, P-well) extending in the Y direction extends in the Y direction in the connection unit shown in FIG. 23, and the p-well (P-well) ), the n-well and the p-well are arranged in the X direction.

Further, the active region AcS for power supply is provided in the connection unit region, and the three active regions AcS are arranged in the X direction. Between these active regions (AcS) is a component separation region (STI).

Specifically, each active region AcS is an exposed region of each well (P-well, N-well, P-well), and is formed in a substantially rectangular shape having a long side in the X direction. Further, the active region AcS of 3 is disposed on the same line extending in the X direction.

The first plug P1 is disposed on the active region AcS on the p-well on the right side in the figure, and the first layer wiring M1 is disposed on the first plug P1. Further, the second plug P2 is disposed on the first layer wiring M1 (FIG. 23). The second layer wiring M2 is disposed on the second plug P2. (LVSSB) (Figure 24).

The second layer wiring M2 (LVSSB) is a second ground potential line and is a wiring different from the ground potential line (the second layer wiring M2 (LVSS)) described in the column of the "pattern layout of the memory cell". Further, in the connection unit region, the third plug P3 is disposed on the second layer wiring M2 (LVSS), and the third layer wiring M3 is disposed on the upper portion thereof. The third layer wiring M3 is a common second ground potential line that is connected to each of the second ground potential lines of the connection unit arranged in the X direction (FIG. 24).

Similarly, the first plug P1 is disposed on the active region AcS on the p-well on the right side in the figure, and the first layer wiring M1 is disposed on the first plug P1. Further, the second plug P2 is disposed on the first layer wiring M1. The second layer wiring M2 (LVSSB) is disposed on the second plug P2.

The second layer wiring M2 (LVSSB) is a second ground potential line and is different from the ground potential line (the second layer wiring M2 (LVSS)) described in the column of "the layout of the memory cell". Further, in the connection unit region, the third plug P3 is disposed on the second layer wiring M2 (LVSS), and the third layer wiring M3 is disposed on the upper portion thereof. The third layer wiring M3 is the common second ground potential line that is connected to each of the second ground potential lines of the connection unit arranged in the X direction (FIG. 24).

In the active region AcS on the n-well, the first plug P1, the first layer wiring M1, and the second layer via the plug P2 are disposed in the same manner as in the first embodiment. Wiring M2 (LVDD). This second layer wiring M2 (LVDD) is becoming "memory" The power potential line described in the column of the grid pattern layout. Further, in the connection unit region, the third plug P3 is disposed on the second layer wiring M2 (LVDD), and the third layer wiring M3 (CVDD) is disposed on the upper portion thereof. The third layer wiring M3 (CVDD) is a common power supply potential line that is connected to each ground potential line of the connection unit arranged in the X direction (see FIG. 24, FIG. 17).

In the connection unit region, a common ground potential line is disposed via the third plug P3 on the ground potential line (the second layer wiring M2 (LVSS)) extending from the memory cell region (the third layer wiring M3 (CVSS) )) (Fig. 24, Fig. 17).

As described above, in the present embodiment, since the ground potential line connected to the memory cell supplies power to the p-well (P-well) by another wiring, the p-well can be individually fixed. The potential (the back gate potential of the transistor) and the potential connected to the ground potential of the memory cell.

For example, the potential of the ground potential line connected to the memory cell can be set to about 0.1 V, and the fixed potential of the p-well (P-well) (the back gate potential of the transistor) can be set to 0V. By thus lowering the fixed potential of the p-type well to the potential of the ground potential line connected to the memory cell, a feedback bias effect is generated, and a leakage current can be reduced. By thus connecting the ground potential line connected to the memory cell and the wiring for power supply of the p-well (P-well) as individual wirings, fine adjustment of the transistor characteristics can be performed, and the device characteristics can be improved.

Fig. 25 is a circuit diagram showing a memory cell of the SRAM of the embodiment. The composition of the memory cell and the circuit operation are the same as those in the first embodiment. Similarly, for example, the connection relationship of the transistors is the same as the circuit diagram shown in FIG. 1 or FIG. 5, but the back gate potential of the transistors (TND2, TNA1, TND1, TND3, TNA2, TND4) constituting the memory cell of the SRAM (in This is VSSB) different.

That is, although not explicitly shown in FIG. 5, the back gate potential of the n-type transistors (TND2, TNA1, TND1, TND3, TNA2, TND4) is actually the ground potential of the back gate of the eight transistors. (VSS), the back gate potential of the p-type transistor (TP1, TP2) is the power supply potential (VDD). On the other hand, in FIG. 25, the back gate potential of the n-type transistors (TND2, TNA1, TND1, TND3, TNA2, TND4) becomes the second ground potential (VSSB). In addition, the back gate potential of the p-type transistor (TP1, TP2) is the power supply potential (VDD).

Further, in the present embodiment, the ground potential line is set to another wiring, but the power supply potential line may be set as another wiring.

For example, in the active region AcS on the n-well shown in FIG. 16, the first plug P1 is placed in the same manner as in the first embodiment, and the first plug P1 is placed on the first plug P1. Layer wiring M1. The second plug P2 is provided on the first layer wiring M1, and the second layer wiring is disposed. This second layer wiring is disposed on the right side of the power supply potential line (LVDD) shown in FIG. 16 and becomes the second power supply potential line (LVDDB). In other words, among the two second layer wirings, the left side is set to the power supply potential line (LVDD), and the right side is set to the second power supply potential line (LVDDB). Then, the power supply potential line (LVDD) and the second power supply potential line (LVDDB) are respectively connected to the respective third layer wiring (common power source potential line via the third plug P3). The second power supply potential line is connected.

According to the above configuration, the back gate potential of the p-type transistor (TP1, TP2) can be set to the second power supply potential (VDDB). For example, by providing a p-type transistor having a relatively high on-resistance value between the second power supply potential line (LVDDB) and a power supply potential line (power supply potential line (LVDD)) connected to the memory cell, the latch can be suppressed. The occurrence of a lock-up phenomenon.

As described above, the ground potential (VSS) side may be configured as another wiring, and the power supply potential (VDD) side may be set to another wiring configuration. Of course, other wiring configurations may be applied to both the ground potential (VSS) side and the power supply potential (VDD) side.

(Embodiment 4)

In the memory cell described in the first embodiment, six active regions (Fig. 2) are arranged in the X direction in the order of AcP2, AcP1, AcN1, AcN2, AcP3, and AcP4, but the positions of AcP2 and AcP1 may be replaced. And replace the position of AcP3 and AcP4 (refer to Figure 26).

[Composition of memory]

[Memory grid layout]

26 to 28 are plan views showing the configuration of the memory cell of the SRAM of the embodiment. FIG. 26 shows the arrangement of the active region Ac, the gate electrode G, and the first plug P1. FIG. 27 shows the arrangement of the first plug P1, the first layer wiring M1, and the second plug P2. Figure 28 is a diagram showing the second plug P2, the arrangement of the second layer wiring M2, the third plug P3, and the third layer wiring M3. Therefore, in FIGS. 26 and 27, the plan view is superimposed on the basis of the first plug P1, whereby the positional relationship of the patterns displayed in the respective drawings is clear. Further, in FIGS. 27 and 28, the plan view is superimposed on the basis of the second plug P2, whereby the positional relationship of the patterns displayed in the respective drawings is clear. In addition, the area of the rectangle surrounded by a dotted line in the figure is a memory cell area indicating 1 (1 bit).

As shown in FIG. 26, in the semiconductor substrate, a p-well, an n-well, and a p-well are arranged in the X direction. In Fig. 26, only one (1-bit) memory cell area is displayed. However, as described above, the memory cell is repeatedly arranged in the X direction and the Y direction (refer to Figs. 12 to 14), and the wells are P-well, N-well, P-well) is formed to extend in the Y direction. In addition, the exposed regions of the wells become active regions (active regions, Ac).

Further, in the semiconductor substrate, six active regions are arranged side by side in the X direction. Unlike the case of the first embodiment, in the present embodiment, AcP1, AcP2, AcN1, AcN2, AcP4, and AcP3 are arranged in this order.

The other configurations (G, P1, etc.) are the same as those in the first embodiment, and thus detailed description thereof will be omitted. Further, in the first plug P1 shown in FIGS. 27 and 28, the arrangement of the first layer wiring M1, the second plug P2, the second layer wiring M2, the third plug P3, and the third layer wiring M3 is also one side. The case of the first embodiment described with reference to Figs. 3 and 4 is substantially the same, and thus detailed description thereof will be omitted.

As described above, in the present embodiment, in the memory cell region, the arrangement of the substantially rectangular active regions AcP1 and AcP2 having the long sides in the Y direction is such that the AcP1 longer than the long side is away from the n-well (N-well). Configuration. Further, in the memory cell region, the arrangement of the substantially rectangular active regions AcP4 and AcP3 having long sides in the Y direction is arranged such that AcP3 longer than the long side is disposed away from the n-well (N-well). With such a configuration, the well proximity effect can be reduced.

The well proximity effect means that, for example, a photoresist film is formed in a region other than the introduction region of the n-type impurity, and introduction of the n-type impurity is prevented, whereby the n-type well is implanted into the end portion of the photoresist film (for example) The n-type impurity in the element isolation region STI is diffused to the gate electrode or the source ‧thole region of the n-type transistor formed in the p-type well, and the characteristics of the n-type transistor are deteriorated. Similarly, in a p-type transistor, it is also affected by a p-type impurity at the time of formation of a p-type well. As described above, in the boundary portion between the n-type well and the p-type well, variation in the transistor characteristics due to the well-contact effect is likely to occur, and this problem is remarkable due to the miniaturization of the memory cell.

However, in the present embodiment, the active region longer than the long side, in other words, the active regions (AcP1 and AcP3) in which more transistors are disposed away from the n-well and the p-well (P) -well) is configured to reduce the well proximity effect and improve transistor characteristics.

Further, for reference, eight transistors (TND2, TNA1, TND1, TP1, TP2, TND3, TNA2, TND4) are arranged corresponding to the above-mentioned "pattern layout of the memory cell", and a circuit diagram showing the connection states is shown. In Figure 29.

As can be seen from Fig. 29, the transistors TNA1 and TNA2 are arranged away from the boundary of the n-well and the p-well (see the arrows in the figure).

In this way, the well proximity effect can be reduced, and the transistor characteristics (for example, characteristics of TNA1 or TNA2, etc.) can be improved.

In the present embodiment, in addition to the effects described in detail in the first embodiment, the above effects can be achieved.

(Embodiment 5)

In the memory cell described in the first embodiment, the first plug P1 is provided on the source ‧th pole region of each transistor and the gate electrode G, and the upper layer wiring is used to connect the wires. The common plug (common contact) SP1 is used to connect the wires.

30 to 32 are plan views showing the configuration of the memory cell of the SRAM of the embodiment. FIG. 30 shows an arrangement of the active region Ac, the gate electrode G, the first plug P1, and the common first plug SP1. FIG. 31 shows an arrangement in which the first plug P1 shares the first plug SP1 and the first layer wiring M1 and the second plug P2. FIG. 32 shows the arrangement of the second plug P2, the second layer wiring M2, the third plug P3, and the third layer wiring M3. Therefore, in FIGS. 30 and 31, the plan view is superimposed on the basis of the first plug P1 and the common first plug SP1, whereby the positional relationship of the patterns displayed in the respective drawings is clear. Further, in FIGS. 31 and 32, the plan view is superimposed on the basis of the second plug P2, whereby the positional relationship of the patterns displayed in the respective drawings is clear. In addition, the area of the rectangle surrounded by a dotted line in the figure is 1 (1) The memory cell area of the bit).

[Memory grid layout]

In the pattern layout of the memory cell of the present embodiment, the configuration other than the portion in which the first plug SP1 is shared is the same as that in the first embodiment. Therefore, the detailed description thereof will be omitted, and the configuration in which the vicinity of the first plug SP1 is shared will be described in detail. .

As shown in Fig. 30, in the present embodiment, as in the first embodiment, the p-well, the n-well and the p-well are arranged in the X direction. Configuration. Further, six active regions (AcP2, AcP1, AcN1, AcN2, AcP3, AcP4) are arranged in the X direction. Between these active regions (Ac) is a component separation region (STI).

In the above six active regions (AcP2, AcP1, AcN1, AcN2, AcP3, AcP4), the gate electrode G is extended by a gate insulating film (GO) so as to be able to pass through each active region in the X direction. The eight transistors described in the column of "circuit configuration" of the first embodiment are constructed.

Specifically, a common gate electrode G1 is disposed so as to pass through the active regions AcP2, AcP1, and AcN1. Thereby, TND2 is disposed on the active region AcP2, TND1 is disposed on the active region AcP1, and TP1 is disposed on the active region AcN1 to connect the gate electrodes (G). In the active region AcP1, another gate electrode G2 is disposed in parallel with the above-described common gate electrode G1. In this way, TNA1 is disposed on the active region AcP1, and the source ‧thole region of TNA1 and the source ‧thole region of TND1 are connected (commonized).

Further, a common gate electrode G3 is disposed so as to pass through the active regions AcP4, AcP3, and AcN2. Thereby, TND4 is disposed on the active region AcP4, TND3 is disposed on the active region AcP3, and TP2 is disposed on the active region AcN2, and the gate electrode (G) is connected to the active region AcN2. In the active region AcP3, another gate electrode G4 is disposed in parallel with the above-described common gate electrode G3. Thereby, TNA2 is disposed on the active region AcP3, and the source ‧thole region of the TNA 2 and the source ‧thole region of the TND 3 are connected (combined).

Further, the four gate electrodes G are arranged on the same line. Specifically, the common gate electrode G1 passing through the active region AcP2, AcP1 and AcN1 and the gate electrode G4 on the active region AcP3 are arranged on the same line extending in the X direction. The common gate electrode G3 passing through the active region AcP4, AcP3 and AcN2 and the gate electrode G2 on the active region AcP1 are arranged on the same line extending in the X direction.

The first plug P1 is disposed on the source ‧th pole region of the above eight transistors (TND2, TNA1, TND1, TP1, TP2, TND3, TNA2, TND4). Further, the first plug P1 is also disposed on the four gate electrodes.

Here, in the source ‧th pole region of one of TP2 and the common gate electrode G1 of TP1, TND2, and TND1, a common plug (integrated plug) is disposed to share the first plug SP1. And, at TP1 On the common gate electrode G3 of one of the source ‧th pole regions and TP2, TND3, and TND4, the first plug SP1 is provided with a continuous plug.

In this manner, the source ‧thole region and the gate electrode G to be electrically connected can be connected by using the common first plug SP1.

By using the shared first plug SP1 as described above, the arrangement of the first plugs P1d and P1h shown in FIG. 2 is not required, so that the distance between the active regions AcN1 and AcN2 can be reduced as shown in FIG. Therefore, for example, compared with the memory cell of the first embodiment (see Fig. 2), the memory cell area can be reduced.

In addition, the layout of the pattern of the upper layer of the first plug P1 and the common first plug SP1, that is, the first layer wiring M1, the second plug P2, the second layer wiring M2, the third plug P3, and the third As shown in FIG. 31 and FIG. 32, the arrangement of the layer wiring M3 is almost the same as that of the first embodiment described with reference to FIGS. 3 and 4, and thus detailed description thereof will be omitted.

Further, for reference, eight transistors (TND2, TNA1, TND1, TP1, TP2, TND3, TNA2, TND4) are arranged corresponding to the above-mentioned "pattern layout of the memory cell", and a circuit diagram showing the connection states is shown. In Figure 33.

In this FIG. 33, according to the above-mentioned common junction of the first plug SP1, corresponding to the circle in the figure, the source ‧thole region and the gate electrode G utilize a continuous plug (shared 1 plug SP1) to tie the line.

By using the shared first plug SP1 as described above, the memory cell area can be reduced.

In the present embodiment, in addition to the effects described in detail in the first embodiment, the above effects can be achieved.

(Embodiment 6)

In the first embodiment, the length (the length in the vertical direction in the drawing) of the side of the Y-direction extending in the memory cell region of the substantially rectangular shape is the length (height) of two parts of the transistor to be described later. The length of the side in the Y direction extending from the memory cell region of the substantially rectangular shape is set to be the length of 4 parts of the transistor. The length of one part of the transistor means the sum (a1+b1) of a1 and b1 when the width of the gate electrode in the Y direction is a1 and the distance in the Y direction between the gate electrodes is b1. For example, in the first embodiment, the length of the side extending in the Y direction of the memory cell region is 2 (a1 + b1), which is the length of two copies of the transistor (see Fig. 2). Further, in the present embodiment, the length of the side extending in the Y direction extending from the memory cell region is 4 (a1 + b1).

In other words, in the first embodiment, the gate electrode G is arranged in two stages (two rows). However, in the present embodiment, the gate electrode G is arranged in four stages (four rows).

The circuit configuration and circuit operation of the memory cell of the SRAM of the present embodiment are the same as those of the first embodiment described with reference to Fig. 1 .

[Structure of SRAM]

[Composition of memory]

34 to 36 are diagrams showing the memory cell of the SRAM of the embodiment. The floor plan that constitutes. FIG. 34 shows the arrangement of the active region A, the gate electrode G, and the first plug P1. FIG. 35 shows the arrangement of the first plug P1, the first layer wiring M1, and the second plug P2. FIG. 36 shows the arrangement of the second plug P2, the second layer wiring M2, the third plug P3, and the third layer wiring M3. Therefore, in FIGS. 34 and 35, the plan view is superimposed on the basis of the first plug P1, whereby the positional relationship of the patterns displayed in the respective drawings is clear. Further, in FIGS. 35 and 36, the plan view is superimposed on the basis of the second plug P2, whereby the positional relationship of the patterns displayed in the respective drawings is clear. In addition, the area of the rectangle surrounded by a dotted line in the figure is a memory cell area indicating 1 (1 bit).

[Memory grid layout]

[A, G, P1]

As shown in FIG. 34, in the semiconductor substrate, a p-well, an n-well, and a p-well are arranged in the X direction. In Fig. 34, only one (1 bit) memory cell area is displayed, but the actual memory cell is repeatedly arranged in the X direction and the Y direction (refer to Fig. 12), and these wells (P-well, N-well) , P-well) is formed extending in the Y direction. In addition, the exposed regions of the wells become active regions (active regions, A).

Further, in the semiconductor substrate, three active regions (AP1, AN, AP2) are arranged side by side in the X direction. Between these active regions (A) is a component separation region (STI). In other words, the active region (A) is partitioned by a component separation region (STI). And, each of the above wells (P- Well, N-well, P-well) is the lower contact of the element separation region STI.

Specifically, the active region AP1 is an exposed region of a p-well and has a substantially rectangular shape having a long side in the Y direction. In addition, in FIG. 34, only one (1 bit) memory cell area is displayed for convenience, but the actual memory cell is repeatedly arranged in the X direction and the Y direction (refer to FIG. 12), and thus the memory cell array is The active area AP1 is continuously arranged in the active area of the adjacent memory cell (here, the memory cell on the lower side of the memory cell area shown in FIG. 34).

The active region AN is an exposed region of an n-well and has a substantially rectangular shape having a long side in the Y direction.

The active region AP2 is an exposed region of a p-well (P-well) located on the right side of the n-type well, and has a substantially rectangular shape having a long side in the Y direction. Further, the memory cell is repeatedly arranged in the X direction and the Y direction (refer to FIG. 12). Therefore, in the memory cell array, the active area AP2 is adjacent to the memory cell (here, the memory on the upper side of the memory cell area shown in FIG. The active area of the grid is continuously arranged.

In the three active regions (AP1, AN, AP2), the gate electrode G extends through the gate insulating film (GO) so as to be able to pass through the active regions in the X direction, and is configured in Embodiment 1. The eight transistors described in the column of "Circuit Configuration".

Specifically, two common gate electrodes (G1, G3) are disposed so as to pass through the active regions AP1, AN, and AP2. Thereby, on the active area AP2, TND2 and TND3 will share the source ‧ bungee area The domains are arranged in series. On the active region AP1, TND1 and TND4 share a source ‧ a drain region and are arranged in series. Further, in the active region AN, TP1 and TP2 share a source ‧ a drain region and are arranged in series. Further, TND1, TP1 and TND2 gate electrodes (G) are connected by one common gate electrode G1, and TND3, TP2 and TND4 gate electrodes are connected by the other common gate electrode G3 (G). ). The two common gate electrodes (G1, G3) are arranged to extend in parallel in the X direction.

Further, in the active region AP1, a gate electrode G2 is disposed in parallel with the two common gate electrodes G. Thereby, TNA1 is disposed on the active region AP1, and the source ‧thole region of TNA1 and the source ‧thole region of TND1 are connected (commonized). Further, in the active region AP2, another gate electrode G4 is disposed in parallel with the two common gate electrodes (G1, G3). Thereby, TNA2 is disposed on the active region AP2, and the source ‧thole region of the TNA 2 and the source ‧thole region of the TND 3 are connected (combined).

As described above, in the present embodiment, the driver transistor division (TND1, TND2, TND3, and TND4) is disposed on the different active regions (AP1, AP2). Further, by extending the active regions (AP1, AP2) in the Y direction, the layout becomes simple and the processing accuracy is improved.

Therefore, similarly to the first embodiment, the shape of the active region (A) is not provided with a corner portion (bending portion), and the gate width of the access transistor and the gate width of the driver transistor can be easily made 1:2.

Further, since three transistors are disposed in each of the active regions (AP1, AP2), the number of active regions can be reduced. Thereby, a simple layout can be realized, and the memory cell area can be reduced.

Further, by extending the active region (A) in the Y direction, the gate electrode (G) can be extended in the X direction, and not only the processing accuracy of the active region (A) but also the processing accuracy of the gate electrode (G) can be achieved. Upgrade. In particular, as described in detail in the first embodiment, the use of the multiple exposure technique is facilitated, and the processing accuracy can be improved. Moreover, the simulation mode is made easy, and the inspection accuracy can be improved.

[P1, M1, P2]

As shown in FIG. 35, the first plug is placed on the source ‧th pole region of the eight transistors (TND2, TNA1, TND1, TP1, TP2, TND3, TNA2, TND4) described with reference to FIG. P1. Further, the first plug P1 is also disposed on the four gate electrodes described with reference to FIG. 34 described above.

The first layer wiring M1 is disposed on the first plug P1, and electrical connection between the first plugs P1 can be achieved.

Specifically, the first plug P1A on one source ‧ the drain region of TND2, and the first plug P1B on the common source ‧ drain region of TND1 and TNA1, and one source of TP1 The first plug P1C on the drain region and the first plug P1D on the common gate electrode (G3) of TP2, TND3, and TND4 are connected by the first layer wiring (first node wiring) M1A. This first layer wiring M1A can be combined with the accumulation section of FIG. Point A corresponds. The above "one side" is a source ‧ a bungee region on the lower side in the figure.

The first plug P1E on the source ‧th pole region of one of TND4, the first plug P1F on the common source ‧thole region of TND3 and TNA2, and the source ‧thole region of one of TP2 The first plug P1G on the upper plug and the first plug P1H on the common gate electrode (G1) of TP1, TND1, and TND2 are connected by the first layer wiring M1B. The first layer wiring (second node wiring) M1B can correspond to the storage node B of FIG. 1 . Here, "one side" means a source ‧ a bungee region on the upper side in the figure.

Further, a first layer wiring (pad region) M1S is disposed on the first plug P1I on the other source ‧ drain region of the TND 2 . Further, the first layer wiring M1S is disposed on the first plug P1J on the other source ‧ drain region of the TND 1 .

Further, a first layer wiring (pad region) M1D is disposed on the first plug P1K on the common source ‧ drain region of TP1 and TP2. The first layer wiring M1D can correspond to the power supply potential (VDD) of FIG. 1, and is connected to the power supply potential line (LVDD) as will be described later.

Further, the first plug P1L on the other source ‧ drain region of the TNA 1 and the first plug P1M on the other source ‧ drain region of the TNA 2 are respectively arranged with the first layer wiring M1BL.

Further, the first layer wiring M1W is disposed on the first plug P1N on the gate electrode (G2) of the TNA1 and the first plug P1O on the gate electrode (G4) of the TNA2.

The connection state of the first layer wiring M1 between the plurality of first plugs P1 is variously modified as long as it conforms to the state of the junction of the circuit diagram shown in FIG. 1.

[P2, M2, P3, M3]

As shown in FIG. 36, among the first layer wirings M1 described with reference to FIG. 35, the first layer other than the first layer wiring M1 (M1A, M1B) corresponding to the storage node (A or B) The second plug P2 is disposed on the wiring M1, and the second layer wiring M2 is disposed on the upper portion thereof.

Specifically, the first layer wiring M1W connected to the gate electrode (G2) of the TNA 1 is connected to the second layer wiring M2W via the second plug P2. Further, the first layer wiring M1W connected to the gate electrode (G4) of the TNA 2 is connected to the second layer wiring M2W via the second plug P2. The two second layer wirings M2W are disposed at both end portions in the X direction of the memory cell region, and are arranged to extend in the Y direction. Further, the third plug P3 is disposed on the two second layer wirings M2W, and the third layer wiring M3 (WL) is disposed in the X direction so that the two third plugs P3 can be connected. This third layer wiring M3 (WL) is a word line.

Further, the first layer wiring (pad region) M1S connected to the source ‧ 汲 region (P1I) common to TND2 and TND3 is connected to the second layer wiring M2 (LVSS) via the second plug P2. This second layer wiring M2 (LVSS) is a ground potential line. The first layer wiring (pad area) M1S connected to the source ‧thole region (P1J) common to TND1 and TND4 is via the second plug P2 and the second layer wiring M2 (LVSS) connection. This second layer wiring M2 (LVSS) is a ground potential line. The two ground potential lines are inside the two second layer wirings M2 disposed at both end portions of the memory cell region, and are arranged to extend in the Y direction.

Further, the first layer wiring M1BL connected to the other source ‧ drain region of the TNA 1 is connected to the second layer wiring M2 (BL) via the second plug P2. This second layer wiring M2 (BL) is one of the bit lines of the bit line pair. The first layer wiring M1BL connected to the other source ‧ drain region of the TNA 2 is connected to the second layer wiring M2 (/BL) via the second plug P2. This second layer wiring M2 (/BL) is another bit line. The two bit lines (BL, /BL) are arranged inside the two ground potential lines (LVSS) so as to extend in the Y direction.

Further, the first layer wiring (pad region) M1D connected to the source ‧ 汲 region (P1K) common to TP1 and TP2 is connected to the second layer wiring M2 (LVDD) via the second plug. This second layer wiring M2 (LVDD) is a power supply potential line.

The connection state of the second plug P2, the second layer wiring M2, the third plug P3, and the third layer wiring M3 is variously deformed as long as it conforms to the state of the wiring of the circuit diagram shown in FIG. In general, the second layer wiring M2 is mainly extended in the Y direction, and the third layer wiring M3 is mainly extended in the X direction, thereby achieving a simple layout. In addition, in FIG. 34 to FIG. 36, only one (1 bit) memory cell area is displayed for convenience. However, as will be described later, the memory cell is repeatedly arranged in the X direction and the Y direction, and thus is memorized. In the grid array, the above ground potential line (LVSS), the bit line (BL, /BL), the power supply potential line (LVDD) is arranged to extend in the Y direction, and the word line (WL) is arranged to extend in the X direction.

Further, in the present embodiment, since the ground potential line (LVSS) is disposed between the second layer wiring M2W (the second layer wiring connected to the word line) and the bit line (BL, /BL), it is generated. The shielding effect of the ground potential line (LVSS) can reduce the interaction (crosstalk noise) between the second layer wiring M2W (the second layer wiring connected to the word line) and the bit line (BL, /BL).

Further, each of the patterns described with reference to FIGS. 34 to 36 is arranged in point symmetry with respect to the center point of the memory cell region.

Further, for reference, eight transistors (TND2, TNA1, TND1, TP1, TP2, TND3, TNA2, TND4) are arranged corresponding to the above-mentioned "pattern layout of the memory cell", and a circuit diagram showing the connection states is shown. In Figure 37.

[Composition of memory array]

The memory cell array of the SRAM of the present embodiment is arranged in an array in the same manner as in the first embodiment. That is, as described with reference to Fig. 12 in the first embodiment, the memory cell region ("F") is repeatedly arranged in line symmetry with respect to the line extending in the X direction, and is repeated for the line extending in the Y direction. Configured to be line symmetrical.

[Description of Connection Unit Area]

Further, in the memory cell array of the SRAM of the present embodiment, as in the first embodiment, a connection unit region is provided. Each well is supplied with a predetermined potential (for example, a ground potential VSS or a power supply potential VDD) via the connection unit region.

(Embodiment 7)

In the sixth embodiment, the p-well, the n-well and the p-well are arranged in the X direction (Fig. 34), but the n-type may be used. The p-wells on both sides of the well (N-well) are arranged in one side (Fig. 38).

Further, in the present embodiment, as in the sixth embodiment, the length of the side extending in the Y direction extending from the substantially rectangular memory cell region is set to be four lengths of the crystal. In other words, in the present embodiment, the gate electrode G is arranged in four stages (four rows).

The circuit configuration and circuit operation of the memory cell of the SRAM of the present embodiment are the same as those of the first embodiment described with reference to FIG.

[Structure of SRAM]

[Composition of memory]

38 to 40 are plan views showing the configuration of the memory cell of the SRAM of the embodiment. 38 is a view showing the arrangement of the active region A, the gate electrode G, and the first plug P1. FIG. 39 shows the arrangement of the first plug P1, the first layer wiring M1, and the second plug P2. Figure 40 is a view showing the second plug P2, the arrangement of the second layer wiring M2, the third plug P3, and the third layer wiring M3. Therefore, in FIGS. 38 and 39, the plan view is superimposed on the basis of the first plug P1, whereby the positional relationship of the patterns displayed in the respective drawings is clear. Further, in FIGS. 39 and 40, the plan view is superimposed on the basis of the second plug P2, whereby the positional relationship of the patterns displayed in the respective drawings is clear. In addition, the area of the rectangle surrounded by a dotted line in the figure is a memory cell area indicating 1 (1 bit).

[Memory grid layout]

[A, G, P1]

As shown in FIG. 38, in the semiconductor substrate, an n-well and a p-well are arranged in the X direction. In Fig. 38, only one (1 bit) memory cell area is displayed, but the actual memory cell is repeatedly arranged in the X direction and the Y direction (see Fig. 12), so both wells (N-well, P-well) ) is formed extending in the Y direction. In addition, the exposed regions of the wells become active regions (active regions, A).

Further, in the semiconductor substrate, three active regions (AN, AP1, AP2) are arranged side by side in the X direction. Between these active regions (A) is a component separation region (STI). In other words, the active region (A) is partitioned by a component separation region (STI). Further, each of the above wells (N-well, P-well) is associated with the lower portion of the element isolation region STI.

Specifically, the active region AN is an exposed region of an n-well and has a substantially rectangular shape having a long side in the Y direction.

The active region AP1 is an exposed region of a p-well (P-well) located on the right side of the n-type well, and has a substantially rectangular shape having a long side in the Y direction. In addition, in FIG. 38, only one (1 bit) memory cell area is displayed for convenience, but the actual memory cell is repeatedly arranged in the X direction and the Y direction, so in the memory cell array, the active area AP1 It extends linearly in the Y direction.

The active region AP2 is an exposed region of the p-well (P-well), and is disposed beside the active region AP1 and has a substantially rectangular shape having a long side in the Y direction.

In the above three active regions (AN, Ap1, AP2), the gate electrode G is extended so as to pass through each active region in the X direction via the gate insulating film (GO), and is configured in Embodiment 1. The eight transistors described in the column of "Circuit Configuration".

Specifically, two common gate electrodes (G1, G3) are disposed so as to pass through the active regions AN, AP1 and AP2. Therefore, in the active region AP2, TND2 and TND4 share the source ‧thole region and are arranged in series. On the active region AP1, TND1 and TND3 share the source ‧thole region and are arranged in series, and in the active region On the AN, TP1 and TP2 will share the source ‧ 汲 region and be connected in series. Further, TP1, TND1 and TND2 gate electrodes (G) are connected by one common gate electrode G1, and TP2, TND3 and TND4 gate electrodes are connected by the other common gate electrode G3 (G) ). The two common gate electrodes G are arranged to extend in the X direction in parallel.

And, on the active area AP1, the two common gates The electrodes (G1, G3) are arranged in parallel with a gate electrode G2. Thereby, TNA1 is disposed on the active region AP1, and the source ‧thole region of TNA1 and the source ‧thole region of TND1 are connected (commonized). Further, in the active region AP1, another gate electrode G4 is disposed in parallel with the two common gate electrodes G. Thereby, TNA2 is disposed on the active region AP1, and the source ‧thole region of the TNA 2 and the source ‧thole region of the TND 3 are connected (combined).

As described above, in the present embodiment, the driver transistor division (TND1, TND2, TND3, and TND4) is disposed on the different active regions (AP1, AP2). Further, by extending the active regions (AP1, AP2) in the Y direction, the layout becomes simple and the processing accuracy is improved.

Therefore, similarly to the first embodiment, the shape of the active region (A) is not provided with a corner portion (bending portion), and the gate width of the access transistor and the gate width of the driver transistor can be easily made 1:2.

Further, since the access transistor (TNA1, TNA2) is also disposed in the active region (AP1), the number of active regions can be reduced. Here, the access transistor (TNA1, TNA2) is also disposed in the active region (AP1), but one access transistor may be disposed in each of the two active regions AP1 and AP2. In this manner, the remaining n-type transistors may be appropriately disposed in the active region (here, AP1, AP2) disposed to divide the driver transistor. Thereby, the number of active areas can be reduced. As a result, a simple layout can be realized, and the memory cell area can be reduced.

And, by extending the active region (A) in the Y direction, the gate can be The electrode (G) extends in the X direction, and not only the processing accuracy of the active region (A) but also the processing accuracy of the gate electrode (G) can be improved. In particular, as described in detail in the first embodiment, the use of the multiple exposure technique is facilitated, and the processing accuracy can be improved. Moreover, the simulation mode is made easy, and the inspection accuracy can be improved.

[P1, M1, P2]

As shown in FIG. 39, the first insertion is arranged in the source ‧th pole region of the eight transistors (TND2, TNA1, TND1, TP1, TP2, TND3, TNA2, TND4) described with reference to FIG. 38 described above. Plug P1. Further, the first plug P1 is also disposed on the four gate electrodes described with reference to FIG. 38 described above.

The first layer wiring M1 is disposed on the first plug P1, and electrical connection between the first plugs P1 can be achieved.

Specifically, the first plug P1A on one source ‧ the drain region of TND2, and the first plug P1B on the common source ‧ drain region of TND1 and TNA1, and one source of TP1 The first plug P1C on the drain region and the first plug P1D on the common gate electrode (G3) of TP2, TND3, and TND4 are connected by the first layer wiring M1A. This first layer wiring (first node wiring) M1A can correspond to the accumulation node A of FIG. The above "one side" is a source ‧ a bungee region on the lower side in the figure.

The first plug P1E on one of the source ‧ bungee regions of TND4, and the first plug on the common source ‧ bungee region of TND3 and TNA2 The first plug P1G on the source ‧th pole region of one of P1F and TP2, and the first plug P1H on the common gate electrode (G1) of TP1, TND1, and TND2 are connected by the first layer ( The second node wiring) M1B is connected. This first layer wiring M1B can correspond to the accumulation node B of FIG. Here, "one side" means a source ‧ a bungee region on the upper side in the figure.

Further, the first plug P1P on the common source ‧th pole region of TND2 and TND4, and the first plug P1Q on the common source ‧thole region of TND1 and TND3 are connected by the first layer wiring M1S connection. The first layer wiring M1S can correspond to the ground potential (VSS) of FIG. 1, and is connected to the ground potential line (LVSS) as will be described later.

Further, the first layer wiring M1D is disposed on the first plug P1R on the common source ‧ drain region of TP1 and TP2. The first layer wiring M1D can correspond to the power supply potential (VDD) of FIG. 1, and is connected to the power supply potential line (LVDD) as will be described later.

Further, the first layer wiring M1BL is disposed on the first plug P1S on the other source ‧ drain region of the TNA 1 and the first plug P1T on the other source ‧ drain region of the TNA 2 . Further, the first plug P1U on the gate electrode (G2) of the TNA1 and the first plug P1V on the gate electrode (G4) of the TNA 2 are connected by the first layer wiring M1W.

The connection state of the first layer wiring M1 between the plurality of first plugs P1 is variously modified as long as it conforms to the state of the junction of the circuit diagram shown in FIG. 1.

[P2, M2, P3, M3]

As shown in FIG. 40, the first layer wiring M1 described above with reference to FIG. 39 is the first layer other than the first layer wiring M1 (M1A, M1B) corresponding to the storage node (A or B). The second plug P2 is disposed on the layer wiring M1, and the second layer wiring M2 is disposed on the upper portion thereof.

Specifically, the first layer wiring M1W connected to the gate electrode (G2) of the TNA 1 and the gate electrode (G4) of the TNA 2 is connected to the second layer wiring M2W via the second plug P2. The second layer wiring M2W is disposed at an end portion of the memory cell region in the X direction and is arranged to extend in the Y direction. Further, the third plug P3 is disposed on the second layer wiring M2, and the third layer wiring M3 (WL) extending in the X direction is disposed on the third plug P3. This third layer wiring M3 (WL) is a word line.

Also, with the source of the other side of TNA1. The first layer wiring M1BL connected to the drain region (P1S) is connected to the second layer wiring M2 (BL) via the second plug P2. This second layer wiring M2 (BL) is one of the bit lines of the bit line pair.

The first layer wiring M1BL connected to the other source ‧ 汲 region (P1T) of the TNA 2 is connected to the second layer wiring M2 (/BL) via the second plug P2. This second layer wiring M2 (/BL) is another bit line. The two bit lines (BL, /BL) are respectively arranged to extend in the Y direction.

Moreover, the common source ‧ bungee region of the common source ‧ bungee region (P1P) and TND1, TND3 of TND2, TND4 The first layer wiring M1S connected to (P1Q) is connected to the second layer wiring M2 (LVSS) via the second plug P2. This second layer wiring M2 (LVSS) is a ground potential line. This ground potential line is arranged between the two bit lines (BL, /BL) to extend in the Y direction.

Further, the first layer wiring M1D connected to the source ‧ drain region (P1R) common to TP1 and TP2 is connected to the second layer wiring M2 (LVDD) via the second plug. This second layer wiring M2 (LVDD) is a power supply potential line.

The connection state of the second plug P2, the second layer wiring M2, the third plug P3, and the third layer wiring M3 is variously deformed as long as it conforms to the state of the wiring of the circuit diagram shown in FIG. In general, the second layer wiring M2 is mainly extended in the Y direction, and the third layer wiring M3 is mainly extended in the X direction, thereby achieving a simple layout. In addition, in FIG. 34 to FIG. 36, only one (1 bit) memory cell area is displayed for convenience. However, as will be described later, the memory cell is repeatedly arranged in the X direction and the Y direction, and thus is memorized. In the grid array, the ground potential line (LVSS), the bit line (BL, /BL), the power supply potential line (LVDD) are arranged to extend in the Y direction, and the word line (WL) is arranged to extend in the X direction.

Further, in the present embodiment, since the ground potential line (LVSS) is disposed between the bit lines (BL, /BL), the shielding effect of the ground potential line (LVSS) is generated, and the bit line (BL, /BL) interaction (crosstalk noise)

Moreover, in the present embodiment, since in the memory cell area, The p-well is disposed on one side of the well (N-well), so compared with the case of Embodiment 6 (Fig. 34), the n-well and the p-well (P-well) The boundary area will be reduced, which can reduce the aforementioned well proximity effect.

In addition, for reference, eight transistors (TND2, TNA1, TND1, TP1, TP2, TND3, TNA2, TND4) are arranged corresponding to the above-mentioned "pattern layout of the memory cell", and a circuit diagram showing the connection states is shown. In Figure 41.

[Composition of memory array]

The memory cell array of the SRAM of the present embodiment is arranged in an array in the same manner as in the first embodiment. That is, as described with reference to Fig. 12 in the first embodiment, the memory cell region ("F") is repeatedly arranged in line symmetry with respect to the line extending in the X direction, and is repeated for the line extending in the Y direction. Configured to be line symmetrical.

[Description of Connection Unit Area]

Further, in the memory cell array of the SRAM of the present embodiment, as in the first embodiment, a connection unit region is provided. Each well is supplied with a predetermined potential (for example, a ground potential VSS or a power supply potential VDD) via the connection unit region.

The memory cell array of the SRAM of the present embodiment has a connection unit (F') similarly to the first embodiment (Fig. 15). The connecting unit (F') is arranged in each of the n memory cell regions arranged in the Y direction, and the pair extends to Y. The line of the direction is line-symmetrically arranged in the X direction. In Fig. 15, one of the plurality of connection units arranged in the X direction is indicated by "F'".

Fig. 42 and Fig. 43 are plan views showing the configuration of the connection unit (F') of the SRAM of the embodiment. 42 is a view showing the arrangement of the active region AcS, the dummy gate electrode DG, the first plug P1, the first layer wiring M1, and the second plug P2. FIG. 43 shows the arrangement of the second plug P2, the second layer wiring M2, the third plug P3, and the third layer wiring M3. Therefore, in FIGS. 42 and 43, the plan view is superimposed on the basis of the second plug P2, whereby the positional relationship of the patterns displayed in the respective drawings is clear. In addition, the area of the rectangle surrounded by a dotted line in the figure indicates a 1-connected unit area, and is set to be the same size as the memory area, for example.

In the memory cell region, each well (N-well, P-well) extending in the Y direction extends in the Y direction in the connection unit shown in FIG. 42, and the n-well and the p-type The wells (P-well) are arranged in the X direction.

Further, the active region AcS for power supply is provided in the connection unit region, and the two active regions AcS are arranged in the X direction. Between these active regions (AcS) is a component separation region (STI).

Specifically, each active region AcS is an exposed region of each well (P-well, N-well), and is formed in a substantially rectangular shape having a long side in the X direction. Further, the two active regions AcS are arranged on the same line extending in the X direction.

On the active area AcS on the p-well on the left side of the figure The first plug P1 is disposed, and the first layer wiring M1 is disposed on the first plug P1. Further, the second plug P2 is disposed on the first layer wiring M1. The second layer wiring M2 (LVSS) is disposed on the second plug P2. The second layer wiring M2 (LVSS) is a ground potential line described in the column of "pattern layout of the memory cell". Further, in the connection unit region, the third plug P3 is disposed on the second layer wiring M2 (LVSS), and the third layer wiring M3 (CVSS) is disposed on the upper portion thereof. The third layer wiring M3 (CVSS) is a common ground potential line that is connected to each ground potential line of the connection unit arranged in the X direction (FIG. 43).

The first plug P1 is disposed on the active region AcS on the n-well on the left side of the figure, and the first layer wiring M1 is disposed on the first plug P1. Further, the second plug P2 is disposed on the first layer wiring M1. The second layer wiring M2 (LVDD) is disposed on the second plug P2. The second layer wiring M2 (LVDD) is a power supply potential line described in the column of "pattern layout of the memory cell". Further, in the connection unit region, the third plug P3 is disposed on the second layer wiring M2 (LVDD), and the third layer wiring M3 (CVDD) is disposed on the upper portion thereof. The third layer wiring M3 (CVDD) is a common power supply potential line connected to each ground potential line of the connection unit arranged in the X direction (FIG. 43).

Further, in the connection unit area, the bit line (the second layer wiring M2 (BL), the second layer wiring M2 (/BL)) described in the column of the "pattern layout of the memory cell" is extended (FIG. 43). .

Further, as shown in FIG. 42, in the connection unit region, a dummy gate electrode extending in the X direction is disposed on the element isolation region STI. DG. By thus setting the dummy gate electrode DG, the unevenness caused by the gate electrode is regularly repeated, and the regularity of the layout is improved. As a result, manufacturing variations and the like can be reduced, and the device characteristics can be improved.

(Embodiment 8)

In the memory cell described in the seventh embodiment, the three active regions are arranged in the X direction in the order of AN, AP1, and AP2 (FIG. 38), but the positions of AP1 and AP2 may be replaced (see FIG. 44). ).

[Composition of memory]

[Memory grid layout]

44 to 46 are plan views showing the configuration of the memory cell of the SRAM of the embodiment. 44 is a view showing the arrangement of the active region (A), the gate electrode G, and the first plug P1. 45 is a view showing the arrangement of the first plug P1, the first layer wiring M1, and the second plug P2. FIG. 46 shows the arrangement of the second plug P2, the second layer wiring M2, the third plug P3, and the third layer wiring M3. Therefore, in FIGS. 44 and 45, the plan view is superimposed on the basis of the first plug P1, whereby the positional relationship of the patterns displayed in the respective drawings is clear. Further, in FIGS. 45 and 46, the plan view is superimposed on the basis of the second plug P2, whereby the positional relationship of the patterns displayed in the respective drawings is clear. Further, a rectangular area surrounded by a dotted line in the figure is a memory cell area indicating 1 (1 bit).

As shown in FIG. 44, in the semiconductor substrate, an n-well and a p-well are arranged in the X direction. In Figure 44, Only one (1-bit) memory cell area is displayed, but as described above, the memory cell is repeatedly arranged in the X direction and the Y direction (refer to FIG. 12), so the wells (N-well, P-well) ) is to extend in the Y direction. In addition, the exposed regions of the wells become active regions (active regions, A).

Further, in the semiconductor substrate, three active regions are arranged side by side in the X direction. Unlike the case of the seventh embodiment, in the present embodiment, the arrangement is arranged in the order of AN, AP2, and AP1.

The other configurations (G, P1, etc.) are the same as those in the seventh embodiment, and thus detailed description thereof will be omitted. Further, in the first plug P1 shown in FIG. 45 and FIG. 46, the arrangement of the first layer wiring M1, the second plug P2, the second layer wiring M2, the third plug P3, and the third layer wiring M3 is also one side. The case of the first embodiment described with reference to Figs. 39 and 40 is substantially the same, and thus detailed description thereof will be omitted.

As described above, in the present embodiment, in the memory cell region, the active region AP1 extending linearly in the Y direction is disposed away from the boundary between the n-well and the p-well. In other words, the active area in which more transistors are disposed is disposed away from the above-described boundary. Thereby, the distance between the boundary of the n-well and the p-well and the active region AP1 becomes larger, and the aforementioned well-contact effect can be reduced. As a result, the transistor characteristics can be obtained.

Further, for reference, eight transistors (TND2, TNA1, TND1, TP1, TP2, TND3, TNA2, TND4) are arranged corresponding to the above-mentioned "pattern layout of the memory cell", and the circuit in which the connection states are indicated will be described. The figure is shown in Figure 47.

It can also be seen from Fig. 47 that the transistors TNA1 and TNA2 are arranged away from the boundary of the n-well and the p-well (see the arrows in the figure).

In this way, the well proximity effect can be reduced, and the transistor characteristics (for example, characteristics of TNA1 or TNA2, etc.) can be improved.

In the present embodiment, in addition to the effects described in detail in the first embodiment, the above effects can be achieved.

(Embodiment 9)

In the first embodiment, a so-called single-port SRAM (Fig. 1) will be described as an example. However, in the present embodiment, it is directed to a so-called dual-port SRAM (Fig. 48). The applicable examples are explained.

[circuit composition]

Fig. 48 is an equivalent circuit diagram showing a memory cell of the SRAM of the embodiment. Unlike the equivalent circuit diagram (FIG. 1) described in the first embodiment, there are two pairs of bit line pairs (BLA and /BLA, BLB and /BLB) and two word lines (WLA, WLB).

As shown in FIG. 48, the memory cell is disposed at the intersection of the two pairs of bit lines and the two word lines WL. This memory cell has a pair of load transistors (loading MOS, load transistor, load MISFET) TP1, TP2, 2 pairs of access transistors (access MOS, save The transistor is used to access the MISFET, the transfer transistor) TNA1 and TNA3, TNA2 and TNA4, and a pair of driver transistors (driver MOS, drive MISFET) TND2, TND4.

Here, in the present embodiment, the driver transistor TND1 is provided in parallel with the driver transistor (drive MISFET) TND2. Further, the driver transistor TND3 is connected in parallel with the driver transistor (drive MISFET) TND4.

Among the transistors constituting the above memory cell, the loaded transistor is a p-type (p channel type) transistor, and the access transistor and the driver transistor are n-type (n channel type) transistors.

Further, among the eight transistors constituting the memory cell, TND2 and TP1 constitute a CMOS inverter, and TND4 and TP2 constitute another CMOS inverter. The mutual input/output terminals (accumulation nodes A, B) of the pair of CMOS inverters are cross-coupled to form a flip-flop circuit as an information storage unit that stores information of one bit.

Here, in the memory cell of the SRAM of the present embodiment, TND1 is provided in parallel with TND2, and TND3 is provided in parallel with TND4. Therefore, it is also possible to form CMOS inverters with TND1, TND2, and TP1, and TND3, TND4, and TP2. To form other CMOS inverters.

Therefore, the connection relationship of the ten transistors constituting the SRAM memory cell of the present embodiment will be described in detail as follows.

TP1 is connected between the power supply potential (first potential) and the accumulation node A, and TND1 and TND2 are connected in parallel between the storage node A and the ground potential (the reference potential, the second potential lower than the first potential), and The gate electrodes of TP1, TND1 and TND2 are connected to the accumulation node B.

TP2 is connected between the power supply potential (first potential) and the accumulation node B, and TND3 and TND4 are connected in parallel between the storage node B and the ground potential (the reference potential, the second potential lower than the first potential), and TP2 The gate electrodes of TND3 and TND4 are connected to the accumulation node A.

TNA1 is connected between the bit line BLA and the accumulation node A, TNA3 is connected between the bit line /BLA and the accumulation node B, and the gate electrodes of TNA1 and TNA3 are connected to the word line WLA (becomes a word) Yuan line).

Further, TNA2 is connected between the bit line BLB and the accumulation node A, TNA4 is connected between the bit line /BLB and the accumulation node B, and the gate electrodes of TNA2 and TNA4 are connected to the word line WLB ( Become a word line).

As described above, in the SRAM memory cell of the present embodiment, the driver transistor is divided (TND1, TND2, TND3, and TND4).

As described above, the dual-port SRAM is an entrance/exit (埠) for the signal for input and output of two data, and even if the data is read by one of the files, it can be simultaneously written by the other party. Data can be processed at high speed.

[Structure of SRAM]

[Composition of memory]

49 to 51 are plan views showing the configuration of the memory cell of the SRAM of the embodiment. Figure 49 is a diagram showing the active region Ac, the gate electrode G and The configuration of the first plug P1. FIG. 50 shows the arrangement of the first plug P1, the first layer wiring M1, and the second plug P2. FIG. 51 shows the arrangement of the second plug P2, the second layer wiring M2, the third plug P3, and the third layer wiring M3. Therefore, in FIGS. 49 and 50, the plan view is superimposed on the basis of the first plug P1, whereby the positional relationship of the patterns displayed in the respective drawings is clear. Further, in FIGS. 50 and 51, the plan view is superimposed on the basis of the second plug P2, whereby the positional relationship of the patterns displayed in the respective drawings is clear. Further, a rectangular area surrounded by a dotted line in the figure is a memory cell area indicating 1 (1 bit).

[Memory grid layout]

[Ac, G, P1]

As shown in FIG. 49, in the semiconductor substrate, a p-well, an n-well, and a p-well are arranged in the X direction. In Fig. 49, only one (1 bit) memory cell area is displayed. However, as will be described later, the memory cell is repeatedly arranged in the X direction and the Y direction (see Fig. 12), and thus the wells (P- Well, N-well, P-well) is to extend in the Y direction. In addition, the exposed regions of the wells become active regions (active regions, Ac).

Further, in the semiconductor substrate, six active regions (AcP2, AcP1, AcN1, AcN2, AcP3, AcP4) are arranged in the X direction. Between these active regions (Ac) is a component separation region (STI). In other words, the active region (Ac) is distinguished by a component separation region (STI). And, each of the above wells (P-well, N-well, P-well) It is associated with the lower portion of the element isolation region STI.

Specifically, the active region AcP2 is an exposed region of a p-well (P-well) and has a substantially rectangular shape having a long side in the Y direction. The active region AcP1 is disposed adjacent to the active region AcP2 and is an exposed region of a p-well (P-well) having a substantially rectangular shape having a long side in the Y direction. In addition, in FIG. 49, only one (1 bit) memory cell area is displayed for convenience, but the actual memory cell is repeatedly arranged in the X direction and the Y direction, so in the memory cell array, the active area AcP1 And AcP2 extends linearly in the Y direction.

The active region AcN1 is an exposed region of an n-well and has a substantially rectangular shape having a long side in the Y direction. The active region AcN2 is an exposed region of an n-well and has a substantially rectangular shape having a long side in the Y direction.

The active region AcP3 is an exposed region of a p-well (P-well) located on the right side of the n-type well, and has a substantially rectangular shape having a long side in the Y direction. The active region AcP4 is disposed beside the active region AcP3 and is an exposed region of the p-well (P-well), and has a substantially rectangular shape having a long side in the Y direction. Further, in the memory cell array, the active regions AcP3 and AcP4 extend linearly in the Y direction.

On the above six active regions (AcP2, AcP1, AcN1, AcN2, AcP3, AcP4), the gate electrode G is extended by a gate insulating film (GO) so as to be able to pass through each active region in the X direction. The ten transistors described in the column of "Circuit Configuration" described above are constructed.

Specifically, to be able to pass through the active region AcP2, AcP1 and The common gate electrode G1 is configured in the manner of AcN1. Thereby, TND2 is disposed on the active region AcP2, TND1 is disposed on the active region AcP1, and TP1 is disposed on the active region AcN1 to connect the gate electrodes (G). In the active region AcP1, a gate electrode G2b is disposed in parallel with the above-described common gate electrode G1. Thereby, TNA1 is disposed on the active region AcP1, and the source ‧thole region of TNA1 and the source ‧thole region of TND1 are connected (commonized). Further, in the active region AcP2, a gate electrode G2a is disposed in parallel with the common gate electrode G1. Thereby, TNA2 is disposed on the active region AcP2, and the source ‧thole region of the TNA 2 and the source ‧thole region of the TND 2 are connected (combined).

Further, a common gate electrode G3 is disposed so as to pass through the active regions AcP4, AcP3, and AcN2. Thereby, TND3 is disposed on the active region AcP4, TND4 is disposed on the active region AcP3, and TP2 is disposed on the active region AcN2, and the gate electrode (G) is connected to the active region AcN2. In the active region AcP3, a gate electrode G4b is disposed in parallel with the above-described common gate electrode G3. Thereby, TNA4 is disposed on the active region AcP3, and the source ‧thole region of the TNA 4 and the source ‧thole region of the TND 4 are connected (combined). Further, in the active region AcP4, a gate electrode G4a is disposed in parallel with the common gate electrode G3. Thereby, TNA3 is disposed on the active region AcP4, and the source ‧thole region of the TNA 3 and the source ‧thole region of the TND 3 are connected (combined).

Further, each of the six gate electrodes G is arranged on the same line. on. Specifically, the common gate electrode G1 passing through the active region AcP2, AcP1 and AcN1, and the gate electrode G4b on the active region AcP3 and the gate electrode G4a on the active region AcP4 are disposed in the X direction. On the same line. The common gate electrode G3 across the active region AcP4, AcP3 and AcN2, and the gate electrode G2b on the active region AcP1 and the gate electrode G2a on the active region AcP2 are disposed on the same line extending in the X direction.

As described above, in the present embodiment, the driver transistor division (TND1, TND2, TND3, and TND4) is disposed in the different active regions (AcP2 and AcP1, AcP4, and AcP3). Further, by extending the active regions (AcP2, AcP1, AcP4, and AcP3) in the Y direction, the layout becomes simple and the processing accuracy is improved.

Therefore, similarly to the first embodiment, the shape of the active region (Ac) is not provided with a corner portion (bending portion), and the gate width of the access transistor and the gate width of the driver transistor can be easily made 1:2.

Further, since the access transistors (TNA1, TNA2, TNA3, and TNA4) are disposed in the active regions (AcP2, AcP1, AcP4, and AcP3), the number of active regions can be reduced. Thereby, a simple layout can be realized, and the memory cell area can be reduced.

Further, by extending the active region (Ac) in the Y direction, the gate electrode (G) can be extended in the X direction, and not only the processing accuracy of the active region (Ac) but also the processing accuracy of the gate electrode (G) can be achieved. Upgrade. In particular, as described in detail in the first embodiment, the use of the multiple exposure technique is facilitated, and the processing accuracy can be improved. And, the simulation mode is made to become Easy, it can improve the inspection accuracy.

[P1, M1, P2]

As shown in FIG. 50, the source and the ‧th pole region of the ten transistors (TND2, TNA2, TNA1, TND1, TP1, TP2, TND4, TNA4, TND3, TNA3) described with reference to FIG. 49 described above are arranged. There is a first plug P1. Further, the first plug P1 is also disposed on the six gate electrodes described with reference to FIG. 49 described above.

The first layer wiring M1 is disposed on the first plug P1, and the electrical connection between the first plugs P1 is achieved.

Specifically, the common plug of the TND2 and the TNA2 is the first plug P1a on the ‧th pole region, and the first plug P1b on the common source ‧thole region of TND1 and TNA1, and one of the TP1 The first plug P1c on the source ‧thole region and the first plug P1d on the common gate electrode G3 of TP2, TND3, and TND4 are connected by the first layer wiring (first node wiring) M1A. This first layer wiring M1A can correspond to the accumulation node A of FIG. The above "one side" is a source ‧ a bungee region on the upper side in the figure.

TND3, the common source of the TNA3, the first plug P1e on the ‧th pole region, and the common source of the TND4, TNA4, the first plug P1f on the 汲polar region, and the source of one of the TP2 The first plug P1g on the pole region and the first plug P1h on the common gate electrode G of TP1, TND1, and TND2 are connected by the first layer wiring M1B. This first layer wiring M1B can correspond to the accumulation node B of FIG. With the above accumulation node (A Or B) the corresponding first layer wiring M1 (M1A, M1B) is mainly arranged to extend in the X direction. Here, "one side" means a source ‧ a bungee region on the lower side in the drawing.

Further, the first plug P1j on the other source ‧ drain region of the TND 2 and the first plug P1 i on the other source ‧ drain region of the TND 1 are connected by the first layer wiring M1S. The first layer wiring M1S can correspond to the ground potential (VSS) of FIG. 48, and is connected to the ground potential line (LVSS) as will be described later.

The first plug P1k on the other source ‧ drain region of the TND 3 and the first plug P1 m on the other source ‧ drain region of the TND 4 are connected by the first layer wiring M1S. The first layer wiring M1S can correspond to the ground potential (VSS) of FIG. 48, and is connected to the ground potential line (LVSS) as will be described later.

Further, the first plug P1t on the other source ‧th pole region of the TNA 2, the first plug P1n on the other source ‧th pole region of the TNA1, and the other source of the TP1 The first layer wiring M1 (M1BL, M1D) is disposed on the first plug P1o on the drain region. Further, the first plug P1u on the other source ‧th pole region of the TNA3, the first plug P1p on the other source ‧thole region of the TNA4, and the other source of the TP2 The first layer wiring M1 (M1BL, M1D) is disposed on the first plug P1q on the drain region.

Further, the first plug P1r on the gate electrode (G2a) of the TNA2, the first plug P1v on the gate electrode (G2b) of the TNA1, and the first plug P1w on the gate electrode (G4b) of the TNA4 , and the gate of TNA3 The first layer wiring M1W is disposed on each of the first plugs P1s on the electrode (G4a).

The connection state of the first layer wiring M1 between the plurality of first plugs P1 is variously modified as long as it conforms to the state of the wiring of the circuit diagram shown in FIG.

[P2, M2, P3, M3]

As shown in FIG. 51, the first layer wiring M1 described above with reference to FIG. 50 is the first layer other than the first layer wiring M1 (M1A, M1B) corresponding to the storage node (A or B). The second plug P2 is disposed on the layer wiring M1 (M1S, M1D, M1W, M1BL), and the second layer wiring M2 is disposed on the upper layer.

Specifically, the first layer wiring M1W connected to the gate electrode (G2a) of the TNA 2 is connected to the second layer wiring M2W via the second plug P2. Further, the first layer wiring M1W connected to the gate electrode (G4b) of the TNA 4 is connected to the second layer wiring M2W via the second plug P2. The two second layer wirings M2W are arranged in the memory cell region so as to extend in the Y direction. In addition, the third plug P3 is disposed on the two second layer wirings M2W, and the third layer wiring M3 (WLB) is disposed in the X direction so that the two third plugs P3 can be connected. . This third layer wiring M3 (WLB) is a word line.

The first layer wiring M1W connected to the gate electrode (G4a) of the TNA 3 is connected to the second layer wiring M2W via the second plug P2. Further, the first layer wiring M1W connected to the gate electrode (G2b) of the TNA 1 is via The second plug P2 is connected to the second layer wiring M2W. The two second layer wirings M2 are arranged in the memory cell region so as to extend in the Y direction. In addition, the third plug P3 is disposed on the two second layer wirings M2W, and the third layer wiring M3 (WLA) is disposed in the X direction so that the two third plugs P3 can be connected. . This third layer wiring M3 (WLA) is a word line.

Further, the first layer wiring M1S connected to the other source ‧th pole region (P1j) of TND2 and the other source ‧thole region (P1i) of TND1 is via the second plug P2 and the second The layer wiring M2 (LVSS) is connected. This second layer wiring M2 (LVSS) is a ground potential line. The first layer wiring M1S connected to the other source ‧th pole region (P1m) of TND4 and the other source ‧thole region (P1k) of TND3 is via the second plug P2 and the second layer wiring M2 (LVSS) connection. This second layer wiring M2 (LVSS) is a ground potential line.

Further, the first layer wiring M1BL connected to the other source ‧thole region (P1t) of the TNA 2 is connected to the second layer wiring M2 (BLB) via the second plug P2. The first layer wiring M1BL connected to the other source ‧th pole region (P1p) of the TNA 4 is connected to the second layer wiring M2 (/BLB) via the second plug P2. The two second layer wirings M2BL (bit lines (BLB, /BLB)) are constituting bit line pairs, and are arranged to extend in the Y direction.

Further, the first layer wiring M1BL connected to the other source ‧thole region (P1n) of the TNA 1 is connected to the second layer via the second plug P2 Wiring M2 (BLA) connection. The first layer wiring M1BL connected to the other source ‧th pole region (P1u) of the TNA 3 is connected to the second layer wiring M2 (/BLA) via the second plug P2. The two second layer wirings M2 (bit lines (BLA, /BLA)) are constituting bit line pairs, and are arranged to extend in the Y direction.

Further, it is possible to connect the second plug P2 on the first layer wiring M1D connected to the other source ‧ the drain region (P1o) of the TP1, and the other source ‧ the drain region of the TP 2 ( P1q) The second layer wiring M2 (LVDD) is disposed in such a manner as to connect the second plug P2 on the first layer wiring M1D. This second layer wiring M2 (LVDD) is a power supply potential line. The power supply potential line mainly extends in the Y direction and has a line portion extending in the Y direction, and the line portion covers the protrusion portion on the second plug P2.

The connection state of the second plug P2, the second layer wiring M2, the third plug P3, and the third layer wiring M3 is variously modified as long as it conforms to the state of the wiring of the circuit diagram shown in FIG. 48. In general, the second layer wiring M2 is mainly extended in the Y direction, and the third layer wiring M3 is mainly extended in the X direction, thereby achieving a simple layout. In addition, in FIG. 49 to FIG. 51, only one (1 bit) memory cell area is displayed for convenience. However, as will be described later, the memory cell is repeatedly arranged in the X direction and the Y direction, and thus is memorized. In the grid array, the ground potential line (LVSS), the bit line (BLA, /BLA, BLB, /BLB), the power supply potential line (LVDD) are arranged to extend in the Y direction, and the word line (WLA, WLB) is Configured to extend in the X direction.

Further, in the present embodiment, since the active region is divided and disposed (AcP2, AcP1, AcP4, and AcP3), only the device isolation region (STI) portion between the active regions and the driver transistor (TND1 and TND2, TND3, and TND4) are provided. In the case where the formation region is large, the bit line or the ground potential line (LVSS) is disposed between the second layer wiring M2 (the second layer wiring M2W connected to the word line) as described above. Further, since the ground potential line (LVSS) is disposed between the bit lines, a shielding effect of the ground potential line (LVSS) is generated, and the interaction between the bit lines (crosstalk noise) can be reduced.

Further, each of the patterns described with reference to FIGS. 49 to 51 is arranged in point symmetry with respect to the center point of the memory cell region.

Further, for reference, 10 transistors (TND2, TNA2, TNA1, TND1, TP1, TP2, TND4, TNA4, TND3, TNA3) are arranged corresponding to the above-mentioned "pattern layout of the memory cell", and the connections are clearly indicated. A circuit diagram of the state is shown in Figure 52.

(Embodiment 10)

In the ninth embodiment, a dual-port SRAM (Fig. 48) in which the length of the side of the Y-direction extending in the memory cell region of the substantially rectangular shape is set to be twice the length of the transistor is described. The length of the side in the Y direction extending through the substantially rectangular memory cell region can be set to be 4 lengths of the crystal. In the present embodiment, a dual-port SRAM (FIG. 53) in which the length of the side of the Y-direction extending in the memory cell region of the substantially rectangular shape is set to be four copies of the length of the transistor is described.

The circuit configuration of the memory cell of the SRAM of the present embodiment is the same as that of the ninth embodiment described with reference to FIG.

[Structure of SRAM]

[Composition of memory]

53 to 55 are plan views showing the configuration of the memory cell of the SRAM of the embodiment. Fig. 53 shows the arrangement of the active region A, the gate electrode G, and the first plug P1. FIG. 54 shows the arrangement of the first plug P1, the first layer wiring M1, and the second plug P2. 55 is a view showing the arrangement of the second plug P2, the second layer wiring M2, the third plug P3, and the third layer wiring M3. Therefore, in FIGS. 53 and 54, the plan view is superimposed on the basis of the first plug P1, whereby the positional relationship of the patterns displayed in the respective drawings is clear. Further, in FIGS. 54 and 55, the plan view is superimposed on the basis of the second plug P2, whereby the positional relationship of the patterns displayed in the respective drawings is clear. Further, a rectangular area surrounded by a dotted line in the figure is a memory cell area indicating 1 (1 bit).

[Memory grid layout]

[A, G, P1]

As shown in FIG. 53, in the semiconductor substrate, a p-well, an n-well, and a p-well are arranged in the X direction. In Fig. 53, only one (1 bit) memory cell area is displayed, but the actual memory cell is repeatedly arranged in the X direction and the Y direction (refer to Fig. 12), so the wells (P-well, N- Well, P- Well) is formed extending in the Y direction. In addition, the exposed regions of the wells become active regions (active regions, A).

Further, in the semiconductor substrate, three active regions (AP1, AN, AP2) are arranged side by side in the X direction. Between these active regions (A) is a component separation region (STI). In other words, the active region (A) is partitioned by a component separation region (STI). Further, each of the above wells (P-well, N-well, P-well) is associated with the lower portion of the element isolation region STI.

Specifically, the active region AP1 is an exposed region of a p-well, and is a substantially rectangular shape having a long side in the Y direction in the memory cell region. In addition, in FIG. 53, only one (1 bit) memory cell area is displayed for convenience, but the actual memory cell is repeatedly arranged in the X direction and the Y direction (refer to FIG. 12), and thus the memory cell array is used. The active region AP1 extends linearly in the Y direction.

The active region AN is an exposed region of an n-well and has a substantially rectangular shape having a long side in the Y direction.

The active region AP2 is an exposed region of a p-well (P-well) on the right side in the figure of the n-type well, and has a substantially rectangular shape having a long side in the Y direction in the memory cell region. Further, since the memory cells are repeatedly arranged in the X direction and the Y direction (see FIG. 12), in the memory cell array, the active region AP1 extends linearly in the Y direction.

In the three active regions (AP1, AN, AP2), the gate electrode G is extended so as to be able to pass through each active region in the X direction via the gate insulating film (GO), and is configured in the ninth embodiment. "circuit composition" The 10 transistors described in the column.

Specifically, two common gate electrodes (G1, G3) are disposed so as to be able to traverse the active regions AP1, AN, and AP2. Therefore, in the active region AP2, TND2 and TND4 share the source ‧thole region and are arranged in series. On the active region AP1, TND1 and TND3 share the source ‧thole region and are arranged in series, and in the active region On the AN, TP1 and TP2 will share the source ‧ 汲 region and be connected in series. Further, TND1, TP1 and TND2 gate electrodes (G) are connected by one common gate electrode G3, and TND3, TP2 and TND4 gate electrodes are connected by the other common gate electrode G1 (G). ). The two common gate electrodes (G1, G3) are arranged to extend in parallel in the X direction.

Further, in the active region AP1, a gate electrode G4b is disposed in parallel with the two common gate electrodes (G1, G3). Thereby, TNA1 is disposed on the active region AP1, and the source ‧thole region of TNA1 and the source ‧thole region of TND1 are connected (commonized). Further, in the active region AP1, another gate electrode G2a is disposed in parallel with the two common gate electrodes (G1, G3). Thereby, TNA3 is disposed on the active region AP1, and the source ‧thole region of the TNA 3 and the source ‧thole region of the TND 3 are connected (commonized).

Further, on the active region AP2, a gate electrode G4a is disposed in parallel with the above-described common gate electrodes (G1, G3). Thereby, TNA2 is disposed on the active region AP2, and the source ‧thole region of the TNA 2 and the source ‧thole region of the TND 2 are connected (commonized). and Further, in the active region AP2, another gate electrode G2b is disposed in parallel with the two common gate electrodes (G1, G3). Thereby, TNA4 is disposed on the active region AP2, and the source ‧thole region of the TNA 4 and the source ‧thole region of the TND 4 are connected (commonized).

As described above, in the present embodiment, the driver transistor division (TND1, TND2, TND3, and TND4) is disposed on different active regions (AP1, AP2). Further, by extending the active regions (AP1, AP2) in the Y direction, the layout is simplified and the processing accuracy is improved.

Therefore, similarly to the first embodiment, the shape of the active region (A) is not provided with a corner portion (bending portion), and the gate width of the access transistor and the gate width of the driver transistor can be easily made 1:2.

Further, since the access transistors (TNA1, TNA2, TNA3, TNA4) are also disposed in the active regions (AP1, AP2), the number of active regions can be reduced. Thereby, a simple layout can be realized, and the memory cell area can be reduced.

Further, by extending the active region (A) in the Y direction, the gate electrode (G) can be extended in the X direction, and not only the processing accuracy of the active region (A) but also the processing accuracy of the gate electrode (G) can be achieved. Upgrade. In particular, as described in detail in the first embodiment, the use of the multiple exposure technique is facilitated, and the processing accuracy can be improved. Moreover, the simulation mode is made easy, and the inspection accuracy can be improved.

[P1, M1, P2]

As shown in FIG. 54, the source ‧ the drain region of the ten transistors (TND2, TNA2, TNA1, TND1, TP1, TP2, TND4, TNA4, TND3, TNA3) described with reference to FIG. 53 described above is arranged. There is a first plug P1. Further, the first plug P1 is also disposed on the six gate electrodes described with reference to FIG. 53 described above.

The first layer wiring M1 is disposed on the first plug P1, and electrical connection between the first plugs P1 can be achieved.

Specifically, the first plug P1F on the common source ‧th pole region of TNA2 and TND2, and the first plug P1E on the common source ‧thole region of TND1 and TNA1, and one of TP1 The first plug P1G on the source ‧thole region, and the first plug P1H on the common gate electrode (G1) of TP2, TND3, and TND4 are connected by the first layer wiring (first node wiring) M1A connection. This first layer wiring M1A can correspond to the accumulation node A of FIG. The above "one side" is a source ‧ a bungee region on the upper side in the figure.

TNA3, the common source of the TND3, the first plug P1B on the 汲polar region, and the common source of the TND4, TNA4, the first plug P1A on the 汲polar region, and the source of one of the TP2 汲The first plug P1C in the polar region and the first plug P1D on the common gate electrode (G3) of TP1, TND1, and TND2 are connected by the first layer wiring (second node wiring) M1B. This first layer wiring M1B can correspond to the accumulation node B of FIG. Here, "one side" means a source ‧ a bungee region on the lower side in the drawing.

And, on the common source ‧ bungee area of TND2 and TND4 The first layer wiring M1S is disposed on the first plug P1I. Further, the first layer wiring M1S is disposed on the first plug P1J on the common source ‧th pole region of the TND1 and the TND3. The first layer wiring M1S corresponds to the ground potential (VSS) of FIG. 48, and is connected to the ground potential line (LVSS) as will be described later.

Further, a first layer wiring (pad region) M1D is disposed on the first plug P1K on the common source ‧ drain region of TP1 and TP2. The first layer wiring M1D corresponds to the power supply potential (VDD) of FIG. 48, and is connected to the power supply potential line (LVDD) as will be described later.

Further, the first layer wiring M1BL is disposed on the first plug P1W on the other source ‧ drain region of the TNA 1 and the first plug P1M on the other source ‧ drain region of the TNA 2 .

Further, the first layer wiring M1BL is disposed on the first plug P1L on the other source ‧ drain region of the TNA 3 and the first plug P1X on the other source ‧ drain region of the TNA 4 .

Further, the first layer wiring M1W is disposed so that the first plug P1Y on the gate electrode (G4b) of the TNA1 and the first plug P1N on the gate electrode (G2a) of the TNA3 can be connected. Further, the first layer wiring M1W is disposed so that the first plug P1O on the gate electrode (G4a) of the TNA 2 and the first plug P1Z on the gate electrode (G2b) of the TNA 4 can be connected.

The connection state of the first layer wiring M1 between the plurality of first plugs P1 is variously modified as long as it conforms to the state of the wiring of the circuit diagram shown in FIG.

[P2, M2, P3, M3]

As shown in FIG. 55, the first layer wiring M1 described above with reference to FIG. 54 is the first layer other than the first layer wiring M1 (M1A, M1B) corresponding to the storage node (A or B). The second plug P2 is disposed on the layer wiring M1 (M1S, M1D, M1W, M1BL), and the second layer wiring M2 is disposed on the upper layer.

Specifically, the first layer wiring M1W connected to the gate electrodes (G4b, G2a) of TNA1 and TNA3 is connected to the second layer wiring M2W via the second plug P2. In the second layer wiring M2W, the third layer wiring M3 (WLA) is disposed via the third plug P3. This third layer wiring M3 (WLA) is a word line extending in the X direction. Further, the first layer wiring M1W connected to the gate electrodes (G4a, G2b) of the TNA 2 and the TNA 4 is connected to the second layer wiring M2W via the second plug P2. In the second layer wiring M2W, the third layer wiring M3 (WLB) is disposed via the third plug P3. This third layer wiring M3 (WLB) is a word line extending in the X direction.

Further, the first layer wiring M1S connected to the source ‧thole region (P1I) common to TND2 and TND4 is connected to the second layer wiring M2 (LVSS) via the second plug P2. This second layer wiring M2 (LVSS) is a ground potential line. The first layer wiring M1S connected to the source ‧thole region (P1J) common to TND3 and TND1 is connected to the second layer wiring M2 (LVSS) via the second plug P2. This second layer wiring M2 (LVSS) is a ground potential line. The two ground potential lines are They are respectively configured to extend in the Y direction.

Further, the first layer wiring M1BL connected to the other source ‧thole region (P1M) of the TNA 2 is connected to the second layer wiring M2 (BLB) via the second plug P2. The first layer wiring M1BL connected to the other source ‧thole region (P1X) of the TNA 4 is connected to the second layer wiring M2 (/BLB) via the second plug P2. The two second layer wirings M2 (bit lines (BLB, /BLB) are constituting bit line pairs, and are arranged to extend in the Y direction, respectively.

Further, the first layer wiring M1BL connected to the other source ‧thole region (P1W) of the TNA 1 is connected to the second layer wiring M2 (BLA) via the second plug P2. The first layer wiring M1BL connected to the other source ‧thole region (P1L) of the TNA 3 is connected to the second layer wiring M2 (/BLA) via the second plug P2. The two second layer wirings M2 (bit lines (BLA, /BLA)) constitute a bit line pair and are arranged to extend in the Y direction.

In the first layer wiring M1D connected to the source ‧ 汲 region (P1K) common to TP1 and TP2, the second layer wiring M2 (LVDD) is disposed via the second plug P2. This second layer wiring M2 (LVDD) is a power supply potential line. This power supply potential line extends in the Y direction.

The connection state of the second plug P2, the second layer wiring M2, the third plug P3, and the third layer wiring M3 is as long as it conforms to the state of the junction of the circuit diagram shown in FIG. 48, but various modifications can be made. As described above, the third layer wiring M2 is mainly extended in the Y direction, and the third layer wiring is used. M3 is mainly extended in the X direction for simple layout. In addition, in FIG. 53 to FIG. 55, only one (1 bit) memory cell area is displayed for convenience. However, as will be described later, the memory cell is repeatedly arranged in the X direction and the Y direction, and thus is memorized. In the grid array, the ground potential line (LVSS), the bit line (BLA, /BLA, BLB, /BLB), the power supply potential line (LVDD) are arranged to extend in the Y direction, and the word line (WLA, WLB) is Configured to extend in the X direction.

Further, in the present embodiment, since the ground potential line (LVSS) is disposed between the second layer wiring and the bit line, the shielding effect of the ground potential line (LVSS) is generated, and the interaction between the wirings can be reduced. Tone noise).

Further, each of the patterns described with reference to FIGS. 53 to 55 is arranged in point symmetry with respect to the center point of the memory cell region.

Further, for reference, 10 transistors (TND2, TNA2, TNA1, TND1, TP1, TP2, TND4, TNA4, TND3, TNA3) are arranged corresponding to the above-mentioned "pattern layout of the memory cell", and the connections are clearly indicated. A circuit diagram of the state is shown in Figure 56.

(Embodiment 11)

The structure of the SRAM is also proposed to form a circuit in which the conductivity types of the respective transistors shown in the first embodiment (FIG. 1) are reversed. In the present embodiment, an SRAM memory cell having such a circuit configuration will be described.

[circuit composition]

Fig. 57 is an equivalent circuit diagram showing a memory cell of the SRAM of the embodiment. As shown in the figure, the memory cell has eight transistors as in the first embodiment, but instead of the n-type transistors (TNA1, TNA2, TND1, TND2, TND3, TND4) shown in Fig. 1, the p-type is used. Transistors (TPA1, TPA2, TPD1, TPD2, TPD3, TPD4). Further, instead of the p-type transistor (TP1, TP2) shown in Fig. 1, an n-type transistor (TN1, TN2) is used.

As such, the conductivity type of the transistor used will be reversed.

Further, the transistors (TPA1, TPA2, TPD1, TPD2, TPD3, TPD4) of the p-type (the second conductivity type in this embodiment) are connected to the power supply potential (VDD, and in this embodiment, the second power supply potential, A potential different from the second power supply potential is higher than the potential of the second power supply).

The transistor (TN1, TN2) of the n-type (the first conductivity type in this embodiment) is connected to the ground potential (VSS, which is the first power supply potential in this embodiment).

Others are the same as the circuit configuration shown in FIG. 1, and therefore, the detailed connection relationship of each transistor is omitted here.

As described above, in the SRAM memory cell of the present embodiment, the driver transistor is also divided (TPD1, TPD2, TPD3, and TPD4).

[Structure of SRAM]

[Composition of memory]

58 to 60 are plan views showing the configuration of the memory cell of the SRAM of the embodiment. Figure 58 is a diagram showing the active region Ac, the gate electrode G and The configuration of the first plug P1. FIG. 59 shows the arrangement of the first plug P1, the first layer wiring M1, and the second plug P2. FIG. 60 shows the arrangement of the second plug P2, the second layer wiring M2, the third plug P3, and the third layer wiring M3. Therefore, in FIGS. 58 and 59, the plan view is superimposed on the basis of the first plug P1, whereby the positional relationship of the patterns displayed in the respective drawings is clear. Further, in FIGS. 59 and 60, the plan view is superimposed on the basis of the second plug P2, whereby the positional relationship of the patterns displayed in the respective drawings is clear. Further, a rectangular area surrounded by a dotted line in the figure is a memory cell area indicating 1 (1 bit).

[Memory grid layout]

As described above, the SRAM memory cell of the present embodiment is configured such that the conductivity type of each of the transistors shown in the first embodiment (FIG. 1) is reversed. Therefore, as shown in Fig. 58, the conductivity type of the well is opposite to that of the first embodiment (Fig. 2). Further, six active regions (AcN2, AcN1, AcP1, AcP2, AcN3, AcN4) are arranged in the X direction. Between these active regions (Ac) is a component separation region (STI). In other words, the active region (Ac) is distinguished by a component separation region (STI).

Among the six active regions (AcN2, AcN1, AcP1, AcP2, AcN3, AcN4), AcN2, AcN1, AcN3, AcN4 are exposed regions of the n-well, and AcP1 and AcP2 are p-type wells. The exposed area of the P-well is the same pattern arrangement as in the case of the first embodiment (FIG. 2). Of course, the impurity conductivity type of the source ‧thole region of the transistor introduced into the active region (Ac) is reversed. also That is, the conductivity type of the source ‧thole region in the active region of the exposed region of the n-well is the p-type, and the source in the active region of the exposed region of the p-well The conductivity type of the drain region is n-type.

Further, since the arrangement of the gate electrode G and the first plug P1 is the same as that of the first embodiment (FIG. 2), the description thereof will be omitted. Further, in the first plug P1 shown in FIG. 59, the arrangement of the first layer wiring M1 and the second plug P2 is also the same as that of the first embodiment (FIG. 3). Further, in the second plug P2 shown in FIG. 60, the arrangement of the second layer wiring M2, the third plug P3, and the third layer wiring M3 is also in place of the ground potential line (LVSS) in place of the first embodiment (FIG. 4). The second layer wiring M2 (LVDD) is disposed in the same manner as in the first embodiment (FIG. 4) except that the second layer wiring M2 (LVDD) is disposed instead of the second layer wiring M2 (LVDD), and thus the description thereof will be omitted.

As described above, in the present embodiment, as in the first embodiment, the driver transistor division (TPD1, TPD2, TPD3, and TPD4) is disposed in different active regions (AcN2, AcN1, AcN4, and AcN3). Further, by extending the active regions (AcN2 and AcN1, AcN4, and AcN3) in the Y direction, the layout becomes simple and the processing accuracy is improved. Further, since the access transistors (TPA1, TPA2) are also disposed in the active regions, the number of active regions can be reduced.

Further, the driving ability of the driver transistor (TPD1, TPD3) can be made larger than that of the access transistor (TPA1, TPA2). For example, by setting the width (length in the X direction) of the active regions (AcN2 and AcN1, AcN4 and AcN3) to 1:1, it is easy to widen the gate width of the access transistor and the gate width of the driver transistor. Set to 1:2.

Further, by dividing the active regions (TPD1 and TPD2, TPD3 and TPD4), each active region can be formed into a substantially rectangular shape. In other words, it is possible to adopt a shape that does not have the above-described corner portion (bending portion). Therefore, the processing accuracy is improved, and the characteristics of the respective transistors formed on the active region (Ac) can be improved. Moreover, manufacturing variations can be reduced, and the operational characteristics of the memory cell array of the SRAM can be improved. Moreover, the manufacturing yield can be improved.

Further, in one of the divided active regions (TPD1, TPD2, TPD3, and TPD4) (AcN1 or AcN3 in FIG. 58), an access transistor (TPA1, TPA2) is disposed in addition to the driver transistor (TPD1, TPD3). ), thus reducing the number of active areas. Thereby, a simple layout can be realized, and the memory cell area can be reduced.

Further, by extending the active region (Ac) in the Y direction, the gate electrode (G) can be extended in the X direction, and not only the processing accuracy of the active region (Ac) but also the processing accuracy of the gate electrode (G) can be achieved. Upgrade. In particular, as described in detail in the first embodiment, the multiple exposure technique is easy to use, and the processing accuracy can be improved. Moreover, the simulation mode is easy to make, and the inspection accuracy can be improved.

In the same manner as in the first embodiment, the second layer wiring M2 is mainly extended in the Y direction, and the third layer wiring M3 is mainly extended in the X direction (FIG. 60), whereby a simple layout can be realized.

Further, in the present embodiment, since the active region is divided and disposed (AcN2 and AcN1, AcN4 and AcN3), only the device isolation region (STI) portion between the active regions and the driver transistor (TPD1 and TPD2, TPD3, and TPD4) are provided. The formation area will become larger, but can be utilized This area is used to configure the power supply potential line (LVDD).

Further, each of the patterns described with reference to FIGS. 58 to 60 is arranged in point symmetry with respect to the center point of the memory cell region.

Further, for reference, eight transistors (TPD2, TPA1, TPD1, TN1, TN2, TPD3, TPA2, TPD4) are arranged corresponding to the above-mentioned "pattern layout of the memory cell", and a circuit diagram showing the connection state is shown. In Figure 61.

(Embodiment 12)

The semiconductor device (including a semiconductor component or an electronic device, etc.) using the SRAM described in detail in the above embodiments is not limited, and for example, can be incorporated in a SoC (System-on-a-chip) or a semiconductor wafer in which a system including a microcomputer is formed. . Fig. 62 is a view showing the layout configuration of the semiconductor wafer of the embodiment. In FIG. 62, the semiconductor wafer has a CPU (Central Processing Unit), an SRAM, and a logic circuit (LOGIC). The above SRAM can use the aforementioned single-chip SRAM (SP-SRAM) or dual-turn SRAM (DP-SRAM). Further, in addition to the SRAM, other memory elements such as an EEPROM (Electrically Erasable Programmable Read Only Memory) may be used, and an analog circuit or the like may be incorporated.

The CPU is also called a central processing unit, and is equivalent to a heart part of a computer or the like. This CPU is interpreted by reading a command from the memory device, and based on this, various calculations or controllers are performed. Inside this CPU, there is a CPU core (CPUcore) built in, and the inside of the CPU core is loaded with SRAM. The SRAM of the CPU core can use a high-performance SRAM, and the SRAM described in the first to eleventh embodiments can be applied. Of course, the SRAM described in the first to eleventh embodiments may be used in the above-described single SRAM (SP-SRAM) unit or dual-turn SRAM (DP-SRAM).

By assembling the SRAMs described in the first to eleventh embodiments to the microcomputer in this way, the characteristics of the microcomputer can be improved.

The invention of the present invention has been described in detail above with reference to the embodiments 1 to 11. However, the present invention is not limited to the embodiments described above, and various modifications may be made without departing from the spirit and scope of the invention.

For example, in the first embodiment, the active region (AcP1, AcP2, etc.) is roughly rectangular, but the intermediate mask (exposure mask) is a rectangular shape, and the pattern after exposure and etching is used. (The actual completed shape) is also not limited to a rectangular shape (rectangular shape). For example, as shown in Fig. 63, there is a case where the corner portion is rounded. Moreover, the width of the pattern varies depending on the place. Even in such a case, in order to achieve the above effects, the present invention is not intended to exclude the shape as shown in Fig. 63.

Further, the gate electrode (G) of each of the figures (for example, FIG. 2 and the like) is displayed in a rectangular shape (rectangular shape), but in actual shape, a rounded corner may be formed, and the present invention also includes such a shape.

Further, a part of the configuration of the above embodiment may be combined. For example, in the pattern layout (Fig. 2) of the first embodiment, the common first plug SP1 of the fifth embodiment (Fig. 30) can be applied. Further, in TP1 and TP2 of the first embodiment (Fig. 2), the sixth embodiment (Fig. 34) can be applied. The pattern of the n-well. It is also applicable to the shared first plug SP1. Further, in the pattern layout (Fig. 2) of the first embodiment, the p-type wells (P-well) may be arranged in one place as in the seventh embodiment (Fig. 38). Further, the SRAM in which the conductivity types of the respective transistors of the eleventh embodiment are reversed is also applicable to the pattern layout of the other embodiment. As described above, the present invention is not limited thereto, and various modifications may be made without departing from the spirit and scope of the invention.

[Industrial use possibility]

The present invention relates to a semiconductor device, and is particularly applicable to a semiconductor device having an SRAM.

P-well‧‧‧p-type well

N-well‧‧n-type trap

P1 (P1a~P1s)‧‧‧1st plug

AcP1~AcP4‧‧‧active area

TNA1, TNA2‧‧‧ access transistor (transistor)

TND1~TND4‧‧‧ drive transistor (transistor)

TP1, TP2‧‧‧ loaded into the transistor (transistor)

AcN1, AcN2‧‧‧ active area

G(G1~G4)‧‧‧ gate electrode

A, B‧‧‧ accumulation node

Claims (5)

A semiconductor device comprising: a memory cell having: (a1) a first conductivity type first MIS transistor connected between a first potential and a first node; (a2) at the first node and a second conductivity type first MIS transistor connected to the second potential different from the first potential; (a3) between the first node and the second potential, and the second conductivity type first MIS a second conductivity type second MIS transistor in which the transistors are connected in parallel; (a4) a first conductivity type second MIS transistor connected between the first potential and the second node; (a5) the second node and the second node a second conductivity type third MIS transistor connected between the second potentials; (a6) a second conductivity type in parallel with the second conductivity type third MIS transistor between the second node and the second potential a fourth MIS transistor; (a7) a second conductivity type fifth MIS transistor connected between the first node and the first bit line; and (a8) of the second node and the second bit line The second conductivity type sixth MIS transistor to be connected is characterized in that: (b1) the second conductivity type first MIS transistor and the second conductivity type 5 MIS are disposed The first active region of one of the crystal; (b2) the pattern of the first active region and the active region is separated, and the second active region of the second conductivity type second MIS transistor is disposed; (b3) the second conductivity type third MIS transistor and the aforementioned a third active region of one of the second conductivity type sixth MIS transistors; and (b4) a pattern of the third active region and the active region is separated, and a fourth active region of the second conductivity type fourth transistor is disposed The first active region, the first active region, the second active region, the fourth active region, and the third active region are arranged in a first direction, and are arranged in the first direction. In the first active region, the first gate wiring is disposed to extend in the first direction, and the second gate wiring is disposed to extend over the first active region and the second active region In the first direction, the third gate wiring is disposed to extend in the first direction, and the fourth gate wiring is disposed in the third active region and the fourth active region. Extending in the aforementioned first direction, being a cascading In the semiconductor device including the plurality of wiring layers, the first gate wiring is connected to the first wiring extending in the second direction intersecting the first direction, and the one end of the second conductivity type first MIS transistor is connected to the first wiring. 2 wiring connection, the second wiring system and the wiring layer in the same layer as the first wiring extend in the second direction and are connected to the second potential One end of the second conductivity type fifth MIS transistor is connected to the third wiring, and the third wiring system and the wiring layer in the same layer as the first wiring extend in the second direction and become the first bit line. The second wiring is disposed between the first wiring and the third wiring. A semiconductor wafer comprising: a central processing unit; and the semiconductor device according to claim 1 of the patent application. A semiconductor device comprising: a memory cell having: (a1) a first conductivity type first MIS transistor connected between a first potential and a first node; (a2) at the first node and a second conductivity type first MIS transistor connected to the second potential different from the first potential; (a3) between the first node and the second potential, and the second conductivity type first MIS a second conductivity type second MIS transistor in which the transistors are connected in parallel; (a4) a first conductivity type second MIS transistor connected between the first potential and the second node; (a5) the second node and the second node a second conductivity type third MIS transistor connected between the second potentials; (a6) a second conductivity type in parallel with the second conductivity type third MIS transistor between the second node and the second potential a 4th MIS transistor; (a7) connected between the first node and the first bit line a second conductivity type fifth MIS transistor; (a8) a second conductivity type sixth MIS transistor connected between the second node and the second bit line; (a9) the first node and the third bit a second conductivity type seventh MIS transistor connected between the element lines; (a10) a second conductivity type eighth MIS transistor connected between the second node and the fourth bit line, having: (b1) a first active region in which the second conductive type first MIS transistor and the second conductive type fifth MIS transistor are disposed; (b2) a pattern of the first active region and the active region is separated, and the second portion is disposed a second active region of the second conductive type second MIS transistor and the second conductive type seventh MIS transistor; (b3) a third active of the second conductive type third MIS transistor and the second conductive type sixth MIS transistor And (b4) the pattern of the third active region and the active region is separated, and the fourth active region of the second conductivity type fourth MIS transistor and the second conductivity type eighth MIS transistor are disposed, and the first And the fourth active region is based on the first active region, the second active region, the fourth active region, and the front The order of the third active region is arranged to be spaced apart from each other in the first direction, and the first gate region is arranged to extend in the first direction in the first active region, and the first active region and The second gate on the second active region The pole wiring is disposed to extend in the first direction, and the third gate wiring is disposed to extend in the first direction and on the third active region and the fourth active region in the third active region The fourth gate wiring is arranged to extend in the first direction, and in the second active region, the fifth gate wiring is arranged to extend in the first direction, and the fourth active region is in the fourth active region. The 6 gate wiring is arranged to extend in the first direction. The semiconductor device according to claim 3, wherein a plurality of wiring layers are stacked, and the first gate wiring is connected to a first wiring extending in a second direction intersecting the first direction, and the second One end of the conductive first MIS transistor is connected to the second wiring, and the wiring layer in the same layer as the first wiring extends in the second direction and is connected to the second potential, and the second One end of the conductive type fifth MIS transistor is connected to the third wiring, and the third wiring system and the wiring layer in the same layer as the first wiring extend in the second direction and become the first bit line. The second wiring is disposed between the wiring and the third wiring. A semiconductor wafer comprising: a central processing unit; and the semiconductor device according to claim 3 of the patent application.