TWI820090B - semiconductor memory device - Google Patents

Abstract

The embodiment provides a data latch circuit and a semiconductor memory device that can be miniaturized.

The data latch circuit of the embodiment includes a first n-channel transistor and a first p-channel transistor. The gate of the first n-channel transistor and the gate of the first p-channel transistor are common.

Description

semiconductor memory device [Related Application]

This application enjoys the priority of the application based on Japanese Patent Application No. 2018-172343 (filing date: September 14, 2018). This application incorporates the entire contents of the basic application by reference to this basic application.

The embodiment relates to a data latch circuit and a semiconductor memory device.

In recent years, in semiconductor memory devices equipped with NAND flash memory, sense amplifiers are used in order to read data stored in each memory cell. If the memory unit is to be highly integrated while maintaining data transfer speed, the number of data latch circuits connected to the sense amplifier will increase, resulting in an increase in the overall area.

The embodiment provides a data latch circuit and a semiconductor memory device that can be miniaturized.

The data latch circuit of the embodiment includes a first n-channel transistor and a first p-channel transistor. The gate and front of the aforementioned 1n-channel transistor The gate electrodes of the first p-channel transistors are common.

A semiconductor memory device according to an embodiment includes a sense amplifier, the data latch circuit, a plurality of electrode films separated from each other and laminated, a semiconductor member penetrating the plurality of electrode films, and a semiconductor member provided between the electrode film and A charge accumulation member between the semiconductor members, a source line connected to one end of the semiconductor member, and a bit line connected between the other end of the semiconductor member and the sense amplifier.

(First Embodiment) Next, the first embodiment will be described. FIG. 1 is a schematic cross-sectional view of the semiconductor memory device of this embodiment. FIG. 2 is a schematic plan view of the sense amplifier circuit of the semiconductor memory device of this embodiment. Figure 3 is a schematic plan view of the data latch circuit of this embodiment. Figure 4(a) is a schematic plan view of a data latch circuit, and (b) is its circuit diagram. FIG. 5 is a schematic cross-sectional view of a memory unit of the semiconductor memory device of this embodiment. In addition, each figure is a model, and components are omitted or emphasized as appropriate. In addition, the number and size ratio of each component may not be consistent between drawings. As shown in FIG. 1 , the semiconductor memory device 1 of this embodiment includes a control circuit substrate 10 and a memory array substrate 80 . In the control circuit substrate 10, a silicon substrate 11 and an interlayer insulating film 12 are laminated, and in the memory array substrate 80, a silicon substrate 81 and an interlayer insulating film 82 are laminated. The control circuit substrate 10 and the memory array substrate 80 are bonded in such a direction that the interlayer insulating film 12 and the interlayer insulating film 82 face each other. First, the control circuit board 10 will be described. As shown in FIG. 2 , in the control circuit board 10 , a control circuit is formed in the upper portion of the silicon substrate 11 and the interlayer insulating film 12 (see FIG. 1 ). The control circuit is provided with a sense amplifier region 13 , and a plurality of sense amplifier circuits 14 are provided in the sense amplifier region 13 . In each sense amplifier circuit 14, one sense amplifier 15 and a plurality of, for example, five data latch circuits 16 are arranged in a line. The sense amplifier 15 sequentially detects electronic signals transmitted from the memory array substrate 80 into binary value data. Each data latch circuit 16 temporarily holds the data detected by the sense amplifier 15 . In addition, in FIG. 2, FIG. 3, and FIG. 4(a), the interlayer insulating film 12 is omitted for simplicity of illustration. Hereinafter, regarding the control circuit board 10, for the sake of simplicity of explanation, the XYZ orthogonal coordinate system is used. The direction in which the plurality of sense amplifier circuits 14 are arranged is defined as the "X direction", the direction in which the sense amplifier 15 and the data latch circuit 16 in each sense amplifier circuit 14 are arranged is defined as the "Y direction", and the relative direction is defined as the "Y direction". The direction that is orthogonal to both the X direction and the Y direction is designated as the "Z direction". In the Z direction, the direction from the silicon substrate 11 to the interlayer insulating film 12 is also called "up", and the opposite direction is called "down". However, this expression is only for convenience and has nothing to do with the direction of gravity. As shown in FIGS. 2 and 3 , in the sense amplifier region 13 , a plurality of data latch circuits 16 are arranged in a matrix along the X direction and the Y direction. A plurality of data latch circuits 16 arranged along the Y direction belong to the same sense amplifier circuit 14 , and a plurality of data latch circuits 16 arranged along the X direction belong to different sense amplifier circuits 14 . The layouts of the plurality of data latch circuits 16 arranged along the Y direction are the same. On the other hand, the layouts of data latch circuits 16 adjacent in the X direction are mirror images of each other. As shown in FIG. 4(a) , on the silicon substrate 11, a plurality of n-wells 21 having an n-type conductivity type and a plurality of p-wells 22 having a p-type conductivity type are provided. The n wells 21 and the p wells 22 are alternately arranged along the X direction. Each n-well 21 and each p-well 22 extend in the Y direction and are arranged across all the data latch circuits 16 arranged along the Y direction. Each data latch circuit 16 is formed across one adjacent n-well 21 and one p-well 22 in the X direction. A certain data latch circuit 16 shares one n-well 21 with another data latch circuit 16 arranged on one side in the X direction, and shares p with another data latch circuit 16 arranged on the other side in the X direction. Well 22. Next, the structure of each data latch circuit 16 will be described. As shown in FIG. 3 and FIG. 4(a), in each data latch circuit 16, p-type layers 31 to 36 having p-type conductivity are provided on the n-well 21. The p-type layers 31 to 36 are isolated from each other and arranged in a row along the Y direction in this order. Between adjacent data latch circuits 16 in the Y direction, the p-type layer 36 and the p-type layer 31 are connected. In addition, between the p-type layer 31 and the p-type layer 32, between the p-type layer 32 and the p-type layer 33, between the p-type layer 34 and the p-type layer 35, and between the p-type layer 35 and the p-type layer 36 Between them, each is interposed with a part of the n well 21. On the other hand, an STI (Shallow Trench Isolation) 23 is provided between the p-type layer 33 and the p-type layer 34 . Thereby, among the two data latch circuits 16 adjacent in the Y direction, the p-type layers 34, 35, and 36 of one of the data latch circuits 16 and the p-type layers 31 and 31 of the other data latch circuit 16 are 32 and 33, together with the n-well 21 between the p-type layers, form an island-shaped semiconductor region (active region). However, at both ends of the row of the plurality of data latch circuits 16 constituting each sense amplifier circuit 14, the p-type layers 31 to 33 or the p-type layers 34 to 36 each form an island-shaped semiconductor region. In addition, in each data latch circuit 16, n-type layers 41 to 45 having n-type conductivity are provided on the p-well 22. The n-type layers 41 to 45 are isolated from each other and arranged in a row along the Y direction in this order. In the data latch circuit 16 adjacent in the Y direction, the n-type layer 45 and the n-type layer 41 are connected. In addition, between n-type layer 41 and n-type layer 42, between n-type layer 42 and n-type layer 43, between n-type layer 43 and n-type layer 44, between n-type layer 44 and n-type layer 45 , each interposing a part of the p well 22. Thus, on each p-well 22, a plurality of sets of n-type layers 41 to 45 arranged along the Y direction will together form a linear semiconductor with the p-well 22 between the n-type layers. area (active area). In the sense amplifier region 13, there are a plurality of island-shaped semiconductor regions each formed by the p-type layers 34 to 36, the p-type layers 31 to 33, and the n-well 21 between the p-type layers. The STI 23 is arranged between a plurality of linear semiconductor regions each formed by the n-type layers 41 to 45 and the p-well 22 between the n-type layers. Each data latch circuit 16 is provided with gates 51 to 56. The gates 51 to 56 extend generally in the X direction and cross the above-mentioned semiconductor region. A gate insulating film (not shown) is provided between the gates 51 to 56 and the semiconductor region. The following describes the positional relationship between the gates 51 to 56 and the p-type layers 31 to 36 and the n-type layers 41 to 45. As shown in FIG. 3 , the gate 51 is disposed across a region directly above the portion of the n-well 21 between the p-type layer 31 and the p-type layer 32 . The data latch circuits 16 adjacent in the X direction have a common gate 51 . That is to say, one gate 51 extending in the X direction and two data latch circuits 16 adjacent in the X direction and having mirror images of each other are arranged between the p-type layer 31 and the n-well 21 The area directly above the portion between p-type layers 32 . Specifically, among the plurality of data latch circuits 16, two data latch circuits 16 adjacent in the X direction and sharing n wells 21 are designated as "data latch circuit 16a" and "data latch circuit 16b" At this time, the p-type layer 31a and p-type layer 32a belonging to the data latch circuit 16a and the p-type layer 31b and p-type layer 32b belonging to the data latch circuit 16b share one gate 51. The gate 52 is disposed across a region directly above a portion of the p-well 22 between the n-type layer 41 and the n-type layer 42 . The data latch circuits 16 adjacent in the X direction have a common gate 52 . That is to say, one gate 52 extending in the X direction and two data latch circuits 16 adjacent in the X direction and having mirror images of each other are arranged between the n-type layer 41 and the n-type layer 41 in the p-well 22 The area directly above the portion between n-type layers 42 . Specifically, among the plurality of data latch circuits 16, two data latch circuits 16 that are adjacent in the X direction and share the p well 22 are designated as "data latch circuit 16a" and "data latch circuit 16c". At this time, the n-type layer 41a and n-type layer 42a belonging to the data latch circuit 16a and the n-type layer 41c and n-type layer 42c belonging to the data latch circuit 16c share one gate 52. The two data latch circuits 16 sharing the gate 51 and the two data latch circuits 16 sharing the gate 52 have different combinations. As described above, a certain data latch circuit 16a shares a gate 51 with the data latch circuit 16b on one side in the X direction, and shares a gate 52 with the data latch circuit 16c on the other side in the X direction. In the entire sense amplifier region 13 , gates 51 and gates 52 are arranged alternately and isolated from each other along the X direction. The gate 53 is used to cross the area directly above the part between the p-type layer 32 and the p-type layer 33 in the n-well 21 and to cross the area between the n-type layer 42 and the n-type layer 43 in the p-well 22. The area directly above the part is configured. Viewed from the Z direction, the shape of the gate 53 is, for example, a crank shape. The gate 54 is used to cross the area directly above the part between the p-type layer 32 and the p-type layer 35 in the n-well 21 and to cross the area between the n-type layer 43 and the n-type layer 44 in the p-well 22. The area directly above the part is configured. Viewed from the Z direction, the shape of the gate 54 is, for example, a crank shape. The gate 55 is disposed across a region directly above a portion of the n-well 21 between the p-type layer 35 and the p-type layer 36 . The data latch circuits 16 adjacent in the X direction have a common gate 55 . That is to say, taking the above example, the gate 55 is common between the data latch circuit 16a and the data latch circuit 16b. The gate 56 is disposed across a region directly above the portion between the n-type layer 44 and the n-type layer 45 in the p-well 22 . Data latch circuits 16 adjacent in the X direction have a common gate 56 . That is to say, taking the above example, the gate 56 is common between the data latch circuit 16a and the data latch circuit 16c. Just like the relationship between the gate 51 and the gate 52 described above, the two data latch circuits 16 sharing the gate 55 and the two data latch circuits 16 sharing the gate 56 have different combinations. As described above, a certain data latch circuit 16a shares a gate 55 with the data latch circuit 16b on one side in the X direction, and shares a gate 56 with the data latch circuit 16c on the other side in the X direction. In the entire sense amplifier region 13 , the gates 55 and 56 are alternately arranged along the X direction and are isolated from each other. In this way, four p-channel transistors p1 to p4 and four n-channel transistors n1 to n4 are formed in each data latch circuit 16 . In more detail, the p-channel transistor p3 is formed by the p-type layer 31 , the p-type layer 32 , the portion between the p-type layer 31 and the p-type layer 32 in the n-well 21 , and the gate 51 . The p-channel transistor p4 is formed by the p-type layer 32, the p-type layer 33, the portion between the p-type layer 32 and the p-type layer 33 in the n-well 21, and the gate electrode 53. The p-channel transistor p2 is formed by the p-type layer 34, the p-type layer 35, the portion of the n-well 21 between the p-type layer 34 and the p-type layer 35, and the gate electrode 54. The p-channel transistor p1 is formed by the p-type layer 35 , the p-type layer 36 , the portion between the p-type layer 35 and the p-type layer 36 in the well 21 , and the gate electrode 55 . In addition, the n-channel transistor n4 is formed by the n-type layer 41 , the n-type layer 42 , the portion of the p-well 22 between the n-type layer 41 and the n-type layer 42 , and the gate electrode 52 . An n-channel transistor n3 is formed by the n-type layer 42 , the n-type layer 43 , the portion of the p-well 22 between the n-type layer 42 and the n-type layer 43 , and the gate electrode 53 . An n-channel transistor n2 is formed by the n-type layer 43 , the n-type layer 44 , the portion of the p-well 22 between the n-type layer 43 and the n-type layer 44 , and the gate electrode 54 . The n-channel transistor n1 is formed by the n-type layer 44 , the n-type layer 45 , the portion of the p-well 22 between the n-type layer 44 and the n-type layer 45 , and the gate electrode 56 . In this way, the p-channel transistor p4 and the n-channel transistor n3 have one gate 53 in total. In addition, the p-channel transistor p2 and the n-channel transistor n2 have a gate 54 in total. Each data latch circuit 16 is provided with contacts 61 to 73. The lower end of the contact 61 is connected to the p-type layer 31 and the p-type layer 36 . The lower end of the contact 62 is connected to the n-type layer 41 and the n-type layer 45 . Contacts 61 and 62 are shared by two data latch circuits 16 adjacent in the Y direction. The lower end of contact 63 is connected to gate 51 . The contact 63, like the gate 51, is shared by two adjacent data latch circuits 16 in the X direction. Contact 64 is connected to the lower end of gate 52 . The contact 64, like the gate 52, is shared by two adjacent data latch circuits 16 in the X direction. The lower end of contact 65 is connected to n-type layer 42 . The lower end of contact 66 is connected to gate 53 . The lower end of contact 67 is connected to p-type layer 33 . The lower end of contact 68 is connected to n-type layer 43 . The lower end of contact 69 is connected to p-type layer 34 . The lower end of contact 70 is connected to gate 54 . The lower end of contact 71 is connected to n-type layer 44 . The lower end of contact 72 is connected to gate 55 . The contact 72, like the gate 55, is shared by two adjacent data latch circuits 16 in the X direction. The lower end of contact 73 is connected to gate 56 . The contact 73, like the gate 56, is shared by two adjacent data latch circuits 16 in the X direction. Each data latch circuit 16 is provided with wirings 76 and 77 . As shown in FIG. 4(a) , the wiring 76 is connected to the upper end of the contact 70 and to the upper end of the contact 65 and the upper end of the contact 67 arranged above the contact 70 in the figure. The wiring 77 is connected to the upper end of the contact 66 and is arranged at the upper end of the contact 71 and the upper end of the contact 69 on the lower side than the contact 66 in the figure. In addition, each of the above-mentioned contacts may also include a plurality of segments of contacts arranged in the Z direction, and the plurality of segments of contacts may also be connected through intermediate wirings. For example, the contacts 61 to 64, 72, and 73 may each include two or more stages of contacts arranged in the Z direction, and may be connected to the wirings 76 and 77 through an intermediate wiring provided on the same layer. As a result of each transistor being connected as described above, each data latch circuit 16 will form a circuit as shown in FIG. 4(b). That is, the source/drain of the p-channel transistor p1 and the source/drain of the p-channel transistor p2 share the same p-type layer 35 and are therefore connected to each other. The other side of the source/drain of the p-channel transistor p2 is connected to the source/drain of the n-channel transistor n1 through the contact 69, the wiring 77, and the contact 71, and the other side of the source/drain of the n-channel transistor n1. The source/drain of the crystal n2 is connected to the common gate 53 of the p-channel transistor p4 and the n-channel transistor n3 through the contact 69, the wiring 77, and the contact 66. On the other hand, the source/drain of the p-channel transistor p3 and the source/drain of the p-channel transistor p4 share the same p-type layer 32 and are therefore connected to each other. The other side of the source/drain of the p-channel transistor p4 is connected to one of the source/drain of the n-channel transistor n4 and the n-channel transistor through the contact 67, the wiring 76, and the contact 65. The source/drain of the crystal n3 is connected to the common gate 54 of the p-channel transistor p2 and the n-channel transistor n2 through the contact 67, the wiring 76, and the contact 70. In addition, on the other side of the source/drain of the p-channel transistor p1 (p-type layer 36), and on the other side of the source/drain (p-type layer 31) of the p-channel transistor p3, through the contact The first reference potential, which is the power supply potential VDD, is applied to point 61 . The other side of the source/drain of the n-channel transistor n2 and the other side of the source/drain of the n-channel transistor n3 are a common n-type layer 43, and the second layer is applied through the contact 68. The reference potential is the ground potential GND. In addition, the second reference potential is not limited to the ground potential, but is a potential lower than the first reference potential. The control signal Vc is input to the gate 56 of the n-channel transistor n1 and the gate 52 of the n-channel transistor n4 through the contact 73 and the contact 64 respectively. Select signals Vs1 and Vs2 are input to the gate 55 of the p-channel transistor p1 and the gate 51 of the p-channel transistor p3 through the contact 72 and the contact 63 respectively. The other side of the source/drain of the n-channel transistor n1 (n-type layer 45), and the other side of the source/drain (n-type layer 41) of the n-channel transistor n4 can pass through the contact 62 And connected to the sense amplifier 15, the data signal SA output from the sense amplifier 15 is applied. In the data latch circuit 16, n-channel transistors n1 and n4 function as transfer gates, n-channel transistors n2 and n3 function as drivers, and p-channel transistors p1 to p4 function as loads. Next, the memory array substrate 80 will be described. As shown in FIG. 5 , in the memory array substrate 80 , a source line 83 made of a conductive material is provided on the silicon substrate 81 . On the source line 83, a laminated body 85 is provided. In the laminated body 85, the insulating film 86 and the electrode film 87 are alternately laminated. In the laminated body 85, a core member 90 extending in the laminating direction of the insulating film 86 and the electrode film 87 is provided. The core member 90 is made of an insulating material such as silicon oxide, for example. The core member 90 has a columnar shape, for example, a substantially cylindrical shape. Silicon pillars 91 are provided around and on the lower surface of the core member 90 . The lower end of the silicon pillar 91 is connected to the source line 83 . Around the silicon pillar 91, a tunnel insulating film 92, a charge accumulation film 93, and a barrier insulating film 94 are laminated in this order. The tunnel insulating film 92 is usually insulating, but allows tunneling current to flow when a predetermined voltage within the driving voltage range of the semiconductor memory device 1 is applied, such as a single-layer silicon oxide film. Or an ONO film formed by sequentially stacking a silicon oxide layer, a silicon nitride layer and a silicon oxide layer. The charge accumulation film 93 is a film capable of accumulating charges, and is made of, for example, a material containing a trap site for electrons, such as silicon nitride. In addition, as the charge accumulation portion, a conductive floating gate may be provided instead of the insulating charge accumulation film 93 . In this case, the floating gates will be isolated according to each electrode film 87 . The barrier insulating film 94 is a film through which current does not substantially flow even if a voltage is applied within the driving voltage range of the semiconductor memory device 1 . The barrier insulating film 94 contains, for example, a material with a higher dielectric constant than silicon oxide. An interlayer insulating film 82 is provided on the sides and above the laminated body 85 . In the interlayer insulating film 82 and on the laminated body 85 , plugs 96 and bit lines 97 are provided. The upper end of the silicon pillar 91 is connected to the bit line 97 through the plug 96 . The bit line 97 is connected to the sense amplifier 15 of the control circuit board 10 (see FIG. 2 ). With this configuration, a memory cell transistor is formed at each intersection between the electrode film 87 and the silicon pillar 91 . In the memory cell transistor, the silicon pillar 91 becomes the channel, the electrode film 87 becomes the gate, and the barrier insulating film 94 becomes the gate insulating film. In addition, by accumulating charges in the charge accumulation film 93, the threshold value of the memory cell transistor is changed, thereby storing data. The threshold value of the memory cell transistor can take a value of 8 levels, for example. By this, 3 bits of data can be stored in one memory cell transistor. Next, the operation of the semiconductor memory device of this embodiment will be described. As shown in Figure 4(b), in the initial state, the selection signals Vs1 and Vs2, the control signals Vc1 and Vc2, and the data signal SA are all "L" (low level). Therefore, the p-channel transistors p1 and p3 are in the ON state, and the n-channel transistors n1 and n4 are in the OFF state. From this state, the selection signal Vs2 is set to "H" (high level) for the data latch circuit 16 that holds the data, and the p-channel transistor p3 is set to the OFF state. In addition, the control signal Vc2 is set to "H" and the n-channel transistor n4 is set to the ON state. Thereby, the potential of the connection point N2 between the p-channel transistor p4 and the n-channel transistor n3 becomes "L". As a result, the p-channel transistor p2 is in the ON state and the n-channel transistor n2 is in the OFF state. Therefore, the potential of the connection point N1 of the p-channel transistor p2 and the n-channel transistor n2 becomes "H". This causes the p-channel transistor p4 to be in the OFF state and the n-channel transistor n3 to be in the ON state. Therefore, the potential of the connection point N2 is stabilized at "L". Thereafter, the selection signal Vs2 is returned to "L", and the p-channel transistor p3 is set to the ON state. In addition, the control signal Vc2 is returned to "L", and the n-channel transistor n4 is set to the OFF state. As shown in FIG. 5 , when data is read from the memory cell transistor, current flows between the source line 83 and the bit line 97 , and this current is input to the sense amplifier circuit 14 shown in FIG. 2 . Test amplifier 15. The sense amplifier 15 detects a value based on the input current, and outputs the data signal SA to the data latch circuit 16 . At this time, the sense amplifier 15 temporarily sets the data signal SA to "H" and then outputs the original data signal SA. Next, the control signal Vc1 is set to "H", the n-channel transistor n1 is set to the ON state, and the value of the data signal SA is written into the data latch circuit 16 . When the data signal SA is "H", since the n-channel transistor n1 is in the ON state, the potential of the connection point N1 will maintain "H", so the potential of the connection point N2 will maintain "L" and be fixed. When the data signal SA is "L", because the n-channel transistor n1 is in the ON state, the potential of the connection point N1 becomes "L". Therefore, the p-channel transistor p4 is in the ON state, and the n-channel transistor n3 is in the OFF state. Therefore, the potential of the connection point N2 becomes "H". Thereby, the p-channel transistor p2 becomes an OFF state, and the n-channel transistor n2 becomes an ON state. As a result, the potential of the connection point N1 is fixed at "L". In summary, when the data signal SA is "H", the potential of the connection point N1 is fixed at "H", and the potential of the connection point N2 is fixed at "L". On the other hand, when the data signal SA is "L", the potential of the connection point N1 is fixed at "L" and the potential of the connection point N2 is fixed at "H". In this way, the data latch circuit 16 can memorize the potential of the data signal SA and maintain the value represented by the data signal SA. For example, by making the potential "H" of the data signal SA correspond to the value "0" and making the potential "L" correspond to the value "1", binary value data can be maintained. Next, the effects of this embodiment will be described. In this embodiment, one gate 53 is used to realize both the gate of the p-channel transistor p4 and the gate of the n-channel transistor n3. In addition, one gate 54 realizes both the gate of the p-channel transistor p2 and the gate of the n-channel transistor n2. This reduces the number of gates in the data latch circuit 16 and allows the data latch circuit 16 to be miniaturized. In addition, in each data latch circuit 16, p-channel transistors p1~p4 and n-channel transistors n1~n4 are arranged separately in the X direction, and the layout of the adjacent data latch circuits 16 in the X direction is adjusted. mirror each other. Thereby, the gates 51, 52, 55, and 56 can be shared among the data latch circuits 16 adjacent in the X direction. This also enables the data latch circuit 16 to be miniaturized. Furthermore, in this embodiment, the control circuit including the sense amplifier region 13 is provided on the control circuit substrate 10 , and the memory cell transistor is provided on the memory array substrate 80 . In this way, if the control circuit is formed on a dedicated substrate, it will not be subjected to the thermal history necessary for the formation of the memory cell transistor during the manufacturing process. Therefore, the p-channel transistors p1 to p4 and the n-channel transistors can be The bodies of type transistors n1~n4 are miniaturized. Thereby, the data latch circuit 16 can also be miniaturized. By miniaturizing the data latch circuit 16, the sense amplifier circuit 14 can be miniaturized, and thus the entire semiconductor memory device 1 can be miniaturized. On the other hand, if the area of the sense amplifier circuit 14 is kept constant, more data latch circuits 16 can be provided in each sense amplifier circuit 14 . As a result, even if the memory cell transistor becomes miniaturized, the channel area becomes smaller, the threshold value changes due to the increase or decrease of one electron accumulated in the charge storage film 93, and the writing and reading of data becomes necessary. Each sense amplifier circuit 14 can still retain a large amount of data for a long time, so the data transfer speed can be kept constant. (Second Embodiment) Next, the second embodiment will be described. FIG. 6 is a schematic plan view of the data latch circuit of this embodiment. Figure 7(a) is a schematic plan view of a data latch circuit, and (b) is its circuit diagram. As shown in FIGS. 6 and 7(a) , the semiconductor memory device 2 of this embodiment has a p-channel transistor p1 compared to the semiconductor memory device 1 of the first embodiment (see FIGS. 1 to 5 ). ~p4 and n-channel transistors n1~n4 have the same structure, but the shapes of the wiring are different. As a result, the area formed by the data latch circuit 18 of this embodiment is different from the area formed by the data latch circuit 16 of the first embodiment. It is explained in detail below. In the sense amplifier region 13 of this embodiment, the shapes, positional relationships and The connection relationship is the same as that of the first embodiment. However, in this embodiment, wirings 78 and 79 are provided instead of the wirings 76 and 77 in the first embodiment. The wiring 78 is connected to the upper end of the contact 70 , and is arranged at the upper end of the contact 65 and the upper end of the contact 67 on the lower side than the contact 70 in the figure. The wiring 79 is connected to the upper end of the contact 66, and is disposed above the contact 66 in the figure at the upper end of the contact 71 and the upper end of the contact 69. Accordingly, each data latch circuit 18 corresponds to a rectangular area including an island-shaped semiconductor area arranged in the n-well 21 and surrounded by the STI 23 and an island-shaped semiconductor area arranged in the p-well 22 . A portion of a strip-shaped semiconductor region. In the island-shaped semiconductor region, p-type layers 34, 35, 36, 31, 32, and 33 are arranged in this order. The p-type layer 36 and the p-type layer 31 are connected, but the other p-type layers are isolated from each other, and a part of the n-well 21 is interposed between adjacent p-type layers. In a part of the strip-shaped semiconductor region, n-type layers 43, 44, 45, 41, and 42 are arranged in this order. The n-type layer 45 and the n-type layer 41 are connected, but the other n-type layers are isolated from each other, and a part of the p-well 22 is interposed between adjacent n-type layers. As shown in Fig. 7(b), with this configuration, the same circuit as the first embodiment can be realized. The structure, operation, and effect of this embodiment other than those mentioned above are the same as those of the aforementioned first embodiment. (Third Embodiment) Next, a third embodiment will be described. FIG. 8 is a schematic plan view of the semiconductor region, gates and contacts in the data latch circuit of this embodiment. FIG. 9 is a schematic plan view of the semiconductor region, gate, contact and first wiring layer in the data latch circuit of this embodiment. FIG. 10 is a schematic plan view of the semiconductor region, gate, contacts, first wiring layer, second wiring layer and third wiring layer in the data latch circuit of this embodiment. Figure 11(a)~(c) is a schematic plan view of a data latch circuit in this embodiment. (a) shows the semiconductor region, gate and contact, (b) in (a) also shows the first wiring layer , (c) further illustrates the second wiring layer and the third wiring layer in (b). Figure 12 is a schematic plan view of four data latch circuits in this embodiment. Figure 13 (a) is a schematic plan view of a data latch circuit in this embodiment, and (b) is a circuit diagram thereof. In addition, FIGS. 8 to 10 are schematic diagrams of the layout relationship between a plurality of data latch circuits. To facilitate viewing of the drawings, part of the detailed structure of each data latch circuit is omitted. On the other hand, Figure 11(a)~(c) and Figure 13(a) are detailed schematic diagrams of the structure of a data latch circuit, and the relationship with other data latch circuits is not shown. Figure 12 illustrates their intermediate concepts, showing four data latch circuits in 2 rows and 2 columns. The semiconductor memory device 3 of this embodiment is different from the semiconductor memory device 1 of the first embodiment (see FIGS. 1 to 5 ) in the structure of the data latch circuit. The structure of the memory array substrate 80 is the same as that of the first embodiment. First, the well, n-type layer, p-type layer and gate provided on the silicon substrate 11 will be described. As shown in FIG. 8 , in the semiconductor memory device 3 of this embodiment, n-wells 21 and p-wells 22 are alternately arranged along the X direction on the silicon substrate 11 . Each n well 21 and each p well 22 extend in the Y direction. In addition, each data latch circuit 116 is set across half of the area of one n-well 21 and two p-wells 22 arranged on both sides. The length of the data latch circuit 116 in the X direction is equal to the total length of one n-well 21 and one p-well 22 . In the sense amplifier region 13 of the semiconductor memory device 3, a plurality of data latch circuits 1 are arranged in a matrix along the X direction and the Y direction. The layouts of the two data latch circuits 116 adjacent in the X direction are mirror images of each other, and the layouts of the two data latch circuits 116 adjacent in the Y direction are also mirror images of each other. Regarding FIGS. 11(a) to 13(a) and 13(a), for convenience of explanation, the p-well 22 included in each data latch circuit 116 is divided into a p-well 22a and a p-well 22b for description. In each data latch circuit 116, p-well 22a and p-well 22b are isolated from each other via n-well 21. On the other hand, the p-well 22a of a certain data latch circuit 116 is connected to the p-well 22b of the data latch circuit 116 adjacent to the data latch circuit 116 in the X direction. As shown in FIG. 11(a) , n-type layers 141 to 143 having n-type conductivity are provided on the p-well 22a. The n-type layers 141 to 143 are isolated from each other and arranged in a row along the Y direction in this order. In the data latch circuits 116 adjacent in the Y direction, the n-type layers 141 are connected to each other, and the n-type layers 143 are also connected to each other. In addition, a part of the p-well 22a is interposed between the n-type layer 141 and the n-type layer 142 and between the n-type layer 142 and the n-type layer 143. Thereby, on each p-well 22a, a plurality of sets of n-type layers 141~143 arranged along the Y direction will together form a linear semiconductor with the p-well 22a between the n-type layers. Area (Active Area) 111. The semiconductor region 111 includes the n-type layer 141 in each data latch circuit 116, the portion between the n-type layer 141 and the n-type layer 142 in the p-well 22a, the n-type layer 142, and the n-type layer in the p-well 22a. 142 and the n-type layer 143, and the n-type layer 143. One semiconductor region 111 extends in the Y direction across a plurality of data latch circuits 116 arranged along the Y direction. On the n-well 21, p-type layers 131 and 132 having p-type conductivity are provided. The p-type layer 131 and the p-type layer 132 are isolated in the Y direction. In the data latch circuits 116 adjacent in the Y direction, the p-type layers 132 are connected to each other. A part of the n-well 21 is interposed between the p-type layer 131 and the p-type layer 132 . Thereby, on each n-well 21, across the two adjacent data latch circuits 116 in the Y direction, the p-type layer 131, and the portion between the p-type layer 131 and the p-type layer 132 in the n-well 21, The common p-type layer 132, the portion between the p-type layer 132 and the p-type layer 131 in the n-well 21, and the p-type layer 131 are continuously arranged in this order along the Y direction to form an island-shaped semiconductor. Area (active area) 112. In addition, p-type layers 133 and 134 whose conductivity type is p-type are provided on the n-well 21 . The p-type layer 133 and the p-type layer 134 are isolated in the Y direction. In the data latch circuits 116 adjacent in the Y direction, the p-type layers 133 are connected to each other. A part of the n-well 21 is interposed between the p-type layer 133 and the p-type layer 134 . Thereby, on each n-well 21, across the two adjacent data latch circuits 116 in the Y direction, the p-type layer 134, and the portion between the p-type layer 134 and the p-type layer 133 in the n-well 21, The common p-type layer 133, the portion between the p-type layer 133 and the p-type layer 134 in the n-well 21, and the p-type layer 134 are continuously arranged in this order along the Y direction to form an island-shaped semiconductor. Area (active area) 113. On the p-well 22b, n-type layers 144 to 146 having n-type conductivity are provided. The n-type layers 144~146 are isolated from each other and arranged in a row along the Y direction in this order. In the data latch circuits 116 adjacent in the Y direction, the n-type layers 144 are connected to each other, and the n-type layers 146 are also connected to each other. In addition, a part of the p-well 22b is interposed between the n-type layer 144 and the n-type layer 145 and between the n-type layer 145 and the n-type layer 146. Therefore, on each p-well 22b, a plurality of sets of n-type layers 144~146 arranged along the Y direction will together form a linear semiconductor with the p-well 22b between the n-type layers. Area (active area) 114. The semiconductor region 114 includes the n-type layer 144 in each data latch circuit 116, the portion between the n-type layer 144 and the n-type layer 145 in the p-well 22b, the n-type layer 145, and the n-type layer in the p-well 22b. 145 and the n-type layer 146, and the n-type layer 146. One semiconductor region 114 extends across a plurality of data latch circuits 116 arranged along the Y direction. In the entire sense amplifier region 13 , the semiconductor region 111 extends continuously along the Y direction. The semiconductor regions 112 are intermittently arranged in a row along the Y direction. The semiconductor regions 113 are also intermittently arranged in a row along the Y direction. The semiconductor region 114 extends continuously along the Y direction. The semiconductor regions 111 to 114 are arranged in this order along the X direction and are isolated from each other. The Y-direction positions of n-type layer 141, p-type layer 133, and n-type layer 144 are approximately the same as each other. The Y-direction positions of n-type layer 142, p-type layer 131, p-type layer 134, and n-type layer 145 are mutually similar. The positions of the n-type layer 143, the p-type layer 132, and the n-type layer 146 in the Y direction are approximately the same. The STI 23 is arranged between the semiconductor regions 111 to 114. The two data latch circuits 116 sharing the semiconductor region 112 and the two data latch circuits 116 sharing the semiconductor region 113 have different combinations. That is, a certain data latch circuit 116 shares the semiconductor region 112 with the data latch circuit 116 on one side in the Y direction, and shares the semiconductor region 113 with the data latch circuit 116 on the other side in the Y direction. Each data latch circuit 116 is provided with gates 151 to 154. The gates 151 to 154 extend generally in the X direction and cross the above-mentioned semiconductor regions 111 to 114. Viewed from the Z direction, the shapes of the gates 151 to 154 are strips extending toward the X direction. A gate insulating film (not shown) is provided between the gates 151 to 154 and the semiconductor regions 111 to 114. The following describes the positional relationship between the gates 151 to 154 and the semiconductor regions 111 to 114. Gate 151 traverses semiconductor region 111 . Specifically, a part of the gate 151 is disposed in a region directly above the portion between the n-type layer 141 and the n-type layer 142 in the p-well 22a. The data latch circuits 116 adjacent in the X direction have a common gate 151 . That is to say, one gate 151 extending in the X direction crosses the semiconductor region 111 with each of the two data latch circuits 116 whose layouts are adjacent in the X direction and mirror each other. The gate 152 crosses the semiconductor region 111 and the semiconductor region 112 . Specifically, a part of the gate 152 is disposed directly above the portion between the n-type layer 142 and the n-type layer 143 in the p-well 22a, and the other part is disposed between the p-type layer 131 and the n-type layer 131 in the n-well 21. The area directly above the portion between p-type layers 132 . The gate 152 is disposed inside each data latch circuit 116 and does not span between adjacent data latch circuits 116 . The gate 153 crosses the semiconductor region 113 and the semiconductor region 114 . Specifically, a part of the gate 153 is disposed directly above the portion between the p-type layer 133 and the p-type layer 144 in the n-well 21, and the other part is disposed between the n-type layer 144 and the p-type layer 144 in the p-well 22b. The area directly above the portion between n-type layers 145 . The gate 153 is disposed inside each data latch circuit 116 and does not span between adjacent data latch circuits 116 . Gate 154 traverses semiconductor region 114 . Specifically, a part of the gate 154 is disposed in a region directly above the portion between the n-type layer 145 and the n-type layer 146 in the p-well 22b. Data latch circuits 116 adjacent in the X direction have a common gate 154 . That is to say, one gate 154 extending in the X direction crosses the semiconductor region 114 with each of the two data latch circuits 116 adjacent in the X direction and having mirror-image layouts. The two data latch circuits 116 sharing the gate 151 and the two data latch circuits 116 sharing the gate 154 have different combinations. A certain data latch circuit 116 shares a gate 151 with the data latch circuit 116 on one side in the X direction, and shares a gate 154 with the data latch circuit 116 on the other side in the X direction. In the entire sense amplifier region 13 , gates 151 and 153 are arranged in a row along the X direction, and gates 152 and gates 154 are arranged in a row along the X direction. As shown in Figures 13(a) and (b), with the above configuration, two p-channel transistors p2 and p4 and four n-channel transistors n1~n4 are formed in each data latch circuit 116. . In more detail, the n-channel transistor n1 is formed by the n-type layer 141, the n-type layer 142, the portion between the n-type layer 141 and the n-type layer 142 in the p-well 22a, and the gate electrode 151. An n-channel transistor n2 is formed by the n-type layer 142, the n-type layer 143, the portion between the n-type layer 142 and the n-type layer 143 in the p-well 22a, and the gate electrode 152. An n-channel transistor n3 is formed by the n-type layer 144, the n-type layer 145, the portion between the n-type layer 144 and the n-type layer 145 in the p-well 22b, and the gate electrode 153. An n-channel transistor n4 is formed by the n-type layer 145, the n-type layer 146, the portion between the n-type layer 145 and the n-type layer 146 in the p-well 22b, and the gate electrode 154. In addition, a p-channel transistor p2 is formed by the p-type layer 131, the p-type layer 132, the portion between the p-type layer 131 and the p-type layer 132 in the n-well 21, and the gate 152. The p-channel transistor p4 is formed by the p-type layer 133 , the p-type layer 134 , the portion between the p-type layer 133 and the p-type layer 134 in the n-well 21 , and the gate 153 . In this way, the n-channel transistor n2 and the p-channel transistor p2 have one gate 152 in total. The n-channel transistor n3 and the p-channel transistor p4 have one gate 153 in total. In addition, the two n-channel transistors n1 provided in the two adjacent data latch circuits 116 in the X direction have one gate 151 in total. The two n-channel transistors n4 provided in the two adjacent data latch circuits 116 in the X direction have a total of one gate 154. Next, the contacts are explained. As shown in FIG. 11(a), FIG. 12, and FIG. 13(a), each data latch circuit 116 is provided with contacts 161~172. Viewed from the Z direction, the shape of the contact point 165 and the contact point 168 is an oblong shape in which the length in the Y direction is longer than the length in the X direction. The shape of the other contacts is slightly round. However, in FIG. 13(a) , contacts belonging to only one data latch circuit 116 are represented by circles or ellipses, and contacts shared by adjacent data latch circuits 116 are represented by semicircles. In addition, like the first embodiment, each contact may include a plurality of segments of contacts arranged in the Z direction, and the plurality of segments of contacts may be connected through an intermediate wiring. The intermediate wiring may be provided on the same layer as the first wiring layer 121 or the second wiring layer 122 described later. The lower end of contact 161 is connected to gate 151 . The contact 161 is shared by two data latch circuits 116 adjacent in the X direction. The lower end of contact 162 is connected to n-type layer 141 . The contact 162 is shared by two data latch circuits 116 adjacent in the Y direction. The lower end of contact 163 is connected to n-type layer 142 . The lower end of contact 164 is connected to n-type layer 143 . The contact 164 is shared by two data latch circuits 116 adjacent in the Y direction. In this way, the contacts 162, 163, and 164 are connected to the same semiconductor region 111 and are arranged along the Y direction. The middle part of the contact 165 in the Z direction is connected to the gate 153, and the lower end is connected to the p-type layer 131. Viewed from the Z direction, the shape of the contact 165 is an oblong shape in which the length in the Y direction is longer than the length in the X direction. The lower end of contact 166 is connected to p-type layer 132 . The contact 166 is shared by two data latch circuits 116 adjacent in the Y direction. In this way, the contacts 165 and 166 are connected to the same semiconductor region 112 and are arranged along the Y direction. The lower end of contact 167 is connected to p-type layer 133 . The contact 167 is shared by two data latch circuits 116 adjacent in the Y direction. The middle part of the contact 168 in the Z direction is connected to the gate 152 , and the lower end is connected to the p-type layer 134 . Viewed from the Z direction, the shape of the contact 168 is an oblong shape in which the length in the Y direction is longer than the length in the X direction. In this way, the contacts 167 and 168 are connected to the same semiconductor region 113 and are arranged along the Y direction. The lower end of contact 169 is connected to n-type layer 144 . The contact 169 is shared by two data latch circuits 116 adjacent in the Y direction. The lower end of contact 170 is connected to n-type layer 145 . The lower end of contact 171 is connected to n-type layer 146 . The contact 171 is shared by two data latch circuits 116 adjacent in the Y direction. In this way, the contacts 169, 170, and 171 are connected to the same semiconductor region 114 and are arranged along the Y direction. The lower end of contact 172 is connected to gate 154 . The contact 172 is shared by two data latch circuits 116 adjacent in the X direction. Above the silicon substrate 11 and the gate, a first wiring layer 121, a second wiring layer 122, and a third wiring layer 123 are sequentially stacked. That is, the first wiring layer 121 is located above the gates 151 to 154 , the second wiring layer 122 is located above the first wiring layer 121 , and the third wiring layer 123 is located above the second wiring layer 122 . Next, the first wiring layer 121 will be described. As shown in FIG. 9, FIG. 11(b), FIG. 12, and FIG. 13(a), the first wiring layer 121 is provided with wiring 121a, wiring 121b, and wiring 121c. The wiring 121a is provided with a stem portion 121d and branch portions 121e and 121f. The trunk portion 121d of the wiring 121a extends in the Y direction between the semiconductor region 112 and the semiconductor region 113 at the center portion of each data latch circuit 116 in the X direction. The stem 121d is provided across a plurality of data latch circuits 116 arranged along the Y direction. The stem 121d passes through the area directly above the gate 152 and the area directly above the gate 153. The branch portion 121e of the wiring 121a extends from the trunk portion 121d toward one side in the X direction and is connected to the upper end of the contact 162. The branch portion 121e is shared by two data latch circuits 116 adjacent in the Y direction. The branch portion 121f of the wiring 121a extends from the trunk portion 121d toward the other side in the X direction and is connected to the upper end of the contact 171. The branch portion 121f is shared by two data latch circuits 116 adjacent in the Y direction. In this way, the wiring 121a is connected to the n-type layer 141 through the contact 162, and is connected to the n-type layer 146 through the contact 171. The wiring 121b extends in the X direction and is connected to the upper end of the contact 163 and the upper end of the contact 165. Thereby, the n-type layer 142, the p-type layer 131 and the gate 153 are connected to each other through the contact 163, the wiring 121b and the contact 165. The wiring 121c also extends in the X direction and is connected to the upper end of the contact 168 and the upper end of the contact 170. Thereby, the n-type layer 145, the p-type layer 134, and the gate 152 are connected to each other through the contact 170, the wiring 121c, and the contact 168. Next, the second wiring layer 122 will be described. As shown in FIGS. 10, 12 and 13(a), the second wiring layer 122 is provided with wiring 122a and wiring 122b. The shapes of the wirings 122a and 122b are linear extending in the X direction, and are provided across the plurality of data latch circuits 116 arranged along the X direction. The wiring 122 a is arranged to pass through the area directly above the gate 151 and the area directly above the gate 153 and is connected to the upper end of the contact 161 . In addition, the wiring 122a also passes through the area directly above the contact 165, but is not connected to the contact 165. Thereby, the wiring 122a is connected to the gate 151 through the contact 161. The wiring 122b is arranged to pass through the area directly above the gate 152 and the area directly above the gate 154, and is connected to the upper end of the contact 172. In addition, the wiring 122b also passes through the area directly above the contact 168, but is not connected to the contact 168. Thereby, the wiring 122b is connected to the gate 154 through the contact 172 . Next, the third wiring layer 123 will be described. As shown in FIGS. 10, 11(c), 12, and 13(a), the third wiring layer 123 is provided with wiring 123a and wiring 123b. The shapes of the wirings 123a and 123b are linear extending in the Y direction, and are provided across the plurality of data latch circuits 116 arranged along the Y direction. The wiring 123a and the wiring 123b are alternately arranged along the X direction. The wiring 123a is arranged along the boundary line of the data latch circuits 116 adjacent in the X direction. For example, it belongs to two adjacent data latch circuits 116 in the X direction and is arranged in the adjacent semiconductor region 111 across the STI 23. and the area directly above the semiconductor region 114 . The wiring 123a is connected to the upper end of the contact 164 and the upper end of the contact 169. Thereby, the wiring 123a is connected to the n-type layer 143 through the contact 164, and is connected to the n-type layer 144 through the contact 169. The wiring 123b is disposed at the center of the data latch circuit 116 in the X direction, for example, in the region directly above the semiconductor region 112 and the region directly above the semiconductor region 113 of each data latch circuit 116. The wiring 123b is connected to the upper end of the contact 166 and the upper end of the contact 167. Thereby, the wiring 123b is connected to the p-type layer 132 through the contact 166, and is connected to the p-type layer 133 through the contact 167. As a result of each transistor being connected as described above, each data latch circuit 116 will form a circuit as shown in FIG. 13(b). In other words, the source/drain of the n-channel transistor n1 and the source/drain of the n-channel transistor n2 share the same n-type layer 142 and are thus connected to each other. The n-type layer 142 is connected to the source/drain side of the p-channel transistor p2 (p-type layer 131), as well as to the p-channel transistor p4 and the n-channel through the contact 163, the wiring 121b and the contact 165. A common gate 153 of type transistor n3. Similarly, the source/drain of the n-channel transistor n3 and the source/drain of the n-channel transistor n4 share the same n-type layer 145 and are thus connected to each other. The n-type layer 145 is connected to the source/drain side of the p-channel transistor p4 (p-type layer 134), as well as to the p-channel transistor p2 and the n-channel through the contact 170, the wiring 121c, and the contact 168. A common gate 152 of type transistor n2. The other side of the source/drain of the n-channel transistor n1 (n-type layer 141) and the other side of the source/drain (n-type layer 146) of the n-channel transistor n4 pass through the contact 162, respectively. And the contact 171 is connected to the wiring 121a. The wiring 121 a may be connected to the sense amplifier 15 and be supplied with the data signal SA output from the sense amplifier 15 . The other side of the source/drain of the n-channel transistor n2 (n-type layer 143) is connected to the wiring 123a of the third wiring layer 123 through the contact 164. The other side of the source/drain of the n-channel transistor n3 (n-type layer 144) is connected to the wiring 123a of the third wiring layer 123 through the contact 169. In the wiring 123a, the other side (p-type layer 132) of the source/drain of the p-channel transistor p2 to which the ground potential GND as the second reference potential is applied is connected to the third wiring layer 123 through the contact 166. Wiring 123b. The other side of the source/drain of the p-channel transistor n4 (p-type layer 133) is connected to the wiring 123b of the third wiring layer 123 through the contact 167. The power supply potential VDD as the first reference potential is applied to the wiring 123b. The gate 151 of the n-channel transistor n1 is connected to the wiring 122a of the second wiring layer 122 through the contact 161. The control signal Vc1 is input to the wiring 122a. The gate 154 of the n-channel transistor n4 is connected to the wiring 122b of the second wiring layer 122 through the contact 172. The control signal Vc2 is input to the wiring 122b. Next, the operation of the semiconductor memory device of this embodiment will be described. As shown in Figure 13(b), in the initial state, the control signals Vc1 and Vc2 and the data signal SA are both "L". Therefore, the n-channel transistors n1 and n4 are in the OFF state. From this state, the control signal Vc2 is set to "H" for the data latch circuit 116 that holds the data, and the n-channel transistor n4 is set to the ON state. Thereby, the potential of the connection point N2 between the p-channel transistor p4 and the n-channel transistor n3 becomes "L". As a result, the p-channel transistor p2 is in the ON state and the n-channel transistor n2 is in the OFF state. Therefore, the potential of the connection point N1 of the p-channel transistor p2 and the n-channel transistor n2 becomes "H". This causes the p-channel transistor p4 to be in the OFF state and the n-channel transistor n3 to be in the ON state. Therefore, the potential of the connection point N2 is stabilized at "L". Thereafter, the control signal Vc2 is returned to "L", and the n-channel transistor n4 is set to the OFF state. Then, the sense amplifier 15 temporarily sets the data signal SA to "H" and then outputs the original data signal SA. Next, the control signal Vc1 is set to "H", the n-channel transistor n1 is set to the ON state, and the value of the data signal SA is written into the data latch circuit 16 . When the data signal SA is "H", since the n-channel transistor n1 is in the ON state, the potential of the connection point N1 will maintain "H", so the potential of the connection point N2 will maintain "L" and be fixed. When the data signal SA is "L", because the n-channel transistor n1 is in the ON state, the potential of the connection point N1 becomes "L". Therefore, the p-channel transistor p4 is in the ON state, and the n-channel transistor n3 is in the OFF state. Therefore, the potential of the connection point N2 becomes "H". This causes the p-channel transistor p2 to be in the OFF state and the n-channel transistor n2 to be in the ON state. Therefore, the potential of the connection point N1 is fixed at "L". In this way, when the data signal SA is "H", the potential of the connection point N1 is fixed at "H", and the potential of the connection point N2 is fixed at "L". , the potential of the connection point N1 is fixed at "L", and the potential of the connection point N2 is fixed at "H". As a result, the data latch circuit 116 can retain the value represented by the data signal SA. Next, the effects of this embodiment will be described. In this embodiment, the data latch circuit 116 can be composed of six transistors. Thereby, compared with the first embodiment, the data latch circuit 116 can be miniaturized. In addition, in this embodiment, one gate 152 is used to realize both the gate of the n-channel transistor n2 and the gate of the p-channel transistor p2. In addition, one gate 153 realizes both the gate of the n-channel transistor n3 and the gate of the p-channel transistor p4. Thereby, the number of gates in the data latch circuit 116 is reduced, and the data latch circuit 116 can be miniaturized. In addition, in this embodiment, the shape of the gate 151 and the gate 153 is a strip extending in the X direction, and are arranged along the X direction. In addition, the gate 152 and the gate 154 are also in the shape of strips extending in the X direction and are arranged along the X direction. Thereby, the number of gate electrodes in each data latch circuit 116 becomes two, and the size of the data latch circuit 116 in the Y direction can be reduced. Furthermore, in this embodiment, the layouts of adjacent data latch circuits 116 in the X direction are mirrored to each other. Thereby, the gate 151 can be made common between the data latch circuits 116 adjacent in the X direction, and the gate 154 can be made common. In addition, the layouts of adjacent data latch circuits 116 in the Y direction are mirrored to each other. Thereby, the n-type layer 141, the n-type layer 143, the p-type layer 132, the p-type layer 133, the n-type layer 144, and the n-type layer 146 can be shared between adjacent data latch circuits 116 in the Y direction. . This also enables the data latch circuit 16 to be miniaturized. The structure, operation, and effect of this embodiment other than those mentioned above are the same as those of the aforementioned first embodiment. (Fourth Embodiment) Next, the fourth embodiment will be described. FIG. 14 is a schematic plan view of the semiconductor region, gate, contact and first wiring layer in the four data latch circuits of this embodiment. FIG. 15 is a schematic plan view of the semiconductor region, gate, contact, first wiring layer, and second wiring layer in the four data latch circuits of this embodiment. FIG. 16 is a schematic plan view of the semiconductor region, gate, contact, first wiring layer, second wiring layer and third wiring layer in the four data latch circuits of this embodiment. Figure 17 (a) is a schematic plan view of a data latch circuit in this embodiment, and (b) is a circuit diagram thereof. As shown in FIGS. 14 to 16 and 17(a), the semiconductor memory device 4 of this embodiment is, compared with the semiconductor memory device 3 of the third embodiment mentioned above (see FIGS. 8 to 13(b)), The structure of the data latch circuit 118 is different. In the data latch circuit 118, the shapes, positional relationships and connection relationships of the n-well 21, the p-well 22, the p-type layers 131~134, the n-type layers 141~146, the gates 151~54, and the contacts 161~172 are as follows Data latch circuit 116 of the third embodiment. On the other hand, the data latch circuit 118 has a different configuration from the data latch circuit 116 in the first wiring layer 121, the second wiring layer 122, and the third wiring layer 123. In addition, the data latch circuit 118 is provided with through holes 181 and 182. First, the first wiring layer 121 will be described. As shown in FIG. 14 and FIG. 17(a) , the first wiring layer 121 of the data latch circuit 118 is provided with wiring 121b, wiring 121c, wiring 121g, wiring 121h, and wiring 121i. The positions and shapes of the wiring 121b and the wiring 121c are the same as those in the third embodiment. The wiring 121h is connected to the upper end of the contact 162 and the lower end of the through hole 181. The wiring 121i is connected to the upper end of the contact 171 and the lower end of the through hole 182. The wiring 121g is provided with a trunk portion 121j, and branch portions 121m and 121n. The trunk portion 121j of the wiring 121g extends in the Y direction between the semiconductor region 112 and the semiconductor region 113 in the X-direction central portion of each data latch circuit 118. The stem 121j is provided across a plurality of data latch circuits 118 arranged along the Y direction. The stem 121 j is arranged to pass through the area directly above the gate 152 and the area directly above the gate 153 . The branch portion 121m of the wiring 121g extends toward one side in the X direction from the trunk portion 121j and is connected to the upper end of the contact 167. The branch portion 121m is shared by two data latch circuits 118 adjacent in the Y direction. The branch portion 121n of the wiring 121g extends from the trunk portion 121j toward the other side in the X direction and is connected to the upper end of the contact 166. The branch portion 121m is shared by two data latch circuits 118 adjacent in the Y direction. In this way, the wiring 121g is connected to the p-type layer 133 through the contact 167, and is connected to the p-type layer 132 through the contact 166. Next, the second wiring layer 122 will be described. As shown in FIG. 15 , the second wiring layer 122 of the data latch circuit 118 is provided with wiring 122c. The wiring 122c is provided with a stem portion 122d and branch portions 122e and 122f. The trunk portion 122d of the wiring 122c extends in the X direction. The stem 122d is provided across a plurality of data latch circuits 118 arranged along the X direction. The stem 122d is arranged so as to pass through the area directly above the wiring 121b and the area directly above the wiring 121c of the first wiring layer 121. The branch portion 122e of the wiring 122c extends from the trunk portion 122d toward one side in the Y direction and is connected to the upper end of the contact 161. The branch portion 122f of the wiring 122c extends from the trunk portion 122d toward the other side in the Y direction and is connected to the upper end of the contact 172. In this way, the wiring 122c is connected to the gate 151 through the contact 161, and is connected to the gate 154 through the contact 172. Next, the third wiring layer 123 will be described. As shown in FIG. 16 , the third wiring layer 123 of the data latch circuit 118 is provided with wirings 123a, 123c, and 123d. The shapes of the wirings 123a, 123c, and 123d are linear extending in the Y direction, and are provided across the plurality of data latch circuits 118 arranged along the Y direction. The position and shape of the wiring 123a are the same as those in the third embodiment. That is, the wiring 123a is arranged along the boundary line of the adjacent data latch circuits 118 in the X direction. For example, two adjacent data latch circuits 118 belonging to the X direction are arranged adjacent to each other across the STI 23. The area directly above the semiconductor region 111 and the semiconductor region 114 . The wiring 123a is connected to the upper end of the contact 164 and the upper end of the contact 169. Thereby, the wiring 123a is connected to the n-type layer 143 through the contact 164, and is connected to the n-type layer 144 through the contact 169. The wiring 123 c is arranged near the area directly above the semiconductor region 112 and is connected to the upper end of the through hole 181 . Thereby, the wiring 123c is connected to the n-type layer 141 through the through hole 181, the wiring 121h and the contact 162. The wiring 123d is disposed near the area directly above the portion between the semiconductor region 113 and the semiconductor region 114, and is connected to the upper end of the through hole 182. Thereby, the wiring 123d is connected to the n-type layer 146 through the via hole 182, the wiring 121i, and the contact 172. As a result of each transistor being connected as described above, each data latch circuit 118 will form a circuit as shown in FIG. 17(b). The connection between the transistors in the data latch circuit 118 is the same as that in the data latch circuit 116 of the third embodiment. In addition, the connection between the n-channel transistors n2 and n3 and the ground potential GND is also like the data latch circuit 116. On the other hand, compared with the data latch circuit 116, the data latch circuit 118 has different input power supply potential VDD, control signal Vc, data signals SA and bSA to each transistor. In addition, the data latch circuit 118 is different from the data latch circuit 116 in that the control signal Vc is common and that the data signals SA and bSA are complementary signals. Among the data signals SA and bSA, if one is "H", the other is "L". The other side of the source/drain of the p-channel transistor p2 (p-type layer 132) is connected to the wiring 121g through the contact 166 and the branch portion 121n. The other side of the source/drain of the p-channel transistor p4 (p-type layer 133) is connected to the wiring 121g through the contact 169 and the branch portion 121m. The power supply potential VDD as the first reference potential is applied to the wiring 121g. The gate 151 of the n-channel transistor n1 is connected to the wiring 122c through the contact 161. The gate 154 of the n-channel transistor n4 is connected to the wiring 122c through the contact 172. A common control signal Vc is applied to the wiring 122c. The other side of the source/drain of the n-channel transistor n1 (n-type layer 141) is connected to the wiring 123b through the contact 162, the wiring 121h, and the through hole 181. The data signal SA is applied to the wiring 123b. The other side of the source/drain of the n-channel transistor n1 (n-type layer 146) is connected to the wiring 123c through the contact 171, the wiring 121i, and the through hole 182. The data signal bSA is applied to the wiring 123c. Next, the operation of the semiconductor memory device of this embodiment will be described. As shown in Figure 17(b), in the initial state, the control signal Vc and the data signal SA are both "L". Therefore, the n-channel transistors n1 and n4 are in the OFF state. From this state, the control signal Vc is set to "H" for the data latch circuit 118 that holds the data, and the n-channel transistors n1 and n4 are set to the ON state. Then, the sense amplifier 15 outputs the data signals SA and bSA to the data latch circuit 118 . The data retention method of n-channel transistors n2 and n3 and p-channel transistors p2 and p4 is the same as in the third embodiment. According to this embodiment, the same effect as that of the third embodiment can be obtained. According to the above-described embodiment, it is possible to realize a miniaturized data latch circuit and semiconductor memory device. Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments or their modifications are included within the scope or gist of the invention, and are included within the scope of the invention described in the patent application and its equivalents.

1, 2, 3, 4: Semiconductor memory device 10:Control circuit substrate 11:Silicon substrate 12: Interlayer insulation film 13: Sense amplifier area 14: Sense amplifier circuit 15: Sense amplifier 16, 16a, 16b, 16c: Data latch circuit 18: Data latch circuit 21:n well 22, 22a, 22b:p well 23: STI 31~36, 31a, 31b, 32a, 32b: p-type layer 41~45, 41a, 41c, 42a, 42c: n-type layer 51~56: Gate 61~73:Contact 76, 77, 78, 79: Wiring 80:Memory array substrate 81:Silicon substrate 82: Interlayer insulation film 83: Source line 85: Laminated body 86:Insulating film 87:Electrode film 90: Core component 91:Silicon pillar 92: Tunnel insulation film 93: Charge accumulation film 94: Barrier insulation film 96:Plug 97:Bit line 111~114: Semiconductor area (active area) 116: Data latch circuit 118: Data latch circuit 121: 1st wiring layer 121a, 121b, 121c: Wiring 121d:cadre 121e, 121f: branches 121g, 121h, 121i: Wiring 121j:cadres 121m, 121n: branches 122: 2nd wiring layer 122a, 122b, 122c: Wiring 122d:cadre 122e, 122f: branches 123: 3rd wiring layer 123a, 123b, 123c, 123d: Wiring 131~134: p-type layer 141~146: n-type layer 151~154: Gate 161~172:Contact 181, 182:Through hole GND: ground potential N1, N2: connection point n1~n4: n-channel transistor p1~p4:p channel transistor SA, bSA: data signal VDD: power supply potential Vc, Vc1, Vc2: control signal Vs1, Vs2: selection signal

[Fig. 1] Schematic cross-sectional view of the semiconductor memory device according to the first embodiment.

[Fig. 2] A schematic plan view of the sense amplifier circuit of the semiconductor memory device according to the first embodiment.

[Fig. 3] A schematic plan view of the data latch circuit of the first embodiment.

[Figure 4] (a) is a schematic plan view of a data latch circuit, and (b) is its circuit diagram.

[Fig. 5] A schematic cross-sectional view of a memory cell of the semiconductor memory device according to the first embodiment.

[Fig. 6] Schematic plan view of the data latch circuit of the second embodiment.

[Fig. 7] (a) is a schematic plan view of a data latch circuit, and (b) is its circuit diagram.

[Fig. 8] A schematic plan view of the semiconductor region, gates, and contacts in the data latch circuit of the third embodiment.

[Fig. 9] A schematic plan view of the semiconductor region, gate, contact and first wiring layer in the data latch circuit of the third embodiment.

[Fig. 10] A schematic plan view of the semiconductor region, gate, contact, first wiring layer, second wiring layer, and third wiring layer in the data latch circuit of the third embodiment.

[Fig. 11] A schematic plan view of a data latch circuit in the third embodiment, (a) shows the semiconductor region, gate and contacts, (b) in (a) further shows the first wiring layer, (c) in (b) further illustrates the second wiring layer and the third wiring layer.

[Fig. 12] Schematic plan view of four data latch circuits of the third embodiment.

[Fig. 13] (a) is a schematic plan view of a data latch circuit in the third embodiment, and (b) is a circuit diagram thereof.

[Fig. 14] A schematic plan view of the semiconductor region, gate, contact and first wiring layer in the four data latch circuits of the fourth embodiment.

[Fig. 15] A schematic plan view of the semiconductor region, gate, contact, first wiring layer, and second wiring layer in the four data latch circuits of the fourth embodiment.

[Fig. 16] A schematic plan view of the semiconductor region, gate, contact, first wiring layer, second wiring layer, and third wiring layer in the four data latch circuits of the fourth embodiment.

[Fig. 17] (a) is a schematic plan view of a data latch circuit in the fourth embodiment, and (b) is a circuit diagram thereof.

11:Silicon substrate

16: Data latch circuit

21:n well

22:p well

23: STI

31~36: p-type layer

41~45: n-type layer

51~56: Gate

61~73:Contact

76, 77: Wiring

GND: ground potential

N1, N2: connection point

n1~n4: n-channel transistor

p1~p4:p channel transistor

SA: data signal

VDD: power supply potential

Vc, Vc1, Vc2: control signal

Vs1, Vs2: selection signal

Claims (4)

A semiconductor memory device, including: a sense amplifier; and a data latch circuit; and a plurality of electrode films separated from each other and laminated; and a semiconductor member penetrating the plurality of electrode films; and provided between the electrode film and the semiconductor member The charge accumulation component between; and the source line connected to the aforementioned semiconductor component; and the bit line connected between the aforementioned semiconductor component and the aforementioned sense amplifier; the aforementioned sense amplifier and the aforementioned data latch circuit are provided in the first 1 substrate, the plurality of electrode films, the semiconductor member, the charge storage member, the source line and the bit line are provided on a second substrate, the first substrate and the second substrate are bonded to each other, and the data lock A storage circuit, including: a 1n-channel transistor; and a 1p-channel transistor; and a 2n-channel transistor; and a 3n-channel transistor; and a 4n-channel transistor; and a 2p-channel transistor. crystal; The gate of the first n-channel transistor and the gate of the first p-channel transistor are a common first common gate, the shape of the first common gate is a crank shape, and the first n-channel transistor is a driver , the aforementioned 1st p-channel transistor is a load, the gate of the aforementioned 2nd n-channel transistor and the gate of the aforementioned 2nd p-channel transistor are a common second common gate, and the source of the aforementioned 3rd n-channel transistor is /The drain side is connected to the second common gate of the second n-channel transistor, the second common gate of the second p-channel transistor, and the source of the first n-channel transistor/ One side of the drain electrode and one side of the source/drain electrode of the aforementioned 1st p-channel type transistor, the other side of the aforementioned source/drain electrode of the aforementioned 3rd n-channel type transistor are connected to the aforementioned sense amplifier, and the aforementioned 4th n-channel type transistor is connected to the sense amplifier. One of the source/drain of the crystal is connected to the first common gate of the first n-channel transistor, the first common gate of the first p-channel transistor, and the second n-channel transistor. One of the source/drain electrodes and one of the source/drain electrodes of the aforementioned 2nd p-channel type transistor, and the other side of the source/drain electrode of the aforementioned 4th n-channel type transistor are connected to the aforementioned sense amplifier. A first reference potential can be applied to the other side of the source/drain of the first p-channel transistor and the other side of the source/drain of the second p-channel transistor, and the source of the first n-channel transistor The other side of the drain electrode and the other side of the source electrode/drain electrode of the second n-channel transistor are of the common n-type layer, the second reference potential is applied. The semiconductor memory device according to claim 1, wherein one of the source/drain of the first p-channel transistor and one of the source/drain of the second p-channel transistor are connected by are separated from each other by the insulating film. In the semiconductor memory device described in claim 2 of the patent application, the insulating film is an element isolation insulating film. The semiconductor memory device described in claim 2, wherein the second common gate shared by the 2n-channel transistor and the 2p-channel transistor has a crank shape, and the 1n-channel transistor has a crank shape. The part on the first p-channel transistor side of the first common gate shared by the first p-channel transistor and the part on the second p-channel transistor side of the second common gate The first distance of the portion is larger than the second distance between the portion of the first common gate on the side of the first n-channel transistor and the portion of the second common gate on the side of the second n-channel transistor. The insulating film is disposed between a portion of the first common gate on the side of the first p-channel transistor and a portion of the second common gate on the side of the second p-channel transistor.