TWI584476B - High voltage metal-oxide-semiconductor transistor device and method of fabricating the same - Google Patents

Description

High-voltage MOS semiconductor transistor component and manufacturing method thereof

The invention relates to a high voltage metal oxide semiconductor transistor component and a manufacturing method thereof, in particular to an M-shaped high voltage metal oxide semiconductor transistor component and a manufacturing method thereof.

High voltage metal-oxide-semiconductor (HV MOS) transistor components have been widely used in central processor power supplies because they can withstand the high voltages provided by general power systems and have switching characteristics. CPU power supply), power management system, AC/DC converter, LCD and plasma TV drivers, automotive electronics, computer peripherals, small DC motor controllers, and consumer Electronic products and other fields.

The conventional HV MOS transistor component is a circular component, that is, the top view of the drain is circular, and the top view of the source is a ring shape, so that the source is centered on the bottom of the bungee. Center of the circle, around the bungee. Moreover, the drain of the HV MOS transistor component is generally electrically connected to the high voltage terminal of the power source, for example, 800 volts or more, so that a withstand voltage structure is provided between the drain and the source to improve the collapse of the HV MOS transistor component. The voltage allows the HV MOS transistor components to operate normally in high voltage environments.

Since the channel width of the circular HV MOS transistor component is determined by the circumferential length of the annular region between the source and the drain, if the on-current of the HV MOS transistor component is to be increased, the circular HV needs to be increased. The radius of the MOS transistor component, but also greatly increases the area of the HV MOS transistor component. In order to simultaneously increase the on-current of the HV MOS transistor element and minimize the area of the HV MOS transistor element, a racetrack-shaped HV MOS transistor element and an M-shaped HV MOS transistor element have been developed.

However, the breakdown voltage of the conventional M-shaped HV MOS transistor element is smaller than the breakdown voltage of the circular HV MOS transistor element, so when a circular HV MOS transistor element, a racetrack HV MOS transistor element, and an M-shaped HV MOS are used When the transistor elements are simultaneously integrated into the same integrated circuit chip, the breakdown voltage of the M-shaped HV MOS transistor element is limited, and the withstand voltage capability of the whole bulk circuit chip is reduced.

In view of this, it is an industry-wide goal to increase the breakdown voltage of the M-shaped HV MOS transistor element and optimize the breakdown voltage of the chip in which the M-shaped HV MOS transistor element and the circular HV MOS transistor element are integrated.

One of the objects of the present invention is to provide a high voltage metal-oxide-semiconductor (HV MOS) transistor component and a method for fabricating the same, which are to improve the breakdown voltage of the M-shaped HV MOS transistor component and optimize it. A breakdown voltage of a wafer integrated with an M-shaped HV MOS transistor element and a circular HV MOS transistor element.

To achieve the above objective, the present invention provides a HV MOS transistor device including a substrate, a deep well region, a first doped region, a high voltage well region, a second doped region, and a third doped region. a gate structure and a fourth doped region. The substrate has a first conductivity type and the substrate has at least one electric field concentration region. The deep well region is disposed in the substrate and has a second conductivity type different from one of the first conductivity types. The first doping region is disposed in the deep well region, wherein the doping concentration of the first doping region in the electric field concentration region has a first ratio to the doping concentration of the deep well region, and the first doping outside the electric field concentration region The doping concentration of the impurity region has a second ratio to the doping concentration of the deep well region, and the first ratio is greater than the second ratio. The high voltage well region is disposed in the substrate and has a first conductivity type. The second doped region is disposed in the deep well region and has the second conductivity type, wherein the first doped region is located between the second doped region and the high voltage well region. The third doped region is disposed in the high voltage well region and has a second conductivity type, wherein the electric field concentration region surrounds a portion of the third doped region. The gate structure is disposed on the high voltage well region between the first doped region and the third doped region. The fourth doped region is disposed in the high voltage well region and has a first conductivity type.

To achieve the above object, the present invention provides a method of fabricating a HV MOS transistor. First, a substrate is provided, the substrate having a first conductivity type, and the substrate having at least one electric field concentration region. Next, a deep well region is formed in the substrate, and the deep well region has a second conductivity type that is different from one of the first conductivity types. Then, a first doped region is formed in the deep well region, and the first doped region has a first conductivity type, wherein the doping concentration of the first doped region in the electric field concentration region and the doping concentration of the deep well region have A first ratio, the doping concentration of the first doping region outside the electric field concentration region has a second ratio to the doping concentration of the deep well region, and the first ratio is greater than the second ratio. Subsequently, a high-pressure well region is formed in the substrate, and a second doping region and a third doping region are formed in the deep well region and the high-voltage well region, respectively, the high-voltage well region has a first conductivity type, and the second doping The region and the third doped region have a second conductivity type, wherein the first doped region is between the second doped region and the high voltage well region, and the electric field concentration region surrounds a portion of the third doped region.

The breakdown voltage of the M-shaped HV MOS transistor device of the present invention is adjusted by adjusting a first ratio of a doping concentration of the first doping region in the electric field concentration region to a doping concentration of the deep well region to be greater than being located outside the electric field concentration region The second ratio of the doping concentration of the first doping region to the doping concentration of the deep well region may be increased, so that the breakdown voltage of the wafer in which the M-shaped HV MOS transistor component and the circular HV MOS transistor component are integrated may be Was effectively improved.

The present invention will be further understood by the following detailed description of the preferred embodiments of the invention, efficacy.

Please refer to FIG. 1 and FIG. 2 . FIG. 1 is a top view of a high voltage metal-oxide-semiconductor (HV MOS) transistor component according to a preferred embodiment of the present invention, and FIG. It is a schematic cross-sectional view along the section line AA' of Fig. 1. As shown in FIGS. 1 and 2, the HV MOS transistor device 100 is fabricated on a substrate 102, such as a germanium substrate, and the substrate 102 has a first conductivity type. The HV MOS transistor component 100 includes a first insulating layer 104, a deep well region 106, a drift region 108, a first doped region 110, a high voltage well region 112, a second doped region 114, and a third doped region. The impurity region 116, a gate structure 118, and a fourth doping region 120. The deep well region 106, the second doping region 114 and the third doping region 116 have a second conductivity type different from the first conductivity type, and the first doping region 110, the high voltage well region 112, and the fourth doping region 120 Has a first conductivity type. The first conductivity type and the second conductivity type of the embodiment are respectively P-type and N-type, but the invention is not limited thereto and may be interchanged.

In the present embodiment, the N-type deep well region 106 is disposed in the P-type substrate 102 and serves as the drain of the HV MOS transistor element 100. A first insulating layer 104 is disposed on the P-type substrate 102 to define the location of the N-type deep well region 106. The N-type drift region 108 is disposed in the N-type deep well region 106. The N-type second doping region 114 is disposed in the N-type drift region 108, and the N-type second doping region 114 has a plurality of protrusions 121 extending in the same direction and parallel to each other, so that between any two adjacent protrusions 121 There is a notch 122. Thereby, the N-type second doping region 114 is an M-shaped structure or a comb-shaped structure, and the N-type deep well region 106 can be electrically connected to a drain metal layer, so that the high voltage generated by the power source can be The drain metal layer is input to the N-type deep well region 106. The P-type high pressure well region 112 is disposed in the N-type deep well region 106, and the N-type deep well region 106 surrounds the P-type high pressure well region 112. Moreover, the P-type high-voltage well region 112 surrounds the N-type second doping region 114 along the N-type second doping region 114 having an M-shaped structure, and has an M-shaped annular structure and is used as an HV MOS transistor. The base of component 100. The N-type third doping region 116 is disposed in the P-type high voltage well region 112 and serves as a source of the HV MOS transistor element 100. The N-type third doped region 116 surrounds the N-type second doped region 114 and has the same M-shaped annular structure as the P-type high voltage well region 112. The P-type fourth doping region 120 is disposed in the P-type high voltage well region 112 and surrounds the N-type third doping region 114 for electrically charging the P-type high voltage well region 112 which is the base of the HV MOS transistor component 100. Sexual connection to the outside world. The gate structure 118 is disposed on the P-type high voltage well region 112 between the P-type first doping region 110 and the N-type third doping region 116 to serve as a gate of the HV MOS transistor component 100. The P-type first doping region 110 is disposed in the N-type deep well region 106 between the N-type second doping region 114 and the P-type high-voltage well region 112, and surrounds the N-type second doping region 114 to improve the The withstand voltage capability of the N-type deep well region 106 between the N-type second doped region 114 and the P-type high-pressure well region 112 prevents the N-type deep well region 106 from collapsing due to excessive voltage. It can be seen that the HV MOS transistor element 100 of the present embodiment is an M-shaped element or a comb-shaped element having a plurality of notches 122, but the HV MOS transistor element 100 of the present invention is not limited to having a plurality of notches 122. It is also possible to have at least one notch 122.

In addition, the substrate 102 has a plurality of electric field concentration regions 124 defined therein, wherein each of the electric field concentration regions 124 is located between the N-type second doping region 114 and the P-type high-pressure well region 112, and is located at the bottom of each of the notches 122. region. The electric field concentration region 124 is located in a portion of the N-type deep well region 106. Moreover, each of the electric field concentration regions 124 is a semi-circular arc-shaped region and surrounds a portion of the N-type third doping region 116. The number of electric field concentration regions 124 of the present invention is determined by the number of recesses 122. Therefore, the substrate 102 is not limited to have a plurality of electric field concentration regions 124, but may have at least one electric field concentration region 124. In this embodiment, the doping concentration of the P-type first doping region 110 in each of the electric field concentration regions 124 has a first ratio with the doping concentration of the N-type deep well region 106, and is located in each electric field concentration region 124. The doping concentration of the outer P-type first doping region 110 has a second ratio to the doping concentration of the N-type deep well region 106. Moreover, the doping concentration of the N-type deep well region 106 located in each electric field concentration region 124 is smaller than that of the N-type deep well region 106 located outside each electric field concentration region 124. The impurity concentration is such that the first ratio is greater than the second ratio. In this embodiment, the doping concentration of the P-type first doping region 110 located in each of the electric field concentration regions 124 is matched with the doping concentration of the N-type deep well region 106 located in each of the electric field concentration regions 124. Adjusting to have a suitable first ratio allows the HV MOS transistor component 100 to achieve the desired operational efficiency. Moreover, the doping concentration of the N-type deep well region 106 in each of the electric field concentration regions 124 of the present embodiment is smaller as it approaches the two sides of the P-type first doping region 110. In other words, in each of the electric field concentration regions 124, the doping concentration of the N-type deep well region 106 adjacent to the inner side and the outer side of each electric field concentration region 124 is greater than that of the N-type deep well region 106 located far from the inner and outer sides of each electric field concentration region 124. The doping concentration, and the closer to the inner side and the outer side of each electric field concentration region 124, the smaller the doping concentration of the N-type deep well region 106, but the present invention is not limited thereto. In other embodiments of the present invention, the doping concentration of the N-type deep well region 106 located in each of the electric field concentration regions 124 may be smaller as it is closer to the inner side of each electric field concentration region 124, or only the more adjacent electric fields. The outer side of the concentration area 124 is smaller. Alternatively, the doping concentration of the N-type deep well region 106 located in each of the electric field concentration regions 124 may not have a gradient change.

It is worth mentioning that when the HV MOS transistor element 100 is turned on, a high electric field is generated between the N-type second doping region 114 electrically connected to the high voltage and the N-type third doping region 116 as the source. And the electric field direction is directed from the N-type second doping region 114 to the N-type third doping region 116. Since each of the electric field concentration regions 124 is a semi-circular arc-shaped region, the length of the outer side of each electric field concentration region 124 is greater than the inner length of each electric field concentration region 124, so that the electric field in each electric field concentration region 124 is from the outer side of each electric field concentration region 124. The inner side of each electric field concentration area 124 is gathered as shown by the arrow in Fig. 1. It can be seen that each is located The P-type first doped region 110 and the N-type deep well region 106 in the electric field concentration region 124 are subjected to a higher voltage density than the P-type first doped region 110 and the N-type deep well region 106 located outside the respective electric field concentration regions 124. The HV MOS transistor element 100 of the present embodiment is improved in the withstand voltage capability of the P-type first doping region 110 and the N-type deep well region 106 in each of the electric field concentration regions 124 by adjusting the first ratio to be greater than the second ratio. It is avoided that the P-type first doping region 110 and the N-type deep well region 106 in each of the electric field concentration regions 124 first collapse due to the excessive voltage of the HV MOS transistor element 100, and the HV MOS transistor element 100 can be simultaneously lifted. The breakdown voltage. In this embodiment, the doping concentration of the N-type deep well region 106 located in each of the electric field concentration regions 124 may also be smaller as it is closer to the P-type high-pressure well region 112, so that the electric field is concentrated in each of the electric field concentration regions 124. The dense N-type deep well region 106 has a lighter doping concentration to increase the breakdown voltage.

In addition, the HV MOS transistor component 100 further includes a second insulating layer 126 and a plurality of field electrodes 128. The second insulating layer 126 is disposed on the P-type first doping region 110 for preventing the high voltage of the N-type second doping region 116 from damaging the gate structure 118. The field electrode 128 is disposed on the second insulating layer 126 and is in a floating state, so that the field electrode 128 can be used to raise the breakdown voltage of the HV MOS transistor element 110.

Please refer to FIG. 3, which is the second ratio and the breakdown voltage of the doping concentration of the P-type first doping region and the doping concentration of the N-type deep well region of different HV MOS transistor components outside the electric field concentration region. Schematic diagram of the relationship. As shown in FIG. 3, the first relationship curve 130 represents the relationship between the second ratio of the circular HV MOS transistor element and the breakdown voltage. The second relationship curve 132 represents a P-type first doping in each of the electric field concentration regions. The relationship between the second ratio of the M-shaped HV MOS transistor element and the breakdown voltage in the case where the first ratio of the doping concentration of the region to the doping concentration of the N-type deep well region is the same as the second ratio. The third relationship curve 134 represents the relationship between the second ratio and the breakdown voltage in the case where the first ratio is greater than the second ratio of the M-shaped HV MOS transistor element of the present embodiment. Comparing the second relationship curve 132 with the third relationship curve 134, when the same second ratio is used, the breakdown voltage of the third relationship curve 134 is greater than the breakdown voltage of the second relationship curve 132. In other words, when the first ratio of the M-shaped HV MOS transistor element is adjusted to be greater than the second ratio, the second relationship curve 132 is shifted upward to become the third relationship curve 134. Moreover, it is worth noting that the breakdown voltage of the first relationship curve 130 of the circular HV MOS transistor element decreases as the second ratio increases, but the second relationship curve 132 and the third of the M-shaped HV MOS transistor element The breakdown voltage of the relationship curve 134 will increase as the second ratio increases. Therefore, the M-shaped HV MOS transistor component of the embodiment can be raised by adjusting the first ratio to be greater than the second ratio so that the breakdown voltage is at the same second ratio, and the first relationship curve 130 and the third relationship are The collapse voltage at the intersection of the relationship curve 134 is greater than the collapse voltage at the intersection of the first relationship curve 130 and the second relationship curve 134. Moreover, the second ratio of the intersection of the first relationship curve 130 and the third relationship curve 134 is closer to a reference value BL than the second ratio of the intersection of the first relationship curve 130 and the second relationship curve 132, thereby avoiding the second ratio The ratio deviates too much from the reference value BL to cause the HV MOS transistor element to malfunction. Therefore, the breakdown voltage of the wafer in which the M-shaped HV MOS transistor element and the circular HV MOS transistor element are integrated can be effectively improved.

The manufacturer of the HV MOS transistor component of the present embodiment will be further described below. law. Please refer to Figures 4 to 9, and refer to Figure 2 together. 4 to 9 are schematic views showing a method of fabricating a HV MOS transistor component according to a preferred embodiment of the present invention. As shown in Fig. 4, a P-type substrate 102 is first provided. Then, a first mask 135 and a plurality of second masks 136, such as a photoresist mask, are formed on the P-type substrate 102. The first mask 135 defines the location of the N-type deep well region 106, and the second mask 136 is located in each of the electric field concentration regions 124. Subsequently, a first ion implantation process is performed on the P-type substrate 102 in a comprehensive manner, and N-type ions are implanted in the P-type substrate 102. As shown in FIG. 5, each of the second masks 136 of the present embodiment is an arc-shaped mask, and each of the second masks 136 surrounds the inner side of each of the electric field concentration regions 124 and is separated from each of the electric field concentration regions 124. The inner side is sequentially arranged to the outer side of each electric field concentration area 124. It should be noted that the closer to the inner side and the outer side of each electric field concentration area 124, the smaller the distance between any two adjacent second masks 136, so that the N-type deep well area 106 formed in each electric field concentration area 124 is subsequently The doping concentration is smaller as it is closer to the two sides of the formed P-type first doping region 110, so that the denser electric field in the electric field concentration region 124 is denser in the N-type deep well region 106, that is, adjacent to P. The N-type deep well region 106 on both sides of the first doped region 110 is doped with a lighter concentration to increase the breakdown voltage. The second mask 136 of the present invention is not limited to an arc-shaped mask, and each of the second masks 136 may also have a strip pattern, and each of the second masks 136 is directed to the inner side of each electric field concentration area 124, such as Figure 6 shows. Thereby, the doping concentration of the N-type deep well region 106 formed in each of the electric field concentration regions 124 is smaller as it approaches the inner side of the formed P-type first doping region 110. The second mask 136 of the present invention is not limited to the above, and the distance between any two adjacent second masks 136 or the width and shape of each second mask may be adjusted according to the required withstand voltage conditions. The doping concentration of the N-type deep well region 106 in the electric field concentration region 124 may or may not have a gradient change.

As shown in FIG. 7, the first mask 135 and the second mask 136 are then removed and a thermal drive process is performed to form an N-type deep well region 106. Since the second mask 136 shields part of the P-type substrate 102 of each of the electric field concentration regions 124, the N-type ion concentration doped in each of the electric field concentration regions 124 is lower than that of the N-doped regions 124. Type ion concentration. Thereby, the doping concentration of the N-type deep well region 106 located in each of the electric field concentration regions 124 may be smaller than the doping concentration of the N-type deep well region 106 located outside the respective electric field concentration regions 124.

As shown in FIG. 8, a third mask 138 and a plurality of fourth masks 140, such as photoresist masks, are simultaneously formed on the P-type substrate 102. The third mask 138 defines the location of the P-type first doped region 110, and the fourth mask 140 is located in each of the electric field concentration regions 124. Then, a second ion implantation process is performed on the P-type substrate 102 in a comprehensive manner to implant P-type ions in the N-type deep well region 106. As shown in FIG. 9, the third mask 138 and the fourth mask 140 are then removed, and a thermal drive process is performed to form a P-type first doped region 110. Since the fourth mask 140 shields a portion of the N-type deep well region 106 of each of the electric field concentration regions 124, the P-type ion concentration doped in each of the electric field concentration regions 124 is lower than that doped outside the respective electric field concentration regions 124. The P-type ion concentration is adjusted to the appropriate first ratio by the doping concentration of the N-type deep well region 106 located in each of the electric field concentration regions 124, so that the HV MOS transistor component 100 can achieve the desired operational efficiency, and The first ratio of the doping concentration of the P-type first doping region 110 located in each of the electric field concentration regions 124 to the doping concentration of the N-type deep well region 106 may be greater than the P-type first doping outside the respective electric field concentration regions 124. A second ratio of the doping concentration of the hetero region 110 to the doping concentration of the N-type deep well region 106. Since the concentration of P-type ions in each electric field concentration region 124 is not lower than each electric power The P-type ion concentration outside the field concentration area 124 can reach a suitable first ratio. Therefore, the method of the present invention is not limited to forming the fourth mask 140 on the P-type substrate 102, and the fourth mask 140 may not be formed. The doping concentration of the P-type first doping region 110 located in each of the electric field concentration regions 124 is the same as the doping concentration of the P-type first doping region 110 located outside the respective electric field concentration regions 124, and may also be made first. The ratio is greater than the second ratio. However, the invention is not limited thereto.

As shown in FIG. 2, a P-type high pressure well region 112 and an N-type drift region 108 are then sequentially formed in the N-type deep well region 106. Subsequently, a second insulating layer 126, such as a field oxide layer, is formed over the P-type first doped region 110. Next, a gate structure 118 and a field electrode 128 are formed on the P-type high-voltage well region 112, the N-type deep well region 106, and the second insulating layer 126, wherein the gate structure 118 extends from the portion of the P-type high-voltage well region 112 to a portion On the second insulating layer 126. An N-type second doped region 114 is then formed in the N-type drift region 108 while an N-type third doped region 116 is formed in the P-type high voltage well region 112. The P-type first doped region 110 is between the N-type second doped region 114 and the P-type high-voltage well region 112, and each of the electric field concentration regions 124 surrounds a portion of the N-type third doped region 116. A P-type fourth doped region 120 is then formed in the P-type high voltage well region 112.

The method of the present invention for forming an N-type deep well region having different doping concentrations is not limited to the use of a photoresist mask. Please refer to FIG. 10, which is a schematic diagram of a method for fabricating a HV MOS transistor component according to another preferred embodiment of the present invention. As shown in FIG. 10, in comparison with the above embodiment, the step of forming the N-type deep well region in the present embodiment uses the halftone mask 142 to perform the first ion implantation process, and the halftone mask 142 corresponds to each electric field. Concentrated area The region other than 124 causes the N-type ion concentration doped in each of the electric field concentration regions 124 to be lower than the N-type ion concentration doped outside the respective electric field concentration regions 124. Thereby, the doping concentration of the N-type deep well region 106 located in each of the electric field concentration regions 124 may be smaller than the doping concentration of the N-type deep well region 106 located outside the respective electric field concentration regions 124. In addition, in other embodiments of the present invention, the P-type first doping region 110 having different doping concentrations may be used, but the halftone mask 142 may be used, but not limited thereto.

In summary, the present invention utilizes an arc-shaped or strip-shaped mask or a halftone mask to shield a portion of the P-type substrate in the electric field concentration region to form an N-type deep well region having different doping concentrations, and is located at each electric field. The doping concentration of the N-type deep well region in the concentration zone is smaller than the doping concentration of the N-type deep well region outside the electric field concentration region. Thereby, the first ratio of the doping concentration of the P-type first doping region in the electric field concentration region to the doping concentration of the N-type deep well region may be greater than the P-type first doping region outside the electric field concentration region. The second ratio of the doping concentration to the doping concentration of the N-type deep well region. Moreover, the breakdown voltage of the M-shaped HV MOS transistor device of the present invention can be increased by adjusting the first ratio to be larger than the second ratio, thereby integrating the M-shaped HV MOS transistor element and the circular HV MOS transistor element at the same time. The chip's breakdown voltage can be effectively boosted.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100‧‧‧High voltage MOS transistor components

102‧‧‧Base

104‧‧‧First insulation

106‧‧‧Shenjing District

108‧‧‧Drift area

110‧‧‧First doped area

112‧‧‧High-pressure well area

114‧‧‧Second doped area

116‧‧‧ Third doped area

118‧‧‧ gate structure

120‧‧‧fourth doping zone

121‧‧‧Protruding

122‧‧‧ Notch

124‧‧‧Electrical field concentration area

126‧‧‧Second insulation

128‧‧ ‧ field electrode

130‧‧‧first relationship curve

132‧‧‧second relationship curve

134‧‧‧ third relationship curve

135‧‧‧ first mask

136‧‧‧second mask

138‧‧‧ third mask

140‧‧‧Fourth mask

142‧‧‧ halftone mask

BL‧‧‧ benchmark value

1 is a top view of a high voltage MOS transistor component according to a preferred embodiment of the present invention. schematic diagram.

Fig. 2 is a schematic cross-sectional view taken along line AA' of Fig. 1.

Fig. 3 is a graph showing the relationship between the doping concentration of the P-type first doped region and the doping concentration of the N-type deep well region and the breakdown voltage of the different HV MOS transistor elements outside the electric field concentration region.

4 to 9 are schematic views showing a method of fabricating a HV MOS transistor component according to a preferred embodiment of the present invention.

FIG. 10 is a schematic view showing a manufacturing method of a HV MOS transistor component according to another preferred embodiment of the present invention.

100. . . High voltage MOS transistor

102. . . Base

104. . . First insulating layer

106. . . Deep well area

108. . . Drift zone

110. . . First doped region

112. . . High pressure well area

114. . . Second doped region

116. . . Third doped region

118. . . Gate structure

120. . . Fourth doped region

124. . . Electric field concentration area

126. . . Second insulating layer

128. . . Field electrode

Claims (19)

A high voltage MOS semiconductor transistor device comprising: a substrate having a first conductivity type, the substrate having at least one electric field concentration region; and a deep well region disposed in the substrate and having a different conductivity type a second conductivity type, wherein the electric field concentration region is located in a portion of the deep well region; a first doped region is disposed in the deep well region, wherein the first doped region is mixed in the electric field concentration region The doping concentration has a first ratio with the doping concentration of the deep well region, and the doping concentration of the first doping region outside the electric field concentration region has a second ratio to the doping concentration of the deep well region, and the The first ratio is greater than the second ratio; a high pressure well region is disposed in the deep well region and has the first conductivity type; a second doped region is disposed in the deep well region and has the second conductivity type The first doped region is located between the second doped region and the high voltage well region, and the electric field concentration region is located between the second doped region and the high voltage well region, and the second doped region Having at least one notch; a third doped region, In the high-voltage well region, and having the second conductivity type, wherein the electric field concentration region surrounds a portion of the third doped region; a gate structure is disposed in the first doped region and the third doped region And the fourth doped region is disposed in the high voltage well region and has the first conductivity type. The high voltage MOS transistor device of claim 1, wherein a doping concentration of the deep well region located in the electric field concentration region is smaller than the concentration outside the electric field concentration region Doping concentration in the deep well area. The high voltage MOS transistor device of claim 1, wherein a doping concentration of the first doping region in the electric field concentration region is mixed with the first doping region outside the electric field concentration region. The impurity concentration is the same. The high voltage MOS transistor device of claim 1, wherein a doping concentration of the deep well region located in the electric field concentration region is smaller as a closer to two sides of the first doping region. The high voltage MOS transistor device of claim 1, further comprising an insulating layer disposed on the first doped region. The high voltage MOS transistor device of claim 5, further comprising a plurality of field electrodes disposed on the insulating layer. The high voltage MOS transistor device of claim 1, wherein the electric field concentration region is a semicircular arc region. The high voltage MOS transistor device of claim 1, wherein the high voltage MOS transistor device is an M-shaped device. A high voltage MOS transistor device as claimed in claim 1, further comprising a drift a region is disposed in the deep well region, and the second doped region is disposed in the drift region. A method of fabricating a high voltage MOS transistor device, comprising: providing a substrate, wherein the substrate has a first conductivity type, and the substrate has at least one electric field concentration region; forming a deep well region in the substrate, and the deep well The region has a second conductivity type different from the first conductivity type, wherein the electric field concentration region is located in a portion of the deep well region; a first doped region is formed in the deep well region, and the first doped region has The first conductivity type, wherein a doping concentration of the first doping region in the electric field concentration region has a first ratio with a doping concentration of the deep well region, and the first doping outside the electric field concentration region The doping concentration of the impurity region has a second ratio to the doping concentration of the deep well region, and the first ratio is greater than the second ratio; and forming a high pressure well region in the substrate, and respectively in the deep well region Forming a second doped region and a third doped region in the high voltage well region, the high voltage well region having the first conductivity type, and the second doped region and the third doped region having the second conductivity type Which of the a doped region is located between the second doped region and the high voltage well region, and the electric field concentration region surrounds a portion of the third doped region, and wherein the electric field concentration region is located in the second doped region and the high voltage region Between the well regions, and the second doped region has at least one recess. The method of fabricating a high voltage MOS transistor according to claim 10, wherein the step of forming the deep well region comprises: Forming a first mask and a plurality of second masks on the substrate, wherein the second masks are located in the electric field concentration region; and performing a first ion implantation process on the substrate comprehensively to form the In the deep well region, the doping concentration of the deep well region located in the electric field concentration region is smaller than the doping concentration of the deep well region outside the electric field concentration region. The method of fabricating a high voltage MOS transistor according to claim 11, wherein each of the second masks is an arc-shaped mask, and each of the second masks surrounds one of the inner sides of the electric field concentration region. The method of fabricating a high voltage MOS transistor according to claim 12, wherein the distance between any two adjacent second masks is closer to the inner side and the outer side of the electric field concentration region. The method of fabricating a high voltage MOS transistor according to claim 11, wherein each of the second masks is a strip mask, and each of the second masks is directed to an inner side of the electric field concentration region. The method of fabricating a high voltage MOS transistor according to claim 10, wherein the step of forming the deep well region comprises performing a first ion implantation process using a halftone mask to cause the deep well located in the electric field concentration region The doping concentration of the region is less than the doping concentration of the deep well region outside the concentration region of the electric field. The method of fabricating the high voltage MOS transistor device of claim 10, wherein the forming the first doped region comprises: forming a third mask and a plurality of fourth masks on the substrate, wherein the And waiting for the fourth mask to be located in the electric field concentration region; and performing a second ion implantation process on the substrate comprehensively to form the first doping region. The method of fabricating the high voltage MOS transistor device of claim 10, further comprising forming a fourth doped region in the high voltage well region, and the fourth doped region has the first conductivity type. The method of fabricating the high voltage MOS transistor device of claim 10, further comprising forming an insulating layer on the first doped region. The method for fabricating a high voltage MOS transistor according to claim 18, further comprising forming a gate structure and a plurality of field electrodes on the insulating layer.