TWI584303B - Method and system for controlling status indication light of pcie hard disk drive - Google Patents

Description

Quick peripheral peripheral interconnection standard hard disk status light control method and system

The present invention relates to the technical field of PCIE solid state hard disks, and in particular to a method and system for controlling a PCIE hard disk status light.

Currently, most of the servers use SATA/SAS hard drives with a transfer rate of 6G, and a small portion uses SATA/SAS hard drives with a transfer rate of 12G. As shown in the first figure, when the status light of the SATA/SAS hard disk with the transmission rate of 6G or 12G is displayed, the central processing unit (CPU) PA1 is connected to the SAS expander by the SAS controller PA2 ( SAS Expander) PA3, SAS expander connects the signal to the SFF-8639 connector PA4, and then the SFF-8639 connector PA4 externally transmits the SATA/SAS hard disk PA5 with a transmission rate of 6G or 12G, thus achieving the CPU PA1 pair transmission rate. Control of 6G or 12G SATA/SAS hard disk PA5 signal lights. Specifically, the system-side tool commands to the CPU PA1 side, and the CPU PA1 controls the SAS expander to issue a Serial General Purpose Input Output (SGPIO) signal to the complex programmable logic controller through the SAS controller PA2 ( Complex Programmable Logic Device (CPLD), which then analyzes the SGPIO group signal and outputs it to the status light of the corresponding hard disk, thereby realizing the control of the status light of the SATA/SAS hard disk PA5 with a transmission rate of 6G or 12G.

With the widespread use of PCIE SSDs, PCIE Solid State Drives (PCIE SSDs) have been used on some servers. As further referred to in the first figure, the SFF-8639 connector PA4 provides non-shared pins for SATA/SAS hard disks and PCIE SSDs, which are mutually exclusive access. However, the existing working mode of the PCIE SSD causes the CPU PA1 to be unable to control the PCIE SSD status light, so that the PCIE SSD usage status cannot be determined in time.

In view of the above disadvantages of the prior art, an object of the present invention is to provide a method and system for controlling a PCIE hard disk status light, which can realize display control of a status light corresponding to a reset and positioning operation of a PCIE hard disk, thereby facilitating timely judgment of PCIE. The state of use of the hard drive.

To achieve the above and other related objects, the present invention provides a method for controlling a PCIE hard disk status light, comprising the steps of: determining a current working mode of a PCIE hard disk; and transmitting, by the CPU, the current working mode information to a south bridge chip; The south bridge chip sends the current working mode information to the complex programmable logic controller; according to the current working mode information, the complex programmable logic controller controls display of the status light corresponding to the current working mode. In an embodiment of the invention, the working mode of the PCIE hard disk includes a hard disk reset mode and a hard disk localization mode.

In an embodiment of the present invention, when the current working mode information is sent to the south bridge chip, the current working mode is recorded by an output level register corresponding to the GPIO serial port expander of the south bridge chip. information.

In an embodiment of the invention, the output level register occupies a total of 64 bits, and the lower 8 bits are occupied by the BIOS, and the working mode of the PCIE hard disk is represented by two bits.

In an embodiment of the invention, when the south bridge chip sends the current working mode information to the complex programmable logic controller, the method includes the following steps: performing Hamming check on the current working mode information (Hamming) Check), generating Hamming Check Code data; and transmitting the generated Hamming check code data to the complex programmable logic controller.

Meanwhile, the present invention further provides a control system for a PCIE hard disk status light, including a determination module, a first transmission module, a second transmission module, and a control module; the determination module is configured to determine a current PCIE hard disk a working mode; the first sending module is connected to the determining module, configured to send the current working mode information to a south bridge chip through a CPU; and the second sending module is connected to the first sending module And sending, by the south bridge chip, the current working mode information to a complex programmable logic controller; the control module is connected to the second sending module, configured to use, according to the current working mode information, The display of the status light corresponding to the current working mode is controlled by the complex programmable logic controller.

In an embodiment of the invention, the working mode of the PCIE hard disk includes a hard disk reset mode and a hard disk localization mode.

In an embodiment of the present invention, when the first sending module sends the current working mode information to the south bridge chip, an output level register corresponding to the GPIO serial port expander of the south bridge chip To record the current working mode information.

The specific embodiments of the present invention will be further described by the following examples and drawings.

In an embodiment of the invention, the output level register occupies a total of 64 bits, and the lower 8 bits are occupied by the BIOS, and the working mode of the PCIE hard disk is represented by two bits.

In an embodiment of the present invention, when the south bridge chip sends the current working mode information to the complex programmable logic controller, the method includes the following steps: performing a Hamming check on the current working mode information, and generating Hamming check code data; send the generated Hamming check code data to the complex programmable logic controller.

As described above, the control method and system for the PCIE hard disk status lamp of the present invention have the following beneficial effects: (1) The CPU controls the CPLD by the south bridge chip, thereby realizing the state corresponding to the reset and positioning operation of the PCIE hard disk. Display control of the lamp; (2) able to judge the use status of the PCIE hard disk in time; (3) ensure the accurate display of the status light by performing Hamming check on the current working mode information.

PA1‧‧‧CPU

PA2‧‧‧SAS controller

PA3‧‧‧SAS expander

PA4‧‧‧SFF-8639 connector

PA5‧‧‧SATA/SAS hard drive

100‧‧‧CPU

200‧‧‧SFF-8639 connector

300‧‧‧PCIE hard disk

1‧‧‧Judgement module

2‧‧‧First Sending Module

3‧‧‧Second Transmitter

4‧‧‧Control Module

The first figure shows the structure of the state light control system of the SATA/SAS hard disk in the prior art; the second figure shows the structure of the state light control system of the PCIE hard disk in the technology of the present invention; the third figure shows the present invention. A flowchart of a method for controlling a PCIE hard disk status lamp; and a fourth diagram showing a structure of a control system for a PCIE hard disk status lamp of the present invention.

The embodiments of the present invention are described below by way of specific examples, and those skilled in the art can readily understand other advantages and effects of the present invention from the disclosure of the present disclosure. The invention may also be embodied or applied by various other specific embodiments, each of the The details of the items may also be varied and changed without departing from the spirit and scope of the invention. It should be noted that the features in the following embodiments and embodiments may be combined with each other without conflict.

It should be noted that the illustrations provided in the following embodiments merely illustrate the basic concept of the present invention in a schematic manner, and only the components related to the present invention are shown in the drawings, rather than the number and shape of components in actual implementation. Dimensional drawing, the actual type of implementation of each component's type, number and proportion can be a random change, and its component layout can be more complicated.

The control method and system for the PCIE hard disk status lamp of the present invention realizes the reset status of the PCIE hard disk and the status light corresponding to the positioning operation by the Complex Programmable Logic Device (CPLD). Display control. The control method and system of the PCIE hard disk status lamp of the present invention generate data to the CPLD, and the CPLD can control the power supply of the PCIE hard disk, thereby implementing control of the PCIE hard disk status light.

Referring to the second figure, the CPU 100 converts the PCIE signal line into a SAS signal line and directly connects to the SFF-8639 connector 200, and then connects the PCIE hard disk 300 to the SFF-8639 connector PA4. The PCIE hard disk 300 described in the present invention generally refers to various hard disks that use the PCIE interface to transmit data and signals, including a PCIE solid state drive (PCIE SSD).

Referring to the third figure, the control method of the PCIE hard disk status light of the present invention comprises the following steps: Step S1: determining the current working mode of the PCIE hard disk. Among them, the working mode of the PCIE hard disk includes a hard disk reset mode and a hard disk positioning mode. Compared with the prior art, the present invention increases the hard disk reset mode, so that the use state of the PCIE hard disk can be judged in time according to the display of the status light.

Step S2: The CPU sends the current working mode information to a Platform Controller Hub (PCH). When the current working mode information is sent to the PCH, the output level register corresponding to the GPIO Serial eXpander (GSX) of the south bridge chip is modified from the system side to record the current working mode information. Output The level register occupies a total of 64 bits, wherein the lower 8 bits are occupied by the BIOS, and the two bits of the remaining 56 bits except the lower 8 bits occupied by the BIOS are represented by the 64 bits. The working mode of the hard disk. Among them, the high bit indicates the hard disk positioning mode, and the low bit indicates the hard disk reset mode.

Step S3: The PCH sends the current working mode information to the complex programmable logic controller. Wherein, step S3 comprises the following steps:

31) Perform Hamming check on the current working mode information to generate Hamming check code data. Among them, Hamming code can correct one-bit error, detect two-element error, and reduce the bit error rate in transmission. By using Hamming check, it is ensured that the current working mode information can be accurately transmitted to ensure accurate display of the LED status lights.

32) Send the generated Hamming check code data to the CPLD.

Step S4: The complex programmable logic controller controls the display of the status light corresponding to the current working mode according to the current working mode information. Specifically, the CPLD parses the received data, obtains the current working mode information, and outputs a signal to the corresponding LED status light to control the display of the corresponding LED status light.

In the prior art, the largest application scenario in the server includes 24 PCIE hard disks. The control method of the PCIE hard disk status light of the present invention is described below based on the application scenario of 12 hard disks.

First, the BASE ADDRESS (0xfed04000) of the GSX register is mapped to the memory by the MMAP function. The register accounts for 0x400h bytes, and the offset of the output level register corresponding to the GSX is 0x30h. Since the lower 8 bits of the output level register are occupied by the BIOS, bit 8~bit 63 is used. However, in order to facilitate calculation, when designing the code, first encode according to bit 0~bit 55, and finally shift the final value to the left by 8 bits and perform the OR operation with the lower 8 bits of the BIOS control before outputting. It should be noted that the above algorithm is only applied to the scene of 12 hard disks, and the scene of 24 hard disks requires fine tuning of the code.

The distribution relationship between the hard disk number and the respective control bits is shown in the table below.

When performing Hamming check on the current working mode information, you need to add the Hamming check code. The encoding rule of Hamming check code is to insert the check code into the normal data bits, which are placed in 2n bits, n=0, 1, 2, 3, 4..., Hamming check code. The relationship between the length and the length of the data bits is shown in Table 2.

Since only 24 bits are needed to represent the two control bits of 12 hard disks, only five check codes are needed. The arrangement relationship between the check code and the data bits is as shown in Table 3. The data bits are represented by Di and the check bits are represented by Pj.

It can be seen from Table 3 that the length of the whole check data is 29 bits, and the check bit P1 starts from the 0th bit, and every other check verifies that the 0th bit, 2 bits, 4 bits, 6-bit, 8-bit...

The check bit P2 starts from the first bit, continuously checks two bits, and is separated by two bits, and then checks two bits, that is, the first and second bits are verified, and the fifth and sixth bits are used. 9, 10 bits... the rest of the way.

The check bit P3 starts from the third bit, continuously checks four bits, is separated by four bits, and then checks four bits, that is, checks the third, fourth, fifth, and sixth bits, the eleventh, the twelfth 13, 13 and 14 bits, 19th, 20th, 21st, 22nd...

The check bit P4 starts from the 7th bit, continuously checks the octet, divides the octet, and checks the octet, that is, checks the 7, 8, 9, 10, 11, 12, 13, 14 bits, 23, 24, 25, 26, 27, 28 bits.

The check bit P5 starts from the 15th bit, continuously checks the 16-bit, divides the 16-bit, and then checks the 16-bit, that is, the 15th, 16th, 17th, 18th, 19th, 20th. , 21, 22, 23, 24, 25, 26, 27, 28 bits.

Because for the backplane of the number of 12 hard disks, only a total of 29 data bits and check digits are needed, and the excess is no longer verified. If it is a scene with 24 hard disks, you need 6 checksums. The program needs to be adjusted accordingly.

The parity check code is generated by using the even check, that is, the data bit to be verified by each check code together with the check code itself, and the number of "1" is even, and the specific check relationship is as shown in Table 4. .

Place the valid data bits in the correct Hamming code position. The code based on the relationship between the original encoding and the Hamming code position is as follows: if(0==strcmp(argv[1], ResetCmd)) { //gsxOut0=0x1<<hd_index; base=2; /*The empty location is reserver for parity bit.*/ if(hd_index>=1) offset++; if(hd_index>=2) offset++; if(hd_index>=6 Offset++; } if(0==strcmp(argv[1],LocateCmd)∥0==strcmp(argv[1],UnFreezeCmd)) { //gsxOut0=0x02<<hd_index; base=4; /*The empty Location is reserver for parity bit.*/ if(hd_index>=2) offset++; if(hd_index>=5) offset++; } if(0==strcmp(argv[1],UnFreezeCmd)) gsxOut0 &=~(1< <(hd_index * 2+base+offset));//unfreeze action need to clear the locate bit of corresponding hard disk. Else gsxOut0 |=1<<(hd_index * 2+base+offset);//move the locate bit to the correct location.

After placing the valid data bits in the correct position, the code for generating the verification data is as follows: for(i=0;i<MaxParityIndex;i++) { counter=0; parityBit=0; dataPower=(0x1<<i)-1; gsxOut0 &=~(0x1<<dataPower);//Clear the parity bit. for(j=dataPower;j<TotalBitsNumber;j++) { parityBit+=((gsxOut0>>j)&0x1);counter++; if(counter= =(0x1<<i)) { j+=counter; counter=0; } } gsxOut0 |=((parityBit &0x1)<<dataPower);//even parity check,save the parity bit to corresponding locateion. gsxOut1=(gsxOut0>>24); gsxOut0=(gsxOut0<<8)|(value_olvl1 &0x000000FF); Since the data bit plus check digit needs to be vacated by the lower 8 bits used by the BIOS, the sum of the transmitted data will be The 32 bits of the output register 0 of GSX overflow. /*BIOS set the default value to 0xFFFFFFFF, and we need to clean this value when the value is 0xFFFFFFFF to 0x000000FF. * And we need to keep the Locate LED data when system not reset.*/ if(value_olvl1==0xFFFFFFFF) gsxOut0 =(value_olvl1 &0x000000FF)>>8; else gsxOut0=(value_olvl1>>8)|(value_olvl2<<24); Finally, the calculated data is written back to the output level register of GSX, also because the data is output from GSX The scratchpad 0 overflows, so the overflow data is stored in the GSX output register 1. *((unsigned int *)addr_olvl1)=gsxOut0; *((unsigned int *)addr_olvl2)=gsxOut1; and the serial number process is turned on. addr_CMD=gsx_base+0x40; *((unsigned int *)addr_CMD)=1; For the hardware reset call, after the data is sent, the original data needs to be reset, because the reset operation is only one-time and does not need to be maintained. If(0==strcmp(argv[1],ResetCmd))//the reset command need to clean the reset bit after transfer. { *((unsigned int *)addr_olvl1)=value_olvl1;//zwg 2015-07-24 The locate action *((unsigned int *)addr_olvl2)=value_olvl2; } Finally terminates the transmission *((unsigned int *)addr_CMD)=0; completes the operation.

Referring to the fourth figure, the control system of the PCIE hard disk status light of the present invention comprises a determination module 1, a first transmission module 2, a second transmission module 3 and a control module 4.

The judging module 1 is configured to judge the current working mode of the PCIE hard disk. Among them, the working mode of the PCIE hard disk includes a hard disk reset mode and a hard disk positioning mode. Compared with the prior art, the present invention increases the hard disk reset mode, so that the use state of the PCIE hard disk can be judged in time according to the display of the status light.

The first sending module 2 is connected to the determining module 1 and configured to send the current working mode information to the PCH by the CPU. Wherein, when the current working mode information is sent to the PCH, the output level register corresponding to the GPIO Serial eXpander (GSX) of the south bridge chip is modified from the system side to record the current working mode information. . The output level register occupies a total of 64 bits, wherein the lower 8 bits are occupied by the BIOS, and the two bits of the remaining 56 bits except the lower 8 bits occupied by the BIOS are represented by the 64 bits. A working mode of a hard drive. Among them, the high bit indicates the hard disk positioning mode, and the low bit indicates the hard disk reset mode.

The second sending module 3 is connected to the first sending module 2 for transmitting the current working mode information to the complex programmable logic controller by the PCH. The second sending module 3 sends the current working mode information by the following steps:

31) Perform Hamming check on the current working mode information to generate Hamming check code data. Among them, Hamming code can correct one-bit error, detect two-element error, and reduce the bit error rate in transmission. By using Hamming check, it is possible to ensure that the current working mode information can be accurately performed. Transmission to ensure accurate display of LED status lights.

32) Send the generated Hamming check code data to the CPLD.

The control module 4 is connected to the second sending module 3, and is configured to control the display of the status light corresponding to the current working mode by the complex programmable logic controller according to the current working mode information. Specifically, the CPLD parses the received data, obtains the current working mode information, and outputs a signal to the corresponding LED status light to control the display of the corresponding LED status light. In summary, the control method and system CPU of the PCIE hard disk status lamp of the present invention controls the CPLD by the south bridge chip, thereby realizing the display control of the status light corresponding to the reset and positioning operation of the PCIE hard disk; therefore, Timely judge the use status of the PCIE hard disk. At the same time, by performing Hamming check on the current working mode information, the accurate display of the status light can be further ensured. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

The above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Modifications or variations of the above-described embodiments may be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and scope of the invention will be covered by the appended claims.

Claims (8)

A method for controlling a standard peripheral hard disk status light, comprising the steps of: determining a current working mode of a Peripheral Component Interconnect Express (PCIE) hard disk; and utilizing a central processing unit (Central Processing Unit; The CPU transmits the current working mode information to a south bridge chip; the south bridge chip performs a Hamming Check on the current working mode information to generate a Hamming Check Code data. And generating the generated Hamming check coded data to a complex programmable logic controller; and according to the current working mode information, the complex programmable logic controller controls the status light corresponding to the current working mode Display. The method for controlling a PCIE hard disk status light according to claim 1, wherein the working mode of the PCIE hard disk comprises a hard disk reset mode and a hard disk positioning mode. The method for controlling a PCIE hard disk status lamp according to claim 1, wherein the current working mode information is sent to the south bridge chip by a GPIO serial port expander of the south bridge chip. The level register is output to record the current operating mode information. The method for controlling a PCIE hard disk status lamp according to claim 3, wherein the output level register occupies a total of 64 bits, and the lower 8 bits are input by a basic input. The system (Basic Input/Output System; BIOS) occupies the work of the PCIE hard disk by using two bits of the remaining 56 bits except the lower 8-bit occupied by the BIOS. mode. A control system for a fast peripheral interconnect standard hard disk status light, comprising: a judgment module for determining a current working mode of a Peripheral Component Interconnect Express (PCIE) hard disk; a first transmit mode a group, connected to the determining module, configured to send the current working mode information to a south bridge chip through a central processing unit (CPU); a second sending module, and the first sending The modules are connected to perform a Hamming Check on the current working mode information by the south bridge chip, generate a Hamming Check Code data, and generate the sea The clear check code data is sent to a complex programmable logic controller; and a control module is connected to the second sending module, configured to be controlled by the complex programmable logic according to the current working mode information The device controls display of the status light corresponding to the current working mode. The control system of the PCIE hard disk status light according to claim 5, wherein the working mode of the PCIE hard disk comprises a hard disk reset mode and a hard disk positioning mode. The control system of the PCIE hard disk status lamp of claim 5, wherein the first transmitting module transmits the current working mode information to the south bridge wafer by using the south bridge wafer The output level register corresponding to the GPIO serial port expander records the current working mode information. The control system of the PCIE hard disk status lamp according to claim 7, wherein the output level register occupies 64 bits, and the lower 8 bits are occupied by the BIOS, and the 64 bits are used. Two of the 56 bits remaining in the remaining 56 bits other than the low 8-bit occupied by the BIOS represent the operating mode of the PCIE hard disk.