WO2022252987A1 - Method and apparatus for testing memory chip - Google Patents

Abstract

The present application relates to the technical field of chips. Disclosed are a method and apparatus for testing a memory chip, which method and apparatus are used for improving the reliability of a determined value of an initialization parameter. The method comprises: testing a value of an initialization parameter of a memory chip by using a first binary sequence and a second binary sequence, wherein the second binary sequence has H forward jumps relative to the first binary sequence and I backward jumps relative to the first binary sequence, one of N data signal lines of the memory chip transmits the first binary sequence, and at least one of the other (N-1) data signal lines transmits the second binary sequence, and H and I are integers greater than or equal to 1; determining a reference value of the initialization parameter according to a value range of the initialization parameter that is obtained by means of testing; and performing data transmission with the memory chip according to the reference value.

Description

Method and device for testing a memory chip

Cross References to Related Applications

This application claims the priority of the Chinese patent application submitted to the China Patent Office on May 31, 2021, with the application number 202110601640.8 and the application name "A Method and Device for Testing Memory Chips", the entire contents of which are incorporated herein by reference. Applying.

technical field

The embodiments of the present application relate to the field of chip technology, and in particular, to a method and device for testing a memory chip.

Background technique

Most of the current electronic devices are integrated with processors and memory chips. Wherein, the memory chip is the basis for the processor to perform calculations, and is used to temporarily store calculation data in the processor. The memory chip needs to go through the initialization process after the electronic device is turned on. The memory chip is first tested to obtain the best reference value of the initialization parameters of the memory chip before normal high-speed data transmission can be performed. For example: after obtaining the reference value for judging whether the level of the data signal transmitted between the processor and the memory chip is high or low, thereby judging whether the transmitted data signal carries a reference level of "1" or "0", In order to perform normal high-speed data transmission.

The binary sequence selected during the test directly affects the result of the obtained reference value of the initialization parameter. The more the selected binary sequence can stimulate the crosstalk (crosstalk) and intersymbol interference (inter symbol interference, ISI) of the data signal, the more appropriate the result will be. At the same time, the shorter the binary sequence selected, the shorter the time to test the memory chip, and the more user-friendly the boot experience. Among them, two binary sequences are used in the test process of the memory chip, one binary sequence is used as the victim line pattern, the other binary sequence is used as the offending line pattern, and one of the N data signal lines of the memory chip is a data signal line The data signal carrying the pattern of the victim line is transmitted, and the other N-1 data signal lines transmit the data signal carrying the pattern of the offending line. ISI is mainly determined by the pattern of the victim line, and crosstalk is mainly determined by the pattern of the offending line around the pattern of the victim line. Decide. But simple binary sequences (such as 0101, 0011, etc.) cannot effectively stimulate the ISI and crosstalk of the data signal.

In order to stimulate the ISI and crosstalk of the data signal, the pseudorandom binary sequence (PRBS) has been widely used in the testing process of the memory chip, one PRBS is used as the victim line pattern, and the other PRBS is used as the violation line pattern, PRBS The characteristic is that PRBS with an order of N can traverse 2 ^N -1 kinds of coding combinations, and the longest N consecutive 1s and N-1 consecutive 0s can appear. Each frequency component is very rich, which can effectively stimulate the data signal. ISI and crosstalk. However, using two different PRBS, one PRBS as the victim line pattern and the other PRBS as the offending line pattern, does not stimulate the crosstalk of the data signal very well, which will affect the reliability of the obtained reference value of the initialization parameters. sex.

Contents of the invention

Embodiments of the present application provide a memory chip testing method and device, which are used to improve the reliability of reference values of determined initialization parameters.

In the first aspect, the embodiment of the present application provides a method for testing a memory chip, which can be performed by electronic devices such as smart phones, tablet computers, smart cameras, self-driving vehicles, and personal computers. The method includes: using the first binary The sequence and the second binary sequence test the value of the initialization parameter of the memory chip, wherein the second binary sequence has H jumps in the same direction and I with respect to the first binary sequence With respect to the reverse jump of the first binary sequence, one of the N data signal lines of the memory chip transmits the first binary sequence, and one of the other N-1 data signal lines At least one data signal line transmits the second binary sequence, the N is an integer greater than or equal to 2, the H and the I are integers greater than or equal to 1; the initialization parameters obtained according to the test The value range is to determine the reference value of the initialization parameter; perform data transmission with the memory chip according to the reference value. That is to say, one or more of the N data signal lines of the memory chip transmits the first binary sequence, and among the N data signal lines, except for the data signal line used to transmit the first binary sequence One or more of the remaining data signal lines transmit the second binary sequence. Two or more data signal lines among the N data signal lines of the memory chip, at least one of which is used to transmit the first binary sequence, and at least one of the remaining data signal lines is used to transmit the second binary sequence sequence.

In the embodiment of this application, the jump is the conversion of two adjacent bits in a binary sequence, such as the change of the values of two adjacent bits (such as the first bit and the second bit) in a binary sequence from 0 to 1 Or change from 1 to 0. The comparison of the same direction jump and the reverse jump is whether the direction of the two jumps from the same bit position in the first binary sequence and the second binary sequence is the same direction or the reverse direction, and the same direction refers to this Both jumps are from 1 to 0 or both are from 0 to 1. Reverse means that one of the two jumps changes from 0 to 1, and the other jumps from 0 to 1. 1 to 0 variation.

Due to the coupling effect between data signals, a level change on one data signal will cause a similar level change on another data signal, which will bring crosstalk to another data signal and affect the transmission of another data signal. In the embodiment of the present application, when testing the memory chip, since the second binary sequence has rich transitions in the same direction and reverse transitions compared with the first binary sequence, the carrying capacity transmitted in the data signal line Compared with the data signal carrying the first binary sequence transmitted in the data signal line, the data signal of the second binary sequence has the same level change in the same direction at multiple transmission moments (for example, the data signals at a certain transmission moment are all changed by High level (carrying "1") changes to low level (carrying "0")), and the same reverse level change at multiple transmission moments (such as a data signal at a certain transmission moment is high level (carrying "0")) 1") changes to low level (carrying "0"), another data signal is low level (carrying "0") and changes to high level (carrying "1")), which will give the second binary signal The data signal of the sequence brings the interference of the same direction level change and the reverse level change, and then brings strong crosstalk to the data signal carrying the second binary sequence, thereby improving the reference value of the determined initialization parameter. reliability.

In a possible design, the initialization parameters include one or more of a reference level, a data strobe signal (data strobe signal, DQS) phase adjustment amplitude, and the like.

Wherein, the reference level is the level at which the memory chip or the processor recognizes the state of the data signal level during data transmission. Specifically, when identifying the level state of the data signal, if the level of the data signal is greater than or equal to the reference level level, it is high level, the level of the data signal is lower than the reference level, then the level of the data signal is low level; DQS phase adjustment range indicates the transmission delay of DQS, and DQS is the trigger data transmission process The memory chip or processor recognizes the signal of the data signal level state. By changing the value of the DQS phase adjustment range, the moment when DQS triggers the memory chip or processor to recognize the data signal level state can be adjusted.

In a possible design, the first binary sequence is a pseudo-random binary sequence with a variable marking ratio.

The more random the level of the data signal, the stronger the interference between the various levels of the data signal, the stronger the inter-symbol interference received by the data signal, and the variable mark ratio pseudo-random binary sequence is pseudo-random in the immutable mark ratio The AND operation based on the binary sequence is more random than the immutable tag ratio pseudo-random binary sequence, and the number of consecutive bits with the same value "0 or 1" that can appear in the sequence is more. In the above design, the pseudo-random binary sequence with variable marking ratio is used as the first binary sequence, which can make the level of the data signal carrying the first binary sequence (the high level carrying "1" and the high level carrying "0") Low level) is more random, which brings stronger inter-symbol interference, thereby improving the reliability of the reference value of the determined initialization parameter. At the same time, the length of the first binary sequence can also be shortened while ensuring the reliability of the reference value of the determined initialization parameter, thereby improving the testing efficiency of the memory chip and improving the user's booting experience.

In a possible design, the second binary sequence is determined by performing reverse processing on one or more jumps in the first binary sequence to determine the second binary sequence sequence.

In the above design, one or more jumps in the first binary sequence can be reversed, such as converting two adjacent 10s in the first binary sequence to 01, or converting two adjacent The bit 01 is transformed into 10, and the second binary sequence is quickly obtained, which is beneficial to improving the test efficiency of the memory chip.

In a possible design, the second binary sequence is determined in the following manner: the first binary sequence is divided in units of M bits, and in the first binary sequence Determine a plurality of coding units, wherein there is no repeated bit between any two coding units in the plurality of coding units, and the M is an integer greater than or equal to 2; the target coding combination carried in the plurality of coding units The coding unit of is marked as the target coding unit, wherein the target coding combination is one or more of the 2 ^M coding combinations corresponding to the coding unit; the target coding unit in the first binary sequence is The transition is reversed to determine the second binary sequence.

In the above design, each M bit in the first binary sequence can be used as the coding unit for coding, and one or more of the 2 ^M coding combinations corresponding to the coding unit can be used as the target coding combination, and the target coding The jumps in the combined target coding unit are reversely processed to determine the second binary sequence, and quickly obtain the second binary sequence, which is beneficial to improving the test efficiency of the memory chip.

In a possible design, half of the 2 ^M coding combinations are the target coding combinations.

In the above design, half of the 2 ^M coding combinations are used as the target coding combination, which is conducive to balancing the number of forward jumps and reverse jumps of the second binary sequence relative to the first binary sequence, Fully stimulate the crosstalk brought by the jumps in the same direction and the reverse direction to the data signal carrying the first binary sequence, and improve the reliability of the reference value of the determined initialization parameter.

In the second aspect, the embodiment of the present application provides a device for initializing a memory chip. The device has the function of realizing the above-mentioned first aspect or any possible design method of the first aspect. The function can be realized by hardware, or A corresponding software implementation may be performed by hardware. The hardware or software includes one or more units (modules) corresponding to the above functions, such as an initialization test unit, a determination unit and a transmission unit.

In a third aspect, an embodiment of the present application provides an electronic device, the electronic device includes a processor, a memory, and a memory chip, and when the processor executes the computer program stored in the memory, the memory chip executes the above-mentioned first The method described in one aspect or any possible design of the first aspect.

In a fourth aspect, an embodiment of the present application provides a chip system, the chip system includes: a processor and an interface, the processor is used to call and execute a computer program from the interface, when the processor executes the computer program , the method described in the first aspect or any possible design of the first aspect may be implemented.

In the fifth aspect, the embodiment of the present application provides a computer-readable storage medium, the computer-readable storage medium has a computer for executing the method described in the above-mentioned first aspect or any possible design of the first aspect program.

In the sixth aspect, the embodiment of the present application also provides a computer program product, including a computer program, when the computer program is executed, it can realize the above-mentioned first aspect or any possible design of the first aspect. method.

Please refer to the technical effects achieved by the first aspect above for the technical effects achieved by the second aspect to the sixth aspect above, and will not be repeated here.

Description of drawings

FIG. 1 is a schematic diagram of the connection between a processor and a memory chip in an electronic device provided by an embodiment of the present application;

Fig. 2 is the DQ schematic diagram that the embodiment of the present application provides;

FIG. 3 is one of the relative timing diagrams of DQ and DQS provided by the embodiment of the present application;

FIG. 4 is the second schematic diagram of the relative timing of DQ and DQS provided by the embodiment of the present application;

Figure 5 is a conceptual diagram of the automatic rotation victim-aggressor pattern provided by the embodiment of the present application;

Fig. 6 provides the schematic diagram of memory chip test pattern excitation mode for the embodiment of the present application;

FIG. 7 is one of the schematic structural diagrams of electronic equipment provided by the embodiment of the present application;

Fig. 8 is the second schematic diagram of the structure of the electronic device provided by the embodiment of the present application;

FIG. 9 is a schematic diagram of a test method for a memory chip provided in an embodiment of the present application;

FIG. 10 is a schematic diagram of the level change of DQ interference provided by the embodiment of the present application;

FIG. 11 is a schematic diagram of the first binary sequence and the second binary sequence provided by the embodiment of the present application;

FIG. 12 is a schematic diagram of transition processing in a coding unit provided by an embodiment of the present application;

Fig. 13 is the schematic diagram that produces PRBS 7 that the embodiment of the present application provides;

FIG. 14 is a schematic diagram of generating a VMRQ-PRBS provided by an embodiment of the present application;

FIG. 15 is a schematic diagram of determining the value range of the DQS phase adjustment amplitude provided by the embodiment of the present application;

FIG. 16 is a schematic diagram of the memory training algorithm provided by the embodiment of the present application;

Figure 17 is one of the schematic diagrams of the simulation results provided by the embodiment of the present application;

Figure 18 is the second schematic diagram of the simulation results provided by the embodiment of the present application;

Figure 19 is the third schematic diagram of the simulation results provided by the embodiment of the present application;

FIG. 20 is a schematic diagram of an initialization device for a memory chip provided by an embodiment of the present application.

Detailed ways

In current electronic devices (such as smartphones, tablet computers, smart cameras, self-driving vehicles, personal computers (PCs), etc.), most of them are integrated with processors and memory chips. Wherein, the memory chip is the basis for the processor to perform calculations, and is used to temporarily store calculation data in the processor. The processor and the memory chip can be connected through a memory bus. Wherein, the memory bus may include data signal lines and timing signal lines. The data signal line can transmit the data signal (data signal), and DQ is used to represent the data signal in this application, wherein, DQ is a double data rate synchronous dynamic random access memory (DDR SDRAM) protocol, also known as DDR protocol, the abbreviation of the data signal defined in it, and the timing signal line can transmit the data strobe signal (data strobe signal). In this application, DQS is used to represent the data strobe signal. Among them, DQS is defined in the DDR protocol The abbreviation of the data strobe pulse signal, DQ and DQS are both periodic signals, and the two generally have the same cycle length.

As shown in Figure 1, it is a schematic diagram of the connection between the processor and the memory chip in an electronic device provided by the embodiment of the present application through a memory bus, wherein the memory bus may include N data signal lines and M timing signal lines, N , M is an integer greater than or equal to 2. In the embodiment of the present application, the memory bus includes a total of 8 data signal lines from data signal line DQ0 to data signal line DQ7, and a total of 2 timing signal lines from timing signal line DQS0 to timing signal line DQS1 Take this as an example.

Before introducing the embodiments of the present application, some terms involved in the embodiments of the present application are firstly explained, so as to facilitate the understanding of those skilled in the art.

1) Jumping. In the embodiment of the present application, jumping refers to the change of two adjacent bit values in a binary sequence, such as the change of two adjacent bit values from 0 to 1 or from 1 to 0. Among them, the comparison of the same direction jump and the reverse jump is whether the direction of the two jumps from the same bit position in the two binary sequences is the same direction or the same direction, and the same direction means that the two jumps are from 0 to The change of 1 or both changes from 1 to 0, and the reverse means that one of the two jumps changes from 0 to 1, and the other jump changes from 1 to 0. For example: the value of the 1st bit and the 2nd bit in the first binary sequence are "10", and the value of the 1st bit and the 2nd bit in the second binary sequence are "10", the transition between the first bit and the second bit in the first binary sequence "10" and the transition between the first bit and the second bit in the second binary sequence" 10" is jumping in the same direction. Another example: the value of the 5th bit and the 6th bit in the first binary sequence are "10", the value of the 5th bit and the 6th bit in the second binary sequence If it is "01", then the transition "10" between the 5th bit and the 6th bit in the first binary sequence and the transition between the 5th bit and the 6th bit in the second binary sequence "01" is the reverse jump. In addition, in a data signal carrying a binary sequence, usually the high level of the data signal carries "1", and the low level carries "0". Jumping can also refer to the high-low change (or conversion) of the level (that is, voltage) in the data signal, including changing from high level (carrying "1") to low level (carrying "0"), and changing from low level to low level (carrying "0"). Low level (carrying "0") changes to high level (carrying "1").

2), inter symbol interference (inter symbol interference, ISI), refers to the interference of the same signal due to the overlapping of multipath propagation at the receiving end, and can also be called inter symbol interference. Usually caused by signal transmission multipath and fading and distortion.

3) Crosstalk, crosstalk is noise caused by coupling between two data signal lines, mutual inductance and mutual capacitance between data signal lines. It is an undesired amount of energy produced by the coupling of one data signal to another data signal, which can lead to data loss and transmission errors.

4) The pressure of the binary sequence can also be called the pattern pressure. In the embodiment of the present application, the pressure of the binary sequence can be understood as when the memory chip is tested using the binary sequence, the binary sequence stimulates the transmission between the processor and the memory chip. The ability of crosstalk and/or intersymbol interference of the data signal, the greater the pressure of the binary sequence, the stronger the ability to stimulate crosstalk and/or intersymbol interference. Among them, the ability to stimulate inter-symbol interference is mainly related to the maximum length of contiguous identical digits (CID) that can appear in the binary sequence carried by the data signal, that is, the maximum number of continuous 1s and 0s that can appear. The longer the CID length, the stronger the ability to stimulate inter-symbol interference; the ability to stimulate crosstalk is mainly related to the number of forward transitions and reverse transitions between binary sequences carried between adjacent data signals. The more the number of forward transitions and reverse transitions, the more interference between data signals, and the stronger the ability to stimulate crosstalk.

The processor in the electronic device can not only read data from the memory chip, but also write data to the memory chip. Taking the processor writing data to the memory chip as an example, as shown in Figure 1, the processor can pass the data signal line DQ0 -The data signal line DQ7 sends DQ to the memory chip, and sends DQS to the memory chip through the timing signal line DQS0 and timing signal line DQS1, where DQ can carry the data that the processor wants to write into the memory chip, and DQS can trigger the memory chip to identify the above DQ level state, and then the data carried in DQ can be written into the memory chip.

Specifically, the data signal line DQ0-data signal line DQ7 can transmit 8 DQs in parallel. For example, the data signal line DQ0 can transmit DQ0, the data signal line DQ1 can transmit DQ1, . . . , and the data signal line DQ7 can transmit DQ7. The timing signal line DQS0 can transmit DQS0, and the timing signal line DQS1 can transmit DQS1. Among them, DQ0-DQ7 can be periodic signals, and different data can be carried by controlling the level in the cycle, so as to realize data transmission. As shown in Figure 2, DQ (can be any DQ in DQ0-DQ7) can transmit 1 bit (bit) data in one cycle, and if DQ is high level in one cycle, it can transmit 1 bit data "1" , if DQ is low level in one cycle, 1 bit data "0" can be transmitted. As an example, the levels of the DQ carrying 1010001 are high, low, high, low, low, low, high in sequence during the 7 cycles of transmitting 1010001, and are used to transmit 7-bit data "1010001".

DQS (can be any DQS in DQS0-DQS1) is usually a data strobe signal with the same period length as DQ, which is used to trigger the memory chip to identify the level state of DQ, and then write the data carried in DQ memory chips. As shown in Figure 3, the timing signal line DQS0 can transmit DQS0, and the timing signal line DQS1 can transmit DQS1, wherein DQS0 and DQS1 are anti-phase signals (that is, in the same cycle, one of DQS0 and DQS1 is high level, and the other is Low level), the intersection point between DQS0 and DQS1 (that is, the point where the levels of DQS0 and DQS1 are equal) can be used as a trigger point to trigger the memory chip to recognize the level state of DQ. That is to say, when the memory chip determines that the received DQS0 and DQS1 are at the intersection point, that is, at the moment when the levels of DQS0 and DQS1 are equal, the memory chip can identify the current level state of DQ, so that the data carried by DQ can be Writing into the memory chip, for the convenience of expression, DQS is used to refer to DQS0 and DQS1 in the embodiment of the present application.

In addition, during data transmission, the memory chip identifies whether the level state of DQ is high or low relative to the reference level, where the reference level is configured by the processor and can be used to identify the level of DQ status level. Wherein, if at the trigger point of identifying the level state of DQ, the level of DQ is greater than or equal to the reference level, then the memory chip determines that the level of DQ is a high level; if at the trigger point of identifying the level state of DQ, If the level of DQ is lower than the reference level, the memory chip determines that the level of DQ is a low level. As shown in Figure 4, whether the memory identification can accurately identify the level state of DQ is closely related to the relative timing (relative time delay) between DQS and DQ and the value of the reference level. The value of the reference level is unreasonable and/or the relative timing setting between DQS and DQ is unreasonable, which will cause the memory chip to misidentify the high level of DQ as a low level at the trigger point of identifying the level state of DQ. Cause the memory chip to misjudge the "1" carried by DQ as "0"; of course, it may also cause the memory chip to misidentify the low level of DQ as a high level at the trigger point of identifying the level state of DQ, causing the memory chip to The "0" carried by the DQ is misjudged as "1". The relative delay between DQS and DQ can be adjusted by the DQS phase adjustment range (that is, the transmission delay of DQS). By adjusting the DQS phase adjustment range, the timing (that is, delay) of DQS relative to DQ can be changed.

Therefore, after the electronic device is started, the processor usually needs to test the memory chip, such as performing a write (write)/read (read) test, to obtain the best initialization parameters (such as DQS phase adjustment range and/or reference voltage) High-speed data transmission with the memory chip can only be performed after the value is referenced. During the test, the value of the initialization parameter is usually constantly adjusted to test whether the data signal in the data signal line can be accurately transmitted under different values, and then determine the value range of the initialization parameter that can enable the accurate transmission of the data signal, and According to the value range of the initialization parameter, an optimal value is selected from the value range of the initialization parameter as a reference value for data transmission between the processor and the memory chip.

At present, the write/read test of the memory chip mainly includes the following schemes:

Scheme 1: victim (victim)-aggressor (aggressor) algorithm, victim-aggressor algorithm has two main features: (1) using two different pseudo-random binary sequences (pseudo-random binary sequence, PRBS), a PRBS As the victim line pattern used by the victim, one PRBS is used as the aggressor's aggressor line pattern, and the two PRBS are completely random. (2) Provide victim-aggressor mode (pattern) automatic rotation function, multiple data signal lines switch between victim and aggressor roles in turn. As shown in Figure 5, it includes 17 parallel data signal lines. Each square represents the role of the data signal line, such as the role of victim or the role of aggressor. The role of different data signal lines will change over time, such as data signal Line 1 will take on the role of aggressor, aggressor, aggressor and victim in turn as time changes. Specifically, when performing a read/write test on the memory chip, the data signal line to be tested between the processor and the memory chip acts as a victim to transmit the data signal carrying the pattern of the victim line, and the other data signal lines act as the role of the aggressor to transmit the pattern of the pattern of the victim line. The data signal, trying to introduce stronger ISI and crosstalk. However, the existing victim-aggressor algorithm uses two completely random PRBSs for the victim line pattern and the aggressor line pattern, which cannot bring sufficient crosstalk to the data signal carrying the victim line pattern.

Scheme 2: Scheme 2 is similar to the above scheme, the difference is that scheme 2 adopts two PRBS15 (that is, PRBS with an order of 15) as the victim line pattern and the offending line pattern respectively, and the PRBS15 adopted by the offending line pattern is The first PRBS15 and the PRBS15 adopted by the code pattern of the victim line is the second PRBS15 as an example. Wherein the first PRBS15 can adopt a completely random PRBS15, and the second PRBS15 is the first PRBS15 that is reversed, wherein the negative of the first PRBS15 refers to the negative of the value "1" or "0" of the bit in the first PRBS15, wherein "1" and "0" are mutually opposite values. Taking the first PRBS 15 as "010...10" as an example, the inverted first PRBS 15 is "101...01".

Taking 8 data signal lines (data signal line DQ0-data signal line DQ7) between the processor and the memory chip of the electronic device as an example, as shown in Figure 6, each rectangle represents a data signal transmission of the data signal line, The rectangle filled with black represents the data signal carrying the first PRBS15, and the rectangle without black filling represents the data signal carrying the second PRBS15. Specifically, when the memory chip is read/written, the tested data signal line between the processor and the memory chip transmits the data signal carrying the second PRB15, and other data signal lines transmit the data signal carrying the first PRB15 (such as the second group) -Example of group 9), it is also possible to additionally test whether the data signals in the data signal lines can be transmitted accurately by allowing the 8 data signal lines to transmit the data signals carrying the first PRB15. However, this solution directly adopts two completely opposite PRBS15, which cannot guarantee sufficient crosstalk to the data signal carrying the victim line pattern (i.e. the second PRBS15), and the length of the PRBS15 is longer, and the test efficiency of the memory chip is relatively low. If it is low, it will lead to a longer boot time and affect the user's boot experience.

The present application aims to provide a test scheme of a memory chip, by adopting H jumps in the same direction with respect to the first binary sequence and having I jumps in the opposite direction with respect to the first binary sequence The second binary sequence utilizes the characteristics that the second binary sequence has rich transitions in the same direction and reverse transitions compared with the first binary sequence, and fully stimulates the second transmission of at least one data signal line of the memory chip. Binary sequence (that is, the transmitted data signal carrying the second binary sequence), and the first binary sequence transmitted in a certain data signal line of the memory chip (that is, the transmitted data signal carrying the first binary sequence) The crosstalk brought by the data signal), thereby improving the reliability of the reference value of the determined initialization parameter.

FIG. 7 is a schematic structural diagram of an electronic device provided by an embodiment of the present application. FIG. 7 is obtained by logically dividing the electronic device shown in FIG. 1 according to software layers and hardware layers. The electronic device in Fig. 7 may include a hardware layer and a software layer, wherein the software layer may include one or more application programs and an operating system, the hardware layer may include a processor, a memory chip, and a memory, and the operating system is used to manage hardware and software The system software of resources, the processor and the memory chip in FIG. 7 may be the processor and the memory chip in FIG. 1 .

The processor is the control center of the electronic device. It uses various interfaces and buses to connect various components of the electronic device, such as connecting to the memory chip through the memory bus. The specific connection between the processor and the memory chip through the memory bus can be referred to in Figure 1. Let me repeat. In some embodiments, a processor may include one or more processing units, or referred to as physical cores, for example, the processor in FIG. 7 includes core 0 and core 1 . The processor may also include registers, which may be used to store reference values of initialization parameters of the memory chip and the like. The processor can be a central processing unit (central processing unit, CPU), and the processor can also be other general-purpose processors, digital signal processors (digital signal processors, DSP), application specific integrated circuits (application specific integrated circuits, ASICs), Off-the-shelf programmable gate array (field-programmable gate array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor, or the processor may be any conventional processor, or the like.

The memory chip (also called memory) can be DDR SDRAM, such as the 4th generation DDR (4th DDR, DDR4) SDRAM, the 5th generation DDR (5th DDR, DDR5) SDRAM, etc. Dynamic random access memory (low power double data rate SDRAM, LPDDR), etc., can be used to temporarily store computing data in the processor. In addition, the memory chip may further include registers, which may be used to store reference values of initialization parameters of the memory chip and the like.

The memory may store an operating system and an application program, and may also store data generated by the operating system and the application program during operation.

As shown in FIG. 7 , the electronic device may further include firmware (firmware). Since firmware is a kind of software embedded in hardware, including computer instructions, it can be divided into software layers according to logical division. The basic input/output system (BIOS) is a common piece of firmware that performs hardware initialization during the power-on boot phase and provides runtime services for the operating system. In the embodiment of the present application, the BIOS of the electronic device can be used to execute the computer instructions of the memory chip test method. After the electronic device is turned on, the BIOS executes the memory chip test method to test the memory chip. After the test is completed, Write the obtained reference value of the initialization parameter into the register of the processor and/or the register of the memory chip, according to the reference value of the initialization parameter in the register of the processor and/or the register of the memory chip, the processor and the memory chip High-speed data transmission can be realized, wherein the reference value of the initialization parameter obtained by the test of writing (the processor reads data from the memory chip) in the register of the processor, and writing (the processor reads the data from the memory chip) in the register of the memory chip. The reference value of the initialization parameter obtained from the memory chip write data) test.

The computer instructions in the BIOS can be stored on the motherboard of the electronic device, specifically can be stored in the read-only memory (read-only memory, ROM) chip on the motherboard, of course the BIOS can also be stored in the electronic device as shown in Figure 7. In the memory of the device, the memory includes but is not limited to flash memory (flash memory), hard disk, optical disk, universal serial bus (universal serial bus, USB) disk, etc. In an implementation manner, the memory and the memory chip may be the same storage medium, that is, the memory chip stores computer instructions for implementing the memory testing method. When the processor of the electronic device invokes the BIOS to perform hardware initialization, the computer instruction is invoked to execute the memory testing method provided by each embodiment of the present application to complete the memory chip test.

Taking the BIOS stored in the memory as an example, the schematic diagram of the physical structure of the electronic device may be as shown in Figure 8, including a memory, a processor, and a memory chip, and the processor, memory chip, and memory may be the processor, memory chip, and memory shown in Figure 7. Part and all of the implementation manner can refer to the corresponding description in FIG. 7 .

In addition, it should be understood that in this application, multiple" refers to two or more than two. "And/or" describes the association relationship of associated objects, indicating that there may be three relationships, for example, A and/or B , can mean: there is A alone, A and B exist at the same time, and B exists alone. In the text description of this application, the character "/" generally indicates that the associated objects are an "or" relationship. In addition, unless To the contrary, the embodiments of this application refer to ordinal numerals such as "first" and "second" to distinguish multiple objects, and are not used to limit the order, timing, priority or importance of multiple objects, and The description of "the first" and "the second" does not limit the objects to be different. The various numbers involved in the application are only for the convenience of description and are not used to limit the scope of the embodiments of the application. Above-mentioned The size of the sequence number of each process does not mean the sequence of execution, and the execution sequence of each process should be determined with its function and internal logic.In this application, words such as "exemplary" or "for example" are used to represent examples, To illustrate or illustrate, any embodiment or design described as "exemplary" or "for example" should not be construed as being preferred or more advantageous than other embodiments or designs. The use of "exemplary" or " Words such as "are intended to present related concepts in a specific manner for easy understanding. The embodiments of the present application will be described in detail below in conjunction with the accompanying drawings.

FIG. 9 is a schematic diagram of a method for testing a memory chip provided in an embodiment of the present application, the method comprising:

S901: The processor uses the first binary sequence and the second binary sequence to test the value of the initialization parameter of the memory chip.

Among the N data signal lines of the memory chip, one data signal line transmits the first binary sequence (that is, transmits the data signal carrying the first binary sequence), and one of the other N-1 data signal lines At least one data signal line transmits the second binary sequence (ie, transmits a data signal carrying the second binary sequence).

Whether the first binary sequence can be correctly written into the memory chip is related to the interference received by the data signal carrying the first binary sequence sent by the processor to the memory chip through the data signal line, as shown in Figure 10, the data When the signal is subject to crosstalk and/or intersymbol interference, the level of the data signal will change, which may cause the first binary sequence carried by the data signal to be incorrectly written into the memory chip. The crosstalk is mainly related to the forward jump and reverse jump between the binary sequences carried by adjacent data signals. In order to stimulate the crosstalk suffered by the data signal carrying the first binary sequence to a greater extent, in this application In an embodiment, when the memory chip is tested, the second binary sequence used has H jumps in the same direction relative to the first binary sequence and I reverse jumps relative to the first binary sequence jump, H and I are integers greater than or equal to 1; and one data signal line in the N data signal lines of the memory chip can transmit the first binary sequence, and the other N-1 data signal lines can all transmit the second binary sequence.

Among them, the comparison of the same direction jump and the reverse jump is whether the direction of the two jumps from the same bit position in the first binary sequence and the second binary sequence is the same direction or the same direction, and the same direction refers to These two jumps are both changes from 0 to 1 or both are changes from 1 to 0. The reverse means that one of the two jumps changes from 0 to 1, and the other jumps from 0 to 1. 1 to 0 variation. As shown in Figure 11, taking the first binary sequence as 101000111001010 and the second binary sequence as 011000110110010 as an example, the second binary sequence has 3 jumps in the same direction and 3 reverse transitions relative to the first binary sequence.

In the embodiment of the present application, the first binary sequence can adopt a completely random PRBS, such as a PRBS with a completely random order of 7, etc., where the PRBS with an order of 7 refers to the initial code (initial code) that generates PRBS 7 Composed of 0 and/or 1), the number of bits or the size is 7, that is, the PRBS is obtained by performing an exclusive OR operation on several initial codes and performing circular shift output. And the second binary sequence can be determined based on the first binary sequence. In some implementations, the processor can reverse process one or more transitions in the first binary sequence to determine the second binary sequence.

Taking the first binary sequence as 10111011001110000110 (only a part is shown) as an example, the processor may randomly select one or more transitions in the first binary sequence that do not have repeated bits between each other for reverse processing, Get the second binary sequence. For example: the processor can select "10" in the first bit and the second bit in the first binary sequence, "10" in the fifth bit and the sixth bit, and "10" in the first bit and the second bit There is no repeated bit between the corresponding transition "10" and the transition "10" corresponding to the 5th bit and the 6th bit, and the "10" of the first bit and the second bit is converted by the decoding circuit is "01", convert the "10" of the 5th bit and the 6th bit into "01", and realize the "10" and the 5th bit of the 1st bit and the 2nd bit in the first binary sequence The reverse processing of "10" of the 6th bit and the 6th bit obtains the second binary sequence "01110111001110000110 (only a part is shown)". The decoding circuit can be integrated in the processor, or it can be separately set in the electronic device and connected to the processor, which is not limited in this application.

As another example, the processor may also divide the first binary sequence in units of 2 bits to obtain multiple coding units with no repeated bits between any two coding units, such as obtaining 10, 11, 10, 11, 00, 11, 10, 00, 01, 10 and other coding units, and reverse the coding unit corresponding to a specific jump through the decoding circuit, such as encoding the corresponding jump "10" The unit is converted to "01". The second binary sequence "01 11 01 11 00 11 01 00 01 01 (only part shown)" obtained after being processed by the decoding circuit.

In some implementations, the processor may also divide the first binary sequence in units of M bits, and determine that there is no repeated bit multiple encoding between any two coding units in the first binary sequence unit, mark the coding unit carrying the target coding combination among the multiple coding units as the target coding unit, and perform reverse processing on the transition in the target coding unit in the first binary sequence, and then determine the second binary sequence . Wherein, M is an integer greater than or equal to 2.

Specifically, part of the 2 ^M coding combinations corresponding to the coding unit may be used as the target coding combination, or all of the 2 ^M coding combinations may be used as the target coding combination, which is not limited in this application. In addition, in order to ensure that the obtained second binary sequence has sufficient reverse jumps and forward jumps relative to the first binary sequence to achieve the best crosstalk effect, the 2 ^M coding combinations can be combined Half of the coding combinations are used as target coding combinations.

Taking M as 3 as an example, a coding unit including M bits corresponds to 8 coding combinations, which are 000, 001, 010, 011, 100, 101, 110, and 111, respectively. 100, 101, 110, 111 can be used as the target coding combination, the coding unit carrying 100, 101, 110, 111 can be marked as the target coding unit, and the transition in the target coding unit is reversely processed.

As an example, as shown in Figure 12, the processor can reversely process the transitions in the target coding units carrying 100, 101, 110, and 111 through the decoding circuit, and then the output of 100 after processing through the decoding circuit It can be 01X, 101, the output processed by the decoding circuit can be 010, 110, the output processed by the decoding circuit can be X01, and the output of 111 processed by the decoding circuit can be XXX, where X can be 0 or 1 . The processor can also maintain the jumps in the non-target coding units carrying 000, 001, 010, and 011 unchanged, then the output of 000 processed by the decoding circuit can be XXX, and the output of 001 processed by the decoding circuit can be The output of X01 and 010 processed by the decoding circuit can be 010, and the output of 011 processed by the decoding circuit can be 01X, where X can be 0 or 1.

In some implementations, the coding combination containing X can also be set as a high-frequency coding combination (such as 010, 101, 011, etc.), so as to increase the crosstalk capability of the determined second binary sequence to the first binary sequence. As shown in Figure 12, the decoding circuit can be set to output the input 000 as 010, the input 001 as 101, the input 010 as 010, the input 011 as 011, and the input 100 as 011. Output the input 101 as 010, output the input 110 as 001, and output the input 111 as 101.

It should be understood that the above is an example of the non-target coding units carrying 000, 001, 010, and 011 being processed by the decoding circuit. In some implementations, the non-target coding units carrying 000, 001, 010, and 011 The unit may not be processed by the decoding circuit, and the value of each bit in the non-target coding unit remains unchanged.

In addition, it should be understood that the first binary sequence may not be integrally divided by M, and some bits in the first binary sequence that cannot be integrally divided by M may not be processed. Still taking M as 3, the decoding circuit adopts the processing method shown in Figure 12 as an example, assuming that the first binary sequence is 101 110 110 011 100 001 10, then the obtained second binary sequence is 010 001 001 011 011 101 10, the last 2 bits of the second binary sequence are the same as the last 2 bits of the first binary sequence, and the last 2 bits of the first binary sequence are not corrected when determining the second binary sequence to process.

The ratio of the number of bits occupied by "0" and "1" in the PRBS is equal, that is, the number of bits with a value of 0 and the number of bits with a value of 1 in the PRBS are the same. As shown in Figure 13, it is a schematic diagram of generating PRBS 7 (that is, a PRBS with an order of 7). PRBS is generated by a linear feedback shift register (linear feedback shift register, LFSR), through a set of initial codes (for PRBS7, the initial code is 7 Bits, consisting of 0 and/or 1) are subjected to XOR operation and circularly shifted to output, and a pseudo-random binary sequence in which the ratio of the number of bits occupied by "0" and "1" is equal can be obtained.

In order to stimulate the inter-symbol interference suffered by the data signal carrying the first binary sequence to a greater extent, so that the obtained reference value of the initialization parameter is suitable for the real service transmission between the processor and the memory chip, in the embodiment of the present application , the first binary sequence can also use a variable mark ratio pseudo-random binary sequence (variable mark ratio quasi-PRBS, VMRQ-PRBS), that is, a 0/1 ratio variable pseudo-random binary sequence.

VMRQ-PRBS is a kind of PRBS with a variable ratio of the number of bits occupied by "0" and "1". It is generated by ANDing certain bits of PRBS on the basis of N-order PRBS. The common ratio is 1 /8, 1/4, 3/4, and 7/8. As shown in Figure 14, the AND operation is performed on the 2 bits in the PRBS output by the standard PRBS7 pattern generator (standard PRBS7 pattern generator), and the pseudo-random binary whose value is 1 and the number of bits occupied is 1/4 of the total number of PRBS bits can be obtained Sequence, that is, to obtain a VMRQ-PRBS with a proportion of 1/4; perform an AND operation on the 3 bits in the output PRBS, and obtain a pseudo-random binary sequence whose value is 1 and the number of bits is 1/8 of the total number of PRBS bits , that is, a VMRQ-PRBS with a ratio of 1 to 1/8 is obtained. Inverting the VMRQ-PRBS with 1 proportions of 1/4 and 1/8 can obtain the VMRQ-PRBS with 0 proportions of 1/4 and 1/8.

As shown in Table 1, it is 1/4 ratio (ratio) 1 bit displacement (bit shift) VMRQ-PRBS7 (that is, VMRQ-PRBS7 with a ratio of 1/4) and PRBS 7 The longest continuous 1 number and the most Long consecutive 0 count. The ability of the binary sequence to stimulate intersymbol interference is mainly related to the maximum CID length that can appear in the binary sequence. By using VMRQ-PRBS as the first binary sequence, it can effectively stimulate the interference received by the data signal carrying the first binary sequence. The inter-symbol interference makes the obtained reference value of the initialization parameter suitable for the real service transmission of the processor and the memory chip. It is also beneficial to shorten the length of the first binary sequence while ensuring the reliability of the obtained reference value of the initialization parameter, thereby improving the test efficiency of the memory chip.

model	Longest streak of 1	The longest consecutive number of 0
PRB7	7	6
1/4ratio1 bit shift VMRQ-PRBS7	12	12

Table 1

The following takes the write test of the memory chip using the first binary sequence and the second binary sequence as an example, and introduces how to use the first binary sequence and the second binary sequence to set the value of the initialization parameter of the memory chip carry out testing.

The processor can send DQ0 carrying the first binary sequence to the memory chip through the data signal line DQ0, send DQ1-DQ7 carrying the second binary sequence to the memory chip through the data signal line DQ1-data signal line DQ7, and pass The timing signal line DQS0 and the timing signal line DQS1 send DQS to the memory chip. As shown in A in Figure 15, under the default reference level and the default DQS phase adjustment range, that is, under the default reference level value and the default DQS phase adjustment range value, the processor gradually reduces the DQS The value of the phase adjustment amplitude is reached until the first binary sequence carried by DQ0 cannot be correctly written into the memory chip. At this time, the relative timing position between the trigger point for identifying the level state of DQ and DQ0 determined according to DQS may be as shown in B in FIG. 15 .

After the first binary sequence carried by DQ0 cannot be correctly written into the memory chip, the processor gradually increases the value of the DQS phase adjustment range until the first binary sequence carried by DQ0 cannot be correctly written into the memory again. chip. At this time, the relative timing position between the trigger point for identifying the level state of DQ and DQ0 determined according to DQS may be shown as C in FIG. 15 . Assuming that the value of the DQS phase adjustment range in B in Figure 15 is P1, and the value of the DQS phase adjustment range in C in Figure 15 is P2, the processor can obtain the value range of the DQS phase adjustment range from P1 to P2 .

Similarly, for the test of the reference level, under the default reference level and the default DQS phase adjustment range, the processor can gradually reduce the value of the reference level until the first binary sequence carried by DQ0 cannot be written correctly. memory chips. At this time, it is assumed that the value of the reference level is Q1.

After the first binary sequence carried by DQ0 cannot be correctly written into the memory chip, the processor gradually increases the value of the reference level until the first binary sequence carried by DQ0 cannot be correctly written into the memory chip again. . At this time, assuming that the value of the reference level is Q2, the processor obtains that the value range of the reference level is Q1 to Q2.

S902: The processor determines a reference value of the initialization parameter according to the value range of the initialization parameter obtained through testing.

In practical applications, affected by factors such as noise, the trigger point for identifying the DQ state determined by the memory chip based on DQS may deviate from the ideal trigger point for identifying the DQ state. For example, the trigger point for identifying the DQ state is earlier than the ideal trigger point or snooze. The DQ level recognized by the memory chip may also deviate from the ideal DQ level, for example, the DQ level recognized by the memory chip may be higher or lower than the DQ level sent by the processor.

In order to ensure that the reference value of the determined DQS phase adjustment range has more redundancy to deal with the influence of factors such as noise, in some embodiments, taking the value range of the DQS phase adjustment range from P1 to P2 as an example, then DQS The reference value of the phase adjustment range may be (P1+P2)/2, that is, the median of the value range of the DQS phase adjustment range, so as to have more redundancy to cope with the influence of factors such as noise.

In addition, if the processor also obtains the value ranges of multiple sets of DQS phase adjustment amplitudes based on the data signal line DQ1-data signal line DQ7 test, that is, multiple sets of P1 and P2, the processor can also use the data signal line DQ0-data signal line DQ7 The group P1 and P2 with the largest difference among the corresponding groups of P1 and P2 is used to determine the reference value of the DQS phase adjustment range.

In order to ensure that the reference value of the determined reference level has more redundancy to deal with the influence of factors such as noise, in some embodiments, taking the value range of the reference level as an example from Q1 to Q2, the reference level The reference value of can be (Q1+Q2)/2, that is, the median of the value range of the reference level.

In addition, if the processor also tests the value ranges of multiple sets of reference levels based on the data signal line DQ1-data signal line DQ7, that is, multiple sets of Q1 and Q2, the processor can also use the data signal line DQ0-data signal line DQ7 The group of Q1 and Q2 with the largest difference among the corresponding groups of Q1 and Q2 is used to determine the reference value of the reference level.

In some implementations, in order to improve the accuracy of the test of the memory chip, the processor can also first determine the reference value of the DQS phase adjustment range, and then base the reference value on the basis of the reference value of the DQS phase adjustment range and the default reference level. Test the value of the level to determine the value range of the reference level, and then determine the reference value of the reference level; or first determine the reference value of the reference level, and then adjust the amplitude and reference level in the default DQS phase The DQS phase adjustment range is tested on the basis of the reference value, so as to determine the value range of the DQS phase adjustment range, and then determine the reference value of the DQS phase adjustment range.

S903: The processor performs data transmission with the memory chip according to the reference value.

After obtaining the reference value of the DQS phase adjustment range and/or the reference value of the reference level by performing a write test on the memory chip, the processor writes the obtained reference value of the DQS phase adjustment range and/or the reference value of the reference level The memory chip can identify the level of the data signal sent by the processor based on the reference value of the DQS phase adjustment range and/or the reference value of the reference level stored in the register, and then identify the data signal The data carried by the processor enables the processor to write data to the memory chip.

The above mainly introduces how to determine the reference value of the DQS phase adjustment range and the reference value of the reference level from the aspect of writing the memory chip. When the memory chip is read and tested, the memory chip can pass the data signal. The line DQ0 to the data signal line DQ7 sends DQ to the processor, and sends DQS to the processor through the timing signal line DQS0 and the timing signal line DQS1, wherein the DQ can carry the data to be read by the processor. How to determine the reference value of the DQS phase adjustment range and the reference value of the reference level when performing a read test on a memory chip can refer to How to determine the reference value and reference value of the DQS phase adjustment range when performing a write test on a memory chip The realization of the reference value of the level will not be repeated here.

After obtaining the reference value of the DQS phase adjustment range and/or the reference value of the reference level by performing a read test on the memory chip, the processor will obtain the reference value of the DQS phase adjustment range and/or the reference value of the reference level The value is written into the register of the processor, and the processor can identify the level of the data signal sent by the memory chip based on the reference value of the DQS phase adjustment range and/or the reference value of the reference level stored in the register, and then identify The data carried by the data signal enables the processor to read data from the memory chip.

It should be understood that the memory chip testing method of the present application can be used in the training or testing scenarios of the memory chip. Binary sequence) to stimulate the DQ victim line eye diagram, and then use a certain algorithm to find the center point of the inner contour through the inner contour of the DQ victim line eye diagram, which is also the reference value of the initialization parameters of the memory chip. As shown in Figure 16, the first binary sequence (victimized line pattern) and the second binary sequence (violated line pattern) are used to test the memory chip by the memory chip training algorithm (such as the DDR training algorithm) as For example, it mainly includes using the default reference level (default-VREF) as a reference to find the left and right boundaries of the inner contour of the eye diagram of the DQ victim line (that is, the value range of the DQS phase adjustment range), and average the left and right boundaries to determine the DQS phase adjustment The reference value of the amplitude. Based on the reference value of the DQS phase adjustment range, find the upper and lower boundaries of the eye diagram of the DQ victim line (that is, the value range of the reference voltage), and average the upper and lower boundaries to determine the reference value of the reference voltage.

As shown in Table 2, for a group of 8 DQs, the victim line pattern (the first binary sequence) of this application adopts VMRQ-PRBS11 (that is, the VMRQ-PRBS whose order is 11), the above-mentioned first scheme and the first Two kinds of schemes all adopt PRBS15 (that is, the PRBS that the order is 15) as an example, wherein the pattern length required by the second scheme is 9*32767 bits; the pattern length required by this application is 8*4094 bits (requires 8 DQ transmits the victim line code pattern respectively); The code pattern length of the present application is 1/9 of the second scheme.

We use simulation analysis to verify the pressure of the code pattern. Taking the simulation of a 1-bit signal as an example, the simulation results are shown in Figure 17, Figure 18, and Figure 19 under different transmission rates. It can be seen that the code pattern length of the victim line in this application is short. However, the resulting intersymbol interference and crosstalk are the largest, and the reference value of the initialization parameter with the highest reliability can be determined. Among them, EH means eye height (eye high), and EW means eye width (eye width).

Table 2

The above mainly introduces the solutions provided by the present application from the perspective of method flow, and the following will elaborate on the technical solutions of the embodiments of the present application from the perspective of hardware or logic division modules. It can be understood that, in order to realize the above functions, the device may include corresponding hardware structures and/or software modules for performing various functions. Those skilled in the art should easily realize that the present application can be implemented in the form of hardware or a combination of hardware and computer software in combination with the units and algorithm steps of each example described in the embodiments disclosed herein. Whether a certain function is executed by hardware or computer software drives hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but such implementation should not be regarded as exceeding the scope of the present application.

In the case of using an integrated unit, FIG. 20 shows a possible exemplary block diagram of the memory chip initialization device involved in the embodiment of the present application. The memory chip initialization device 2000 may exist in the form of a software module or a hardware module. . The memory chip initialization apparatus 2000 may include: an initialization testing unit 2001 , a determination unit 2002 and a transmission unit 2003 .

In an example, the apparatus may exist in the form of a software module, and the firmware of the electronic device as shown in FIG. 7 includes a software module for implementing the software module. The computer instructions of the software module may be stored in a storage medium, such as the memory in FIG. 7 or the storage space inside the memory chip in FIG. 7 . When the electronic device is turned on, the processor of the electronic device calls firmware (such as BIOS) to perform hardware initialization. In this link, the processor will call the stored computer instructions for realizing the functions of each software module of the device, use the first binary sequence and the second binary sequence to test the memory chip, and finally obtain the memory chip The processor can configure the registers in the memory chip or the registers in the processor according to the obtained reference value, so as to realize a more reliable test of the memory chip and make the direct data transmission between the processor and the memory chip more efficient. reliable.

Specifically, in one embodiment, the initialization testing unit 2001 is configured to use the first binary sequence and the second binary sequence to test the value of the initialization parameter of the memory chip, wherein the second binary sequence The binary sequence has H jumps in the same direction relative to the first binary sequence and 1 reverse jumps relative to the first binary sequence, and the N data signal lines of the memory chip One of the data signal lines transmits the first binary sequence, and at least one data signal line in the other N-1 data signal lines transmits the second binary sequence, wherein the jump becomes two adjacent binary sequences in a binary sequence Changes in bit values, the N is an integer greater than or equal to 2, the H and the I are integers greater than or equal to 1;

The determining unit 2002 is configured to determine a reference value of the initialization parameter according to the value range of the initialization parameter obtained by testing;

The transmission unit 2003 is configured to perform data transmission with the memory chip according to the reference value.

In a possible design, the first binary sequence is a pseudo-random binary sequence with a variable marking ratio.

In a possible design, the determining unit 2002 is further configured to reversely process one or more transitions in the first binary sequence to determine the second binary sequence.

In a possible design, the determining unit 2002 is further configured to divide the first binary sequence in units of M bits, and determine multiple codes in the first binary sequence unit, wherein there is no repeated bit between any two coding units in the plurality of coding units, and the M is an integer greater than or equal to 2; mark the coding unit carrying the target coding combination in the plurality of coding units is the target coding unit, wherein the target coding combination is one or more of the 2 ^M coding combinations corresponding to the coding unit; the jump in the target coding unit in the first binary sequence is reversed For processing, the second binary sequence is determined.

In a possible design, half of the 2 ^M coding combinations are the target coding combinations.

In a possible design, the initialization parameters include at least one of the following: a reference level, and a phase adjustment amplitude of the data strobe signal DQS.

As another form of this embodiment, a computer-readable storage medium is provided, on which a computer program (or instruction) is stored, and when the computer program runs on an electronic device, the electronic device can execute the method described in the above-mentioned embodiment. The test method of the memory chip. As an example, as shown in FIG. 8, the computer-readable storage medium may be a memory in an electronic device, and the BIOS stored in the memory stores a computer program for implementing a test method for a memory chip, and the processor in the electronic device may Scheduling and running the computer program to implement the memory chip testing method in the above method embodiment.

As another form of this embodiment, a computer program product is provided. The computer program product includes a computer program for implementing a memory chip testing method. When the computer program is executed, it can implement the method in the above-mentioned embodiment. The test method of the memory chip. As an example: as shown in FIG. 8, the computer program product may be written into the memory of the electronic device (or in the BIOS), and the processor in the electronic device may schedule and run the computer program included in the computer program product, The method for testing the memory chip in the above method embodiment is realized.

As another form of this embodiment, a chip system is provided, the chip system includes: a processor and an interface, and the processor is used to call and execute a computer program for implementing a test method of a memory chip from the interface , when the processor executes the computer program, the memory chip testing method in the above method embodiment is realized. As an example, the interface can be an interface circuit, as shown in Figure 8, the processor can call and execute the computer program stored in the memory for implementing the test method of the memory chip through the interface circuit connecting the processor and the memory , implementing the method for testing the memory chip in the above method embodiment.

Those skilled in the art should understand that the embodiments of the present application may be provided as methods, systems, or computer program products. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.

The present application is described with reference to flowcharts and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present application. It should be understood that each procedure and/or block in the flowchart and/or block diagram, and a combination of procedures and/or blocks in the flowchart and/or block diagram can be realized by computer program instructions. These computer program instructions may be provided to a general purpose computer, special purpose computer, embedded processor, or processor of other programmable data processing equipment to produce a machine such that the instructions executed by the processor of the computer or other programmable data processing equipment produce a An apparatus for realizing the functions specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.

These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to operate in a specific manner, such that the instructions stored in the computer-readable memory produce an article of manufacture comprising instruction means, the instructions The device realizes the function specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.

These computer program instructions can also be loaded onto a computer or other programmable data processing device, causing a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process, thereby The instructions provide steps for implementing the functions specified in the flow chart or blocks of the flowchart and/or the block or blocks of the block diagrams.

While preferred embodiments of the present application have been described, additional changes and modifications to these embodiments can be made by those skilled in the art once the basic inventive concept is appreciated. Therefore, the appended claims are intended to be construed to cover the preferred embodiment and all changes and modifications which fall within the scope of the application.

Apparently, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. In this way, if the modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and equivalent technologies, the present application also intends to include these modifications and variations.

Claims (16)

1. A method for testing a memory chip, characterized in that it comprises:

   The value of the initialization parameter of the memory chip is tested by using the first binary sequence and the second binary sequence, wherein the second binary sequence has H values corresponding to the first binary sequence To jump and 1 reverse jump relative to the first binary sequence, one data signal line in the N data signal lines of the memory chip transmits the first binary sequence, and the other N- One or more data signal lines in one data signal line transmit the second binary sequence, wherein the jump is a change of two adjacent bit values in a binary sequence, and the N is an integer greater than or equal to 2, The H and the I are integers greater than or equal to 1;

   Determine the reference value of the initialization parameter according to the value range of the initialization parameter obtained by the test;

   Data transmission is performed with the memory chip according to the reference value.
2. The method according to claim 1, wherein the first binary sequence is a variable marking ratio pseudo-random binary sequence.
3. The method according to claim 1 or 2, wherein the second binary sequence is determined in the following manner:

   performing reverse processing on one or more jumps in the first binary sequence to determine the second binary sequence.
4. The method according to any one of claims 1-3, wherein the second binary sequence is determined in the following manner:

   dividing the first binary sequence in units of every M bits, and determining a plurality of coding units in the first binary sequence, wherein any two coding units in the plurality of coding units There is no repeated bit between, and the M is an integer greater than or equal to 2;

   Mark the coding unit carrying the target coding combination among the multiple coding units as the target coding unit, where the target coding combination is one or more of the 2 ^M coding combinations corresponding to the coding unit;

   performing reverse processing on transitions in the target coding unit in the first binary sequence to determine the second binary sequence.
5. The method according to claim 4, wherein half of the 2 ^M coding combinations are the target coding combinations.
6. The method according to any one of claims 1-5, wherein the initialization parameters include at least one of the following:

   Reference level, data strobe pulse signal DQS phase adjustment range.
7. An initialization device for a memory chip, characterized in that it includes: an initialization test unit, a determination unit, and a transmission unit;

   The initialization test unit is used to test the value of the initialization parameter of the memory chip by using the first binary sequence and the second binary sequence, wherein the second binary sequence has H values corresponding to the The jump in the same direction of the first binary sequence and one reverse jump relative to the first binary sequence, one data signal line in the N data signal lines of the memory chip transmits the first The binary sequence, one or more data signal lines in the other N-1 data signal lines transmit the second binary sequence, wherein the jump is the change of two adjacent bit values in a binary sequence, the N is an integer greater than or equal to 2, said H and said I are integers greater than or equal to 1;

   The determination unit is configured to determine the reference value of the initialization parameter according to the value range of the initialization parameter obtained by testing;

   The transmission unit is configured to perform data transmission with the memory chip according to the reference value.
8. The device according to claim 7, wherein the first binary sequence is a variable marking ratio pseudo-random binary sequence.
9. The device according to claim 7 or 8, wherein the determining unit is further configured to reversely process one or more jumps in the first binary sequence to determine the second binary sequence binary sequence.
10. The device according to any one of claims 7-9, wherein the determining unit is further configured to divide the first binary sequence in units of every M bits, and in the A plurality of coding units are determined in a binary sequence, wherein there is no repeated bit between any two coding units in the plurality of coding units, and the M is an integer greater than or equal to 2; the plurality of coding units The coding unit carrying the target coding combination in the unit is marked as the target coding unit, wherein the target coding combination is one or more of the 2 ^M coding combinations corresponding to the coding unit; the first binary sequence The transition in the target coding unit is reversely processed to determine the second binary sequence.
11. The device according to claim 10, wherein half of the 2 ^M coding combinations are the target coding combinations.
12. The device according to any one of claims 7-11, wherein the initialization parameters include at least one of the following:

    Reference level, data strobe pulse signal DQS phase adjustment range.
13. An electronic device, characterized in that it includes a processor, a memory and a memory chip;

    The memory is used to store program instructions;

    The processor is configured to execute the method according to any one of claims 1-6 through the memory chip by calling program instructions stored in the memory.
14. A computer-readable storage medium, characterized in that the computer-readable storage medium is used to store a computer program, and when the computer program is run on an electronic device, the electronic device executes the method described in claims 1-6. any one of the methods described.
15. A chip system, characterized in that the chip system includes:

    A processor and an interface, the processor is used to invoke and execute a computer program from the interface, and when the processor executes the computer program, the method according to any one of claims 1-6 is realized.
16. A computer program product, characterized in that the computer program product includes a computer program, and when the computer program is executed, the method according to any one of claims 1-6 is implemented.

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