TWI579983B - Semiconductor package having id code of molding map hidden in leadframe - Google Patents

Description

Semiconductor package structure with hidden patterned map code in lead frame

The present invention relates to the field of semiconductor chip packaging, and more particularly to a semiconductor package structure for a hidden-mold map code in a lead frame.

In the Mold Array Packaging process (MAP), a large area of the molding encapsulant is formed on a patterned array region to seal a plurality of package units arranged in an array, after being sawed and separated A plurality of semiconductor package structures are obtained. The wafer carrier used in the packaged array packaging process is typically a substrate strip or an external legless leadframe. It is known that a semiconductor package structure using a circuit substrate can easily produce an identification code directly on the surface of the substrate as a tracking of the production process because the complicated circuit layout and effective color recognition can be easily performed on the core layer of the substrate. . The current semiconductor package structure without external pin-type lead frame, especially the saw-type quad flat no-saw (saw QFN) package structure is limited by the design and packaging process capability of the all-metal lead frame, and cannot be like the circuit substrate. The identification surface of the lead frame is directly recognizable. When the product is found to be abnormal during the manufacturing process, the relative position of the packaged product in the molded array area cannot be effectively tracked in the final test (FT), and thus the difference cannot be distinguished. Good and bad products can not be diagnosed with key errors to improve the packaging process yield.

In order to solve the above problems, the main object of the present invention is to provide a semiconductor package structure with a hidden-mold map code in a lead frame, so as to effectively track the relative position of the packaged product in the molded array area, thereby distinguishing between good products and Defective product.

The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The invention discloses a semiconductor package structure with a hidden-mold map code in a lead frame, comprising a wafer holder of a lead frame and a plurality of pins, a wafer and a mold sealing body. The upper surface of the wafer holder has a die-bonding region and a coding region surrounding the die-bonding region. The chip is disposed on the die bond region and electrically connected to the pins. The mold encapsulation system seals the wafer and bonds the wafer holder to the pins. Wherein, the coding region has a plurality of identification points and a reference point, wherein the reference point defines an order of the identification points, and an identification code hole arrangement comprises one or more concave holes, which are selectively formed on the The identification points are combined to form a unit identification code, and the unit identification code is converted into a map code to determine the address of the package array of the wafer holder in the lead frame.

The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures.

In the foregoing semiconductor package structure, the wafer holder may be formed with a plating layer outside the coding region such that the coding region is interposed between the die bond region and the plating layer to facilitate identification.

In the foregoing semiconductor package structure, the mold encapsulation system can be filled in the The recessed hole allows the identification point of the recessed hole to be dark.

In the foregoing semiconductor package structure, the reference point can be an arc-arc edge of the plating layer, so that the reference point can be easily formed and fabricated, and the reference point can also be a non-circular hole such as a cross or an L shape or Non-circular pattern.

In the foregoing semiconductor package structure, the die bond region may be a recess, and the wafer system may be slightly sunk in the die bond region to prevent the crystal grain material from being improperly contaminated to the identification points.

In the foregoing semiconductor package structure, the recessed depth of the die-bonding region may not penetrate the wafer holder to prevent the die-bonding of the die-bonding material from being exposed.

In the foregoing semiconductor package structure, a plurality of bonding wires may be further included, and a plurality of pads of the wafer may be electrically connected to the pins, and the molding compound system may further seal the bonding wires.

In the foregoing semiconductor package construction, the identification points may be equally spaced around the wafer holder.

In the foregoing semiconductor package structure, a first lower surface of the wafer holder and a plurality of second lower surface portions of the pins may be exposed at the bottom of the mold sealing body to form a package type without an external lead lead frame. State, such as a quad flat no-pin (QFN) package.

In the foregoing semiconductor package structure, the recessed holes may not penetrate the wafer holder to prevent the first lower surface of the wafer holder from being contaminated by the molding gel.

By the above technical means, the present invention can be achieved in a lead frame An identification code hole arrangement is formed in the limited space of the wafer holder, and the concave hole is selectively formed in a semi-etching manner to mark the position of the identification point, and then indirectly converted into a map code corresponding to the mask array area, which is increased After this structure is designed, it can correctly track the distinction between good and bad products, and achieve the quality control level.

100‧‧‧Semiconductor package construction

110, 110A, 110B, 110C, 110D‧‧‧ wafer holder

111‧‧‧Macked area

112‧‧‧ coding area

113‧‧‧ Identification points

114‧‧‧ benchmark

115‧‧‧First lower surface

116‧‧‧ tied

120‧‧‧ pin

121‧‧‧Second lower surface

130‧‧‧ wafer

131‧‧‧ solder pads

132‧‧‧Active surface

133‧‧‧ back

140‧‧‧Mold sealant

150‧‧‧ recessed hole

160‧‧‧Electroplating

170‧‧‧Core material

180‧‧‧welding line

1 is a cross-sectional view showing a semiconductor package structure in which a map code is hidden in a lead frame in accordance with an embodiment of the present invention.

Figure 2 is a plan view of the wafer holder of the semiconductor package structure on its upper surface in accordance with an embodiment of the present invention.

Figure 3 is a partial cross-sectional view of the wafer holder of the semiconductor package structure taken along a line of the second embodiment of the present invention, taken along the line of Figure 2-3.

Figure 4 is a diagram showing the order of identification points of wafer holders corresponding to a semiconductor package construction in accordance with an embodiment of the present invention.

Figure 5 is a schematic diagram showing a first modular map in which a sealed array address and a map code are compared in accordance with an embodiment of the present invention.

FIG. 6A is a schematic diagram showing a first identification dot hole arrangement on a wafer holder of a semiconductor package structure according to an embodiment of the invention.

FIG. 6B is a schematic diagram showing the conversion of the first unit identification code composed of the first identification point hole configuration into the first map code and comparing to the first template map according to an embodiment of the present invention.

FIG. 7A is a schematic diagram showing a second identification dot hole arrangement on a wafer holder of another semiconductor package structure according to an embodiment of the present invention.

FIG. 7B is a schematic diagram showing the conversion of the second unit identification code composed of the second identification point hole configuration into the second map code and comparing to the first template map according to an embodiment of the present invention.

Figure 8 is a schematic diagram showing a second modular map in which the relationship between the encapsulated array address and the map code is displayed in accordance with an embodiment of the present invention.

FIG. 9A is a schematic diagram showing a third identification dot hole arrangement on a wafer holder of another semiconductor package structure according to an embodiment of the present invention.

FIG. 9B is a schematic diagram showing conversion of a third unit identification code composed of the third identification point hole configuration into a third map code according to an embodiment of the present invention.

FIG. 10A is a schematic diagram showing a fourth identification dot hole arrangement on a wafer holder of another semiconductor package structure according to an embodiment of the present invention.

FIG. 10B is a schematic diagram showing conversion of a fourth unit identification code composed of the fourth identification point hole configuration into a fourth map code according to an embodiment of the present invention.

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. The components and combinations related to this case, the components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios are proportional to other related sizes or have been exaggerated or simplified to provide clearer description of. Number, shape and size of actual implementation The ratio is an optional design, and the detailed component layout may be more complicated.

In accordance with an embodiment of the present invention, a semiconductor package structure 100 in which a die-encapsulated map code is hidden in a lead frame is illustrated in cross-section in FIG. 2 is a schematic plan view showing the wafer holder of the semiconductor package structure on the upper surface thereof. FIG. 3 is a partial cross-sectional view showing the wafer holder of the semiconductor package structure taken along the line of FIG. 3-3, taken at one of the identification points and being formed at the hole. A semiconductor package structure 100 for concealing a seal map code in a lead frame includes a wafer holder 110 and a plurality of pins 120, a wafer 130, and a mold seal 140. The wafer holder 110 and the pins 120 are made of a metal, such as a copper alloy or an iron alloy. In the packaging process, the wafer holder 110 and the pins 120 can be integrally connected to the lead frame. The wafer holder 110 is electrically separated from the pins 120 in a package configuration. Usually, the wafer holder 110 is integrally connected to the lead frame by a plurality of tie bars for carrying the wafer 130 in the process, and some of the tie bars remain in the package structure after sawing and singulation. . The semiconductor package structure 100 can be a saw-type quad flat no-spot (saw QFN) package structure, that is, the pins 120 do not have lateral extensions to the outside of the molding compound 140 and are bent outside the pins. Instead, the lower surface of the pins 120 is utilized as a surface joint region for solder bonding.

The upper surface of the wafer holder 110 has a die-bonding region 111 and a coding region 112. The code region 112 surrounds the die-bond region 111. The die-bond region 111 is a region where the wafer 130 is mounted. The region 112 is part of the wafer holder 110 that is not covered by the wafer 130. Usually, the coding region 112 is smaller than the die bonding region. 111. More importantly, the coding region 112 has a plurality of identification points 113 and a reference point 114, and the reference point 114 defines the order of the identification points 113. In the present embodiment, FIG. 4 is a diagram defining the order of the identification points 113 of the wafer holder 110 of the semiconductor package structure 100. The reference point 114 is the reference Pin1 of the orientation determination, and can be clockwise. The manner defines the order of the identification points 113, for example, the identification point position from 1 to 10. More specifically, the identification points 113 are equally arranged around the four wafer holders 110, and the identification points 113 on the same side are the same pitch, and the closest neighboring points of the identification points 113 on different sides are larger than The spacing on the same side.

The wafer 130 is disposed on the die bond region 111 and electrically connected to the pins 120. The wafer 130 can be a microelectronic component cut from a wafer. The wafer 130 can have an active surface 132 and an opposite back surface 133. The plurality of solder pads 131 can be disposed on the active surface 132. The active surface 132 is a surface on which the integrated circuit is formed on the wafer 130. The pads 131 are electrodes that communicate the integrated circuit. The back surface 133 of the wafer 130 may be adhered to the die bonding region 111 by a liquid coating or film type die bonding material 170. The plurality of bonding wires 180 formed by wire bonding may be electrically connected to the wafer 130. A plurality of pads 131 are connected to the pins 120. Specifically, the die-bonding region 111 can be a recess, and the wafer 130 can be slightly sunk in the die-bonding region 111 (as shown in FIG. 1) to prevent the die-bonding material 170 from being improperly contaminated to the code. The area 112 and the identification points 113. Preferably, the recessed depth of the die-bonding region 111 may not penetrate the wafer holder 110 to prevent the die-bonding of the die-bonding material 170 from being exposed.

The molding compound 140 seals the wafer 130 and bonds the wafer holder 110 to the pins 120. The molding compound 140 can be a mold ring compound (EMC), or thermoset composite electrical insulation. In the present embodiment, the molding compound 140 can seal the bonding wires 180 more. Referring to FIG. 1 , the first lower surface 115 of the wafer holder 110 and the plurality of second lower surfaces 121 of the pins 120 can be exposed at the bottom of the molding compound 140 to become an external pin. The package type of the lead frame, such as a quad flat no-pin (QFN) package.

Figure 5 is a schematic diagram showing a first modular map in which the seal array address is compared with the map code. The molded map is used to direct a plurality of semiconductor package structures to a masked array address in an external leadless lead frame. In this embodiment, the first molded map can be combined with an array having 34 straight rows and 9 horizontally arranged package units in a sealed array region, so the first molded map contains a total of 306 molded arrays. address. The first sealed map corresponds to a sealed array area arranged by a package unit arranged by 34 times 9 matrix, each of which is given a unique map code, and the local map code can be indirectly, hidden and When the proper conversion mode is expressed in the limited space of the wafer holder 110, the position of each semiconductor package structure in the die-array array process in the die-array array process can be discriminated in a hidden manner, and the semiconductor is not caused. The difference in appearance and specifications of the package construction. In addition, different and corresponding molded maps should be prepared in accordance with the patterned array regions arranged by different numbers of package units.

An identification code hole arrangement (described in detail later) as shown in FIGS. 6A, 7A, 9A, and 10A includes one or more recessed holes 150 selectively formed in the identification points 113 to constitute a unit identification code (unit ID code) shown in FIGS. 6B, 7B, 9B and 10B, and converted into a map code by the unit identification code to determine a sealed array address of the wafer holder 110 in the lead frame . X-ray perspective The semiconductor package structure 100 can observe the identification code hole arrangement in the coding area 112. The identification point of the concave hole 150 can be recognized as “1”, and the identification point without the concave hole can be recognized as “0”, and then the identification point is recognized. The location of the unit constitutes the unit identification code. Preferably, as shown in FIGS. 1 and 3, the recess 150 may not penetrate the wafer holder 110 to prevent the first lower surface 115 of the wafer holder 110 from being contaminated by the molding compound 140. As shown in FIG. 3, the recess 150 can be formed by a half etching. The recess 150 can have a diameter ranging from 0.09 mm to 0.15 mm, and the recess 150 can have a standard depth of 0.08 mm. The system can be between 0.05 and 0.11 mm. Further, the width of the code region 112 can be 0.2 mm. The thickness of the wafer holder 110 is about 0.2 mm, and the recessed depth of the die-bonding region 111 can range from 0.11 mm to 0.17 mm. Therefore, the depth of the recess 150 may not be greater than the recess depth of the die region 111 to maintain the peripheral structure of the wafer holder 110.

Referring to FIGS. 1 and 3 , the wafer holder 110 is formed with a plating layer 160 outside the coding region 112 such that the coding region 112 is interposed between the die bond region 111 and the plating layer 160 . Easy to identify between. More preferably, referring to FIG. 1 , the molding compound 140 can be filled into the recess 150 such that the identification point 113 having the recess 150 is dark-colored for identification. In addition, referring to FIG. 2, the reference point 114 can be an arc-arc edge of the plating layer 160, so that it has the effect of easy forming and low-cost fabrication. The reference point 114 can also be a cross or an L shape. Non-circular holes or non-circular patterns. The particular shape of the fiducial 114 can be selected as a corresponding molded map. In this embodiment, the plating layer 160 may be further formed on a plurality of tie bars 116 of the wafer holder 110 to increase the grounding of the wafer holder 110 or The wire bonding area of the power connection.

FIG. 6A is a schematic diagram showing a first identification dot hole arrangement on a wafer holder of a semiconductor package structure. A first semiconductor package structure includes a wafer holder 110A, and a coding area 112 on an upper surface thereof is formed with a first identification code hole arrangement, including two concave holes 150, which are located at the identification points of the 7th and 9th positions. 113. As shown in FIG. 6B, the first identification code hole can be configured to form a first unit identification code "0000001010", and then converted into a decimal by the binary to form a first map code "10", the first map. The code comparison to the first template map may refer to a first template map address, which is located at a position of a second straight line and a first line of 34 times 9 matrix, which indicates the first semiconductor package structure The wafer holder 110A is located in the unit position of the second straight line and the first course in the 34×9 mold array region of the dependent lead frame in the mold array packaging process.

FIG. 7A is a schematic diagram showing a second identification dot hole arrangement on a wafer holder of another semiconductor package structure. A second semiconductor package structure includes a wafer holder 110B, and a coding area 112 on the upper surface thereof is formed with a second identification code hole arrangement, and includes six concave holes 150, which are located at the second, fifth, seventh, Identification points 113 of the eighth, ninth and tenth positions. As shown in FIG. 7B, the second identification code hole can be configured to form a second unit identification code "0100101111", and then the second map code "303" is formed by converting the binary bit into a decimal position. The code comparison to the first mask map may refer to a second mask map address, which is located at 34th and 9th rows of the 34th straight row and the sixth row, which indicates the second semiconductor package structure The wafer carrier 110B is located in its associated lead frame in the packaged array packaging process. The ×9 mold-sealed array is located at the unit positions of the 34th straight row and the 6th horizontal row.

Figure 8 is a schematic diagram showing a second modular map in which the encapsulated array address is compared with the map code. In this embodiment, the second mold map can be combined with an array of package units having 64 straight rows and 16 horizontal rows in a patterned array region, so the second mold map comprises a total of 1024 mold arrays. address. The second molded map corresponds to a sealed array area arranged by a package unit arranged by 64 times 16 matrix, each of which is given a unique map code, the map code is indirectly, hidden and A suitable conversion mode is manifested in the limited space of the wafer holder 110.

FIG. 9A is a schematic diagram showing a third identification dot hole arrangement on a wafer holder of another semiconductor package structure. A third semiconductor package structure includes a wafer carrier 110C having a coded region 112 on the upper surface thereof having a triangular or other pattern reference point 114, which may be formed by a portion of the plating layer 160 to designate the second mode The map is sealed and the order of the identification points 113 is defined. The coding area 112 on the upper surface of the wafer holder 110C is formed with a third identification code hole arrangement, and includes two recessed holes 150, which are located at the identification points 113 of the 9th and 10th positions. As shown in FIG. 9B, the third identification code hole can be configured to form a third unit identification code "0000000011", and then converted into a decimal by the binary conversion to form a third map code "3", the third map. The code is compared to the second mask map as shown in FIG. 8, which may refer to a third modular map address, which is located at a position of the first straight line and the third horizontal line of 64 times 16 matrix. The wafer carrier 110C representing the third semiconductor package structure is located at the cell position of the first straight row and the third row in the 64×16 mask array region of the dependent lead frame in the die package array packaging process.

FIG. 10A is a schematic diagram showing a fourth identification dot hole arrangement on a wafer holder of another semiconductor package structure. A fourth semiconductor package structure includes a wafer holder 110D. The code region 112 on the upper surface of the wafer holder 110D is formed with a fourth identification code hole arrangement, and includes nine concave holes 150, which are located in the first and the first 2. Identification points 113 of the third, fourth, fifth, sixth, seventh, eighth and ninth positions. As shown in FIG. 10B, the fourth identification code hole can be configured to form a fourth unit identification code "1111111110", and then a binary map code "1022" is formed by converting the binary into a decimal, the fourth map. The code is compared to the second mask map as shown in Fig. 8, which may refer to a fourth modular map address, which is located at 64 times the 64th straight line and the 14th horizontal position of the 16 matrix. The wafer holder 110D representing the fourth semiconductor package structure is located at the unit position of the 64th straight row and the 14th row in the 64×16 mold array region of the dependent lead frame in the die package array packaging process. In addition, the unit identification code corresponding to the map code "1023" can be "1111111111", and the unit identification code corresponding to the map code "1024" can be "0000000000", which is indicated by an unmarked mark when the identification point is defined (position When 1 to 10) are identified as "0" without a recess, the reference point is used as the identification point of the hyperplasia (ie, position 0), and the unit identification code can be "10000000000", so the map code "1024" can be obtained. "."

Therefore, the semiconductor package structure of the hidden die seal map code in the lead frame of the present invention is disposed in a limited space of the wafer holder, and the identification dot hole arrangement is formed by a half etching method to form an indirect corresponding to the molded map. Unit identification code, so it can determine the address of the module array in the lead frame of the wafer holder in the process, effectively track the relative position of the packaged product in the molded array area, and then distinguish Good quality and bad products, to achieve quality control standards.

The above is only the preferred embodiment of the present invention, and the scope of the present invention is not limited thereto, and thus equivalent changes made in the claims of the present invention are still within the scope of the present invention.

110‧‧‧ wafer holder

111‧‧‧Macked area

112‧‧‧ coding area

113‧‧‧ Identification points

114‧‧‧ benchmark

116‧‧‧ tied

160‧‧‧Electroplating

Claims (10)

A semiconductor package structure for concealing a seal map code in a lead frame, comprising: a wafer holder and a plurality of pins of a lead frame, the upper surface of the wafer holder having a die bond region and a coding region, the code a region surrounding the die-bonding region; a wafer disposed on the die-bonding region and electrically connected to the pins; and a molding compound sealing the wafer and bonding the wafer carrier to the pins Wherein the coding region has a plurality of identification points and a reference point, the reference point defines an order of the identification points, and an identification code hole arrangement comprises one or more concave holes, which are selectively formed on The identification points are combined to form a unit identification code, and the unit identification code is converted into a map code to determine the address of the package array of the wafer holder in the lead frame. The semiconductor package structure of the die-encapsulated map code in the lead frame of claim 1, wherein the wafer holder is formed with a plating layer outside the coding region, so that the coding region is interposed between the die bond Between the zone and the plating layer. The semiconductor package structure of the die-encapsulated map code in the lead frame of claim 2, wherein the mold encapsulation system fills the recess. The semiconductor package structure of the die-encapsulated map code in the lead frame of claim 2, wherein the reference point is an arc-arc edge of the plating layer. The semiconductor package structure of the recessed-molded map code in the lead frame according to claim 1, wherein the die-bonding region is a recess, and the wafer is slightly sunk in the die-bonding region. The semiconductor package structure of the die-encapsulated map code in the lead frame of claim 5, wherein the recessed depth of the die-bonding region does not penetrate the wafer holder. The semiconductor package structure of the recessed-molded map code in the lead frame according to the first aspect of the patent application, further comprising a plurality of bonding wires electrically connected to the plurality of pads of the chip to the pins, the die seal The glue system seals the wire bonds more. The semiconductor package structure of the recessed-molded map code in the lead frame according to claim 1, wherein the identification points are arranged equidistantly around the wafer holder. The semiconductor package structure of the recessed-molded map code in the lead frame according to any one of claims 1 to 8, wherein the first lower surface of the one of the wafer holders and the plurality of second pins of the pins The surface system is exposed at the bottom of the molding compound. The semiconductor package structure of the die-encapsulated map code in the lead frame of claim 9, wherein the recessed hole does not penetrate the wafer holder.