TWI575754B - Thin film transistor and production method thereof, display apparatus, image sensor, x-ray sensor, and x-ray digital imaging apparatus - Google Patents

Description

Thin film transistor and manufacturing method thereof, display device, image sensor, X-ray sensor and X-ray digital camera

The invention relates to a thin film transistor and a manufacturing method thereof, a display device, an image sensor, an X-ray sensor and an X-ray digital photographing device.

In recent years, research and development of thin film transistors (TFTs) using an oxide semiconductor thin film of In-Ga-Zn-O system (hereinafter referred to as IGZO) for an active layer (channel layer) are actively being carried out. Since the oxide semiconductor thin film can exhibit low-temperature film formation and exhibit higher mobility than amorphous germanium and is transparent to visible light, a flexible thin film transistor can be formed on a substrate such as a plastic plate or a film.

Here, Table 1 shows comparison of field effect mobility, process temperature, and the like of various transistor characteristics.

As shown in Table 1, the thin film transistor in which the active layer is polycrystalline germanium can obtain a mobility of about 100 cm ² /Vs, but since the process temperature is 450 ° C or more and is very high, it can be formed only on a substrate having high heat resistance, and Not suitable for low cost, large area, and flexibility. In addition, the thin film transistor in which the active layer is amorphous germanium can be formed at a relatively low temperature of about 300 ° C. Therefore, the selectivity of the substrate is wider than that of polycrystalline germanium, but only a mobility of up to about 1 cm ² /Vs can be obtained, and is uncomfortable. For high-definition display applications.

On the other hand, in the case of a low-temperature film formation, the thin film transistor in which the active layer is an organic material can be formed at 100 ° C or lower. Therefore, it can be expected to be applied to a flexible display using a plastic film substrate having low heat resistance and the like. However, the mobility is only as good as that of amorphous germanium.

For example, Japanese Laid-Open Patent Publication No. 2010-21555 discloses a thin film transistor in which indium zinc oxide (IZO) and indium tin oxide (ITO) are disposed on the side close to the gate electrode. a high mobility layer of oxide of gallium doped Zinc Oxide (GZO) or Aluminium-doped Zinc Oxide (AZO) as an active layer, and Zn is disposed on a side away from the gate electrode The oxide layer serves as an active layer.

Further, it is reported that a thin film transistor using an oxide semiconductor and an oxide semiconductor containing In, Ga, and Zn as an active layer has a property of a threshold voltage to a negative shift when irradiated with light having a wavelength of less than 460 nm (refer to CS Zhuang et al., SID 08 Digest, page 13 (CSChuang et al., SID 08 DIGEST, P-13)).

The blue light-emitting layer used in an organic electroluminescence (EL) element or a liquid crystal exhibits a wide range of light emission having a peak value of about λ = 450 nm, but considering the light emission of the blue light of the organic EL element When the tail of the spectrum continues to 420 nm and the blue color filter passes through about 400% of light of 400 nm, deterioration of characteristics of light irradiation in a wavelength region of less than 450 nm is required to be low. When the optical band gap of the IGZO film is assumed to be relatively narrow and the region has optical absorption, there arises a problem of causing a threshold shift of the transistor.

On the other hand, with the increase in size and high definition of the display, further high mobility of the thin film transistor for display driving is required, and it is also proposed to be in an amorphous germanium or an existing IGZO element (mobility: 10 cmA ^{2 ).} High-performance display that cannot be surpassed in /Vs.

One of the methods for achieving such high mobility is a TFT having a structure in which a plurality of active layers including an oxide semiconductor are laminated. However, in such a laminated TFT, a protective layer or the like for lowering the characteristic deterioration of light irradiation or a barrier layer is not provided on the active layer, and an attempt to improve the light irradiation stability is not substantially performed.

Here, for example, when the threshold displacement amount (ΔVth) under light irradiation of 420 nm is set to 1 V or less, it is difficult to achieve light irradiation at 420 nm as an index of stability against light irradiation. A layered TFT of ΔVth ≦ 1V.

In Japanese Laid-Open Patent Publication No. 2010-21555, a high mobility TFT can be realized by using an IZO system or the like as a current path layer, but the light irradiation characteristics are not mentioned. Further, in CS Zhuang et al., SID 08 Abstract, page 13 (CSChuang et al., SID 08 DIGEST, P-13), the TFT element of the conventional IGZO single film was evaluated for deterioration in characteristics of light irradiation, but When the above numerical values are used as a reference, the characteristics are still insufficient with respect to light irradiation stability.

In addition, when a laminated TFT structure is used, it is assumed that a large number of defect energy levels which cause deterioration in light stability due to damage or the like at the time of film formation are easily formed at the laminated interface. In addition, in the laminated structure, migration of carriers due to lamination of the active layer is usually caused, so that an off current is increased and a hump effect is easily generated, and light stability of the TFT is caused. And deterioration of on/off characteristics.

Due to such a situation, it is difficult to achieve high light stability in the laminated TFT and suppress the hump effect.

An object of the present invention is to provide a laminated thin film transistor which realizes high light stability (ΔVth ≦ 1 V under light irradiation of λ = 420 nm) and suppresses hump effect in Vg-Id characteristics, and can be borrowed A method for manufacturing a thin film transistor of the thin film transistor, and a display device, an image sensor, an X-ray sensor, and an X-ray digital photographing device are manufactured by a relatively simple manufacturing process.

Examples of the form of the present invention are described below.

<1> A method of producing a thin film transistor, comprising: a film forming step of forming a first region and a second region as having a gate electrode, a gate insulating film, an oxide semiconductor layer, and a source electrode; In the oxide semiconductor layer of the thin film transistor of the gate electrode, the first region has In _(a) Ga _(b) Zn _(c) O _(d) (a > 0, b ≧ 0, c > 0, d >0, and a+b+c=1) indicates that the composition of b≦91a/74-17/40 is satisfied; and the second region is disposed on a side farther from the gate electrode than the first region, and has In _(e) Ga _(f) Zn _(g) O _(h) (e>0, f>0, g>0, h>0, and e+f+g=1) indicates that the composition is different from the first region described above And satisfying a composition of f/(e+f) ≧ 0.80; and a heat treatment step of heat-treating the oxide semiconductor layer at 300 ° C or higher in an oxidizing gas atmosphere after the film forming step.

<2> The method for producing a thin film transistor according to the above aspect, wherein the heat treatment temperature in the heat treatment step is 400 ° C or higher.

(3) The method for producing a thin film transistor according to the above aspect, wherein the gas atmosphere in the heat treatment step is a moisture content in the entire gas atmosphere of -36 ° C or less in terms of dew point temperature. Dry gas environment.

<4> A thin film transistor having a gate electrode, a gate insulating film, an oxide semiconductor layer, a source electrode, and a drain electrode; wherein the oxide semiconductor layer includes: a first region having In _(a) Ga _(b) Zn _(c) O _(d) (a>0, b≧0, c>0, d>0, and a+b+c=1) indicates and satisfies b≦91a/74-17/ a composition of 40; and a second region disposed on a side farther from the gate electrode than the first region, having In _(e) Ga _(f) Zn _(g) O _(h) (e>0, f> 0, g>0, h>0, and e+f+g=1) indicates a composition having a composition different from the first region described above and satisfying f/(e+f)≧0.80.

<5> The thin film transistor according to <4>, wherein the composition of the first region is satisfied: c≦3/5, b>0, b≧3a/7-3/14, b≧9a/5-53/50, b≦-8a/5+33/25, and b≦91a/74-17/ The range of 40.

<6> The thin film transistor according to <4>, wherein the composition of the first region satisfies: b≦17a/23-28/115, b≧3a/37, b≧9a/5-53/50, And b≦1/5 range.

<7> The thin film transistor according to <4>, wherein the composition of the first region is b=0.

<8> The thin film transistor according to <7>, wherein the composition of the first region is 0.4 ≦ a ≦ 0.75.

<9> The thin film transistor according to <7>, wherein the composition of the first region is 0.4 ≦ a ≦ 0.5.

The thin film transistor according to any one of <4>, wherein the film thickness of the second region is more than 10 nm and less than 70 nm.

The thin film transistor according to any one of <4>, wherein the first region has a film thickness of 5 nm or more and less than 10 nm.

The thin film transistor according to any one of <4>, wherein the oxide semiconductor layer is amorphous.

<13> A display device comprising the thin film transistor according to any one of <4> to <12>.

<14> An image sensor according to any one of <4> to <12>.

<15> An X-ray sensor, comprising the thin film transistor according to any one of <4> to <12>.

<16> An X-ray digital photographing apparatus comprising the X-ray sensor according to <15>.

According to the present invention, it is possible to provide a laminated thin film transistor which realizes high light stability (ΔVth ≦ 1 V under light irradiation of λ = 420 nm) and suppresses hump effect in Vg-Id characteristics, and can be borrowed A method for manufacturing a thin film transistor of the thin film transistor, and a display device, an image sensor, an X-ray sensor, and an X-ray digital photographing device are manufactured by a relatively simple manufacturing process.

1, 2, 2a, 2b‧‧‧ film transistor

5‧‧‧Liquid crystal display device

6‧‧‧Organic EL display device

7‧‧‧X-ray sensor

11, 60‧‧‧ substrate

12‧‧‧Oxide semiconductor layer

13, 13a, 13b‧‧‧ source electrode

14, 14a, 14b‧‧‧汲electrode

15‧‧‧gate insulating film

16, 16a, 16b‧‧‧ gate electrode

A1‧‧‧1st area

A2‧‧‧2nd area

19, 79‧‧‧ contact holes

51, 66, 81‧‧‧ gate wiring

52, 67, 82‧‧‧ data wiring

53, 69, 70‧‧‧ capacitors

54, 61a, 61b‧‧‧ passivation layer

55‧‧‧pixel lower electrode

56‧‧‧for the upper electrode

57‧‧‧Liquid layer

58‧‧‧RGB color filter

59a, 59b‧‧‧ polarizing plate

62‧‧‧lower electrode

63, 73‧‧‧ upper electrode

64‧‧‧Organic light-emitting layer

65‧‧‧Organic light-emitting elements

68‧‧‧Drive wiring

71‧‧‧Electrical electrodes for charge collection

72‧‧‧X-ray conversion layer

75‧‧‧passivation film

76‧‧‧The lower electrode for capacitor

77‧‧‧Upper electrode for capacitor

78‧‧‧Insulation film

200‧‧‧Probe platform

FIG. 1 is a schematic view showing a configuration of an example of a thin film transistor (bottom gate-top contact type) of the present invention.

2 is a schematic view showing a configuration of an example of a thin film transistor of the present invention (top gate-bottom contact type).

3(A) is a cross-sectional scanning transmission electron microscope (STEM) image of the IGZO laminated film immediately after lamination, and FIG. 3(B) is a cross-sectional view showing the IGZO laminated film after annealing at 600 ° C. STEM image.

4 is a schematic view of a light irradiation characteristic evaluation method.

Fig. 5 is a graph showing the dependence of the A2 layer composition of the Vg-Id characteristic.

Fig. 6 is a graph showing changes in Vg-Id characteristics under light irradiation in Example 3.

Fig. 7 is a schematic cross-sectional view showing a part of a liquid crystal display device of the embodiment.

Fig. 8 is a schematic configuration diagram of electric wiring of the liquid crystal display device of Fig. 7;

FIG. 9 is a schematic cross-sectional view showing a part of an organic EL display device according to an embodiment.

FIG. 10 is a schematic configuration diagram of electric wiring of the organic EL display device of FIG. 9. FIG.

Fig. 11 is a schematic cross-sectional view showing a part of an X-ray sensor array according to an embodiment.

Fig. 12 is a schematic configuration diagram of electric wiring of the X-ray sensor array of Fig. 11;

FIG. 13 is a view showing the composition range of the first region in the oxide semiconductor layer of the thin film transistor of the present invention and the composition and migration of the first region in the oxide semiconductor layer of the example and the comparative example by the ternary phase diagram method. Rate map.

Hereinafter, the film of the embodiment of the present invention will be described with reference to the drawings. A transistor, a method of manufacturing the same, and a display device, a sensor, and an X-ray sensor (digital imaging device) having a thin film transistor according to an embodiment of the present invention will be specifically described. In the drawings, members (components) having the same or corresponding functions are denoted by the same reference numerals, and description thereof will be appropriately omitted.

<Thin Film Transistor>

The thin film transistor of the present invention (referred to as "TFT" as appropriate) has a voltage applied to the gate electrode to control a current flowing in the oxide semiconductor layer, and switches a current between the source electrode and the drain electrode. Functional. The thin film transistor of the present invention has a gate electrode, a gate insulating film, an oxide semiconductor layer, a source electrode, and a drain electrode, and the oxide semiconductor layer includes: a first region having In _(a) Ga _(b) Zn _(c) O _(d) (a>0, b≧0, c>0, d>0, and a+b+c=1 represents, and satisfies the composition of b≦91a/74-17/40; a second region disposed on a side of the first region away from the gate electrode, having In _(e) Ga _(f) Zn _(g) O _(h) (e>0, f>0, g>0, h >0, and e+f+g=1) indicates that f/(e+f)≧0.80 is satisfied, and the composition is different from the first region.

In general, when the active layer is a laminated thin film transistor having a laminated structure, the carrier has a small electron affinity, and the carrier flows into a region having a large electron affinity due to the magnitude of the electron affinity of each region. Further, when the carrier is caused to flow into the first region relatively close to the gate electrode, a parasitic conduction path may be formed in addition to the main channel path generated at the interface between the first region and the gate insulating film. The presence of such parasitic conduction results in a hump effect in the Vg-Id characteristic, which deteriorates the on/off ratio. In addition, if the carrier in the parasitic conduction path increases due to light irradiation, or the carrier that is excited by light in other layers is near the parasitic conduction path When caught, it causes an increase in the off current or a displacement of the rising voltage of the current in the transistor, and causes light instability.

On the other hand, the thin film transistor of the present invention is a laminated thin film transistor having a first oxide semiconductor region and a second oxide semiconductor region, and the first region close to the gate electrode is composed of an IGZO layer or an IZO layer having a specific composition. The second region located at a position away from the first region with respect to the gate electrode is composed of an IGZO layer, and the Ga content is increased so as to satisfy Ga/(In+Ga) ≧ 0.80 (atomic ratio In: Ga: Zn = 0.4: 1.6: 1), whereby the hump effect can be suppressed and high light stability can be achieved.

In the thin film transistor of the present invention, even if the carrier is caused to flow from the second region to the first region, the carrier concentration in the second region can be suppressed to an extremely low level in order to increase the Ga content in the second region. When the inventors confirmed by the hole measurement, the carrier concentration in the second region was 1.0 × 10 ¹⁴ cm ^-3 or less. Therefore, it is possible to suppress the formation of the parasitic conduction path in the first region due to the inflow of the carrier. Therefore, in the TFT of the present invention, an increase in the off current or a change in the rising voltage due to light irradiation can be suppressed, and high light stability can be achieved.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. Although the TFT shown in FIG. 1 and FIG. 2 as a representative example is specifically described, the present invention can also be applied to a TFT of another form (structure).

The element structure of the TFT of the present invention may be any one of a so-called bottom gate type structure (also referred to as an inverted staggered structure) and a top gate type structure (also referred to as a stagger structure) depending on the position of the gate electrode. . The so-called top gate structure, When the substrate on which the TFT is formed is the lowermost layer, a gate electrode is disposed on the upper side of the gate insulating film, and an active layer is formed on the lower side of the gate insulating film. In the case of the bottom gate type, when the substrate on which the TFT is formed is the lowermost layer, a gate electrode is disposed on the lower side of the gate insulating film, and an active layer is formed on the upper side of the gate insulating film.

Further, the element structure of the TFT of the present invention may be a so-called top contact type structure and a bottom portion depending on the contact portion of the oxide semiconductor layer and the source electrode and the drain electrode (referred to as "source-drain electrode" as appropriate). Any form of contact structure. The bottom contact type structure is a form in which a source-drain electrode is formed earlier than an active layer and a lower surface of the active layer is in contact with a source-drain electrode. The top contact type structure is a form in which the active layer is formed first than the source-drain electrode and the upper surface of the active layer is in contact with the source-drain electrode.

Further, the TFT of the present invention may have various configurations in addition to the above, and may be configured to include a protective layer on the active layer or an insulating layer on the substrate.

1 is a cross-sectional view showing a configuration of a thin film transistor 1 according to a first embodiment of the present invention, and FIG. 2 is a cross-sectional view schematically showing a configuration of a thin film transistor 2 according to a second embodiment of the present invention. In the thin film transistor 1 of FIG. 1 and the thin film transistor 2 of FIG. 2, the same reference numerals are given to the common elements.

The thin film transistor 1 of the first embodiment shown in FIG. 1 is a bottom gate-top contact type transistor, and the thin film transistor 2 of the second embodiment shown in FIG. 2 is a top gate-bottom contact type transistor. In the embodiment shown in FIGS. 1 and 2, the arrangement of the gate electrode 16, the source electrode 13, and the drain electrode 14 with respect to the oxide semiconductor layer 12 Different, but the elements given the same symbol have the same function, and the same material can be applied.

The thin film transistor 1 and the thin film transistor 2 according to the embodiment of the present invention have a gate electrode 16, a gate insulating film 15, an oxide semiconductor layer 12, a source electrode 13, and a drain electrode 14, and the oxide semiconductor layer 12 is on the film. The first direction A1 and the second area A2 are provided in the thick direction from the side close to the gate electrode 16. The first region A1 and the second region A2 constituting the oxide semiconductor layer 12 are continuously formed into a film, and a layer other than the oxide semiconductor layer such as the edge layer or the electrode layer is not interposed between the first region A1 and the second region A2. And includes an oxide semiconductor film.

Hereinafter, the substrate on which the TFT1 and the TFT2 of the present invention are formed is also included, and each constituent element will be described in detail.

(substrate)

The shape, structure, size, and the like of the substrate 11 for forming a thin film transistor of the present invention are not particularly limited, and may be appropriately selected depending on the purpose. The structure of the substrate 11 may be a single layer structure or a laminate structure.

For example, a substrate containing an inorganic material such as glass or Yttria Stabilized Zirconia (YSZ), a resin, or a resin composite material can be used. Among them, in terms of lightweightness and flexibility, a substrate comprising a resin or a resin composite material is preferred. Specific examples include: polybutylene terephthalate, polyethylene terephthalate, polyethylene naphthalate, polybutylene naphthalate, polystyrene, polycarbonate, polyfluorene, Polyether oxime, polyarylate, allyl diglycol carbonate, polyamine, polyimine, polyamidimide, polyether phthalimide, polybenzoxazole, polyphenylene sulfide, poly a fluororesin such as a cycloolefin, a norbornene resin or a polychlorotrifluoroethylene, Liquid crystal polymer, acrylic resin, epoxy resin, fluorenone resin, ionic polymer resin, cyanate resin, crosslinked fumaric acid diester, cyclic polyolefin, aromatic ether, maleic acid A substrate of a synthetic resin such as an imine-olefin, a cellulose, or an episulfide compound.

Further, a substrate comprising a composite plastic material such as a synthetic resin and cerium oxide particles as described above may be used, and includes a synthetic resin or the like, a metal nanoparticle, an inorganic oxide nanoparticle, or an inorganic nitride nanoparticle. A substrate of a composite plastic material, a substrate comprising a composite plastic material such as a synthetic resin and a carbon fiber or a carbon nanotube, and a substrate comprising a composite plastic material such as a synthetic resin and glass cullet, glass fiber or glass beads. A substrate comprising a composite plastic material such as a synthetic resin or a clay mineral or a particle having a mica-derived crystal structure, and a laminated plastic substrate having at least one bonding interface between the thin glass and any of the synthetic resins described above. a substrate comprising a composite material having barrier properties of at least one bonding interface by alternately laminating an inorganic layer and an organic layer (synthesized resin described above), a stainless steel substrate or a stainless steel laminated with a different kind of metal Metal multilayer substrate, aluminum substrate or oxidation treatment (such as anodizing treatment) on the surface to improve the surface Of an aluminum substrate with an oxide film.

The resin substrate is preferably excellent in heat resistance, dimensional stability, solvent resistance, electrical insulating properties, workability, low air permeability, and low moisture absorption. The resin substrate may include a gas barrier layer for preventing the permeation of moisture or oxygen, or an undercoat layer for improving the flatness of the resin substrate or the adhesion to the lower electrode.

When a flexible substrate is used, the thickness of the substrate 11 is preferably 50 μm. Up, 500 μm or less. When the thickness of the substrate 11 is 50 μm or more, the flatness of the substrate itself is further improved. When the thickness of the substrate 11 is 500 μm or less, the flexibility of the substrate itself is further improved, and the use as a substrate for a flexible element becomes easier. Further, since the thickness of the substrate 11 is sufficient to have sufficient flatness and flexibility, it is necessary to set the thickness depending on the substrate material, but the range is approximately 50 μm to 500 μm.

(oxide semiconductor layer)

The oxide semiconductor layer 12 includes the first region A1 (referred to as "A1 layer" as appropriate) and the second region A2 (referred to as "A2 layer" as appropriate) from the gate electrode 16 in order to separate the gate insulating film. 15 is disposed opposite to the gate electrode 16. The first region A1 has an In _(a) Ga _(b) Zn _(c) O _(d) (a>0, b≧0, c>0, d>0, and a+b+c=1) And satisfy the composition of b≦91a/74-17/40 IGZO layer or IZO layer. On the other hand, the second region A2 on the side opposite to the surface of the first region A1 that is in contact with the gate insulating film 15 on the side far from the first region A1 with respect to the gate electrode 16 is In _(e) Ga _(f) Zn _(g) O _(h) (e>0, f>0, g>0, h>0, and e+f+g=1) indicates that f/(e+f)≧0.80 is satisfied. And constituting an IGZO layer different from the first region A1.

- Zone 1 -

The first region A1 is represented by In _(a) Ga _(b) Zn _(c) O _(d) (a>0, b≧0, c>0, d>0, a+b+c=1), And the IGZO layer (when b>0) or the IZO layer (when b=0) of the composition of b≦91a/74-17/40 is satisfied.

The first region is the form of the IGZO layer

When the composition of the first region A1 is b>0, that is, the IGZO layer, the composition of the first region A is desirably c≦3/5, b>0, b≧3a/7-3/14, b≧9a/5. -53/50, b≦-8a/5+33/25, b≦91a/74-17/40 (where a+b+c=1). In the case of such a composition region, since the first region A1 has a larger electron affinity than the second region A2, the conduction channel is formed in the first region A1. The carrier mobility is also larger in the above composition region, so that a high mobility exceeding 20 cm ² /Vs can also be achieved.

Further, since the film of the first region A1 having the above-described composition has a high carrier concentration, it is difficult to obtain a sufficiently low shutdown current or switching characteristics when the film of the first region A1 is used alone as an active layer.

Further, the first area A1 is desirably b≦17a/23-28/115, b≧3a/37, b≧9a/5-53/50, b≦1/5 (where a+b+c=1 is set) ). If the composition of the first region A1 is within the composition range, field-effect mobility exceeding 30 cm ² /Vs can be achieved.

The first region is the form of the IZO layer

When the composition of the first region A1 is b=0, that is, the IZO layer, the composition of the first region A1 is desirably a composition range of 0.4≦a≦0.75. In such a composition range, since the first region A1 has a larger electron affinity than the second region A2, the conduction channel in the laminated thin film transistor is formed in the first region A1. In the region A1 having the above composition, the carrier mobility is also larger, so that a high mobility exceeding 30 cm ² /Vs can also be achieved.

Further, the first region A1 is desirably within the composition range represented by 0.4 ≦ a ≦ 0.5. If it is within this composition range, the field-effect mobility exceeding 30 cm ² /Vs and the normal break (Id of Vg = 0 V is 1 × 10 ^-9 A or less) can be simultaneously achieved.

In either form, the thickness of the first region A1 is desirably less than 10 nm. The first region A1 is preferably an IZO film or an IGZO film rich in In which is easy to achieve high mobility, but such a high mobility film has a large concentration and a negative displacement to the negative side due to a high carrier concentration. The possibility. When the thickness of the first region A1 is 10 nm or more, the total carrier concentration in the active layer is excessive, and it is difficult to pinch-off.

On the other hand, in any of the aspects, the thickness of the first region A1 is preferably 5 nm or more from the viewpoint of obtaining uniformity of the oxide semiconductor layer 12 and high mobility.

- Zone 2 -

The second region A2 of the oxide semiconductor layer 12 is located on the opposite side of the surface of the first region A1 that is in contact with the gate insulating film 15 with respect to the gate electrode 16 on the side away from the first region A1, and is In _{(e) ) Ga (f) Zn (g} ) O (h) (e> 0, f> 0, g> 0, h> 0, and e + f + g = 1) indicates, satisfies f / (e + f) ≧ 0.80 and an IGZO layer different from the first region A1.

Since the second region A2 is an IGZO layer having a very high Ga content with respect to In, it is possible to suppress the inflow of carriers into the first region A1 and the formation of a parasitic conduction path therewith, so that high light stability can be achieved.

The thickness of the second region A2 is desirably 30 nm or more. When the thickness of the second region A2 is 30 nm or more, it is possible to more reliably expect a decrease in the shutdown current. On the other hand, when the thickness of the second region A2 is 10 nm or less, there is a concern that the shutdown current increases or the S value deteriorates. In addition, the thickness of the second region A2 is desirably smaller than 70nm. When the thickness of the second region is 70 nm or more, the decrease in the off current is expected, but the electric resistance between the source-drain electrode layer and the first region A1 increases, and as a result, the mobility may be lowered. Therefore, the thickness of the second region A2 is desirably more than 10 nm and less than 70 nm.

Oxide semiconductor layer as a whole

The film thickness (total film thickness) of the entire oxide semiconductor layer 12 is preferably about 10 nm to 200 nm, more preferably 35 nm or more and less than 80 nm from the viewpoint of film uniformity and patterning property.

The oxide semiconductor layer 12 (including the first region A1 and the second region A2) is preferably amorphous. When the first region A1 and the second region A2 are amorphous films, crystal grain boundaries are not present, and a film having high uniformity can be obtained.

Further, whether or not the laminated film including the first region A1 and the second region A2 is amorphous can be confirmed by X-ray diffraction measurement. That is, when a clear peak indicating a crystal structure is not detected by X-ray diffraction measurement, it can be judged that the laminated film is amorphous.

The control of the carrier concentration of the oxide semiconductor layer 12 is performed by adjusting the composition of each of the regions A1 and A2, and by controlling the partial pressure of oxygen at the time of film formation.

Specifically, the control of the oxygen concentration can be performed by controlling the partial pressure of oxygen at the time of film formation of the first region A1 and the second region A2, respectively. When the oxygen partial pressure at the time of film formation is increased, the carrier concentration can be lowered, and a decrease in the shutdown current can be expected. On the other hand, if the partial pressure of oxygen at the time of film formation is lowered, the concentration of the carrier can be increased, and the field effect can be expected. The increase in mobility. Further, for example, by performing a treatment of irradiating oxygen radicals or ozone after film formation in the first region A1, oxidation of the film can be promoted, and the amount of oxygen vacancies in the first region A1 can be lowered.

In addition, by doping a part of Zn having a wider band gap in a part of Zn including the oxide semiconductor layer 12 of the first region A1 and the second region A2, it is possible to impart stable light irradiation with an increase in optical band gap. Sex. Specifically, the band gap of the film can be increased by doping Mg. For example, by doping Mg in each of the regions of the A1 layer and the A2 layer, the band profile state of the laminated film can be maintained as compared with a system in which only the composition ratio of In, Ga, and Zn is controlled. Increase the band gap.

Since the blue light-emitting layer used for the organic EL exhibits a wide range of light emission having a peak at around λ = 450 nm, it is assumed that the optical band gap of the IGZO film is relatively narrow and the region has optical absorption, which causes a threshold of the transistor. Displacement. Therefore, particularly as a thin film transistor used in organic EL driving applications, it is preferred that the material for the channel layer has a larger band gap.

Further, the carrier density of the first region A1 and the second region A2 can be arbitrarily controlled by doping cations. When it is desired to increase the carrier density, it is sufficient to dope a material (for example, Ti, Ta, or the like) which is likely to be a cation having a relatively large valence. However, when a cation having a large valence is used, the number of constituent elements of the oxide semiconductor film is increased, so that it is disadvantageous in terms of simplification and cost reduction of the film formation process, and therefore it is preferable to use oxygen concentration (oxygen vacancy amount). ) Control the carrier density.

(source-drain electrode)

If both the source electrode 13 and the drain electrode 14 have high conductivity, the material and The structure is not particularly limited. For example, metals such as Al, Mo, Cr, Ta, Ti, Au, Ag, metal oxides such as Al-Nd, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), and indium zinc oxide (IZO) can be used. The conductive film or the like is formed into a single layer or a laminated structure of two or more layers to form the source electrode 13 and the drain electrode 14.

When the source electrode 13 and the drain electrode 14 are made of the above metal or metal oxide, the thickness is independent, preferably in consideration of film formability, patterning property by etching or lift-off method, conductivity, and the like. It is preferably 10 nm or more and 1000 nm or less, and more preferably 50 nm or more and 100 nm or less.

(gate insulating film)

The gate insulating film 15 is a layer in which the gate electrode 16 and the oxide semiconductor 12, the source electrode 13, and the drain electrode 14 are insulated from each other, and it is preferable to have high insulating properties. For example, the gate insulating film 15 may be formed of an insulating film of SiO ₂ , SiNx, SiON, Al ₂ O ₃ , Y ₂ O ₃ , Ta ₂ O ₅ , HfO ₂ or the like, or an insulating film containing two or more of these compounds.

Further, the gate insulating film 15 must have a sufficient thickness in order to reduce leakage current and improve voltage resistance. On the other hand, if the thickness is too large, the driving voltage is increased. The thickness of the gate insulating film 15 is also dependent on the material, and is preferably 10 nm to 10 μm, more preferably 50 nm to 1000 nm, and particularly preferably 100 nm to 400 nm.

(gate electrode)

The gate electrode 16 is not particularly limited as long as it has high conductivity. For example, metals such as Al, Mo, Cr, Ta, Ti, Au, Ag, etc., Al-Nd, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), indium zinc oxide (IZO), etc. may be oxidized. The conductive film of the object or the like is formed into a single layer or a laminated structure of two or more layers to form a gate electrode.

When the gate electrode 16 is made of the above metal or metal oxide, the thickness is preferably 10 nm or more and 1000 nm or less in consideration of film formability, patterning property by etching or lift-off method, conductivity, and the like. More preferably, it is 50 nm or more and 200 nm or less.

<Method of Manufacturing Thin Film Transistor>

Next, a method of manufacturing the bottom gate-top contact type thin film transistor 1 shown in FIG. 1 will be described. In addition, each constituent material, thickness, and the like are omitted in the following description in order to avoid redundancy.

(formation of gate electrode)

First, the substrate 11 is prepared, and a layer other than the thin film transistor 1 is formed on the substrate 11 as needed, and then the gate electrode 16 is formed.

The gate electrode 16 is subjected to a wet method such as a printing method or a coating method, a physical method such as a vacuum deposition method, a sputtering method, or an ion plating method, depending on the suitability of the material to be used, and chemical vapor deposition ( The film formation may be carried out by a method selected as appropriate in chemical methods such as chemical vapor deposition (CVD) and plasma CVD. For example, after the electrode film is formed into a film and patterned into a specific shape by etching or lift-off, the gate electrode 16 is formed. At this time, it is preferable to simultaneously pattern the gate electrode 16 and the gate wiring.

(Formation of gate insulating film)

After the gate electrode 16 is formed, the gate insulating film 15 is formed.

The gate insulating film 15 is in a wet manner such as a printing method or a coating method depending on the suitability of the material to be used, a vacuum evaporation method, a sputtering method, and an ion plating method. It is sufficient to form a film by a physical method such as a chemical method such as CVD or plasma CVD. For example, the gate insulating film 15 can be patterned into a specific shape by photolithography and etching.

(Formation of an oxide semiconductor layer)

Next, the first region A1 and the second region A2 are sequentially formed on the gate insulating film 15 at a position facing the gate electrode 16 to form an oxide semiconductor layer 12.

The method of forming the first region A1 and the second region A2 constituting the oxide semiconductor layer 12 is not particularly limited, and it is preferable to form a film by a sputtering method. Since the sputtering method has a high film formation rate and a film having high uniformity can be formed, a low-cost and large-area oxide semiconductor film can be formed. When forming a film by sputtering, for example, when forming an IGZO film, a composite oxide target which is adjusted in advance so as to have a desired cation composition can be used, and In ₂ O ₃ or Ga ₂ O ₃ can also be used. ZnO 3 yuan common sputtering.

The substrate temperature in the film formation can be arbitrarily selected depending on the substrate. However, when a resin flexible substrate is used, in order to prevent deformation of the substrate or the like, the substrate temperature is preferably closer to room temperature.

When the first region A1 is an IGZO-based oxide semiconductor, as the oxide semiconductor layer 12, for example, In _(a) Ga _(b) Zn _(c) O _(d) (c≦3/5, b>) 0, b≧3a/7-3/14, b≧9a/5-53/50, b≦-8a/5+33/25, b≦91a/74-17/40 (where a+b+ is set) The first region A1 indicated by c=1)) and the side closer to the gate electrode 16 than the first region A1 are represented by In _(e) Ga _(f) Zn _(g) O _(h) and satisfy f/ (e+f) ≧ 0.80, and the second region A2 having a composition different from the first region A1 is formed into a film.

On the other hand, when the first region A1 is an IZO-based oxide semiconductor, as the oxide semiconductor layer 12, for example, In _(a) Zn _(c) O _(d) (a > 0, c > 0, The first region A1 indicated by a+c=1, preferably 0.4≦a≦0.75), and the side of the first region A1 away from the gate electrode 16 and In _(e) Ga _(f) Zn _{(g) )} O _(h), said satisfies f / (e + f) ≧ 0.80, and the composition of the second region and the first region A1 and A2 respectively different deposition.

In addition, the film formation in the second region A2 may be a method in which film formation is temporarily stopped after film formation in the first region A1, and oxygen partial pressure in the deposition chamber and electric power applied to the target are changed, and then film formation is resumed; The method of changing the oxygen partial pressure in the deposition chamber and the electric power applied to the target quickly or slowly without stopping the film formation.

In addition, the target may be changed by directly using the target used for film formation in the first region A1, or may be stopped when the film is switched from the first region A1 to the second region A2. A method of applying electric power to a target used for film formation in the first region A1, and applying electric power to a different target including In, Ga, and Zn; and further, in addition to the target used for film formation of the first region A1, A method of applying electric power to each target.

The substrate temperature at the time of forming the second region A2 can be arbitrarily selected depending on the substrate. However, when a resin flexible substrate is used, it is preferable that the substrate temperature is further close to room temperature as in the case of film formation in the first region A1. .

When each of the regions A1 and A2 is formed by sputtering, it is preferred that the oxide semiconductor layer 12 is continuously formed without being exposed to the atmosphere. By forming the film without exposing the oxide semiconductor layer 12 to the atmosphere, it is possible to prevent the regions A1 and A2 in each region. Impurities are mixed in between, and as a result, more excellent transistor characteristics can be obtained. Further, since the number of film forming steps can be reduced, the manufacturing cost can also be reduced.

Further, in the present embodiment, in the production of the bottom gate type thin film transistor 1, the oxide semiconductor layer 12 may be formed in the order of the first region A1 and the second region A2, and the top gate shown in FIG. In the production of the polar thin film transistor 2, the film may be formed in the order of the second region A2 and the first region A1.

(post annealing)

After the oxide film which becomes the first region A1 and the second region A2 is formed into a film, heat treatment (post annealing) of 300 ° C or higher is performed in an oxidizing gas atmosphere, and more preferably 400 ° C or higher. When the heat treatment temperature is 400 ° C or higher, the light irradiation stability (for example, |ΔVth|≦0.1 V under light irradiation at 420 nm) can be extremely improved.

On the other hand, when heat treatment is performed at a temperature of 600 ° C or higher, cation diffusion occurs between the first region A1 and the second region A2, and the two regions are mixed. At this time, it is difficult to concentrate the carrier only in the first region A1. Therefore, it is desirable that the heat treatment temperature in the post-annealing step is less than 600 °C. In addition, whether or not mutual diffusion of cations is caused in the first region A1 and the second region A2 can be confirmed by, for example, analysis by a transmission electron microscope (TEM).

3 is a cross-sectional STEM (scanning electron microscope) image of a laminated film in which an IGZO film of Ga/(In+Ga)=0.75 and an IGZO film of Ga/(In+Ga)=0.25 are laminated in a total of five layers. , the figure (left; Fig. 3 (A)) shows the person just after lamination (before annealing treatment), the figure (right; Fig. 3 (B)) shows that the annealing temperature is 600 ° C Line handler. 3(A) and FIG. 3(B), it was confirmed that in the laminated structure of the IGZO film, even if it is annealed at 600 ° C, a certain layered structure is maintained, but at the interface of different cation compositions, it is seen. The state of contrast blur. This suggests that the mutual diffusion of the different phases starts to occur, and the upper limit temperature in the heat treatment step is desirably 600 ° C or less.

Further, in the method for producing a thin film transistor of the present invention, it is preferred that the moisture content in the entire gas atmosphere is -36 ° C or less (absolute humidity: 0.21 g / m ^-3 or less) in terms of dew point temperature. Annealing in a gaseous environment. By performing annealing in the dry gas atmosphere, light stability can be improved as compared with the case of annealing in a humid gas atmosphere (for example, an atmosphere or the like).

Next, the oxide semiconductor layer 12 is patterned. Patterning can be performed by photolithography and etching. Specifically, a resist pattern is formed by photolithography in a remaining portion, and an exposed portion is etched by an acid solution such as hydrochloric acid, nitric acid, dilute sulfuric acid, or a mixed solution of phosphoric acid, nitric acid, and acetic acid to form an oxide semiconductor. The pattern of layer 12.

(Formation of source-drain electrodes)

Next, a metal film for forming the source electrode 13 and the drain electrode 14 is formed on the oxide semiconductor layer 12.

The source electrode 13 and the drain electrode 14 are each a wet type such as a printing method or a coating method, and a physical method such as a vacuum deposition method, a sputtering method, or an ion plating method, depending on the suitability of the material to be used. In the method, a film may be formed by a method selected as appropriate in a chemical method such as CVD or plasma CVD.

Forming a metal film into a specific shape by, for example, etching or stripping Source electrode 13 and drain electrode 14. At this time, it is preferable to simultaneously pattern the source electrode 13 and the drain electrode 14 and the wiring (not shown) connected to the electrode 13 and the electrode 14.

According to the above procedure, the thin film transistor 1 shown in Fig. 1 can be produced.

By using the method for producing a thin film transistor of the present invention, a protective layer or the like for reducing deterioration of characteristics against light irradiation is used for the active layer, and high mobility and high light irradiation stability can be obtained. It is of course also possible to provide a protective layer as described above on the active layer. For example, stability against light irradiation can be further improved by providing a protective layer that absorbs and reflects light in an ultraviolet region (having a wavelength of 400 nm or less).

The thin film transistor of the present invention is a one which suppresses the hump effect and has high light irradiation stability, and can be applied to various elements. The display device and the sensor of the present invention using the thin film transistor of the present invention can exhibit good characteristics by low power consumption. In addition, the "characteristic" as used herein is a display characteristic at the time of a display device and a sensitivity characteristic at the time of a sensor.

<Liquid crystal display device>

FIG. 7 is a schematic cross-sectional view showing a part of a liquid crystal display device as an embodiment of a display device including the thin film transistor of the present invention, and FIG. 8 is a schematic configuration view of the electric wiring.

As shown in FIG. 7, the liquid crystal display device 5 of the present embodiment includes the top gate-bottom contact type thin film transistor 2 shown in FIG. 2, and the gate electrode 16 of the thin film transistor 2 protected by the passivation layer 54. From the lower electrode of the pixel 55 and its upper part The liquid crystal layer 57 sandwiched between the electrodes 56 and the RGB color filter 58 for emitting light of different colors corresponding to each pixel, and having a polarizing plate 59a on the substrate 11 side of the TFT 2 and the color filter 58, respectively. The configuration of the polarizing plate 59b.

In addition, as shown in FIG. 8 , the liquid crystal display device 5 of the present embodiment includes a plurality of gate wirings 51 that are parallel to each other, and a data wiring 52 that is parallel to the gate wirings 51 and that is parallel to each other. Here, the gate wiring 51 is electrically insulated from the data wiring 52. A thin film transistor 2 is provided in the vicinity of the intersection of the gate wiring 51 and the data wiring 52.

The gate electrode 16 of the thin film transistor 2 is connected to the gate wiring 51, and the source electrode 13 of the thin film transistor 2 is connected to the data wiring 52. Further, the drain electrode 14 of the thin film transistor 2 is electrically connected to the pixel lower electrode 55 via a contact hole 19 provided in the gate insulating film 15 (a conductor is embedded in the contact hole 19). The pixel lower electrode 55 and the grounded opposite electrode 56 constitute a capacitor 53.

The liquid crystal device of the present embodiment shown in FIG. 7 is provided with a top gate type thin film transistor. However, the thin film transistor used in the liquid crystal device as the display device of the present invention is not limited to the top gate type. It can also be a bottom gate type thin film transistor.

Since the thin film transistor of the present invention has high mobility, it is possible to realize high-quality display with high definition, high-speed response, high contrast, and the like in a liquid crystal display device, and is also suitable for a large screen. In addition, when the active layer (oxide semiconductor layer) 12 is amorphous, it is possible to suppress unevenness in device characteristics and achieve excellent display quality without unevenness in a large screen. Moreover, since the characteristic displacement is small, the gate voltage can be lowered, and the power consumption of the display device can be reduced.

<Organic EL display device>

FIG. 9 is a schematic cross-sectional view showing a part of an active matrix type organic EL display device, and FIG. 10 is a schematic configuration view of the electric wiring.

There are two types of driving methods for the organic EL display device: a simple matrix method and an active matrix method. The simple matrix method has the advantage of being able to be manufactured at low cost, but since the pixels are illuminated by selecting the scanning lines one by one, the number of scanning lines is inversely proportional to the lighting time of each scanning line. Therefore, it is difficult to achieve high definition and large screen. In the active matrix method, since a transistor or a capacitor is formed in each pixel, the manufacturing cost is high, but there is no problem that the number of scanning lines cannot be increased as in the simple matrix method. Therefore, it is suitable for high definition and large screen.

In the active matrix type organic EL display device 6 of the present embodiment, the substrate 60 including the passivation layer 61a is provided with a top gate-top contact type thin film transistor as the driving TFT 2a and the switching TFT 2b. The thin film transistor 2a and the thin film transistor 2b are provided with an organic light-emitting element 65 including an organic light-emitting layer 64 sandwiched between the lower electrode 62 and the upper electrode 63, and the upper surface is also protected by a passivation layer 61b.

In addition, as shown in FIG. 10, the organic EL display device 6 of the present embodiment includes a plurality of gate wirings 66 that are parallel to each other, and a data wiring 67 and a driving wiring 68 that are parallel to each other and intersect with the gate wiring 66. Here, the gate wiring 66 is electrically insulated from the data wiring 67 and the driving wiring 68. The gate electrode 16b of the thin film transistor 2b for switching is connected to the gate wiring 66, and the source electrode 13b of the thin film transistor 2b for switching It is connected to the data wiring 67. Further, the drain electrode 14b of the switching thin film transistor 2b is connected to the gate electrode 16a of the driving thin film transistor 2a, and the driving thin film transistor 2a is maintained in an on state by using the capacitor 69. The source electrode 13a of the driving thin film transistor 2a is connected to the driving wiring 68, and the drain electrode 14a is connected to the organic EL light emitting element 65.

The organic EL device of the present embodiment shown in FIG. 9 also includes a top gate type thin film transistor 2a and a top gate type thin film transistor 2b, but is used in an organic EL device as a display device of the present invention. The transistor is not limited to the top gate type, and may be a bottom gate type thin film transistor.

Since the thin film transistor of the present invention has high mobility, power consumption is low and high-quality display can be realized. Therefore, according to the present invention, it is possible to provide a flexible organic EL display device having excellent display quality.

Further, in the organic EL display device shown in FIG. 9, the upper electrode 63 can be made into a top emission type as a transparent electrode, and each electrode of the lower electrode 62, the TFT 2a, and the TFT 2b can be used as a transparent electrode. It is a bottom-emitting type.

<X-ray sensor>

Fig. 11 is a schematic cross-sectional view showing a part of an X-ray sensor which is one embodiment of the sensor of the present invention, and Fig. 12 is a schematic configuration view of the electric wiring.

The X-ray sensor 7 of the present embodiment includes a thin film transistor 2 and a capacitor 70 formed on the substrate 11, a charge collection electrode 71 formed on the capacitor 70, an X-ray conversion layer 72, and an upper electrode 73. A passivation film 75 is provided on the thin film transistor 2.

The capacitor 70 has a structure in which the insulating film 78 is sandwiched between the capacitor lower electrode 76 and the capacitor upper electrode 77. The capacitor upper electrode 77 is connected to any of the source electrode 13 and the drain electrode 14 of the thin film transistor 2 (the gate electrode 14 in FIG. 11) via the contact hole 79 provided in the insulating film 78.

The charge collection electrode 71 is provided on the capacitor upper electrode 77 in the capacitor 70, and is in contact with the capacitor upper electrode 77. The X-ray conversion layer 72 is a layer containing amorphous selenium, and is provided in such a manner as to cover the thin film transistor 2 and the capacitor 70. The upper electrode 73 is disposed on the X-ray conversion layer 72 and is in contact with the X-ray conversion layer 72.

As shown in FIG. 12, the X-ray sensor 7 of the present embodiment includes a plurality of gate wirings 81 that are parallel to each other, and a plurality of data wirings 82 that cross the gate wirings 81 and are parallel to each other. Here, the gate wiring 81 is electrically insulated from the data wiring 82. The thin film transistor 2 is provided in the vicinity of the intersection of the gate wiring 81 and the data wiring 82.

The gate electrode 16 of the thin film transistor 2 is connected to the gate wiring 81, and the source electrode 13 of the thin film transistor 2 is connected to the data wiring 82. Further, the drain electrode 14 of the thin film transistor 2 is connected to the charge collection electrode 71, and the charge collection electrode 71 and the grounded opposite electrode 76 constitute a capacitor 70.

In the X-ray sensor 7 of the present configuration, the X-ray is irradiated from the upper portion (the upper electrode 73 side) in FIG. 11, and an electron-hole pair is generated in the X-ray conversion layer 72. A high electric field is applied to the X-ray conversion layer 72 by the upper electrode 73, and the generated charges are accumulated in the capacitor 70, and the thin film transistor 2 is sequentially scanned to be read.

The X-ray sensor of the present invention has high current and reliability due to the on-state current Since the thin film transistor 2 is excellent in S/N and excellent in sensitivity characteristics, an image having a wide dynamic range can be obtained when used in an X-ray digital photographing apparatus.

In particular, the X-ray digital photographing apparatus of the present invention is preferably used for an X-ray digital photographing apparatus, which can perform photographing of a moving image and photography of a still image, and not only static image capturing. Further, when the first region A1 and the second region A2 constituting the active layer in the thin film transistor 2 are amorphous, an image excellent in uniformity can be obtained.

Further, the X-ray sensor of the present embodiment shown in FIG. 11 includes a top gate type thin film transistor, but the thin film transistor used in the sensor of the present invention is not limited to the top gate type. It can also be a bottom gate type thin film transistor.

[Examples]

The experimental examples are described below, but the present invention is not limited to these examples.

The present inventors have used the following experiment to verify that the hump effect can be suppressed by laminating an oxide semiconductor of a specific composition, and at the same time, it has high light irradiation stability (|ΔVth|≦1V (light at 420 nm) Under irradiation)).

<A2 layer composition dependence of TFT characteristics>

It was verified by fabricating a TFT having the following structure that high light stability was obtained by laminating an oxide semiconductor film of a specific composition on the active layer of the thin film transistor.

First, a bottom gate and a top contact type thin film transistor as follows were fabricated.

As the substrate, a p-type tantalum substrate (manufactured by Mitsubishi Materials Co., Ltd.) which is doped with a high concentration doped with an oxide film of SiO ₂ of 100 nm on the surface is used.

Next, a first region (A1 layer) and a second region (A2 layer) are sequentially laminated on the p-type germanium substrate as an oxide semiconductor layer. The sputtering conditions other than the composition of each region are as follows, and are common to the following experiments.

(sputter condition of the first area A1)

Reaching vacuum: 6×10 ^-6 Pa

Film formation pressure: 4.4 × 10 ^-1 Pa

Film formation temperature: room temperature

Oxygen partial pressure / argon partial pressure: 0.067

(sputtering conditions of the second region A2)

Reaching vacuum: 6×10 ^-6 Pa

Film formation pressure: 4.4 × 10 ^-1 Pa

Film formation temperature: room temperature

Oxygen partial pressure / argon partial pressure: 0.033

After the oxide semiconductor layer was formed by sputtering, an electrode layer containing Ti (10 nm)/Au (40 nm) was formed on the laminated film by a sputtering method interposed with a metal mask. After the formation of the electrode layer, post-annealing treatment was performed in a gas atmosphere at 400 ° C and a partial pressure of oxygen of 100%.

According to the above, as the bottom gate type thin film transistor having a channel length of 180 μm and a channel width of 1 mm, TFTs of Examples 1 to 15, Example A to Example C, and Comparative Example 1 to Comparative Example 4 were obtained. And carry out the following evaluation.

[mobility]

For the TFTs of Examples 1 to 15, Example A, Example B, and Example C and Comparative Example 1 to Comparative Example 4, a semiconductor parameter analyzer 4156C (trade name; Agilent Technologies) was used. Manufactured by the company, the measurement of the transistor characteristics (Vg-Id characteristics) and the mobility μ was performed.

The Vg-Id characteristic is measured by fixing the gate voltage (Vd) to 10 V, scanning the gate voltage (Vg) in the range of -30 V to +30 V, and measuring each gate voltage (Vg). The drain current (Id) in the middle. The off current is defined by the current value at Vg = 0 V in the Vg-Id characteristic.

Further, the mobility is calculated based on the Vg-Id characteristic of the linear region, and the Vg-Id characteristic of the linear region is in the range of -30V to +30V in a state where the gate voltage (Vd) is fixed to 1V. Internal scanning gate voltage (Vg) derived.

[Light irradiation stability]

After evaluating the Vg-Id characteristics of the produced TFT, the stability of the TFT characteristics for light irradiation was evaluated by irradiating monochromatic light having a variable wavelength. The outline of the measurement of the TFT characteristics under irradiation of monochromatic light is shown in Fig. 4 . As shown in Fig. 4, each TFT was placed on the probe stage 200, and the dry atmosphere was circulated for 2 hours, and then the TFT characteristics were measured in the dry atmosphere. The irradiation intensity of the monochromatic light source is set to 10 μW/cm ² , the range of the wavelength λ is set to 360 nm to 700 nm, and the Vg-Id characteristic when the monochromatic light is not irradiated is compared with the Vg-Id characteristic when the monochromatic light is irradiated. Thereby, the light irradiation stability (ΔVth) was evaluated. The measurement conditions of the TFT characteristics under the irradiation of the monochromatic light were measured by fixing the Vds=10 V and scanning the gate voltage in the range of Vg=-15 V to 15 V. In addition, all the measurements were performed after irradiating monochromatic light for 10 minutes, except for the case specifically mentioned below. The displacement amount ΔVth of the threshold value under light irradiation at 420 nm was used as an index of the light stability of the TFT.

(The first area is the case of the IGZO system)

Regarding the oxide semiconductor layer, In _(a) Ga _(b) Zn _(c) O _{(d) is} firstly performed at a thickness of 5 nm (a = 37/60, b = 3/60, c = 20/60, d > 0). The sputtering is performed as a first region A1.

In a state where the composition of the A1 layer is fixed, In _(e) Ga _(f) Zn _(g) O _(h) (e>0, f>0, g>0, h>0) is represented by a thickness of 50 nm. The IGZO layer was sputtered into a film as an A2 layer. The composition of the A2 layer was adjusted in the form of Table 2 below. The oxide semiconductor layer is continuously formed into a film without being exposed to the atmosphere between the respective regions. The sputtering of each of the regions A1 and A2 is performed by ternary co-sputtering using an In ₂ O ₃ target, a Ga ₂ O ₃ target, or a ZnO target. The film thickness adjustment of each of the regions A1 and A2 is performed by adjusting the film formation time.

The sputtering conditions of the second region (layer A2) and the characteristics of the produced TFT are shown in Table 2 below.

For the TFTs of Examples 1 to 3 and Comparative Example 1, monochromatic light was used. The I-V characteristic at the time of (wavelength: 420 nm) irradiation is shown in FIG. Further, the above evaluation methods are common to the following examples.

As is clear from Fig. 5, in the case of Comparative Example 1 in which f/(e+f) = 0.75, the hump effect of the peak in the I-V characteristic was remarkable due to the influence of the parasitic conduction path. On the other hand, it is understood that the hump effect is suppressed in the first to third embodiments which are set to f/(e+f) ≧ 0.80.

Further, in the TFT produced in Example 3, the Vg-Id characteristic under irradiation of monochromatic light in the range of 360 nm to 700 nm is shown in Fig. 6 . As can be seen from Fig. 6, in the TFT of the third embodiment, the hump effect can be suppressed regardless of the wavelength of light irradiation, and the threshold shift (?Vth) is small.

(The first area is the case of the IZO system)

In _(a) Zn _(c) O _(d) (a = 0.5, c = 0.5, d > 0) was sputtered into a film at a thickness of 5 nm as the first region A1. In a state where the composition of the A1 layer is fixed, In _(e) Ga _(f) Zn _(g) O _(h) (e>0, f>0, g>0, h>0) will be expressed at 50 nm. The IGZO layer was sputter-deposited as an A2 layer. The composition of the A2 layer was adjusted in the form of Table 2 below. The oxide semiconductor layer is continuously formed into a film without being exposed to the atmosphere between the respective regions. The sputtering in each region was carried out in the region of A1 and A2 by ternary co-sputtering using an In ₂ O ₃ target, a Ga ₂ O ₃ target, or a ZnO target. The film thickness adjustment of each region is performed by adjusting the film formation time.

The sputtering conditions of the second region (layer A2) and the characteristics of the produced TFT are shown in Table 3 below.

[table 3]

Table 2 summarizes the TFT characteristics when the first region is IGZO-based, but in Examples 1 to 3, the mobility exceeds 20 cm ² /Vs, and the threshold shift amount under 420 nm light irradiation Both are below 0.1V, and the result is extremely stable light.

Further, Table 3 shows the results when the first region was set to the IZO system, but the same results as in the case of the IGZO system were obtained.

Therefore, when the composition of the A1 layer is fixed, according to the above embodiment, it is understood that the hump effect can be suppressed by controlling the composition of the A2 layer, and as a result, high mobility and light stability can be simultaneously achieved.

<A1 layer composition dependence of TFT characteristics>

(The first area is the case of the IGZO system)

Next, the second region is fixed to the IGZO layer (f/(e+f)=0.85), and the first region A1 is in the IGZO system (In _(a) Ga _(b) Zn _(c) O _(d) ) The TFT characteristics at the time of composition modulation are summarized in Table 4.

According to Table 4, if the composition of the A1 layer is b≦91a/74-17/40, b≧3a/7-3/14, c≦3/5, b≧9a/5-53/50, b≦ A composition range represented by -8a/5+33/25 (where a+b+c=1) (Examples 7 to 15) can produce a TFT having a field effect mobility of 20 cm ² /Vs or more. Moreover, it can be seen that if the composition of the A1 layer is b≦17a/23-28/115, b≧3a/37, b≧9a/5-53/50, b≦1/5 (where a+b+c is set) When the composition range indicated by =1), a TFT having a field effect mobility of 30 cm ² /Vs or more can be produced.

On the other hand, in Examples A to C in which the In content was increased, although a high field-effect mobility was obtained, since the carrier concentration was excessive, the light was irradiated by 420 nm. The threshold value was significantly shifted to the negative side from the TFTs of Examples 7 to 15. For example, in the viewpoint of low power consumption, the elements of the embodiments A to C are not preferable to the elements of the seventh embodiment to the fifteenth embodiment.

Further, the composition of the A1 layer exceeded Comparative Example 3 and Comparative Example 4 except a>0, b≧0, c>0, d>0, a+b+c=1, and b≦91a/74-17/40. In the case of the TFT having a small amount of displacement due to light irradiation at 420 nm, the mobility is insufficient.

(The first area is the case of the IZO system)

The second region is fixed to the IGZO layer (f/(e+f)=0.85), and when the first region A1 is modulated in the IZO system (In _(a) Zn _(c) O _(d) ) The TFT characteristics are summarized in Table 5 below.

According to Table 5, when the first region is IZO-based and the composition range is represented by 0.40≦a≦0.75 (the composition range consisting of Examples 16 to 20), the field-effect mobility can be made more than 30 cm. ² /Vs TFT. Further, it is understood that a TFT having a field-effect mobility exceeding 30 cm ² /Vs and being normally broken can be produced within a composition range represented by 0.40 ≦ a ≦ 0.50.

On the other hand, when the ratio (a) of In is increased (Example D), the carrier concentration is excessive, and a negative value having a relatively large margin is obtained. On the other hand, it is also known that when the ratio (a) of In is reduced from the ideal composition range (Comparative Example 7), it becomes a TFT having extremely low mobility, and it is difficult to produce a high mobility element.

As described above, when the cation composition of the second region A2 is fixed, the composition of the first region (IGZO-based or IZO-based) in the laminated TFT structure can be adjusted to a specific composition range. The TFT characteristics of mobility.

With respect to the TFTs produced in the examples and the comparative examples, the composition range of the first region A1 is shown in FIG. 13 by a ternary phase diagram.

<A2 layer film thickness dependence of TFT characteristics>

Next, in order to investigate how the film thickness of the second region A2 affects the TFT characteristics, the following bottom gate and top contact type thin film transistors were produced as Examples 21 to 23 and Example E. At this time, the composition of the A1 layer was set to a=37/60, b=3/60, and c=20/60, and the composition of the A2 layer was set to IGZO layer (f/(e+f)=0.85). A transistor in which the film thickness of the A1 layer was set to 5 nm and only the film thickness of the A2 layer was changed to 10 nm, 30 nm, 50 nm, or 70 nm was produced. The film thickness of the A2 layer and the TFT characteristics are shown in Table 6.

As described above, when the thickness of the A2 layer is 10 nm or less, the mobility is high, but the S value is deteriorated (more than 1 V/10 times), and the shutdown current tends to increase. On the other hand, when the thickness of the A2 layer is 30 nm or more, the S value is expected to be good (1 V/10 times or less) and the shutdown current is lowered. Therefore, when the composition of the first region is the same, it is preferable that the film thickness of the second region exceeds 10 nm, and preferably 30 nm or more. Further, it is understood that when the film thickness of the second region is 70 nm, the mobility is slightly lowered. Therefore, it is more preferable that the film thickness of the second region A2 is less than 70 nm.

<A1 layer film thickness dependence of TFT characteristics>

In order to investigate how the film thickness of A1 affects the TFT characteristics, a bottom gate and a top contact type thin film transistor shown in Table 7 below were produced as Example 24 and Example 25. At this time, the composition of the A1 layer was set to a=37/60, b=3/60, and c=20/60, and the composition of the A2 layer was set to IGZO layer (f/(e+f)=0.85). In Example 25, the film thickness of the A1 layer was set to 10 nm.

As is clear from Table 7, when the film thickness of the A1 layer is 10 nm, the field effect mobility can be sufficiently ensured, but the threshold value is shifted to the negative side, and the shutdown current tends to increase. The reason for this is considered to be that the A1 layer uses an oxide semiconductor layer having a high carrier concentration, and if the film thickness of the A1 layer is increased, the total carrier concentration is increased and it is difficult to pinch. Therefore, it is understood that the thickness of the A1 layer is preferably less than 10 nm.

As described above, by modifying the composition and film thickness of the laminated structure A1 layer and the A2 layer of the active layer, it is possible to produce a TFT having a characteristic composition and a high mobility and high light stability among the film thickness.

<Relationship of post-annealing conditions of TFT>

In order to clarify the manner in which the TFT characteristics and the photostability were changed under post-annealing conditions, the post-annealing conditions were changed in the manner shown in Table 8 below using the same TFT structure and composition as in Example 21.

According to the above results, it is understood that at 300 ° C or higher, the oxidizing gas atmosphere has both high mobility and high light stability. On the other hand, when annealing is performed in an inert gas such as argon gas, the hump effect is remarkable and the photostability is not high. The reason for this is considered to be that when annealing is performed in an inert gas, a low-resistance parasitic conduction path is generated on the surface or inside of the active layer due to the detachment of oxygen from the surface or the inside of the active layer, thereby generating a hump effect. Therefore, it is understood that in the heat treatment step, annealing is preferably performed in an oxidizing gas atmosphere.

In addition, according to Example 26 and Example 27, high light stability can be obtained under heat treatment conditions of 300 ° C or higher under the same annealing gas atmosphere, while according to Example 27, Example 29, and Example 30 It can be seen that when the heat treatment temperature is set to 400 ° C or higher, the light stability can be improved as much as possible (light irradiation at 420 nm) The amount of ΔVth below is 0.1 V or less).

Further, according to the results of Example 27 and Example 28, it is understood that the annealing is performed in an oxygen 100% gas atmosphere (supply from a gas storage tank, the humidity is 1% or less), and in the atmosphere (humidity is about 50%). In the case of the treatment, the light stability is higher, and therefore it is desirable to dry the moisture content in the entire gas atmosphere to -36 ° C or less (absolute humidity of 0.21 g / m ^-3 or less) in terms of dew point temperature. Annealing in a gaseous environment.

Further, for example, according to the comparison between Example 27 and Example 32, even in the same dew point temperature, 100% oxygen in slightly 100% oxygen and 20% oxygen can slightly improve light stability. Further, according to Example 28, Example 33, and Example 34, it is understood that reducing the humidity enhances light stability.

The use of the thin film transistor of the present invention described above is not particularly limited, and is suitable, for example, as a display device (for example, a liquid crystal display device, an organic EL (Electro Luminescence) display device, an inorganic EL display device, etc.) as an electro-optical device. Drive component.

Further, the thin film transistor of the present invention is suitably used as an element of a flexible display or the like which can be produced by a low-temperature process using a resin substrate, a charge coupled device (CCD), a complementary metal oxide semiconductor (Complementary Metal Oxide). Semiconductor, CMOS), etc., various types of sensors such as image sensors, X-ray sensors, and drive elements (drive circuits) in various electronic components such as Micro Electro Mechanical System (MEMS).

The display device and the sensor of the present invention using the thin film transistor of the present invention exhibit good characteristics by low power consumption. In addition, the "characteristic" here is a display characteristic at the time of a display device, and is a sensitivity characteristic at the time of a sensor.

The disclosure of Japanese Patent Application No. 2012-110772 is incorporated herein in its entirety by reference.

All the documents, patent applications, and technical standards described in the present specification are incorporated by reference to the respective documents, patent applications, and technical standards, to the extent that they are specifically and separately described, Into this manual.

1‧‧‧film transistor

11‧‧‧Substrate

12‧‧‧Oxide semiconductor layer

13‧‧‧Source electrode

14‧‧‧汲electrode

15‧‧‧gate insulating film

16‧‧‧gate electrode

A1‧‧‧1st area

A2‧‧‧2nd area

Claims (14)

A method for producing a thin film transistor, comprising: a film forming step of forming a first region and a second region as having a gate electrode, a gate insulating film, an oxide semiconductor layer, a source electrode, and a drain electrode In the above oxide semiconductor layer of the thin film transistor of the electrode, the first region has In _(a) Ga _(b) Zn _(c) O _(d) (a > 0, b ≧ 0, c > 0, d > 0) And a+b+c=1) indicates that the composition of b≦91a/74-17/40 is satisfied; and the second region is disposed on a side farther from the gate electrode than the first region, and has In _{(e) ) Ga (f) Zn (g} ) O (h) (e> 0, f> 0, g> 0, h> 0, and e + f + g = 1) indicates, the composition of the first region is different and a composition satisfying 1.0>f/(e+f)≧0.85; a heat treatment step in which the oxide semiconductor layer is 400° C. or more and less than 400° C. in an oxidizing gas atmosphere having a partial pressure of oxygen of 100% after the film forming step. The heat treatment was carried out at 600 °C. The method for producing a thin film transistor according to the first aspect of the invention, wherein the gas atmosphere in the heat treatment step is a dryness of -36 ° C or less in terms of a dew point temperature in a moisture content of the entire gas atmosphere. Gas environment. A thin film transistor having a gate electrode, a gate insulating film, an oxide semiconductor layer, a source electrode, and a drain electrode, wherein the oxide semiconductor layer includes: a first region having In _(a) Ga _(b) Zn _(c) O _(d) (a>0, b≧0, c>0, d>0, and a+b+c=1) indicates and satisfies b≦91a/74-17/40 And a second region disposed on a side farther from the gate electrode than the first region, having In _(e) Ga _(f) Zn _(g) O _(h) (e>0, f >0) , g>0, h>0, and e+f+g=1) indicates that the composition is different from the first region, and satisfies a composition of 1.0>f/(e+f)≧0.85, and the second region The film thickness is 50 nm or more and less than 70 nm. The thin film transistor according to claim 3, wherein the composition of the first region satisfies: c≦3/5, b>0, b≧3a/7-3/14, b≧9a/5- 53/50, b≦-8a/5+33/25, and b≦91a/74-17/40 range. The thin film transistor according to claim 3, wherein the composition of the first region satisfies: b≦17a/23-28/115, b≧3a/37, b≧9a/5-53/50, And b≦1/5 range. The thin film transistor according to claim 3, wherein the composition of the first region is b=0. The thin film transistor according to claim 6, wherein the first The composition of the area is 0.4≦a≦0.75. The thin film transistor according to claim 6, wherein the composition of the first region is 0.4 ≦ a ≦ 0.5. The thin film transistor according to the third aspect of the invention, wherein the first region has a film thickness of 5 nm or more and less than 10 nm. The thin film transistor according to claim 3, wherein the oxide semiconductor layer is amorphous. A display device comprising: the thin film transistor according to any one of claims 3 to 10. An image sensor comprising the thin film transistor according to any one of claims 3 to 10. An X-ray sensor comprising the thin film transistor according to any one of claims 3 to 10. An X-ray digital photographing apparatus comprising the X-ray sensor according to claim 13 of the patent application.