TWI575745B - Mos transistor and process thereof - Google Patents
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本發明係關於一種MOS電晶體及其製程,且特別係關於一種具有金屬閘極的MOS電晶體及其製程。 The present invention relates to a MOS transistor and a process thereof, and more particularly to a MOS transistor having a metal gate and a process therefor.
在習知半導體產業中,多晶矽係廣泛地應用於半導體元件如金氧半導體(metal-oxide-semiconductor,MOS)電晶體中,作為標準的閘極填充材料選擇。然而,隨著MOS電晶體尺寸持續地微縮,傳統多晶矽閘極因硼穿透(boron penetration)效應導致元件效能降低,及其難以避免的空乏效應(depletion effect)等問題,使得等效的閘極介電層厚度增加、閘極電容值下降,進而導致元件驅動能力的衰退等困境。因此,半導體業界更嘗試以新的閘極填充材料,例如利用功函數(work function)金屬來取代傳統的多晶矽閘極,用以作為匹配高介電常數(High-K)閘極介電層的控制電極。 In the conventional semiconductor industry, polycrystalline lanthanide is widely used in semiconductor components such as metal-oxide-semiconductor (MOS) transistors as a standard gate filling material. However, as the size of the MOS transistor continues to shrink, the conventional polysilicon gate causes a decrease in component efficiency due to boron penetration effects, and an unavoidable depletion effect, etc., resulting in an equivalent gate. The thickness of the dielectric layer increases, and the value of the gate capacitance decreases, which leads to the dilemma of the deterioration of the component driving capability. Therefore, the semiconductor industry is trying to replace the traditional polysilicon gate with a new gate filling material, such as a work function metal, to match the high dielectric constant (High-K) gate dielectric layer. Control electrode.
本發明提出一種MOS電晶體及其製程,其將低電阻率材料擴散至潤濕層而形成具有功函數層功能的過渡層,因此不需再另外形成功函數層。 The present invention provides a MOS transistor and a process thereof for diffusing a low resistivity material to a wetting layer to form a transition layer having a function of a work function layer, so that it is not necessary to additionally form a success function layer.
本發明提供一種MOS電晶體,包含有一閘極結構位於一基底上,且閘極結構由下至上包含一潤濕層、一過渡層以及一低電阻率 材料,其中過渡層具有一功函數層的功能,而閘極結構中不含有任何的功函數層。 The invention provides an MOS transistor, comprising a gate structure on a substrate, and the gate structure comprises a wetting layer, a transition layer and a low resistivity from bottom to top A material in which the transition layer has the function of a work function layer, and the gate structure does not contain any work function layer.
本發明提供一種MOS電晶體製程,包含有下述步驟。形成一閘極結構於一基底上,且閘極結構由下至上包含一潤濕層、一過渡層以及一低電阻率材料,其中過渡層係由低電阻率材料擴散至潤濕層所形成,且過渡層具有一功函數層的功能,而閘極結構中不含有任何的功函數層。 The present invention provides a MOS transistor process comprising the following steps. Forming a gate structure on a substrate, and the gate structure comprises a wetting layer, a transition layer and a low resistivity material from bottom to top, wherein the transition layer is formed by diffusion of the low resistivity material to the wetting layer, And the transition layer has the function of a work function layer, and the gate structure does not contain any work function layer.
基於上述,本發明提供一種MOS電晶體及其製程,其先形成一潤濕層以及一低電阻率材料,再藉由將低電阻率材料之成分擴散至潤濕層,而形成一過渡層於潤濕層以及低電阻率材料之間。過渡層具有一功函數層的功能,因而本發明所形成之金屬閘極中不需再含有其他的功函數層。如此一來,本發明之MOS電晶體及其製程,可改善填洞困難的問題以及降低製程成本。 Based on the above, the present invention provides a MOS transistor and a process thereof, which first form a wetting layer and a low resistivity material, and then form a transition layer by diffusing a component of the low resistivity material to the wetting layer. Between the wetting layer and the low resistivity material. The transition layer has the function of a work function layer, so that the metal gate formed by the present invention does not need to contain another work function layer. In this way, the MOS transistor of the present invention and the process thereof can improve the problem of filling holes and reduce the process cost.
以下係以將本發明搭配一前置高介電常數後閘極(Gate-Last for High-K First)製程為例,但在其他實施例中本發明亦可應用於一後置高介電常數後閘極(Gate-Last for High-K Last)製程等,但本發明不以此為限。 The following is an example in which the present invention is combined with a Gate-Last for High-K First process, but in other embodiments, the present invention can also be applied to a post-high dielectric constant. The Gate-Last for High-K Last process, etc., but the invention is not limited thereto.
第1-6圖係繪示本發明一第一實施例之MOS電晶體製程之剖面示意圖。如第1圖所示,提供一基底110,基底110例如是一矽基底、一含矽基底、一三五族覆矽基底(例如GaN-on-silicon)、一石墨 烯覆矽基底(graphene-on-silicon)或一矽覆絕緣(silicon-on-insulator,SOI)基底等半導體基底。形成一絕緣結構10於基底110中,以電性絕緣各電晶體。絕緣結構10例如為一淺溝隔離(shallow trench isolation,STI)結構,其例如以一淺溝隔離製程形成,詳細形成方法為本領域所熟知故不再贅述,但本發明不以此為限。 1 to 6 are schematic cross-sectional views showing a process of a MOS transistor according to a first embodiment of the present invention. As shown in FIG. 1, a substrate 110 is provided. The substrate 110 is, for example, a germanium substrate, a germanium-containing substrate, a tri-five-layered germanium substrate (eg, GaN-on-silicon), and a graphite. A semiconductor substrate such as a graphene-on-silicon or a silicon-on-insulator (SOI) substrate. An insulating structure 10 is formed in the substrate 110 to electrically insulate the respective transistors. The insulating structure 10 is, for example, a shallow trench isolation (STI) structure, which is formed, for example, by a shallow trench isolation process. The detailed formation method is well known in the art and will not be described again, but the invention is not limited thereto.
接續,由下而上依序形成一緩衝層(未繪示)、一閘極介電層(未繪示)、一底阻障層(未繪示)、一犧牲電極層(未繪示)以及一蓋層(未繪示)覆蓋基底110;隨之,將蓋層(未繪示)、犧牲電極層(未繪示)、底阻障層(未繪示)、閘極介電層(未繪示)以及緩衝層(未繪示)圖案化,以形成一緩衝層122、一閘極介電層124、一底阻障層126、一犧牲電極層128以及一蓋層129於基底110上。此時則由緩衝層122、閘極介電層124、底阻障層126、犧牲電極層128以及蓋層129,形成一犧牲閘極G。 Continuing, a buffer layer (not shown), a gate dielectric layer (not shown), a bottom barrier layer (not shown), and a sacrificial electrode layer (not shown) are sequentially formed from bottom to top. And a cap layer (not shown) covering the substrate 110; subsequently, a cap layer (not shown), a sacrificial electrode layer (not shown), a bottom barrier layer (not shown), a gate dielectric layer ( The buffer layer (not shown) is patterned to form a buffer layer 122, a gate dielectric layer 124, a bottom barrier layer 126, a sacrificial electrode layer 128, and a cap layer 129 on the substrate 110. on. At this time, a sacrificial gate G is formed by the buffer layer 122, the gate dielectric layer 124, the bottom barrier layer 126, the sacrificial electrode layer 128, and the cap layer 129.
緩衝層122可為一氧化層,其例如以熱氧化製程或化學氧化製程形成,但本發明不以此為限。緩衝層122位於閘極介電層124與基底110之間,以作為閘極介電層124與基底110緩衝之用。本實施例係為一前置高介電常數後閘極(Gate-Last for High-K First)製程,因此本實施例之閘極介電層124為一高介電常數閘極介電層,其可選自氧化鉿(hafnium oxide,HfO2)、矽酸鉿氧化合物(hafnium silicon oxide,HfSiO4)、矽酸鉿氮氧化合物(hafnium silicon oxynitride,HfSiON)、氧化鋁(aluminum oxide,Al2O3)、氧化鑭(lanthanum oxide,La2O3)、氧化鉭(tantalum oxide,Ta2O5)、氧化釔(yttrium oxide,Y2O3)、氧化鋯(zirconium oxide,ZrO2)、鈦酸鍶(strontium titanate oxide, SrTiO3)、矽酸鋯氧化合物(zirconium silicon oxide,ZrSiO4)、鋯酸鉿(hafnium zirconium oxide,HfZrO4)、鍶鉍鉭氧化物(strontium bismuth tantalate,SrBi2Ta2O9,SBT)、鋯鈦酸鉛(lead zirconate titanate,PbZrxTi1-xO3,PZT)與鈦酸鋇鍶(barium strontium titanate,BaxSr1-xTiO3,BST)所組成之群組,但本發明不以此為限。在另一實施例中,當應用於一後置高介電常數後閘極(Gate-Last for High-K Last)製程時,則閘極介電層124將於後續製程中先被移除,再另外填入高介電常數閘極介電層,故此實施態樣下之閘極介電層124可僅為一般方便於後續製程中移除之犧牲材料,或者毋需形成閘極介電層124,等到移除犧牲電極層128後再形成一高介電常數閘極介電層作為閘極介電層。底阻障層126位於閘極介電層124上,其例如為氮化鉭(tantalum nitride,TaN)、氮化鈦(titanium nitride,TiN)等單層結構或複合層結構。犧牲電極層128可例如由多晶矽所形成,但本發明不以此為限。蓋層129可包含氮化層或氧化層等單層或多層之結構,用以當作圖案化的硬遮罩。 The buffer layer 122 can be an oxide layer, which is formed, for example, by a thermal oxidation process or a chemical oxidation process, but the invention is not limited thereto. The buffer layer 122 is located between the gate dielectric layer 124 and the substrate 110 for buffering the gate dielectric layer 124 and the substrate 110. In this embodiment, the gate dielectric layer 124 is a high dielectric constant gate dielectric layer, and the gate dielectric layer 124 is a high dielectric constant gate dielectric layer. It may be selected from hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO 4 ), hafnium silicon oxynitride (HfSiON), aluminum oxide (aluminum oxide, Al 2 ). O 3 ), lanthanum oxide (La 2 O 3 ), tantalum oxide (Ta 2 O 5 ), yttrium oxide (Y 2 O 3 ), zirconium oxide (ZrO 2 ), Strontium titanate oxide (SrTiO 3 ), zirconium silicon oxide (ZrSiO 4 ), hafnium zirconium oxide (HfZrO 4 ), strontium bismuth tantalate (SrBi 2 ) Ta 2 O 9 , SBT), lead zirconate titanate (PbZr x Ti 1-x O 3 , PZT) and barium strontium titanate (Ba x Sr 1-x TiO 3 , BST) A group is formed, but the invention is not limited thereto. In another embodiment, when applied to a post-gate high-potential (Gate-Last for High-K Last) process, the gate dielectric layer 124 is removed first in subsequent processes. In addition, a high dielectric constant gate dielectric layer is additionally filled. Therefore, the gate dielectric layer 124 in this embodiment may be a sacrificial material which is generally convenient for removal in a subsequent process, or a gate dielectric layer is not required. 124. Wait until the sacrificial electrode layer 128 is removed to form a high dielectric constant gate dielectric layer as the gate dielectric layer. The bottom barrier layer 126 is located on the gate dielectric layer 124, and is, for example, a single layer structure or a composite layer structure such as tantalum nitride (TaN) or titanium nitride (TiN). The sacrificial electrode layer 128 may be formed, for example, of polysilicon, but the invention is not limited thereto. The cap layer 129 may comprise a single layer or a plurality of layers such as a nitride layer or an oxide layer for use as a patterned hard mask.
然後,形成一間隙壁130於犧牲閘極G側邊的基底110上,再進行一離子佈植製程,以自動對準地於其側邊的基底110中形成一源/汲極區140。間隙壁130例如是以氮化矽或氧化矽等材質所組成之單層或多層複合結構。之後,可選擇性地進行一自動對準金屬矽化物(Salicide)製程以形成一金屬矽化物(未繪示)於源/汲極區140上。而後,可選擇性地全面覆蓋一接觸洞蝕刻停止層(contact etch stop layer,CESL)150於閘極結構G、間隙壁130以及基底110上。當然,在進行離子佈植製程以形成源/汲極區140之前, 可另外再形成一襯層並進行一離子佈植製程,以形成一輕摻雜源/汲極區(未繪示)。 Then, a spacer 130 is formed on the substrate 110 on the side of the sacrificial gate G, and an ion implantation process is performed to form a source/drain region 140 in the substrate 110 on its side. The spacer 130 is, for example, a single layer or a multilayer composite structure composed of a material such as tantalum nitride or tantalum oxide. Thereafter, an automatic alignment metal salicide process can be selectively performed to form a metal halide (not shown) on the source/drain region 140. Then, a contact etch stop layer (CESL) 150 can be selectively overlaid on the gate structure G, the spacers 130, and the substrate 110. Of course, before the ion implantation process is performed to form the source/drain region 140, A liner layer may be additionally formed and an ion implantation process may be performed to form a lightly doped source/drain region (not shown).
接著,覆蓋一層間介電層(未繪示)於基底110以及犧牲閘極G上,再將其平坦化至移除犧牲電極層128上之接觸洞蝕刻停止層(contact etch stop layer,CESL)150以及蓋層129,而如第2圖所示,形成一層間介電層160並曝露犧牲電極層128。接著,移除犧牲電極層128,而如第3圖所示形成一凹槽r並露出底阻障層126。 Then, an interlayer dielectric layer (not shown) is overlying the substrate 110 and the sacrificial gate G, and then planarized to remove the contact etch stop layer (CESL) on the sacrificial electrode layer 128. 150 and cap layer 129, and as shown in FIG. 2, an interlayer dielectric layer 160 is formed and the sacrificial electrode layer 128 is exposed. Next, the sacrificial electrode layer 128 is removed, and a recess r is formed as shown in FIG. 3 and the bottom barrier layer 126 is exposed.
接著,移除底阻障層126,並如第4圖所示,重新形成一U形的底阻障層126’覆蓋閘極介電層124以及層間介電層160,其中U形的底阻障層126’亦可例如為氮化鉭(tantalum nitride,TaN)、氮化鈦(titanium nitride,TiN)等單層結構或複合層結構。然後,形成一蝕刻停止層127於U形的底阻障層126’上,其中蝕刻停止層127則為由氮化鉭等材料所組成,用以在CMOS電晶體整合製程時去除其中之p型電晶體中之功函數層時作為蝕刻停止層之用。而後,形成一功函數層172覆蓋蝕刻停止層127。在本實施例中,係為形成一NMOS電晶體,是以所形成之功函數層172為一鋁鈦金屬層,但本發明不以此為限。在其他實施例中,功函數層172亦可為氮化鈦層等功函數層,用以形成具有其他電性之電晶體。而後,形成一頂阻障層174於功函數層172上。頂阻障層174可為一氮化鈦層等,用以防止後續形成於其上之材料層中的成分向下擴散至功函數層172、蝕刻停止層127、底阻障層126或閘極介電層124等,降低電 晶體之功函數值等電性品質。 Next, the bottom barrier layer 126 is removed, and as shown in FIG. 4, a U-shaped bottom barrier layer 126' is formed to cover the gate dielectric layer 124 and the interlayer dielectric layer 160, wherein the U-shaped bottom resistance The barrier layer 126' may be, for example, a single layer structure or a composite layer structure such as tantalum nitride (TaN) or titanium nitride (TiN). Then, an etch stop layer 127 is formed on the U-shaped bottom barrier layer 126', wherein the etch stop layer 127 is composed of a material such as tantalum nitride for removing the p-type during the CMOS transistor integration process. The work function layer in the transistor is used as an etch stop layer. Then, a work function layer 172 is formed to cover the etch stop layer 127. In this embodiment, an NMOS transistor is formed, and the formed work function layer 172 is an aluminum-titanium metal layer, but the invention is not limited thereto. In other embodiments, the work function layer 172 may also be a work function layer such as a titanium nitride layer to form a transistor having other electrical properties. A top barrier layer 174 is then formed over the work function layer 172. The top barrier layer 174 may be a titanium nitride layer or the like for preventing components in the material layer subsequently formed thereon from diffusing downward to the work function layer 172, the etch stop layer 127, the bottom barrier layer 126 or the gate. Dielectric layer 124, etc., reduce electricity The isoelectric property of the work function value of the crystal.
如第5圖所示,形成一潤濕層176於頂阻障層174上。在本實施例中,潤濕層176為一鈦層,但本發明不以此為限。潤濕層176可例如由鈦、鈷或釕等金屬材料所組成,其介於頂阻障層174以及後續欲形成之低電阻率材料之間,用以作為二者之緩衝以及低電阻率材料附著之用。而後,形成一低電阻率材料178於潤濕層176上。低電阻率材料178可包含由鋁或鎢等材料所組成。低電阻率材料178的電阻率係為小於潤濕層176的電阻率。 As shown in FIG. 5, a wetting layer 176 is formed over the top barrier layer 174. In the present embodiment, the wetting layer 176 is a titanium layer, but the invention is not limited thereto. The wetting layer 176 can be composed, for example, of a metal material such as titanium, cobalt or tantalum, which is interposed between the top barrier layer 174 and the subsequently formed low resistivity material to serve as a buffer for both and a low resistivity material. For attachment. A low resistivity material 178 is then formed over the wetting layer 176. The low resistivity material 178 can comprise a material comprised of aluminum or tungsten. The resistivity of the low resistivity material 178 is less than the resistivity of the wetting layer 176.
如第6圖所示,進行一例如化學機械研磨(chemical mechanical polishing,CMP)製程等平坦化製程,均勻地平坦化至露出層間介電層160,並於凹槽r內形成一金屬閘極M1,其包含緩衝層122、閘極介電層124、平坦化後的一U形的底阻障層126”、平坦化後的一蝕刻停止層127’以及平坦化後的一功函數層172’、一頂阻障層174’、一潤濕層176’與一低電阻率材料178’。接著,例如進行一微影暨蝕刻製程,於層間介電層160中形成至少一接觸洞R,而暴露出源/汲極區140(或金屬矽化物(未繪示))。之後,可再填入例如銅等金屬,以於接觸洞R中形成接觸插塞(未繪示),將源/汲極區140向外電連接其他半導體元件。當然,接觸插塞(未繪示)亦會形成於金屬閘極M1之上方,以將金屬閘極M1向外電連接其他半導體元件。例如,在其他實施態樣中,可在形成接觸洞R之前,先再形成一層間介電層(未繪示)於層間介電層160上,以覆蓋層間介電層160以及金屬閘極M1。然後,同時形成各接觸洞R於層間介電 層(未繪示)以及層間介電層160中,再填入例如銅等金屬並平坦化,進而同時形成各接觸插塞(未繪示)於源/汲極區140(或金屬矽化物(未繪示))以及金屬閘極M1上。 As shown in FIG. 6, a planarization process such as a chemical mechanical polishing (CMP) process is performed, uniformly planarized to expose the interlayer dielectric layer 160, and a metal gate M1 is formed in the recess r. The buffer layer 122, the gate dielectric layer 124, the flattened U-shaped bottom barrier layer 126", the planarized etch stop layer 127', and the planarized work function layer 172' a top barrier layer 174', a wetting layer 176' and a low resistivity material 178'. Then, for example, a lithography and etching process is performed to form at least one contact hole R in the interlayer dielectric layer 160, and The source/drain region 140 (or metal telluride (not shown) is exposed. Thereafter, a metal such as copper may be refilled to form a contact plug (not shown) in the contact hole R, and the source/ The drain region 140 is electrically connected to other semiconductor components. Of course, a contact plug (not shown) is also formed over the metal gate M1 to electrically connect the metal gate M1 to other semiconductor components. For example, in other implementations. In the aspect, an interlayer dielectric layer may be formed before the contact hole R is formed (not Illustrated on the interlayer dielectric layer 160 to cover the interlayer dielectric layer 160 and the metal gate M1. Then, the contact holes R are simultaneously formed to inter-layer dielectric A layer (not shown) and an interlayer dielectric layer 160 are further filled with a metal such as copper and planarized, thereby simultaneously forming contact plugs (not shown) in the source/drain region 140 (or metal germanide (or metal halide). Not shown)) and the metal gate M1.
以上,本發明形成金屬閘極M1,其包含緩衝層122、閘極介電層124、平坦化的U形的底阻障層126”、平坦化的蝕刻停止層127’、功函數層172’、頂阻障層174’、潤濕層176’以及低電阻率材料178’的一堆疊結構。然而,當半導體元件之尺寸日趨縮小的趨勢下,過多之此些材料層形成於凹槽r中,會導致低電阻率材料178’因凹槽r所剩之開口過小而難以填入,且需經過多道製程才能分別形成此些材料層,致使製程成本高居不下。 In the above, the present invention forms a metal gate M1 including a buffer layer 122, a gate dielectric layer 124, a planarized U-shaped bottom barrier layer 126", a planarized etch stop layer 127', and a work function layer 172' a stack structure of a top barrier layer 174', a wetting layer 176', and a low resistivity material 178'. However, as the size of the semiconductor component shrinks, too many of the material layers are formed in the recess r. The low resistivity material 178' is difficult to fill due to the small opening of the groove r, and it is necessary to go through multiple processes to form these material layers separately, resulting in high process cost.
因此,本發明再提出第二實施例,以進一步改善第一實施例恐發生填洞困難等問題,並能簡化製作工序以降低製程成本。第7-9圖係繪示本發明一第二實施例之MOS電晶體製程之剖面示意圖。本實施例之前製程如第1-3圖與第一實施例相同,換言之,本實施例之形成犧牲閘極G於基底110上;形成間隙壁130於犧牲閘極G側邊的基底110上;形成源/汲極區140於間隙壁130側邊的基底110中;形成一金屬矽化物(未繪示)於源/汲極區140上;選擇性地全面覆蓋一接觸洞蝕刻停止層(contact etch stop layer,CESL)150於閘極結構G、間隙壁130以及基底110上;形成層間介電層160並曝露犧牲電極層128;形成凹槽r並露出底阻障層126等製程步驟皆與第一實施例相同。 Therefore, the second embodiment of the present invention is further proposed to further improve the problems such as difficulty in filling holes in the first embodiment, and to simplify the manufacturing process to reduce the process cost. 7-9 are schematic cross-sectional views showing a process of a MOS transistor according to a second embodiment of the present invention. The process of the present embodiment is the same as that of the first embodiment, as in the first embodiment, in other words, the sacrificial gate G is formed on the substrate 110; the spacer 130 is formed on the substrate 110 on the side of the sacrificial gate G; Forming a source/drain region 140 in the substrate 110 on the side of the spacer 130; forming a metal halide (not shown) on the source/drain region 140; selectively covering a contact hole etch stop layer (contact The etch stop layer (CESL) 150 is on the gate structure G, the spacer 130, and the substrate 110; the interlayer dielectric layer 160 is formed and the sacrificial electrode layer 128 is exposed; the process of forming the recess r and exposing the bottom barrier layer 126 are performed. The first embodiment is the same.
在形成凹槽r並露出底阻障層126之後,先行移除底阻障層126,並如第7圖所示,重新形成一U形的底阻障層126’覆蓋閘極介電層124以及層間介電層160,其中U形的底阻障層126’亦可例如為氮化鉭(tantalum nitride,TaN)、氮化鈦(titanium nitride,TiN)等單層結構或複合層結構。然後,形成一蝕刻停止層127於U形的底阻障層126’上,其中蝕刻停止層127則為由氮化鉭等材料所組成,用以在CMOS電晶體整合製程時去除其中之p型電晶體中之功函數層時作為蝕刻停止層之用。而後,本第二實施例係直接形成一頂阻障層274覆蓋蝕刻停止層127,而不形成如第一實施例所述之功函數層。然後,形成一潤濕層276於頂阻障層274上。在一較佳的實施例中,頂阻障層274以及潤濕層276係為原位(in-situ)形成。例如,當頂阻障層274為一氮化鈦層而潤濕層276為一鈦層時,則可進行例如物理氣相沉積(physical vapor deposition,PVD)製程等一沉積製程,其可先在鍍鈦時通入氮氣形成氮化鈦層,再停止氮氣通入以形成鈦層,但本發明不以此為限。如此一來,則可減少頂阻障層274加上潤濕層276的厚度,並能有效防止頂阻障層274在欲形成潤濕層276之前被氧化,而增加一額外氧化層的厚度且降低導電效果。舉例而言,在第一實施例中,頂阻障層174’為一氮化鈦層,其厚度為40埃(angstroms),而潤濕層176’為一鈦層,其厚度為100埃(angstroms),而且頂阻障層174’與潤濕層176’係在不同機台製備,不但需破真空,影響產能,而容易造成頂阻障層274被氧化的狀況,且使後續潤濕層176’不易附著;但在本實施例中,頂阻障層274加上潤濕層276的厚度僅為100埃(angstroms),而且 藉由控制氮氣通入的時間,以原位(in-situ)的方式連續形成頂阻障層274以及潤濕層276,不但鍵結良好,製程簡化,而且更省去原來頂阻障層174’的厚度。更進一步而言,潤濕層276之底層S1厚度較佳為大於其側壁S2之厚度(例如潤濕層276之底層S1厚度為80埃(angstroms),而側壁S2之厚度為40埃(angstroms)),如此潤濕層276之底層S1部分可充分防止後續形成於其上方之成分向下擴散,而潤濕層276較薄之側壁S2部分又能增加凹槽r之開口寬度,使後續低電阻率材料填洞更容易。 After the recess r is formed and the bottom barrier layer 126 is exposed, the bottom barrier layer 126 is removed first, and as shown in FIG. 7, a U-shaped bottom barrier layer 126' is overlaid to cover the gate dielectric layer 124. And the interlayer dielectric layer 160, wherein the U-shaped bottom barrier layer 126 ′ can also be a single layer structure or a composite layer structure such as tantalum nitride (TaN) or titanium nitride (TiN). Then, an etch stop layer 127 is formed on the U-shaped bottom barrier layer 126', wherein the etch stop layer 127 is composed of a material such as tantalum nitride for removing the p-type during the CMOS transistor integration process. The work function layer in the transistor is used as an etch stop layer. Then, the second embodiment directly forms a top barrier layer 274 to cover the etch stop layer 127 without forming a work function layer as described in the first embodiment. A wetting layer 276 is then formed over the top barrier layer 274. In a preferred embodiment, top barrier layer 274 and wetting layer 276 are formed in-situ. For example, when the top barrier layer 274 is a titanium nitride layer and the wetting layer 276 is a titanium layer, a deposition process such as a physical vapor deposition (PVD) process may be performed, which may be preceded by When titanium is applied, nitrogen gas is introduced to form a titanium nitride layer, and then nitrogen gas is stopped to form a titanium layer, but the invention is not limited thereto. In this way, the thickness of the top barrier layer 274 plus the wetting layer 276 can be reduced, and the top barrier layer 274 can be effectively prevented from being oxidized before the wetting layer 276 is formed, and the thickness of an additional oxide layer is increased. Reduce the electrical conductivity. For example, in the first embodiment, the top barrier layer 174' is a titanium nitride layer having a thickness of 40 angstroms, and the wetting layer 176' is a titanium layer having a thickness of 100 angstroms ( Angstroms), and the top barrier layer 174' and the wetting layer 176' are prepared on different machines, not only need to break the vacuum, affecting the productivity, but also easily cause the top barrier layer 274 to be oxidized, and the subsequent wetting layer 176' is not easily attached; but in the present embodiment, the top barrier layer 274 plus the wetting layer 276 has a thickness of only 100 angstroms, and By controlling the time of nitrogen gas flow, the top barrier layer 274 and the wetting layer 276 are continuously formed in an in-situ manner, which not only has good bonding, process simplification, but also eliminates the original top barrier layer 174. 'thickness of. Furthermore, the thickness of the bottom layer S1 of the wetting layer 276 is preferably greater than the thickness of the side wall S2 (for example, the thickness of the bottom layer S1 of the wetting layer 276 is 80 angstroms, and the thickness of the side wall S2 is 40 angstroms). The portion of the bottom layer S1 of the wetting layer 276 can sufficiently prevent the components formed subsequently thereon from diffusing downward, and the thinner side wall portion S2 of the wetting layer 276 can increase the opening width of the recess r, so that the subsequent low resistance Rate material filling holes is easier.
接續如第8圖所示,形成一低電阻率材料280於潤濕層276上。值得注意的是,本第二實施例係藉由低電阻率材料280擴散至潤濕層276,以直接於低電阻率材料280與潤濕層276之間形成一過渡層290,並藉由選擇低電阻率材料280與潤濕層276的材料,而使過渡層290具有功函數層的功能,俾使所形成之閘極結構不含有任何的功函數層,尤其是頂阻障層274與蝕刻停止層127之間,較佳者,在潤濕層276與閘極介電層124之間不具有任何的功函數層。如此,由於不需再另外形成如第一實施例所述之功函數層172’,而且利用原位(in-situ)的方式連續形成頂阻障層274及潤濕層276具有更薄的膜厚,故本實施例可解決前一實施例中低電阻率材料280填洞困難以及減少製程成本的優勢。具體而言,潤濕層276可例如為一鈦層而低電阻率材料280例如由鋁所組成。如此一來,由於低電阻率材料280之鋁向下擴散至潤濕層276,而可與部分潤濕層276中的鈦反應形成鋁鈦金屬層之過渡層290。過渡層290之化學式可包含TixAly,較佳而言y>x,例如過渡層290之化學式較佳 為TiAl3,但本發明不以此為限。在本實施例中,過渡層290亦為一鋁鈦金屬層,因此可取代第一實施例中之功函數層172’(其亦為一鋁鈦金屬層,用以形成一NMOS電晶體)。在其他實施例中,潤濕層276及低電阻率材料280亦可為其他材料之組合。例如,潤濕層276可包含由鈦、鈷或釕等所組成,而搭配的低電阻率材料280可包含由鎢、鋁等所組成。以鎢所組成之低電阻率材料280,具有較鋁更慢之擴散速率,因此可再進一步降低其下方之U形的底阻障層126’、蝕刻停止層127以及頂阻障層274’的厚度。 Next, as shown in FIG. 8, a low resistivity material 280 is formed on the wetting layer 276. It should be noted that the second embodiment diffuses to the wetting layer 276 by the low resistivity material 280 to form a transition layer 290 directly between the low resistivity material 280 and the wetting layer 276, and by selecting The low resistivity material 280 and the material of the wetting layer 276, the transition layer 290 has the function of a work function layer, so that the formed gate structure does not contain any work function layer, especially the top barrier layer 274 and etching Between the stop layers 127, preferably, there is no work function layer between the wetting layer 276 and the gate dielectric layer 124. Thus, since it is not necessary to additionally form the work function layer 172' as described in the first embodiment, the top barrier layer 274 and the wetting layer 276 are continuously formed in an in-situ manner to have a thinner film. The embodiment can solve the problem that the low resistivity material 280 is difficult to fill holes and the process cost is reduced in the previous embodiment. In particular, the wetting layer 276 can be, for example, a titanium layer and the low resistivity material 280, for example, aluminum. As such, as the aluminum of the low resistivity material 280 diffuses down to the wetting layer 276, it can react with the titanium in the partially wetting layer 276 to form the transition layer 290 of the aluminum titanium metal layer. The chemical formula of the transition layer 290 may include Ti x Al y , preferably y > x. For example, the chemical formula of the transition layer 290 is preferably TiAl 3 , but the invention is not limited thereto. In this embodiment, the transition layer 290 is also an aluminum-titanium metal layer, and thus can replace the work function layer 172' (which is also an aluminum-titanium metal layer for forming an NMOS transistor) in the first embodiment. In other embodiments, the wetting layer 276 and the low resistivity material 280 can also be a combination of other materials. For example, the wetting layer 276 can comprise titanium, cobalt or tantalum, etc., and the combined low resistivity material 280 can comprise tungsten, aluminum, or the like. The low-resistivity material 280 composed of tungsten has a slower diffusion rate than aluminum, so that the lower U-shaped bottom barrier layer 126', the etch stop layer 127, and the top barrier layer 274' can be further reduced. thickness.
如第9圖所示,進行一例如化學機械研磨製程等研磨製程,平坦化低電阻率材料280、過渡層290、潤濕層276、頂阻障層274、蝕刻停止層127以及U形的底阻障層126’,以形成平坦化後的一U形的底阻障層126”、平坦化後的一蝕刻停止層127’以及平坦化後的一頂阻障層274’、一潤濕層276’、一過渡層290’以及一低電阻率材料280’,如此形成一金屬閘極M2。之後,形成至少一接觸洞R於層間介電層160中並暴露出源/汲極區140(或金屬矽化物(未繪示))。而後,可再形成一接觸插塞(未繪示)於接觸洞R中,俾使源/汲極區140(或金屬矽化物(未繪示))向外電連接其他半導體元件。同樣的,在其他實施態樣中,亦可在形成接觸洞R之前,先再形成一層間介電層(未繪示)於層間介電層160上,以覆蓋層間介電層160以及金屬閘極M2。然後,同時形成各接觸洞R於層間介電層(未繪示)以及層間介電層160中,再填入例如銅等金屬並平坦化,進而同時形成各接觸插塞(未繪示)於源/汲極區140(或金屬矽化物(未繪 示))以及金屬閘極M2上。之後,可再進行其他後續的半導體製程,其為本領域所熟知,故不再贅述。 As shown in FIG. 9, a polishing process such as a chemical mechanical polishing process is performed to planarize the low resistivity material 280, the transition layer 290, the wetting layer 276, the top barrier layer 274, the etch stop layer 127, and the U-shaped bottom. The barrier layer 126' is formed to form a planarized U-shaped bottom barrier layer 126", a planarized etch stop layer 127', and a planarized top barrier layer 274', a wetting layer 276', a transition layer 290', and a low resistivity material 280', thus forming a metal gate M2. Thereafter, at least one contact hole R is formed in the interlayer dielectric layer 160 and the source/drain region 140 is exposed ( Or a metal telluride (not shown). Then, a contact plug (not shown) may be formed in the contact hole R to cause the source/drain region 140 (or metal telluride (not shown)). The other semiconductor components are electrically connected to the outside. Similarly, in other embodiments, an interlayer dielectric layer (not shown) may be formed on the interlayer dielectric layer 160 before the contact holes R are formed to cover the interlayer layers. Dielectric layer 160 and metal gate M2. Then, each contact hole R is simultaneously formed on the interlayer dielectric layer (not shown) and between the layers Layer 160, a metal such as copper and then filled and planarized, thereby forming the contact plug (not shown) 140 (or a metal silicide in the source / drain regions at the same time (not Show)) and the metal gate M2. Thereafter, other subsequent semiconductor processes can be performed, which are well known in the art and will not be described again.
承上,本發明應用上述之MOS電晶體製程,即可形成一MOS電晶體,其可如第9圖所示,具有金屬閘極M2(或者亦可指一閘極結構)位於基底110上。此金屬閘極M2可為一堆疊結構,由下而上可包含緩衝層122、閘極介電層124、U形的底阻障層126”、蝕刻停止層127’、頂阻障層274’、潤濕層276’、過渡層290’以及低電阻率材料280’。由於本發明之過渡層290’具有功函數層的功能,因此本發明之金屬閘極M2中不須再含有其他的功函數層,尤其是在潤濕層276’與閘極介電層124之間不具有任何的功函數層。如此一來,由於本發明不須再另外進行一沉積功函數層的步驟,因此即便在半導體元件之尺寸日趨縮小的趨勢下,亦可具有較大之凹槽r之開口可填入低電阻率材料280’,因而可解決第一實施例之填洞困難的問題,並且降低製程成本。例如,本發明之潤濕層276’可由鈦層所組成,而低電阻率材料280’可由鋁所組成,而二者所形成之過渡層290’即為一鋁鈦金屬層,其可具有功函數層之功能。詳細而言,藉由調整低電阻率材料280’之製程溫度或者在形成低電阻率材料280後再進行一退火製程,即可改變過渡層290’之相態(phase),而能改變過渡層290’之微結構,進而調整其功函數值等電性參數,以達到所需之用途。例如,在不同低電阻率材料280’之製程溫度或者不同退火製程之溫度下,過渡層290’可具有之化學式可為TixAly,其x,y值可調變;或者,x,y值隨其不同的位置或深度 可具有不同之分佈等。 According to the present invention, a MOS transistor can be formed by applying the above MOS transistor process. As shown in FIG. 9, the metal gate M2 (or a gate structure) can be disposed on the substrate 110. The metal gate M2 may be a stacked structure, and may include a buffer layer 122, a gate dielectric layer 124, a U-shaped bottom barrier layer 126", an etch stop layer 127', and a top barrier layer 274' from bottom to top. a wetting layer 276', a transition layer 290', and a low resistivity material 280'. Since the transition layer 290' of the present invention has the function of a work function layer, the metal gate M2 of the present invention does not need to contain other work. The function layer, in particular, does not have any work function layer between the wetting layer 276' and the gate dielectric layer 124. Thus, since the present invention does not require another step of depositing a work function layer, even In the tendency that the size of the semiconductor element is shrinking, the opening having the larger groove r can be filled with the low-resistivity material 280', thereby solving the problem of filling holes in the first embodiment and reducing the process cost. For example, the wetting layer 276' of the present invention may be composed of a titanium layer, and the low-resistivity material 280' may be composed of aluminum, and the transition layer 290' formed by the two is an aluminum-titanium metal layer, which may have Function of the work function layer. In detail, by adjusting the low resistivity material 28 The process temperature of 0' or an annealing process after forming the low resistivity material 280 can change the phase of the transition layer 290', and can change the microstructure of the transition layer 290', thereby adjusting the work function. Value isoelectric parameters to achieve the desired use. For example, at different process temperatures of the low resistivity material 280' or different annealing processes, the transition layer 290' may have a chemical formula of Ti x Al y , The x, y values may be variable; or, the x, y values may have different distributions depending on their different positions or depths.
另外,本發明可藉由調整U形的底阻障層126’、蝕刻停止層127、頂阻障層274’、潤濕層276’、過渡層290’以及低電阻率材料280’的厚度或材料,來改變所形成之電晶體之功函數值等電性參數。例如,藉由改變U形的底阻障層126’、蝕刻停止層127、頂阻障層274’的厚度或材料,可控制低電阻率材料280’等成分擴散至其中或其下方之閘極介電層124的含量,而改變電晶體之功函數值、等效氧化層厚度(Equivalent Oxide Thickness,EOT)或漏電流密度(leakage current density,Jg)等電性參數。一般而言,因為當低電阻率材料280’等成分擴散至閘極介電層124,就會發生漏電流的問題,一般以控制為擴散至U形的底阻障層126’或蝕刻停止層127而不再向下擴散為佳。但更佳而言,增厚蝕刻停止層127係較增厚U形的底阻障層126’或頂阻障層274’的厚度為佳,因為增厚U形的底阻障層126’或頂阻障層274’的厚度會使功函數值朝向與所需相反之數值,其中增厚蝕刻停止層127的方法,例如由原子層沉積(atomic layer deposition,ALD)製程形成時,可增加製程循環數(cycles),即可增厚蝕刻停止層127。另外,例如當頂阻障層274’的材料為氮化鈦時,可藉由調整其氮和鈦的比例,控制其上方之金屬成分等向下擴散的程度,以改變功函數值等電性參數。更甚者,由於調整U形的底阻障層126’或蝕刻停止層127即可防止其上方之金屬成分等向下擴散,因此可省略掉頂阻障層274’,以進一步降低製程成本以及改善填洞困難的問題。 In addition, the present invention can be adjusted by adjusting the thickness of the U-shaped bottom barrier layer 126', the etch stop layer 127, the top barrier layer 274', the wetting layer 276', the transition layer 290', and the low resistivity material 280' or Material to change the isoelectric parameter of the work function value of the formed transistor. For example, by changing the thickness or material of the U-shaped bottom barrier layer 126', the etch stop layer 127, the top barrier layer 274', the gate of the low-resistivity material 280' and the like can be controlled to diffuse to or below the gate. The content of the dielectric layer 124 changes the electrical function value of the transistor, the Equivalent Oxide Thickness (EOT) or the leakage current density (Jg). In general, since a low-resistivity material 280' or the like diffuses to the gate dielectric layer 124, a problem of leakage current occurs, and the bottom barrier layer 126' or the etch stop layer is generally controlled to diffuse into a U-shape. 127 instead of spreading down is better. More preferably, however, the thickened etch stop layer 127 is preferably thicker than the thicker U-shaped bottom barrier layer 126' or top barrier layer 274' because of the thickened U-shaped bottom barrier layer 126' or The thickness of the top barrier layer 274' may cause the work function value to be opposite to the desired value, wherein the method of thickening the etch stop layer 127, for example, by an atomic layer deposition (ALD) process, may increase the process The etch stop layer 127 can be thickened by cycles. In addition, for example, when the material of the top barrier layer 274' is titanium nitride, the degree of downward diffusion of the metal component or the like above can be controlled by adjusting the ratio of nitrogen and titanium to change the work function value isoelectricity. parameter. Moreover, since the U-shaped bottom barrier layer 126' or the etch stop layer 127 is adjusted to prevent the metal component or the like above from diffusing downward, the top barrier layer 274' can be omitted to further reduce the process cost and Improve the difficulty of filling holes.
綜上所述,本發明提供一種MOS電晶體及其製程,其先形成一潤濕層以及一低電阻率材料,再藉由將低電阻率材料之成分擴散至潤濕層而形成一過渡層。過渡層具有一功函數層的功能,因而本發明所形成之金屬閘極中不需再含有其他的功函數層。如此一來,本發明之MOS電晶體及其製程,可改善填洞困難的問題以及降低製程成本。更進一步而言,可藉由調整底阻障層、蝕刻停止層、頂阻障層、潤濕層、過渡層以及低電阻率材料的材料及厚度,來改變所形成之電晶體之電性參數,例如功函數值、等效氧化層厚度(Equivalent Oxide Thickness,EOT)或漏電流密度(leakage current density,Jg)。 In summary, the present invention provides a MOS transistor and a process thereof, which first form a wetting layer and a low resistivity material, and then form a transition layer by diffusing a component of the low resistivity material to the wetting layer. . The transition layer has the function of a work function layer, so that the metal gate formed by the present invention does not need to contain another work function layer. In this way, the MOS transistor of the present invention and the process thereof can improve the problem of filling holes and reduce the process cost. Furthermore, the electrical parameters of the formed transistor can be changed by adjusting the material and thickness of the bottom barrier layer, the etch stop layer, the top barrier layer, the wetting layer, the transition layer, and the low resistivity material. For example, work function value, Equivalent Oxide Thickness (EOT) or leak current density (Jg).
再者,本發明之頂阻障層、潤濕層可由原位形成。例如當頂阻障層為一氮化鈦層而潤濕層為一鈦層,則可進行一物理氣相沉積(physical vapor deposition,PVD)製程等一沉積製程,其可先在鍍鈦時通入氮氣形成氮化鈦層,再停止氮氣通入以電鍍形成鈦層。如此,可減少頂阻障層加上潤濕層的厚度,並防止頂阻障層在欲形成潤濕層之前被氧化。 Furthermore, the top barrier layer and the wetting layer of the present invention may be formed in situ. For example, when the top barrier layer is a titanium nitride layer and the wetting layer is a titanium layer, a deposition process such as a physical vapor deposition (PVD) process can be performed, which can be first performed during titanium plating. Nitrogen gas was introduced to form a titanium nitride layer, and then nitrogen gas flow was stopped to form a titanium layer by electroplating. Thus, the thickness of the top barrier layer plus the wetting layer can be reduced, and the top barrier layer can be prevented from being oxidized before the wetting layer is to be formed.
雖然在圖示中U形的底阻障層126”、蝕刻停止層127’、頂阻障層274’、潤濕層276’、過渡層290’以及低電阻率材料280’具有共平面(即切齊)之上表面,但應瞭解,在形成此些膜層之後及進行如圖9之化學機械研磨製程等研磨製程之前,可針對此些膜層中的一或多者進行回蝕製程以使其上表面低於研磨過之層間介電層160的上表面。 Although the U-shaped bottom barrier layer 126", etch stop layer 127', top barrier layer 274', wetting layer 276', transition layer 290', and low resistivity material 280' are coplanar in the illustration (ie, The upper surface is cut, but it should be understood that an etch back process may be performed for one or more of the film layers after forming the film layers and performing a polishing process such as the chemical mechanical polishing process of FIG. The upper surface is made lower than the upper surface of the ground interlayer dielectric layer 160.
以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。 The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.
10‧‧‧絕緣結構 10‧‧‧Insulation structure
110‧‧‧基底 110‧‧‧Base
122‧‧‧緩衝層 122‧‧‧buffer layer
124‧‧‧閘極介電層 124‧‧‧ gate dielectric layer
126‧‧‧底阻障層 126‧‧‧ bottom barrier
126’、126”‧‧‧U形的底阻障層126’ 126', 126"‧‧ U-shaped bottom barrier layer 126'
127、127’‧‧‧蝕刻停止層 127, 127' ‧ ‧ etch stop layer
128‧‧‧犧牲電極層 128‧‧‧Sacrificial electrode layer
129‧‧‧蓋層 129‧‧‧ cover
130‧‧‧間隙壁 130‧‧‧ spacer
140‧‧‧源/汲極區 140‧‧‧Source/Bungee Zone
150‧‧‧接觸洞蝕刻停止層 150‧‧‧Contact hole etch stop layer
160‧‧‧層間介電層 160‧‧‧Interlayer dielectric layer
172、172’‧‧‧功函數層 172, 172'‧‧‧ work function layer
174、174’、274、274’‧‧‧頂阻障層 174, 174', 274, 274' ‧ ‧ top barrier
176、176’、276、276’‧‧‧潤濕層 176, 176', 276, 276' ‧ ‧ wetting layer
178、178’、280、280’‧‧‧低電阻率材料 178, 178', 280, 280'‧‧‧ low resistivity materials
290、290’‧‧‧過渡層 290, 290’ ‧ ‧ transition layer
G‧‧‧犧牲閘極 G‧‧‧sacrificial gate
M1、M2‧‧‧金屬閘極 M1, M2‧‧‧ metal gate
r‧‧‧凹槽 R‧‧‧ groove
R‧‧‧接觸洞 R‧‧‧Contact hole
S1‧‧‧底層 S1‧‧‧ bottom
S2‧‧‧側壁 S2‧‧‧ side wall
第1-6圖係繪示本發明一第一實施例之MOS電晶體製程之剖面示意圖。 1 to 6 are schematic cross-sectional views showing a process of a MOS transistor according to a first embodiment of the present invention.
第7-9圖係繪示本發明一第二實施例之MOS電晶體製程之剖面示意圖。 7-9 are schematic cross-sectional views showing a process of a MOS transistor according to a second embodiment of the present invention.
10‧‧‧絕緣結構 10‧‧‧Insulation structure
110‧‧‧基底 110‧‧‧Base
122‧‧‧緩衝層 122‧‧‧buffer layer
124‧‧‧閘極介電層 124‧‧‧ gate dielectric layer
126”‧‧‧U形的底阻障層 126"‧‧‧U-shaped bottom barrier
127’‧‧‧蝕刻停止層 127’‧‧‧etch stop layer
130‧‧‧間隙壁 130‧‧‧ spacer
140‧‧‧源/汲極區 140‧‧‧Source/Bungee Zone
150‧‧‧接觸洞蝕刻停止層 150‧‧‧Contact hole etch stop layer
160‧‧‧層間介電層 160‧‧‧Interlayer dielectric layer
274’‧‧‧頂阻障層 274’‧‧‧Top barrier
276’‧‧‧潤濕層 276'‧‧‧ Wetting layer
280’‧‧‧低電阻率材料 280'‧‧‧ Low resistivity material
290’‧‧‧過渡層 290’‧‧‧Transition layer
M2‧‧‧金屬閘極 M2‧‧‧Metal Gate
R‧‧‧接觸洞 R‧‧‧Contact hole
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US6977217B1 (en) * | 2002-12-03 | 2005-12-20 | Cypress Semiconductor Corporation | Aluminum-filled via structure with barrier layer |
US20110006354A1 (en) * | 2009-07-08 | 2011-01-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal gate structure of a semiconductor device |
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Patent Citations (2)
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---|---|---|---|---|
US6977217B1 (en) * | 2002-12-03 | 2005-12-20 | Cypress Semiconductor Corporation | Aluminum-filled via structure with barrier layer |
US20110006354A1 (en) * | 2009-07-08 | 2011-01-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal gate structure of a semiconductor device |
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