TW201318068A - Semiconductor device having metal gate and manufacturing method thereof - Google Patents

Abstract

A manufacturing method of a semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench, forming a first work function metal layer in the first gate trench, forming a second work function metal layer in the first gate trench and the second gate trench, forming a first patterned mask layer exposing portions of the second work function metal layer in the first gate trench and the second gate trench, and performing an etching process to remove the exposed second work function metal layer.

Description

Semiconductor component with metal gate and manufacturing method thereof

The present invention relates to a semiconductor device having a metal gate and a method of fabricating the same, and more particularly to a semiconductor device having a metal gate in a gate last process and a method of fabricating the same.

As semiconductor components continue to shrink, work function metals are used to replace conventional polysilicon as control electrodes for matching high-k dielectric layers. The bi-function function metal gate can be divided into two types: front gate (gate first) and back gate (gate last). The latter gate process can avoid the source/bungee ultra-shallow. The joint activation tempering and high-heat budget process such as metal telluride, and a wider material selection, gradually replaced the front gate process.

In the conventional gate process, a dummy gate or a replacement gate is formed first, and after the fabrication of the general MOS transistor is completed, the dummy/replacement gate is removed. A gate trench is formed, and different metals are filled in the gate trench according to electrical requirements. However, as the line width of the transistor component continues to shrink, the aspect ratio of the gate trench becomes a major challenge for the metal film layer to be successfully filled into the gate trench. Simply put, as the line width of the transistor component shrinks, the opening width of the gate trench also shrinks, causing the metal film layer to be difficult to fill the gate trench, and even the gate trench can not be filled into the gap to affect the electricity. Problems such as electrical performance of crystal components. In addition, due to the different work function metals required for different conductivity types, the removal of excess metal may also cause damage to other layers such as the dielectric layer, and cause subsequent filling of the metal to remain in the dielectric layer. Defects in metal residues.

It can be seen that the post-gate process can avoid the high-heat budget process such as source/drain ultra-shallow junction activation and tempering, and has a wide material selection, but still faces the integration of complex processes. Reliability issues such as gate trench filling capacity and metal residue defects.

Accordingly, it is an object of the present invention to provide a semiconductor device having a metal gate and a method of fabricating the same, which can improve the gate trench filling capability and avoid defects such as metal residue.

The present invention provides a method of fabricating a semiconductor device having a metal gate. The fabrication method first provides a substrate having a first semiconductor component and a second semiconductor component formed on a surface thereof, and the first semiconductor component and the second A first gate trench and a second gate trench are formed in the semiconductor component. Next, a first work function metal layer is formed in the first gate trench, and then a second work function metal layer is formed in the first gate trench and the second gate trench. After the second work function metal layer is formed, a first patterned mask layer is formed in the first gate trench and the second gate trench, and the first patterned mask layer exposes the portion. The second work function metal layer. An etching process is then performed to remove the exposed portion of the second work function metal layer.

The invention further provides a semiconductor device having a metal gate, the semiconductor device comprising a substrate, a surface of the substrate is formed with a first semiconductor component and a second semiconductor component, and the first semiconductor component and the second semiconductor component are respectively A first gate trench and a second gate trench are formed. The semiconductor device further includes a gate dielectric layer respectively disposed in the first gate trench and the second gate trench, a first U-shaped metal layer disposed in the first gate trench, and a setting a second U-shaped metal layer in the second gate trench, and a filling metal layer disposed on the first U-shaped metal layer and the second U-shaped metal layer. The highest portion of the first U-shaped metal layer is lower than the opening of the first gate trench; and the highest portion of the second U-shaped metal layer is also lower than the opening of the second gate trench.

The method for fabricating a semiconductor device having a metal gate according to the present invention is to remove a part of the work function metal layer in all the gate trenches after forming the second work function metal layer, so that the first work function metal layer and The highest point of the second work function metal layer is lower than the opening of the gate trench and has a U-shaped shape feature. Therefore, the subsequently filled film layer such as the filling metal layer can be smoothly filled into the gate trench, and the formation of the void can be avoided, and the negative influence of the void on the electrical properties of the semiconductor element can be avoided.

Please refer to FIG. 1 to FIG. 6 . FIG. 1 to FIG. 6 are schematic diagrams showing a first preferred embodiment of a method for fabricating a semiconductor device having a metal gate according to the present invention. As shown in FIG. 1, the preferred embodiment first provides a substrate 100, such as a germanium substrate, a germanium-containing substrate, or a silicon-on-insulator (SOI) substrate. A first semiconductor component 110 and a second semiconductor component 112 are formed on the substrate 100, and a shallow trench isolation (shallow trench) for providing electrical isolation is formed in the substrate 100 between the first semiconductor component 110 and the second semiconductor component 112. Isolation, STI) 102. The first semiconductor component 110 has a first conductivity type, and the second semiconductor component 112 has a second conductivity pattern, and the first conductivity pattern is complementary to the second conductivity pattern. In the preferred embodiment, the first semiconductor component 110 is a p-type semiconductor component; and the second semiconductor component 112 is an n-type semiconductor component.

Please continue to see Figure 1. The first semiconductor device 110 and the second semiconductor device 112 each include a gate dielectric layer 104, a bottom barrier layer 106 and a dummy gate (not shown) such as a polysilicon layer. The gate dielectric layer 104 can be a conventional germanium dioxide layer or a high dielectric constant gate dielectric layer or a combination thereof; and the bottom barrier layer 106 comprises titanium nitride (TiN), but is not limited thereto. this. In addition, the first semiconductor component 110 and the second semiconductor component 112 respectively include a first light doped drain (LDD) 120 and a second LDD 122, a sidewall 124, and a first source/汲The pole 130 and a second source/drain 132. In addition, the surface of the first source/drain 130 and the second source/drain 132 respectively comprise a metal halide 134. On the first semiconductor element 110 and the second semiconductor element 112, a contact etch stop layer (CESL) 140 and an inter-layer dielectric (ILD) layer 142 are sequentially formed. . The fabrication steps and material selection of the above components, and even the selective epitaxial growth (SEG) method for forming the source/drain electrodes 130, 132, etc. in the semiconductor industry to provide stress and improve electrical performance. It is well known to those skilled in the art and will not be described here.

Please still refer to Figure 1. After forming the CESL 140 and ILD layer 142, portions of the CESL 140 and ILD layer 142 are removed by a planarization process until the dummy gates of the first semiconductor component 110 and the second semiconductor component 112 are exposed. Then, the dummy gates of the first semiconductor component 110 and the second semiconductor component 112 are removed by a suitable etching process, and a first gate trench 150 is formed in the first semiconductor component 110 and the second semiconductor component 112, respectively. And a second gate trench 152. It should be noted that the preferred embodiment can be integrated with a high-k first process, in which case the gate dielectric layer 104 contains a high dielectric constant (high-k constant). A gate dielectric layer, which may be a metal oxide layer, such as a rare earth metal oxide layer. The high-k gate dielectric layer 104 can be selected from the group consisting of hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSiO ₄ ), and hafnium silicon oxynitride (HfSiON). , aluminum oxide (Al ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ ), yttrium oxide (Y ₂ O ₃ ), oxidation Zirconium oxide (ZrO ₂ ), strontium titanate oxide (SrTiO ₃ ), zirconium silicon oxide (ZrSiO ₄ ), hafnium zirconium oxide (HfZrO ₄ ), yttrium Oxide (strontium bismuth tantalate, SrBi ₂ Ta ₂ O ₉ , SBT), lead zirconate titanate (PbZr _x Ti _1-x O ₃ , PZT) and barium strontium titanate (Ba _x Sr) _a group consisting of _1-x TiO ₃ , BST). In addition, between the high-k gate dielectric layer 104 and the substrate 100, an interfacial layer (not shown) may be disposed. After forming the first gate trench 150 and the second gate trench 152, an etch stop layer may be formed on the bottom barrier layer 106 in the first gate trench 150 and the second gate trench 152 (etch stop) The etch stop layer 108 may include tantalum nitride (TaN), but is not limited thereto.

It is also worth noting that the preferred embodiment can be integrated with a high-k last process, in which case the gate dielectric layer can be a conventional germanium dioxide layer. After the polysilicon layer is removed to form the first gate trench 150 and the second gate trench 152, the gate dielectric layer exposed to the bottom of the first gate trench 150 and the second gate trench 152 can serve as an interface layer ( The figure is not shown). A high-k gate dielectric layer 104 is then formed over the substrate 100, which may comprise the materials described above. After the high-k gate dielectric layer 104 is formed, the foregoing etch stop layer 108 may be formed thereon.

Please refer to Figure 1 again. After the etch stop layer 108 is formed, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or an atomic layer deposition (ALD) process is performed. A first work function metal layer 160 is formed in the first gate trench 150 and the second gate trench 152. The first work function metal layer 160 may be a p-type work function metal layer having a p-type conductivity type, such as titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (tantalum nitride, TaN), tantalum carbide (TaC), tungsten carbide (WC), or aluminum titanium nitride (TiAlN), but is not limited thereto. In addition, the first work function metal layer 160 may be a single layer structure or a composite layer structure.

Please refer to Figure 2. Next, a patterned mask layer 170, such as a patterned photoresist layer, is formed on the substrate 100, but is not limited thereto. The patterned mask layer 170 is used to cover the first semiconductor component 110 and expose the first work function metal layer 160 at the second semiconductor component 112. The first work function metal layer 160 that is not protected by the patterned mask layer 170 is then removed using a suitable etchant such that the etch stop layer 108 is re-exposed within the second gate trench 152. Upon removal of the first work function metal layer 160, the etch stop layer 108 protects the underlying barrier layer 106, the high-k gate dielectric layer 104, and the ILD layer 142. After etching the exposed first work function metal layer 160, the first work function metal layer 160 remains in the first gate trench 150 and the first semiconductor device 110 as shown in FIG.

Please refer to Figure 3. After the first work function metal layer 160 and the patterned mask layer 170 in the second gate trench 152 are removed, another CVD process or PVD process is performed to form a second work function metal layer 162 on the substrate 100. . The second work function metal layer 162 may be an n-type work function metal layer having an n-type conductivity type, such as a titanium aluminide (TiAl) layer, a zirconium aluminide (ZrAl) layer, and a tungsten aluminide ( A tungsten aluminide, WAl) layer, a tantalum aluminide (TaAl) layer or a hafnium aluminide (HfAl) layer, but is not limited thereto. In addition, the second work function metal layer 162 may be a single layer structure or a composite layer structure. Subsequently, a mask layer 172a, such as a photoresist layer, is formed on the second work function metal layer 162, but is not limited thereto. It is also worth noting that the mask layer 172a fills the first gate trench 150 and the second gate trench 152 as shown in FIG. The material of the mask layer 172a is preferably a film layer with good hole filling ability, for example, a photoresist material formed by spin coating, a dielectric anti-reflection coating (DARC), and a light. A light absorbing oxide (DUO), a bottom anti-reflective coating (BARC) layer, a sacrificial light absorbing material (SLAM) layer, or the like, but is not limited thereto.

Please refer to Figure 4. Next, the mask layer 172a is etched back, and a patterned mask layer 172b is formed in the first gate trench 150 and the second gate trench 152, respectively, and the surface of the patterned mask layer 172b is lower than the first surface. The openings of the gate trench 150 and the second gate trench 152 expose a portion of the second work function metal layer 162.

Please refer to Figure 5. After forming the patterned mask layer 172b, an etching process is performed to remove portions of the exposed second work function metal layer 162 and the first work function metal layer 160 until the surface of the etch stop layer 108 is etched. As shown in FIG. 5, after the etching process, a first U-shaped metal layer 160a and a third U-shaped metal layer 162a are formed in the first gate trench 150, and the first U-shaped metal layer 160a includes a first work function. The metal layer 160; and the third U-shaped metal layer 162a includes a second work function metal layer 162. In the second gate trench 152, a second U-shaped metal layer 162b is formed, and the second U-shaped metal layer 162b includes a second work function metal layer 162. Finally, the patterned mask layer 172b is removed.

Please refer to Figure 6. Next, a fill metal layer 168 is formed in the first gate trench 150 and the second gate trench 152. In addition, a top barrier layer (not shown) may be disposed between the second work function metal layer 162 and the filler metal layer 168. The top barrier layer may include TiN, but is not limited thereto. The filling metal layer 168 is used to fill the first gate trench 150 and the second gate trench 152, and may select a metal or metal oxide having excellent filling ability and lower resistance, such as aluminum (Al). Titanium aluminide (TiAl) or titanium aluminum oxide (TiAlO), but is not limited thereto.

Please still refer to Figure 6. Finally, a planarization process, such as a CMP process, is performed to remove the excess fill metal layer 168 and the etch stop layer 108 to complete the fabrication of a first metal gate 180 and a second metal gate 182. In addition, the present embodiment can also selectively remove the ILD layer 142 and the CESL 140 and the like, and then reform the CESL and the dielectric layer to effectively improve the electrical performance of the semiconductor device. Since the above CMP process and the like are known to those of ordinary skill in the art, they are not described herein.

It should be noted that when the first work function metal layer 160 and the second work function metal layer 162 are formed, it can be found that the first work function metal layer 160 and the second work function metal layer 162 are tied to the first gate trench 150 and An overhang is formed at the opening of the second gate trench 152, causing the opening of the first gate trench 150 and the second gate trench 152 to be reduced, and the effect has the first work function metal layer 160 and the second The opening of the first gate trench 150 of the work function metal layer 162 is more pronounced. Therefore, in the preferred embodiment, the overhangs at the openings of the first gate trench 150 and the second gate trench 152 can be simultaneously removed by the etching process, and the first gate trench 150 and the second gate trench are removed. U-shaped metal layers 160a, 162a, and 162b having a special profile are formed in 152, respectively. Since the highest points of the first U-shaped metal layer 160a, the third U-shaped metal layer 162a and the second U-shaped metal layer 162b are lower than the openings of the first gate trench 150 and the second gate trench 152, the shape feature may be Maintaining the original size of the first gate trench 150 and the second gate trench 152, and effectively reducing the aspect ratio of the first gate trench 150 and the second gate trench 152, so the filling metal layer 168 can The smooth filling is performed to avoid a gap when the first gate trench 150 and the second gate trench 152 are filled, and the reliability of the first semiconductor element 110 and the second semiconductor element 112 is ensured.

More importantly, if the overhangs at the openings of the first gate trench 150 and the second gate trench 152 are respectively removed by different etching processes, the first work function metal layer 160 and the second work function can be found. The dielectric layer material under the interface of the metal layer 162, such as the ILD layer 142 and the CESL 140, may be subjected to multiple etching processes (removing the first work function metal layer at the second semiconductor component 112, removing the first gate trench 150) The overhang at the opening, and the overhang at the opening of the second gate trench 152 are damaged, and cause problems with the filling of the metal layer 168 and the metal residue after CMP. Therefore, the preferred embodiment further removes the overhangs at the openings of the first gate trench 150 and the second gate trench 152 under the condition of reducing the two etching processes, and uses the etch stop layer 108 as a protective layer. In order to avoid the influence of multiple etching processes on the ILD layer 142 and the CESL 140 under the interface between the first work function metal layer 160 and the second work function metal layer 162, the problem of the metal residue after the above CMP can be avoided, and the improvement is further improved. Product reliability.

Please refer to FIG. 7 to FIG. 13 . FIG. 7 to FIG. 13 are schematic diagrams showing a second preferred embodiment of a method for fabricating a semiconductor device having a metal gate according to the present invention. It is to be noted that, in the second preferred embodiment, the material selection of the same elements as the first preferred embodiment will not be described herein. As shown in FIG. 7, the preferred embodiment first provides a substrate 200 having a first semiconductor component 210 and a second semiconductor component 212 formed thereon, and between the first semiconductor component 210 and the second semiconductor component 212. The substrate 200 is formed with an STI 202 that provides electrical isolation. In the preferred embodiment, the first semiconductor component 210 is a p-type semiconductor component; the second semiconductor component 212 is an n-type semiconductor component.

Please continue to see Figure 7. The first semiconductor device 210 and the second semiconductor device 212 each include a gate dielectric layer 204, a bottom barrier layer 206 and a dummy gate (not shown). In addition, the first semiconductor device 210 and the second semiconductor device 212 respectively include a first LDD 220 and a second LDD 222, a sidewall 224, a first source/drain 230, and a second source/drain 232. In addition, the surface of the first source/drain 230 and the second source/drain 232 respectively comprise a metal halide 234. On the first semiconductor element 210 and the second semiconductor element 212, a CESL 240 and an ILD layer 242 are sequentially formed.

Please still refer to Figure 7. Then, a portion of the CESL 240 and the ILD layer 242 are removed by a planarization process, and the dummy gates of the first semiconductor device 210 and the second semiconductor device 212 are removed by a suitable etching process while simultaneously being used in the first semiconductor. A first gate trench 250 and a second gate trench 252 are formed in the component 210 and the second semiconductor component 212, respectively. It should be noted that the preferred embodiment can be integrated with a high-k first process, in which case the gate dielectric layer 204 includes a high-k gate dielectric layer. In addition, between the high-k gate dielectric layer 204 and the substrate 200, an interface layer (not shown) may be disposed. The preferred embodiment can also be integrated with the post gate dielectric layer process. The gate dielectric layer can be a conventional germanium dioxide layer and serve as an interface layer (not shown), followed by the substrate 200. A high-k gate dielectric layer 204 is formed thereon. After forming the first gate trench 250 and the second gate trench 252, or forming the high-k gate dielectric layer 204 in the first gate trench 250 and the second gate trench 252, the first An etch stop layer 208 is formed on the bottom barrier layer 250 in the gate trench 250 and the second gate trench 252.

As shown in FIG. 7, after the etch stop layer 208 is formed, a first work function metal layer 260 is formed in the first gate trench 250 and the second gate trench 252. The first work function metal layer 260 can be a p-type work function metal layer having a p-type conductivity. In addition, the first work function metal layer 260 can be a single layer structure or a composite layer structure.

Please refer to Figure 8. Next, a patterned mask 270, such as a patterned photoresist layer, is formed on the substrate 200, but is not limited thereto. It should be noted that the patterned mask layer 270 in the preferred embodiment is as shown in FIG. 8 and is formed only in the first gate trench 250 and has a lower surface than the first gate trench 250. Membrane layer.

Please refer to Figure 9. The first work function metal layer 260 that is not protected by the patterned mask layer 270 is then removed using a suitable etchant. Upon removal of the first work function metal layer 260, the etch stop layer 208 can protect the bottom barrier layer 206, the high-k gate dielectric layer 204, the ILD layer 242, and the CESL 240 underneath. After etching the exposed first work function metal layer 260, the first work function metal layer 260 remains in the first gate trench 250 as shown in FIG. More importantly, the preferred embodiment removes the overhang formed by the first work function metal layer 260 at the opening of the first gate trench 250, and forms a first U shape in the first gate trench 250. The metal layer 260a and the highest point of the first U-shaped metal layer 260a are still lower than the opening of the first gate trench 250. In other words, in the preferred embodiment, the height of the first U-shaped metal layer 260a covering the sidewall of the first gate trench 250 is smaller than the depth of the first gate trench 250, thereby increasing the filling of the subsequent metal film layer. Ability to enter.

Please refer to Figure 10. After the first U-shaped metal layer 260a is formed in the first gate trench 250, a CVD process or a PVD process is performed to form a second work function metal layer 262 on the substrate 200. The second work function metal layer 262 can be an n-type work function metal layer having an n-type conductivity. In addition, the second work function metal layer 262 can be a single layer structure or a composite layer structure. Subsequently, a mask layer 272a is formed on the second work function metal layer 262, and the mask layer 272a may include the foregoing film layer having good hole filling ability, but is not limited thereto. It is also worth noting that the mask layer 272a fills the first gate trench 250 and the second gate trench 252 as shown in FIG.

Please refer to Figure 11. Next, the mask layer 272a is etched back, and a patterned mask layer 272b is formed in the first gate trench 250 and the second gate trench 252, respectively, and the surface of the patterned mask layer 272b is lower than the first layer. An opening of the gate trench 250 and the second gate trench 252 exposes a portion of the second work function metal layer 262.

Please refer to Figure 12. After forming the patterned mask layer 272b, an etching process is performed to remove portions of the exposed second work function metal layer 262 until the surface of the etch stop layer 208 is etched. As shown in FIG. 12, a third U-shaped metal layer 262a is formed in the first gate trench 250 after the etching process, and the third U-shaped metal layer 262a includes a second work function metal layer 262. A U-shaped metal layer 260a. In the second gate trench 252, a second U-shaped metal layer 262b is formed, and the second U-shaped metal layer 262b includes a second work function metal layer 262. Finally, the patterned mask layer 272b is removed.

Please refer to FIG. 14, which is a schematic diagram showing a variation of a method for fabricating a semiconductor device having a metal gate according to the present invention. It should be noted that the surface of the patterned mask layer 272b may be higher or lower than the highest point of the first U-shaped metal layer 260a, in addition to being coplanar with the highest point of the first U-shaped metal layer 260a. For example, when the surface of the patterned mask layer 272b is higher than the highest point of the first U-shaped metal layer 260a, the second work function metal layer 262 is formed as shown in FIG. 14 to form an inverted Ω-shaped metal layer; When the surface of the patterned mask layer 272b is lower than the highest point of the first U-shaped metal layer 260a, the second work function metal layer 262 forms a U shape having a highest point lower than the highest point of the first U-shaped metal layer 260a. Metal layer.

Please refer to Figure 13. Next, a fill metal layer 268 is formed in the first gate trench 250 and the second gate trench 252. In addition, a top barrier layer (not shown) may be disposed between the second work function metal layer 262 and the fill metal layer 268. The fill metal layer 268 is used to fill the first gate trench 250 and the second gate trench 252, and may select a metal or metal oxide having excellent filling ability and lower resistance. Finally, a planarization process, such as a CMP process, is performed to remove the excess fill metal layer 268 and the etch stop layer 208 to complete the fabrication of a first metal gate 280 and a second metal gate 282. In addition, the present embodiment can also selectively remove the ILD layer 242 and the CESL 240 and the like, and then reform the CESL and the dielectric layer to effectively improve the electrical performance of the semiconductor device. Since the above CMP process and the like are known to those of ordinary skill in the art, they are not described herein.

As described above, since the first work function metal layer 260 and the second work function metal layer 262 are formed in the first gate trench, respectively, when the first work function metal layer 260 and the second work function metal layer 262 are formed. 250 forms an overhang at the opening of the second gate trench 252, causing the opening of the first gate trench 250 and the second gate trench 252 to be reduced. Therefore, in the preferred embodiment, the overhangs at the openings of the first gate trench 250 and the second gate trench 252 can be removed by an etching process, and a special profile is formed in the first gate trench 250. A U-shaped metal layer 260a and a third U-shaped metal layer 262a form a second U-shaped metal layer 262b in the second gate trench 252. Due to the shape characteristics of the first U-shaped metal layer 260a, the third U-shaped metal layer 262a and the second U-shaped metal layer 262b, the openings of the first gate trench 250 and the second gate trench 252 can maintain the original size and are effective The aspect ratio of the first gate trench 250 and the second gate trench 252 is reduced, so that the filling metal layer 268 can be smoothly filled to avoid gaps between the first gate trench 250 and the second gate trench 252, thereby ensuring a gap. The reliability of the first conductive type semiconductor element 210 and the second conductive type semiconductor element 212.

In addition, before the second working function metal layer 262 is filled in the first gate trench 250 in the preferred embodiment, the overhang portion formed by the first work function metal layer 260 at the opening of the first gate trench 250 is It is removed, so that the film formation result of the second work function metal layer 262 in the first gate trench 250 can be further improved. In addition, the overhang portion formed by the first work function metal layer 260 at the opening of the first gate trench 250 is simultaneously removed from the first work function metal layer 260 to be removed at the second semiconductor element 212, in other words, The etching process can be reduced once. The overhanging portion formed by the second work function metal layer 262 formed at the opening of the first gate trench 250 and the second gate trench 252 is simultaneously removed, so that the etch stop layer 208 can be used as a protective layer to avoid The ILD layer 242 and the CESL 240 under the interface between the first work function metal layer 260 and the second work function metal layer 262 are affected by multiple etching processes, so that the above metal residue after CMP can be avoided, and the reliability of the product can be improved. .

The method for fabricating a semiconductor device having a metal gate according to the present invention is to remove a portion of all gate trenches after reducing the one to two etching processes after forming the second work function metal layer. The two-function metal layer has a highest point of the first work function metal layer and the second work function metal layer lower than the opening of the gate trench, and has a U-shaped shape feature, respectively. Therefore, the subsequently filled film layer such as the filling metal layer can be smoothly filled into the gate trench, avoiding the formation of voids, and avoiding the negative influence of the void on the electrical properties of the semiconductor element.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100, 200. . . Base

102, 202. . . Shallow trench isolation

104, 204. . . Gate dielectric layer

106, 206. . . Bottom barrier layer

108, 208. . . Etch stop layer

110, 210. . . First semiconductor component

112, 212. . . Second semiconductor component

120, 220. . . First lightly doped bungee

122, 222. . . Second lightly doped bungee

124, 224. . . Side wall

130, 230. . . First source/dip

132, 232. . . Second source/dip

134, 234. . . Metal telluride

140, 240. . . Contact hole etch stop layer

142, 242. . . Inner dielectric layer

150, 250. . . First gate ditches

152, 252. . . Second gate ditches

160, 260. . . First work function metal layer

160a, 260a. . . First U-shaped metal layer

162, 262. . . Second work function metal layer

162a, 262a. . . Third U-shaped metal layer

162b, 262b. . . Second U-shaped metal layer

168, 268. . . Filled metal layer

170, 270. . . Patterned mask layer

172a, 272a. . . Mask layer

172b, 272b. . . Patterned mask layer

180, 280. . . First metal gate

182, 282. . . Second metal gate

1 to 6 are schematic views showing a first preferred embodiment of a method for fabricating a semiconductor device having a metal gate according to the present invention.

7 to 13 are schematic views showing a second preferred embodiment of a method for fabricating a semiconductor device having a metal gate according to the present invention.

Fig. 14 is a schematic view showing a variation of a method for fabricating a semiconductor device having a metal gate provided by the present invention.

100. . . Base

102. . . Shallow trench isolation

104. . . Gate dielectric layer

106. . . Bottom barrier layer

108. . . Etch stop layer

110. . . First semiconductor component

112. . . Second semiconductor component

120. . . First lightly doped bungee

122. . . Second lightly doped bungee

124. . . Side wall

130. . . First source/dip

132. . . Second source/dip

134. . . Metal telluride

140. . . Contact hole etch stop layer

142. . . Inner dielectric layer

150. . . First gate ditches

152. . . Second gate ditches

160. . . First work function metal layer

162. . . Second work function metal layer

172b. . . Patterned mask layer

Claims (20)

A method for fabricating a semiconductor device having a metal gate includes: providing a substrate, a surface of the substrate is formed with a first semiconductor component and a second semiconductor component, and the first semiconductor component and the second semiconductor component are respectively formed a first gate trench and a second gate trench; a first work function metal layer is formed in the first gate trench; and the first gate trench and the first gate Forming a second work function metal layer in the second gate trench; forming a first patterned mask layer in the first gate trench and the second gate trench, and the first pattern The mask layer exposes a portion of the second work function metal layer; and an etching process is performed to remove the exposed portion of the second work function metal layer. The manufacturing method of claim 1, wherein the first semiconductor component has a first conductivity type, the second semiconductor component has a second conductivity pattern, and the first conductivity pattern and the second conductivity pattern Complementary. The manufacturing method of claim 1, wherein the step of forming the first work function metal layer in the first gate trench further comprises: forming the first work function metal layer on the substrate; Forming a second patterned mask layer on the substrate, and the second patterned mask layer exposes at least the first work function metal layer in the second gate trench; and removing the exposed first work function metal Floor. The manufacturing method of claim 3, wherein the surface of the second patterned mask layer is lower than the opening of the first gate trench. The manufacturing method of claim 4, wherein removing the exposed first work function metal layer is followed by forming a first U-shaped metal layer in the first gate trench. The manufacturing method of claim 4, wherein the etching process is performed to remove the exposed second work function metal layer, and a second U-shaped metal layer is formed in the second gate trench. And forming a third U-shaped metal layer in the first gate trench. The manufacturing method of claim 6, wherein the third U-shaped metal layer covers the first U-shaped metal layer. The manufacturing method of claim 7, wherein a highest point of the third U-shaped metal layer and a highest point of the first U-shaped metal layer are coplanar or non-coplanar. The manufacturing method of claim 1, wherein the forming the first patterned mask layer in the first gate trench and the second gate trench further comprises: forming a a first mask layer, and the first mask layer fills the first gate trench and the second gate trench; and etch back the first mask layer to form the first patterned mask layer, And the surface of each of the first mask layers is lower than the openings of the first gate trench and the second gate trench, and a portion of the second work function metal layer is exposed. The manufacturing method of claim 1, wherein the etching process removes the exposed second work function metal layer and the first work function metal layer. The manufacturing method of claim 10, wherein the etching process is performed by forming a first U-shaped metal layer and a third U-shaped metal layer in the first gate trench, and simultaneously forming the second gate trench A second U-shaped metal layer is formed therein. The manufacturing method of claim 11, wherein the first U-shaped metal layer comprises the first work function metal layer, the third U-shaped metal layer comprises the second work function metal layer, and the second The U-shaped metal layer includes the second work function metal layer. The manufacturing method of claim 1, wherein the second gate trench is formed simultaneously with the first gate trench. The manufacturing method of claim 1, further comprising the step of forming a filling metal layer in the first gate trench and the second gate trench respectively, after the etching process. A semiconductor device having a metal gate, comprising: a substrate; a surface of the substrate is formed with a first semiconductor component and a second semiconductor component, and a first gate is formed in the first semiconductor component and the second semiconductor component a gate trench and a second gate trench; a gate dielectric layer respectively disposed in the first gate trench and the second gate trench; a first U-shaped metal layer disposed on the first gate In the trench, the highest point of the first U-shaped metal layer is lower than the opening of the first gate trench; a second U-shaped metal layer is disposed in the second gate trench, and the second U-shaped metal The highest point of the layer is lower than the opening of the second gate trench; and a filling metal layer is disposed on the first U-shaped metal layer and the second U-shaped metal layer. The semiconductor device of claim 15, wherein the gate dielectric layer is a high-k gate dielectric layer. The semiconductor device of claim 15, wherein the first U-shaped metal layer comprises at least a first work function metal layer. The semiconductor device of claim 17, wherein the second U-shaped metal layer comprises a second work function metal layer. The semiconductor device of claim 18, further comprising a third U-shaped metal layer formed between the first U-shaped metal layer and the filling metal layer to cover the first U-shaped metal layer, and The third U-shaped metal layer includes the second work function metal layer. The semiconductor device of claim 19, wherein a highest point of the third U-shaped metal layer is coplanar or non-coplanar with a highest point of the first U-shaped metal layer.