TWI518795B - Manufacturing method for semiconductor device having metal gate - Google Patents

Description

Method for manufacturing semiconductor element having metal gate

The present invention relates to a method of fabricating a semiconductor device having a metal gate.

Gold oxide semi-transistors are a basic structure widely used in various semiconductor elements such as memory elements, image sensors, or displays. High dielectric constant dielectric (High-K) and metal gate (Metal gate) in order to maintain the continuous miniaturization of complementary metal oxide semi-transistors (CMOS) with the demand for light, thin, short, and small electronic components. Technology has become a trend in logic CMOS process technology. In order to provide a proper and appropriate work function value at the interface between the metal gate electrode and the gate dielectric layer, a different work function metal layer must be provided between the metal gate of the NMOS and PMOS and the high-k dielectric layer.

However, the work function metal layer easily forms an overhang at the opening of the gate trench, which causes the opening of the gate trench to shrink, causing the filling metal layer to not be filled smoothly, or causing the filling metal layer to create a gap in the gate trench. And affect the reliability of the component.

The present invention provides a method of fabricating a semiconductor device having a metal gate, which can provide a different work function metal layer between a metal gate of a NMOS and a PMOS and a high-k dielectric layer, and can make the filler metal layer Successfully filled into the gate ditches.

The present invention provides a method of fabricating a semiconductor device having a metal gate. First, a substrate is provided, the first semiconductor element and the second semiconductor element are formed on the surface of the substrate, and the first gate trench and the second gate trench are respectively formed in the first semiconductor component and the second semiconductor component. Then, a first work function metal layer is formed in the first gate trench and the second gate trench. Next, a first shielding layer is formed on the substrate. Thereafter, the step of removing a portion of the first shielding layer is performed for the first time, so that the remaining first shielding layer is located at the bottom of the second gate trench and fills the first gate trench. Then, the second step of removing a portion of the first shielding layer is performed, leaving a first shielding layer at the bottom of the first gate trench, so that the first working function of the second gate trench and the sidewall of the first gate trench The metal layer is bare. Then, with the first shielding layer as a mask, the first work function metal layer not covered by the first shielding layer is removed, leaving only the first work function metal layer at the bottom of the first gate trench. Next, the first obscuring layer is removed.

In an embodiment of the invention, the method further includes: forming a patterned mask layer on the first shielding layer before removing a portion of the first shielding layer, the patterned mask layer covering the first semiconductor component, bare a second semiconductor component; using a patterned mask layer as a mask, performing a first removal of a portion of the first masking layer, removing a portion of the first masking layer on the second semiconductor component; and removing the patterned Cover layer.

In one embodiment of the invention, the method of performing the first step of removing a portion of the first masking layer for the first time comprises an etching process.

In one embodiment of the invention, the method of performing the second step of removing a portion of the first masking layer comprises etching.

In an embodiment of the invention, the first shielding layer comprises a dielectric anti-reflection coating (DARC), a light absorbing oxide (DUO) layer, and a bottom anti-reflective coating (bottom). Anti-reflective coating (BARC) or sacrificial light absorbing material (SLAM) layer.

In an embodiment of the invention, the material of the first work function metal layer comprises titanium nitride, titanium carbide, tantalum nitride, tantalum carbide, tungsten carbide or aluminum titanium nitride.

In an embodiment of the invention, the method for fabricating a semiconductor device having a metal gate further includes forming a second work function metal layer in the first gate trench and the second gate trench.

In an embodiment of the invention, the second work function metal layer comprises a titanium aluminide layer, a zirconium aluminide layer, a tungsten aluminide layer, a tantalum aluminide layer or a tantalum aluminide layer.

In an embodiment of the invention, the method for fabricating a semiconductor device having a metal gate further includes forming a fill metal layer to fill the first gate trench and the second gate trench.

In an embodiment of the invention, the filler metal layer comprises aluminum, titanium aluminide or titanium oxide.

In an embodiment of the invention, the method further includes forming a top barrier layer in the first gate trench and the second gate trench to cover the first work function metal layer.

In an embodiment of the invention, the material of the top barrier layer comprises titanium nitride.

In an embodiment of the invention, before the forming the top barrier layer, the method further includes forming a second work function metal layer in the first gate trench and the second gate trench.

In an embodiment of the invention, the method further includes forming a fill metal layer to fill the first gate trench and the second gate trench.

In an embodiment of the invention, before the forming the first work function metal layer, the method further comprises forming a bottom barrier layer in the first gate trench and the second gate trench.

In an embodiment of the invention, the material of the bottom barrier layer comprises titanium nitride.

In an embodiment of the invention, before the forming the first work function metal layer, the method further comprises forming an etch stop layer on the bottom barrier layer.

In an embodiment of the invention, the material of the etch stop layer comprises tantalum nitride.

In an embodiment of the present invention, before the forming the top barrier layer, the method further includes: forming a second shielding layer on the substrate, covering the first semiconductor element and the second semiconductor element; and partially removing the second shielding layer, Excluding an etch stop layer of the sidewalls of the first gate trench and the second gate trench; removing the exposed portion of the etch stop layer and a portion of the bottom barrier layer by using the remaining second mask layer as a mask; and removing The second shielding layer.

In an embodiment of the present invention, after the second shielding layer is left as a mask, after removing a portion of the etch stop layer and a portion of the bottom barrier layer, the remaining etch stop layer and the top of the bottom barrier layer are lower than The top of the first gate trench and the top of the second gate trench.

In an embodiment of the invention, the second shielding layer comprises a dielectric anti-reflective coating, a light absorbing oxide layer, a bottom anti-reflective coating layer or a sacrificial light absorbing material layer.

The method for fabricating a semiconductor device having a metal gate of the present invention can provide different work function metal layers between the metal gate of the NMOS and the PMOS and the high-k dielectric layer, and the filling metal layer can be smoothly filled in. In the gate ditches.

The above described features and advantages of the present invention will be more apparent from the following description.

1A to 1K are schematic cross-sectional views showing a method of fabricating a semiconductor device having a metal gate according to a first embodiment of the present invention.

Referring to FIG. 1A, this embodiment first provides a substrate 100, such as a germanium substrate, a germanium-containing substrate, or a silicon-on-insulator (SOI) substrate. A first semiconductor element 110 and a second semiconductor element 112 are formed on the substrate 100, and a shallow trench isolation is provided in the substrate 100 between the first semiconductor element 110 and the second semiconductor element 112 to provide electrical isolation. , STI) structure 102. The first semiconductor element 110 has a first conductivity type, and the second semiconductor element 112 has a second conductivity type, and the first conductivity type and the second conductivity type are complementary. In the present embodiment, the first semiconductor element 110 is a p-type semiconductor element; and the second semiconductor element 112 is an n-type semiconductor element.

Referring to FIG. 1A , the first semiconductor element 110 and the second semiconductor element 112 respectively have a first gate trench 150 and a second gate trench 152 . The first semiconductor element 110 and the second semiconductor element 112 respectively include a gate dielectric layer 104, a lower barrier layer 106, and an etch stop layer 108. In addition, the first semiconductor component 110 includes a first light doped drain (LDD) 120 and a first source/drain 130 and a spacer 124; the second semiconductor component 112 includes a second LDD 122 and a second Source/drain 132 and spacer 124. In addition, the surface of the first source/drain 130 and the second source/drain 132 respectively selectively include a metal telluride 134.

Further, on the first semiconductor element 110 and the second semiconductor element 112, a contact etch stop layer (CESL) 140 and an inter-layer dielectric (ILD) layer 142 are sequentially formed. The manufacturing steps and material selection of the above components, and even the selective epitaxial growth (SEG) method for forming the source/drain electrodes 130, 132, etc. in the semiconductor industry to provide stress and improve electrical performance. It is well known to those skilled in the art and will not be described here.

The gate dielectric layer 104 can be a hafnium oxide layer, a high dielectric constant (high-k) gate dielectric layer (dielectric constant greater than 4), or a combination thereof. The high dielectric constant material has a dielectric constant greater than 4, which may be a metal oxide layer, such as a rare earth metal oxide layer. The material having a high dielectric constant may be selected from the group consisting of hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSiO ₄ ), hafnium silicon oxynitride (HfSiON), and aluminum oxide (HfSiO). Aluminum oxide, Al ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ ), yttrium oxide (Y ₂ O ₃ ), zirconium oxide , ZrO ₂ ), strontium titanate oxide (SrTiO ₃ ), zirconium silicon oxide (ZrSiO ₄ ), hafnium zirconium oxide (HfZrO ₄ ), strontium oxide Bismuth tantalate, SrBi ₂ Ta ₂ O ₉ , SBT), lead zirconate titanate (PbZr _x Ti _1-x O ₃ , PZT) and barium strontium titanate (Ba _x Sr _1-x TiO ₃ , BST) consisting of a group, where x is a value between 0 and 1. An interfacial layer 103 may also be disposed between the high dielectric constant gate dielectric layer 104 and the substrate 100. The material of the interface layer 103 is, for example, cerium oxide. The bottom barrier layer 106 then comprises titanium nitride (TiN), which is formed by, for example, atomic layer deposition. The etch stop layer 108 may include tantalum nitride, and the method of forming it is, for example, an atomic layer deposition method, but is not limited thereto.

This embodiment can be integrated with a "post-high dielectric constant gate-high-k last process". That is, the gate dielectric layer 104 of the first semiconductor element 110 and the second semiconductor element 112 is a high dielectric constant material, and is formed after the dummy gate is formed and removed. In more detail, the process method is to form a layer of interface material on the substrate 100 to form a dummy gate layer. The material of the dummy gate layer is, for example, polycrystalline germanium, but is not limited thereto. Thereafter, the interface material layer and the dummy gate layer are patterned to form a patterned interface material layer and a dummy gate. Next, the CESL 140 and ILD layer 142 are formed, and a portion of the CESL 140 and ILD layer 142 are removed by a planarization process until the dummy gates of the first semiconductor component 110 and the second semiconductor component 112 are exposed. Then, the dummy gates of the first semiconductor element 110 and the second semiconductor element 112 are removed by a suitable etching process, and the first gate trenches 150 and the first semiconductor trenches 110 and the second semiconductor components 112 are respectively formed. Two gate ditches 152. The interface material layer can then be selectively removed and the interface layer 103 re-grown, and then a high dielectric constant gate dielectric layer 104 is formed over the substrate 100. Thereafter, a bottom barrier layer 106 and/or an etch stop layer 108 are formed.

Referring to FIG. 1B, after the etch stop layer 108 is formed, a first work function metal layer 160 is formed on the substrate 100, and the first work function metal layer 160 is filled in the first gate trench 150 and the second gate trench 152. . The first work function metal layer 160 may be a p-type work function metal layer having a p-type conductivity type, such as titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN) ), tantalum carbide (TaC), tungsten carbide (WC), or aluminum titanium nitride (TiAlN), but is not limited thereto. The first work function metal layer 160 may be a single layer structure or a composite layer structure. The method for forming the first work function metal layer 160 is, for example, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or an atomic layer deposition (ALD) process. .

Next, a first shielding layer 169 and a mask layer 170 are formed on the substrate 100. The first shielding layer 169 may be a film layer with good hole filling ability, such as a dielectric anti-reflection coating (DARC), a light absorbing oxide (DUO) layer, and a bottom anti-reflection coating. (Bottom anti-reflective coating, BARC) or sacrificial light absorbing material (SLAM) layer, etc., but is not limited thereto, and the method of forming it is, for example, a spin coating method. The material of the mask layer 170 is, for example, a photoresist.

Referring to FIG. 1C, the mask layer 170 is patterned to form a patterned mask layer 170a. The patterned mask layer 170a covers the first masking layer 169 at the first semiconductor component 110 and exposes the first masking layer 169 at the second semiconductor component 112. Thereafter, the patterned mask layer 170a is a mask, removing a portion of the first masking layer 169 that is not covered by the patterned mask layer 170a, leaving a first masking layer 169a among the second gate trenches 152 and The first obscuring layer 169b at the first semiconductor component 110. The surface height of the first shielding layer 169a in the second gate trench 152 is lower than the top end of the second gate trench 152, so that a portion of the first work function metal layer 160 is exposed. The method of removing a portion of the first masking layer 169 that is not covered by the patterned mask layer 170a may utilize an appropriate etchant for the etch back process.

Thereafter, referring to FIG. 1D, the patterned mask layer 170a is removed to expose the first masking layer 169b at the first semiconductor component 110. The method of removing the patterned mask layer 170a may utilize a dry process or a wet process or both. Since the first gate trench 150 and the bottom of the second gate trench 152 are covered by the first shielding layers 169b and 169a, respectively, the plasma can be prevented from passing through the first work function metal layer 160 during the subsequent plasma etching process. The etch stop layer 108, the bottom barrier layer 106, and the high dielectric constant gate dielectric layer 104 are destroyed.

Next, referring to FIG. 1E, the first shielding layer 169b is partially removed, so that the first shielding layer 169a in the second gate trench 152 is completely removed, leaving the first shielding layer 169c at the bottom of the first gate trench 150. . The surface of the first shielding layer 169c is lower than the top end of the first gate trench 150. The thickness of the preferred first shielding layer 169c is as thin as possible, and only needs to be protected in the first gate trench 150 in a subsequent etching process. The first work function metal layer 160 at the bottom, and as far as possible, the first work function metal layer 160 on the sidewall of the first gate trench 150 can be exposed. The method of partially removing the first mask layer 169b may employ an etching method such as a dry etching method.

Subsequently, referring to FIG. 1F, with the first shielding layer 169c as a mask, the first work function metal layer 160 not protected by the first shielding layer 169c is removed by a suitable etchant. When etching is performed, the first work function metal layer 160 on the sidewall of the first gate trench 150 is removed as much as possible, leaving only the first work function metal layer 160a at the bottom of the first gate trench 150, so that the first gate The etch stop layer 108 on the sidewall of the trench 150 is exposed. In FIG. 1F, the first work function metal layer 160a is U-shaped. In another embodiment, the etching time can also be controlled such that the first work function metal layer 160a covers only the bottom of the first gate trench 150 without covering the sidewall of the first gate trench 150.

Thereafter, referring to FIG. 1G, the first shielding layer 169c is removed to expose the surface of the first work function metal layer 160a. The method of removing the first mask layer 169c may employ an etching method such as a dry etching method. Thereafter, a second shielding layer 174 is formed on the substrate 100. The second shielding layer 174 may be a film layer with good filling ability, such as a dielectric anti-reflective coating, a light absorbing oxide layer, a bottom anti-reflective coating layer or a sacrificial light-absorbing material layer, but is not limited thereto, and is formed by The method is, for example, a spin coating method.

Thereafter, referring to FIG. 1H, a portion of the second shielding layer 174 is removed, leaving a second shielding layer 174a located in the first gate trench 150 and a second shielding layer 174b among the second gate trenches 152, bare. The etch stop layer 108 of the sidewall is exited. The method of removing a portion of the second masking layer 174 can utilize an appropriate etchant for the etch back process. The thickness of the second shielding layers 174a and 174b is as thin as possible, and it is only necessary to protect the surface of the first work function metal layer 160a from damage in a subsequent etching process.

Thereafter, referring to FIG. 1I, with the second shielding layers 174a and 174b as masks, the etch stop layer 108 and the bottom barrier layer 106 not protected by the second shielding layers 174a and 174b are removed by a suitable etchant. The process can remove the etch stop layer 108 and the bottom barrier layer 106 of the sidewalls of the first gate trench 150 and the sidewall portion of the second gate trench 152, such that the sidewalls of the first gate trench 150 and the sidewall of the second gate trench 152 The high-k gate dielectric layer 104 is exposed, leaving a low-level U-shaped etch stop layer 108a and a low-height U-type bottom barrier layer in the first gate trench 150 and the second gate trench 152. 106a. The U-type etch stop layer 108a may also be referred to as a first U-type metal layer; the U-type bottom barrier layer 106a may also be referred to as a second U-type metal layer. The heights of the sidewalls of the first U-shaped metal layer, the second U-shaped metal layer and the first work-function metal layer 160a may be the same or different, and the heights of the three are not necessarily as shown in FIG. 1I, and the height of each layer may be etched by etching. The parameters and the height of the first shielding layer 169c and the second shielding layers 174a and 174b are adjusted.

Thereafter, referring to FIG. 1J, the second shielding layers 174a and 174b are removed to expose the first work function metal layer 160a in the first gate trench 150 and the U-type etch stop layer 108a in the second gate trench 152. . Thereafter, a second work function metal layer 162 is formed on the substrate 100. The second work function metal layer 162 may be an n-type work function metal layer having an n-type conductivity type, such as a titanium aluminide (TiAl) layer, a zirconium aluminide (ZrAl) layer, and a tungsten aluminide (tungsten). Aluminide, WAl) layer, tantalum aluminide (TaAl) layer or hafnium aluminide (HfAl) layer, but is not limited thereto. Further, the second work function metal layer 162 may be a single layer structure or a composite layer structure. The second work function metal layer 162 can be formed by a CVD process or a PVD process. Next, a fill metal layer 168 is formed on the substrate 100. The formed fill metal layer 168 is filled in the first gate trench 150 and the second gate trench 152. The filling metal layer 168 is used to fill the first gate trench 150 and the second gate trench 152, and may select a metal or metal oxide having excellent filling ability and lower resistance, such as aluminum (aluminum, aluminum), aluminum. Titanium aluminide (TiAl) or titanium aluminum oxide (TiAlO), but is not limited thereto. In addition, a top barrier layer 163 may be disposed between the second work function metal layer 162 and the fill metal layer 168, and the top barrier layer 163 may include titanium nitride (TiN), which is formed by, for example, atomic layer deposition. But it is not limited to this.

Finally, referring to FIG. 1K, a planarization process, such as a CMP process, can be performed to remove the excess fill metal layer 168, the top barrier layer 163, and the second work function metal layer 162 on the ILD layer 142. Fabrication of a metal gate 168a and a second metal gate 168b. In addition, the present embodiment can also selectively remove the ILD layer 142 and the CESL 140 and the like, and then reform the CESL and the dielectric layer to effectively improve the electrical performance of the semiconductor device. Since the above CMP process and the like are known to those of ordinary skill in the art, they are not described herein.

In the above embodiment, the steps of removing the etch stop layer 108 and the bottom barrier layer 106 of the sidewalls of the first gate trench 150 and the second gate trench 152 by using the second shielding layer 174a, 174b as a mask ( FIG. 1I) is capable of smoothly filling the second work function metal layer 162, the top barrier layer 163, and the filling metal layer 168 in the first gate trench 150 and the second gate trench 152. However, if the size of the upper portion of the first gate trench 150 and the second gate trench 152 is sufficiently large or the thickness of the etch stop layer 108 and the bottom barrier layer 106 is sufficiently thin to make the second work function metal layer 162, the top resistor The barrier layer 163 and the filling metal layer 168 are smoothly filled into the first gate trench 150 and the second gate trench 152, so that the second gate layer 174a, 174b is not required to be used as a mask to remove the first gate. The etch stop layer 108 and the bottom barrier layer 106 of the sidewalls of the trench 150 and the second gate trench 152. Therefore, the second shielding layer 174 corresponding to FIGS. 1G to 1I is formed to remove the first gate trench 150 and the second gate. The steps of the etch stop layer 108 and the bottom barrier layer 106 on the sidewalls of the pole trench 152 are selective and can be adjusted according to actual needs.

In addition, the above embodiments are described by the "post-high dielectric constant gate dielectric layer process", however, the invention is not limited thereto. Another embodiment can also be integrated with a "high-k first process".

2A to 2B are schematic cross-sectional views showing a method of fabricating a semiconductor device having a metal gate according to a second embodiment of the present invention.

Referring to FIG. 2A, the present embodiment is integrated with a "high-k first process". That is, the first semiconductor element 110 and the second semiconductor element 112 also have a first gate trench 150 and a second gate trench 152, respectively. Each of the first semiconductor element 110 and the second semiconductor element 112 includes a gate dielectric layer 104, a lower barrier layer 106, and an etch stop layer 108, respectively. However, a high dielectric constant gate dielectric layer is formed prior to the formation of the dummy gate. In more detail, the process method is to form an interface layer 103 on the substrate 100, form a high dielectric constant gate dielectric layer 104 and a bottom barrier layer 106, and then form a dummy gate. Thereafter, the interface layer 103, the high dielectric constant gate dielectric layer 104, and the bottom barrier layer 106 are patterned into those shown in FIG. 1A. Thereafter, CESL 140 and ILD layer 142 are formed on substrate 100, and portions of CESL 140 and ILD layer 142 are removed by a planarization process until exposed dummy gates of first semiconductor component 110 and second semiconductor component 112 are exposed. pole. Then, the dummy gates of the first semiconductor component 110 and the second semiconductor component 112 are removed by using a suitable etching process, and the first gate trenches 150 and the second gates are respectively formed in the first semiconductor component 110 and the second semiconductor component 112. Gate ditches 152. Subsequently, the aforementioned etch stop layer 108 is formed again.

Thereafter, referring to FIG. 2B, the fabrication of the first metal gate 168a and the second metal gate 168b is completed in accordance with the steps corresponding to FIGS. 1B through 1K.

In the above embodiment of the present invention, before the first work function metal layer 160 in the second gate trench 152 is removed, the bottom of the second gate trench 152 is covered by the first shielding layer 169a instead of being exposed. Therefore, in the subsequent plasma etching process, the plasma can be prevented from passing through the first work function metal layer 160 to destroy the etch stop layer 108, the bottom barrier layer 106, and the high-k gate dielectric under the first work function metal layer 160. Electrical layer 104 (Fig. 1D).

Furthermore, the above embodiment of the present invention simultaneously removes the first work function metal layer 160 and the etch stop layer at the top end of the first gate trench 150 and the second gate trench 152 and near the top end of the trench by an etching process. 108 and the bottom barrier layer 106, only the bottom of the first gate trench 150 and the second gate trench 152 and the sidewall near the bottom of the trench respectively form a first work function metal layer 160a having a special profile, and a U-type etch stop Layer 108a and U-type bottom barrier layer 106a. Since the highest points of the first work function metal layer 160a, the U-type etch stop layer 108a and the U-type bottom barrier layer 106a are lower than the open tops of the first gate trench 150 and the second gate trench 152, the first gate The open top ends of the trenches 150 and the second gate trenches 152 are not covered by the first work function metal layer 160a, the U-type etch stop layer 108a and the U-type bottom barrier layer 106a, and therefore, the shape feature maintains the first gate The pole trench 150 and the second gate trench 152 are opened to the original size (caliber), and the aspect ratio of the first gate trench 150 and the second gate trench 152 is effectively reduced, so that the subsequent top resistance can be made. The barrier layer 163, the second work function metal layer 162, and the filling metal layer 168 are smoothly filled to avoid a gap when the first gate trench 150 and the second gate trench 152 are filled, and the first semiconductor device 110 is ensured. The reliability of the second semiconductor component 112 (Fig. 1J).

In summary, the method for fabricating a semiconductor device having a metal gate according to the present invention is to remove the first work function metal layer before removing the first work function metal layer in the gate trench. A portion of the shielding layer is reserved in the gate trench to prevent the etch stop layer, the bottom barrier layer, and the high-k gate dielectric layer under the first work function metal layer from being damaged during the subsequent etching process. Furthermore, in the method for fabricating a semiconductor device having a metal gate provided by the present invention, the first work function metal layer, the etch stop layer and the bottom barrier layer only cover the bottom of the gate trench and the bottom of the gate trench Therefore, the gate trench can maintain the original size (caliber) and effectively reduce the aspect ratio of the gate trench, so that the subsequent filling metal layer can be smoothly filled in, and the reliability of the semiconductor component can be ensured.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100. . . Base

102. . . Shallow trench isolation structure

103. . . Interface layer

104. . . Gate dielectric layer

106. . . Bottom barrier layer

106a. . . U-shaped bottom barrier layer

108. . . Etch stop layer

108a. . . U-shaped etch stop layer

110. . . First semiconductor component

112. . . Second semiconductor component

120. . . First lightly doped bungee

122. . . Second lightly doped bungee

124. . . Clearance wall

130. . . First source/dip

132. . . Second source/dip

134. . . Metal telluride

140. . . Contact window etch stop layer

142. . . Inner dielectric layer

150. . . First gate ditches

152. . . Second gate ditches

160, 160a. . . First work function metal layer

162, 162a. . . Second work function metal layer

163. . . Top barrier

168. . . Filled metal layer

168a. . . First metal gate

168b. . . Second metal gate

169, 169a, 169b, 169c. . . First shielding layer

170. . . Mask layer

170a. . . Patterned mask layer

174, 174a, 174b. . . Second shielding layer

1A to 1K are schematic cross-sectional views showing a method of fabricating a semiconductor device having a metal gate according to a first embodiment of the present invention.

2A to 2B are schematic cross-sectional views showing a method of fabricating a semiconductor device having a metal gate according to a second embodiment of the present invention.

100. . . Base

102. . . Shallow trench isolation structure

103. . . Interface layer

104. . . Gate dielectric layer

106. . . Bottom barrier layer

108. . . Etch stop layer

110. . . First semiconductor component

112. . . Second semiconductor component

120. . . First lightly doped bungee

122. . . Second lightly doped bungee

124. . . Clearance wall

130. . . First source/dip

132. . . Second source/dip

134. . . Metal telluride

140. . . Contact window etch stop layer

142. . . Inner dielectric layer

150. . . First gate ditches

152. . . Second gate ditches

160. . . First work function metal layer

169a, 169b. . . First shielding layer

Claims (21)

A method of fabricating a semiconductor device having a metal gate includes: providing a substrate, a surface of the substrate is formed with a first semiconductor component and a second semiconductor component, and a first semiconductor component and the second semiconductor component are respectively formed a first gate trench and a second gate trench; forming a first work function metal layer in the first gate trench and the second gate trench; forming a first shielding layer on the substrate; Removing a portion of the first shielding layer at a time, leaving the first shielding layer at the bottom of the second gate trench and filling the first gate trench; performing a second removal portion a step of shielding the first shielding layer at the bottom of the first gate trench to expose the first work function metal layer of the second gate trench and the sidewall of the first gate trench; The first shielding layer is a mask to remove the first work function metal layer not covered by the first shielding layer, leaving only the first work function metal layer at the bottom of the first gate trench; and removing The first shielding layer. The method for manufacturing a semiconductor device having a metal gate according to claim 1, further comprising: forming a patterned mask layer on the first shielding layer before removing a portion of the first shielding layer, The patterned mask layer covers the first semiconductor component to expose the second semiconductor component; and the patterned mask layer is used as a mask to perform the first removing portion of the first shielding layer step Removing the first masking layer from the portion of the second semiconductor component; and removing the patterned mask layer. The method of manufacturing a semiconductor device having a metal gate according to claim 2, wherein the method of performing the step of removing a portion of the first shielding layer for the first time comprises an etching method. A method of fabricating a semiconductor device having a metal gate according to claim 2, wherein the method of performing the second removing of the first masking step comprises etching. The method for fabricating a semiconductor device having a metal gate according to claim 1, wherein the first shielding layer comprises a dielectric anti-reflection coating (DARC) and a light absorbing oxide (light absorbing) Oxide, DUO) layer, bottom anti-reflective coating (BARC) or sacrificial light absorbing material (SLAM) layer. The method for manufacturing a semiconductor device having a metal gate according to claim 1, wherein the material of the first work function metal layer comprises titanium nitride, titanium carbide, tantalum nitride, tantalum carbide, tungsten carbide or nitrogen. Aluminum titanium. The method for fabricating a semiconductor device having a metal gate according to claim 1, further comprising forming a second work function metal layer in the first gate trench and the second gate trench. The method for manufacturing a semiconductor device having a metal gate according to claim 7, wherein the second work function metal layer comprises a titanium aluminide layer, a zirconium aluminide layer, a tungsten aluminide layer, a tantalum layer or Aluminized ruthenium layer. The method for fabricating a semiconductor device having a metal gate according to claim 1, further comprising forming a filling metal layer to fill the first gate trench and the second gate trench. The method of manufacturing a semiconductor device having a metal gate according to claim 9, wherein the filler metal layer comprises aluminum, titanium aluminide or titanium oxide. The method for manufacturing a semiconductor device having a metal gate according to claim 1, further comprising: forming a top barrier layer in the first gate trench and the second gate trench, covering the first Work function metal layer. The method of manufacturing a semiconductor device having a metal gate according to claim 11, wherein the material of the top barrier layer comprises titanium nitride. The method for manufacturing a semiconductor device having a metal gate according to claim 11, wherein before forming the top barrier layer, forming a first portion in the first gate trench and the second gate trench Two work function metal layer. The method for fabricating a semiconductor device having a metal gate according to claim 11, further comprising forming a filling metal layer to fill the first gate trench and the second gate trench. The method for fabricating a semiconductor device having a metal gate according to claim 11 is further included in the first gate trench and the second gate trench before forming the first work function metal layer. A bottom barrier layer. The method of manufacturing a semiconductor device having a metal gate according to claim 15, wherein the material of the bottom barrier layer comprises titanium nitride. The method for fabricating a semiconductor device having a metal gate according to claim 15 further comprises forming an etch stop layer on the bottom barrier layer before forming the first work function metal layer. The method of manufacturing a semiconductor device having a metal gate according to claim 17, wherein the material of the etch stop layer comprises tantalum nitride. The method for fabricating a semiconductor device having a metal gate according to claim 17, further comprising: forming a second shielding layer on the substrate to cover the first semiconductor device and before forming the top barrier layer The second semiconductor component partially removes the second shielding layer, exposing the etch stop layer of the first gate trench and the sidewall of the second gate trench; and leaving the second shielding layer as a mask Removing the exposed portion of the etch stop layer and a portion of the bottom barrier layer; and removing the second mask layer. The method for fabricating a semiconductor device having a metal gate according to claim 19, wherein after the second shielding layer is left as a mask, after the portion of the etch stop layer and a portion of the bottom barrier layer are removed, The etch stop layer and the top of the bottom barrier layer are lower than the top of the first gate trench and the second gate trench. The method for fabricating a semiconductor device having a metal gate according to claim 19, wherein the second shielding layer comprises a dielectric anti-reflective coating, a light absorbing oxide layer, a bottom anti-reflective coating layer or a sacrificial light absorbing material. Floor.